ICS93V855 Integrated Circuit Systems, Inc. DDR Phase Lock Loop Clock Driver Recommended Application: DDR Clock Driver Pin Configuration Product Description/Features: • Low skew, low jitter PLL clock driver • External feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • With bypass mode mux • Operating frequency 60 to 170 MHz Switching Characteristics: • CYCLE - CYCLE jitter:<75ps • OUTPUT - OUTPUT skew: <60ps • Output Rise and Fall Time: 650ps - 950ps 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ICS93V855 GND DDRC0 DDRT0 VDD2.5 CLK_INT CLK_INC AVDD2.5 AGND GND DDRC1 DDRT1 VDD2.5 DDRT2 DDRC2 DDRC4 DDRT4 VDD2.5 GND FB_OUTC FB_OUTT VDD2.5 FB_INT FB_INC GND VDD2.5 DDRT3 DDRC3 GND 28-Pin 4.4mm TSSOP Block Diagram Functionality INPUTS OUTPUTS AVDD CLK_INT CLK_INC DDRT DDRC FB_OUTT FB_OUTC FB_OUTT FB_OUTC DDRT0 DDRC0 DDRT1 DDRC1 Control Logic DDRT2 DDRC2 DDRT3 DDRC3 DDRT4 DDRC4 FB_INT FB_INC CLK_INC CLK_INT AVDD2.5 0497B—06/01/04 PLL GND L H L GND 2.5V (nom) 2.5V (nom) H L L H H L 2.5V <20 MHz <20 MHz (nom) H L H L L H H Hi-Z PLL State H Bypassed/Off H L Bypassed/Off L H On L H L On Hi-Z Hi-Z Hi-Z Off ICS93V855 Pin Descriptions PIN # PIN NAME PIN TYPE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 GND DDRC0 DDRT0 VDD2.5 CLK_INT CLK_INC AVDD2.5 AGND GND DDRC1 DDRT1 VDD2.5 DDRT2 DDRC2 GND DDRC3 DDRT3 VDD2.5 GND PWR OUT OUT PWR IN IN PWR PWR PWR OUT OUT PWR OUT OUT PWR OUT OUT PWR PWR DESCRIPTION 20 FB_INC IN Complement single-ended feedback input, provides feedback signal to internal PLL for synchronization with CLK_INT to eliminate phase error. 21 FB_INT IN True single-ended feedback input, provides feedback signal to internal PLL for synchronization with CLK_INT to eliminate phase error. 22 VDD2.5 PWR 23 FB_OUTT OUT 24 FB_OUTC OUT 25 26 27 28 GND VDD2.5 DDRT4 DDRC4 PWR PWR OUT OUT Ground pin. "Complimentary" Clock of differential pair output. "True" Clock of differential pair output. Power supply, nominal 2.5V "True" reference clock input. "Complimentary" reference clock input. 2.5V Analog Power pin for Core PLL Analog Ground pin for Core PLL Ground pin. "Complimentary" Clock of differential pair output. "True" Clock of differential pair output. Power supply, nominal 2.5V "True" Clock of differential pair output. "Complimentary" Clock of differential pair output. Ground pin. "Complimentary" Clock of differential pair output. "True" Clock of differential pair output. Power supply, nominal 2.5V Ground pin. Power supply, nominal 2.5V True single-ended feedback output, dedicated external feedback. It switches at the same frequency as other DDR outputs, This output must be connect to FB_INT. Complement single-ended feedback output, dedicated external feedback. It switches at the same frequency as other DDR outputs, This output must be connect to FB_INC. Ground pin. Power supply, nominal 2.5V "True" Clock of differential pair output. "Complimentary" Clock of differential pair output. 0497B—06/01/04 2 ICS93V855 Absolute Maximum Ratings Supply Voltage: (VDD & AVDD) . . . . . . . . . . -0.5V to 3.6V (VDDI) . . . . . . . . . . . . . . -0.5V to 4.6V Logic Inputs: VI . . . . . . . . . . . . . . . . . . . . . . . VSS –0.5 V to VDD +0.5 V Logic Outputs: VO . . . . . . . . . . . . . . . . . . . . . VSS –0.5 V to VDD +0.5 V Input clamp current: IIK (VI < 0 or VI > VDD) +/- 50mA Output clamp current: IOK (VO < 0 or VO > VDD) +/- 50mA Continuous output current: IO (VO = 0 to VDD) +/- 50mA Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) SYMBOL MIN TYP PARAMETER CONDITIONS IIH VI = VDD or GND Input High Current 5 VI = VDD or GND IIL Input Low Current CL = 0pf, RL = 120 ohms IDD2.5 Operating Supply Current CL = 0pf, RL = 120 ohms IDDPD VDD = 2.3V, VOUT = 1V -18 Output High Current IOH Output Low Current IOL VDD = 2.3V, VOUT = 1.2V MAX 5 250 100 26 UNITS µA µA mA µA mA mA High Impedance Output Current Input Clamp Voltage IOZ VDD=2.7V, Vout=VDD or GND ±10 µA VIK -1.2 V High-level output voltage VOH Iin = -18mA VDD = min to max, IOH = -1 mA VDD = 2.3V, IOH = -12 mA VDD = min to max IOL=1 mA VDD = 2.3V IOH=12 mA VI = VDD or GND VI = VDD or GND Low-level output voltage VOL VDD - 0.1 V 1.7 V 0.1 0.6 CIN Input Capacitance1 1 C OUT Output Capacitance 1 Guaranteed by design and characterization, not 100% tested in production. 0497B—06/01/04 3 3 3 V pF pF ICS93V855 DC Electrical Characteristics TA = 0°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) SYMBOL MIN PARAMETER CONDITIONS VDDQ, AVDD Supply Voltage 2.3 CLK_INT, CLK_INC, FB_INC, VIL Low level input voltage FB_INT CLK_INT, CLK_INC, FB_INC, VDD/2 + 0.18 VIH High level input voltage FB_INT DC input signal voltage (note VIN -0.3 1,2) Differential input signal CLK_INT, CLK_INC, FB_INC, VID 0.36 voltage (note 3) FB_INT Differential output voltage CLK_INT, CLK_INC, FB_INC, VOD 0.7 FB_INT (note 3) Output differential crossVOX VDD/2 - 0.15 voltage (note 4) Input differential crossVIX VDD/2 - 0.2 voltage (note 4) Operating free-air TA 0 temperature TYP 2.5 MAX 2.7 UNITS V 0.4 VDD/2 - 0.18 V 2.1 VDD/2 V VDD + 0.3 V VDD + 0.6 V VDD + 0.6 V VDD/2 + 0.15 V VDD/2 + 0.2 V 85 °C Notes: 1 Unused inputs must be held high or low to prevent them from floating. 2 DC input signal voltage specifies the allowable DC excursion of differential input. 3 Differential input signal voltage specifies the differential voltage [VTR-VCP] required for switching, where VTR is the true input level and VCP is the complementary input level. 4 Differential cross-point voltage is expected to track variations of VDD and is the voltage at which the differential signal must be crossing. 0497B—06/01/04 4 ICS93V855 Switching Characteristics TA = 0°C to +85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) PARAMETER CONDITION SYMBOL MIN TYP 3 freq 33 Max clock frequency op Application Frequency freqApp 60 Range3 dtin Input clock duty cycle 40 t 1 Input clock slew rate sl(I) TSTAB CLK stabilization Low-to high level propagation CLK_IN to any output 5.5 tPLH1 delay time High-to low level propagation CLK_IN to any output 5.5 tPHL1 delay time ten PD# to any output 5 Output enable time tdis PD# to any output 5 Output disable time tjit (per) -75 Period jitter tjit(hper) -100 Half-period jitter tsl(o) Output clock slew rate Over the application 1 frequency range tcyc-tcyc -75 Cycle to Cycle Jitter t(phase error) -50 Phase error4 tskew 40 Output to Output Skew t , t Rise Time, Fall Time 650 800 Load = 120Ω/16pF r f Notes: 1. Refers to transition on noninverting output in PLL bypass mode. 2. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle=twH/tc, were the cycle (tc) decreases as the frequency goes up. 3. Switching characteristics are guaranteed for application frequency range. The PLL Locks over the Max Clock Frequency range, but the device doe not necessarily meet other timing parameters. 4. Does not include jitter. 0497B—06/01/04 5 MAX 233 UNITS MHz 170 MHz 60 2 100 % v/ns µs ns ns 75 100 2 75 50 60 950 ns ns ps ps v/ns ps ps ps ps ICS93V855 Parameter Measurement Information VDD V(CLKC) R = 60Ω R = 60Ω VDD/2 V(CLKC) ICS93V855 GND Figure 1. IBIS Model Output Load VDD/2 C = 16 pF -V DD/2 ICS93V855 R = 10Ω Z = 60Ω SCOPE Z = 50Ω R = 50Ω V(TT) R = 10Ω Z = 60Ω Z = 50Ω R = 50Ω C = 16 pF V(TT) -VDD/2 -VDD/2 NOTE: V(TT) = GND Figure 2. Output Load Test Circuit YX, FB_OUTC YX, FB_OUTT tc(n) tc(n+1) tjit(cc) = tc(n) ± tc(n+1) 0497B—06/01/04 Figure 3. Cycle-to-Cycle Jitter 6 ICS93V855 Parameter Measurement Information CLK_INC CLK_INT FB_INC FB_INT t( ) n n=N t( ) n 1 t( )= N (N is a large number of samples) Figure 4. Static Phase Offset YX# YX YX, FB_OUTC YX, FB_OUTT t(skew) Figure 5. Output Skew YX, FB_OUTC YX, FB_OUTT tC(n) YX, FB_OUTC YX, FB_OUTT 1 fO t(jit_per) = tc(n) - 1 fO Figure 6. Period Jitter 0497B—06/01/04 7 t ( ) n+1 ICS93V855 Parameter Measurement Information YX, FB_OUTC YX, FB_OUTT t jit(hper_n+1) t jit(hper_n) 1 fo tjit(hper) = t jit(hper_n) - 1 2xfO Figure 7. Half-Period Jitter 80% 80% VID, VOD Clock Inputs and Outputs 20% 20% tslr tslf Figure 8. Input and Output Slew Rates 0497B—06/01/04 8 ICS93V855 4.40 mm. Body, 0.65 mm. Pitch TSSOP c N (173 mil) L E1 INDEX AREA E 1 2 α D A A2 A1 -Ce b SEATING PLANE aaa C SYMBOL A A1 A2 b c D E E1 e L N a aaa (25.6 mil) In Millimeters COMMON DIMENSIONS MIN MAX -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 SEE VARIATIONS 6.40 BASIC 4.30 4.50 0.65 BASIC 0.45 0.75 SEE VARIATIONS 0° 8° -0.10 In Inches COMMON DIMENSIONS MIN MAX -.047 .002 .006 .032 .041 .007 .012 .0035 .008 SEE VARIATIONS 0.252 BASIC .169 .177 0.0256 BASIC .018 .030 SEE VARIATIONS 0° 8° -.004 VARIATIONS N 28 D mm. MIN 9.60 D (inch) MAX 9.80 MIN .378 Reference Doc.: JEDEC Publication 95, MO-153 4.40 mm. Body, 0.65 mm. pitch TSSOP (0.0256 Inch) (173 mil) 10-0035 Ordering Information ICS93V855yGT Example: ICS XXXXXX y G T Designation for tape and reel packaging Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 6 characters) Prefix ICS = Standard Device 0497B—06/01/04 9 MAX .386