ICS95V847 Integrated Circuit Systems, Inc. 2.5V Wide Range Frequency Clock Driver (45MHz - 233MHz) Recommended Application: • Zero Delay Board Fan Out, SO-DIMM • Provides complete DDR registered DIMM solution with ICSSSTV16857, ICSSSTV16859 or ICSSSTV32852 GND CLKC0 CLKT0 GND VDD CLK_INT CLK_INC AVDD AGND CLKC1 CLKT1 VDD Product Description/Features: • Low skew, low jitter PLL clock driver • 1 to 5 differential clock distribution (SSTL_2) • Feedback pins for input to output synchronization • Spread Spectrum tolerant inputs Switching Characteristics: • CYCLE - CYCLE jitter: <60ps • OUTPUT - OUTPUT skew: <60ps • Period jitter: ±30ps • DUTY CYCLE: 49.5% - 50.5% 1 2 3 4 5 6 7 8 9 10 11 12 ICS95V847 Pin Configuration 24 23 22 21 20 19 18 17 16 15 14 13 CLKT4 CLKC4 CLKC3 CLKT3 VDD FB_INT FB_INC FB_OUTC FB_OUTT CLKT2 CLKC2 GND 24-Pin TSSOP 4.40 mm. Body, 0.65 mm. pitch Functionality Block Diagram INPUTS OUTPUTS PLL State AVDD CLK_INT FB_OUTT FB_OUTC CLK_INC CLKT CLKC FB_OUTT FB_OUTC GND L H L H L H Bypassed/off GND H L H L H L Bypassed/off 2.5V (nom) L H L H L H on 2.5V (nom) H L H L H L on FB_INT FB_INC CLK_INC CLK_INT CLKT0 CLKC0 PLL CLKT1 CLKC1 CLKT2 CLKC2 CLKT3 CLKC3 CLKT4 CLKC4 0718D—04/08/05 ICS95V847 Pin Descriptions PIN NUMBER PIN NAME TYPE DESCRIPTION 5, 12, 20 VDD PWR Power supply, 2.5V 1, 4, 13 GND PWR Ground 8 AVDD PWR Analog power supply, 2.5V 9 AGND PWR A n a l o g gr o u n d 3, 11, 15, 21, 24 CLKT[0:4] OUT "Tr ue" Clock of differential pair outputs 2, 10, 14, 22, 23 CLKC[0:4] OUT "Complementar y" clocks of differential pair outputs 6 CLK_INT IN "True" reference clock input 7 CLK_INC IN "Complementar y" reference clock input 16 FB_OUTT OUT "True" " Feedback output, dedicated for external feedback. It switches at the same frequency as the CLK. This output must be wired to FB_INT 17 FB_OUTC OUT "Complementar y" Feedback output, dedicated for external feedback. It switches at the same frequency as the CLK. This output must be wired to FB_INC 19 FB_INT IN "True" Feedback input, provides feedback signal to the internal PLL for synchronization with CLK_INT to eliminate phase error 18 FB_INC IN "Complementar y" Feedback input, provides signal to the internal PLL for synchronization with CLK_INC to eliminate phase error This PLL Clock Buffer is designed for a VDD of 2.5V, an AVDD of 2.5V and differential data input and output levels. ICS95V847 is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to five differential pair of clock outputs (CLKT[4:0], CLKC[4:0]) and one differential pair feedback clock output (FB_OUT, FB_OUTC). The clock outputs are controlled by input clock (CLK_INT, CLK_INC), the feedback clock (FB_INT, FB_INC) and the analog power input (AVDD). When AVDD is grounded, the PLL is turned off and bypassed for test purposes. The PLL in ICS95V847 clock driver uses the input clock (CLK_INC, CLK_INT) and the feedback clock (FB_INT, FB_INC) to provide high-performance, low-skew, low-jitter differential output clocks (CLKT[4:0], CLKC[4:0]). ICS95V847 is also able to track Spread Spectrum Clock (SSC) for reduced EMI. ICS95V847 is characterized for operation from 0°C to 85°C. 0718D—04/08/05 2 ICS95V847 Absolute Maximum Ratings Supply Voltage (VDD & AVDD) . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . -0.5V to 4.6V GND - 0.5V to VDD + 0.5V 0°C to +85°C -65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) PARAMETER Input High Current Input Low Current Operating Supply Current High Impedance Output Current Input Clamp Voltage SYMBOL I IH I IL IDD2.5 IDDPD IOZ VIK High-level output voltage VOH Low-level output voltage VOL CONDITIONS VI = V DD or GND VI = VDD or GND CL = 0pf @ 200MHz CL = 0pf VDD = 2.7V, Vout = VDD or GND VDD = 2.3V Iin = -18mA IOH = -1 mA IOH = -12 mA IOL =1 mA IOH =12 mA VI = GND or V DD MIN 5 TYP MAX 5 148 100 UNITS µA µA mA µA ±10 mA -1.2 V V V V V pF VDD - 0.1 1.7V CIN Input Capacitance1 1 Guaranteed by design at 233MHz, not 100% tested in production. 0718D—04/08/05 3 2.5 0.1 0.6 3.5 ICS95V847 Recommended Operating Condition (see note1) TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) PARAMETER Supply Voltage SYMBOL VDD, A VDD VDD + 0.6 UNITS V V V V V -0.3 VDD + 0.3 V 0.36 0.7 VDD + 0.6 VDD + 0.6 V V V OX VDD/2 - 0.15 V DD/2 + 0.15 V VIX VDD/2 - 0.2 V DD/2 + 0.2 V IOH -6.4 mA Low level output current IOL 5.5 mA Operating free-air temperature TA 85 °C Low level input voltage VIL High level input voltage VIH DC input signal voltage (note 2) Differential input signal voltage (note 3) Output differential crossvoltage (note 4) Input differential crossvoltage (note 4) High level output current CONDITIONS CLKT, CLKC, FB_INC PD# CLKT, CLKC, FB_INC PD# VIN VID DC - CLKT, FB_INT AC - CLKT, FB_INT MIN 2.3 -0.3 V DD/2 + 0.18 1.7 0 Notes: 1. Unused inputs must be held high or low to prevent them from floating. 2. DC input signal voltage specifies the allowable DC execution of differential input. 3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP] required for switching, where VT is the true input level and VCP is the complementary input level. 4. Differential cross-point voltage is expected to track variations of VDD and is the voltage at which the differential signal must be crossing. 0718D—04/08/05 4 TYP 2.5 0.4 MAX 2.7 VDD/2 - 0.18 0.7 2.1 V DD/2 ICS95V847 Timing Requirements TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated) CONDITIONS PARAMETER SYMBOL MIN MAX Max clock frequency Application Frequency Range Input clock duty cycle CLK stabilization 2.5V+0.2V @ 25oC freqop freqApp 2.5V+0.2V @ 25oC dtin UNITS 45 233 MHz 95 210 MHz 40 60 % 15 µs TSTAB Switching Characteristics (see note 3) PARAMETER Low-to high level propagation delay time High-to low level propagation delay time Output enable time Output disable time Period jitter Half-period jitter Input clock slew rate Output clock slew rate Cycle to Cycle Jitter1 Phase error Output to Output Skew SYMBOL CONDITION MIN TYP MAX UNITS tPLH1 CLK_IN to any output 5.5 ns tPLL1 CLK_IN to any output 5.5 ns tEN tdis PD# to any output PD# to any output 100MHz to 200MHz 100MHz to 200MHz 5 5 ns ns ps ps V/ns V/ns ps ps ps Tjit (per) t(jit_hper) t sl(i) t sl(o) Tcyc -Tcyc t(phase error) Tskew -30 -75 1 1 100MHz to 200MHz 4 -50 Notes: 1. Refers to transition on noninverting output in PLL bypass mode. 2. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle=twH/tc, where the cycle (tc) decreases as the frequency goes up. 3. Switching characteristics guaranteed for application frequency range. 4. Static phase offset shifted by design. 0718D—04/08/05 5 0 30 30 4 2.5 60 50 60 ICS95V847 Parameter Measurement Information VDD V(CLKC) R = 60Ω R = 60Ω VDD/2 V(CLKC) ICS95V847 GND Figure 1. IBIS Model Output Load VDD/2 C = 14 pF -VDD/2 ICS95V847 R = 10Ω Z = 60Ω SCOPE Z = 50Ω R = 50Ω V(TT) R = 10Ω Z = 60Ω Z = 50Ω R = 50Ω V(TT) C = 14 pF -VDD/2 -VDD/2 NOTE: V(TT) = GND Figure 2. Output Load Test Circuit YX, FBOUTC YX, FBOUTT tc(n) tc(n+1) tjit(cc) = tc(n) ± tc(n+1) Figure 3. Cycle-to-Cycle Jitter 0718D—04/08/05 6 ICS95V847 Parameter Measurement Information CLK_INC CLK_INT FB_INC FB_INT t( ) n n=N t( ) n 1 t( )= N (N is a large number of samples) Figure 4. Static Phase Offset YX # YX YX, FB_OUTC YX, FB_OUTT t(SK_O) Figure 5. Output Skew YX, FB_OUTC YX, FB_OUTT YX, FB_OUTC YX, FB_OUTT 1 fO t(jit_per) = tC(n) - 1 fO Figure 6. Period Jitter 0718D—04/08/05 7 t ( ) n+1 ICS95V847 Parameter Measurement Information YX, FB_OUTC YX, FB_OUTT t (hper_n+1) t (hper_n) 1 fo t(jit_Hper) = t(jit_Hper_n) - 1 2xfO Figure 7. Half-Period Jitter 80% 80% VID , VOD Clock Inputs and Outputs 20% 20% Rise tsl Fall tsl Figure 8. Input and Output Slew Rates 0718D—04/08/05 8 ICS95V847 c N L E1 INDEX AREA E 1 2 α D A A2 A1 -Ce In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.19 0.30 .007 .012 c 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS D 6.40 BASIC 0.252 BASIC E E1 4.30 4.50 .169 .177 0.65 BASIC 0.0256 BASIC e L 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS N a 0° 8° 0° 8° aaa -0.10 -.004 VARIATIONS N SEATING PLANE b aaa C 24 D mm. MIN 7.70 D (inch) MAX 7.90 MIN .303 Reference Doc.: JEDEC Publication 95, MO-153 10-0035 4.40 mm. Body, 0.65 mm. pitch TSSOP (0.0256 Inch) (173 mil) Ordering Information ICS95V847yGLF-T Example: ICS XXXX y G LF- T Designation for tape and reel packaging Annealed Lead Free (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 0718D—04/08/05 9 MAX .311