Integrated
Circuit
Systems, Inc.
ICS94211
Programmable System Frequency Generator for PII/III™
Features:
•
Programmable ouput frequency.
•
Programmable ouput rise/fall time.
•
Programmable PCICLK, PCICLK_F,
SDRAM skew.
•
Real time system reset output
•
Spread spectrum for EMI control typically by 7dB to 8dB,
with programmable spread percentage.
•
Watchdog timer technology to reset system
if over-clocking causes malfunction.
•
Uses external 14.318MHz crystal.
•
FS pins for frequency select
Key Specifications:
•
CPU – CPU: <175ps
•
SDRAM - SDRAM: <500ps
•
PCI – PCI: <500ps
•
CPU(early)-PCI: Min=1.0ns, Typ=2.0ns, Max=4.0ns
Block Diagram
PLL2
48MHz
24MHz
/2
X1
X2
XTAL
OSC
IOAPIC
BUFFER IN
2
13
PLL1
Spread
Spectrum
2
PCI
CLOCK
DIVDER
FS(3:0) 4
MODE
PCI_STOP#
SDATA
SCLK
94211 Rev A 03/28/01
Control
Logic
Config.
Reg.
STOP
5
REF(1:0)
SDRAM (12:0)
CPUCLK (1:0)
PCICLK (4:0)
PCICLK_F
RESET#
Pin Configuration
VDDREF
*PCI_STOP/REF0
GND
X1
X2
VDDPCI
*MODE/PCICLK_F
**FS3/PCICLK0
GND
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDPCI
BUFFER_IN
GND
SDRAM12
SDRAM11
VDDSDR
SDRAM10
SDRAM9
GND
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ICS94211
Recommended Application:
440BX/VIA Apollo Pro133/ ALI 1631 style chipset.
Output Features:
•
2 - CPUs @2.5V
•
1 - IOAPIC @ 2.5V
•
13 - SDRAM @ 3.3V
•
6 - PCI @3.3V,
•
1 - 48MHz, @3.3V
•
1 - 24MHz @ 3.3V
•
2 - REF @3.3V, 14.318MHz.
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDL
IOAPIC
REF1/FS2*
GND
CPUCLK0
CPUCLK1
VDDLCPU
RESET#
SDRAM0
GND
SDRAM1
SDRAM2
VDDSDR
SDRAM3
SDRAM4
GND
SDRAM5
SDRAM6
VDDSDR
SDRAM7
SDRAM8
VDD48
48MHz/FS0*
24MHz/FS1*
48-Pin 300mil SSOP
* Internal Pull-up Resistor of 120K to VDD
** Internal Pull-down resistor of 120K to GND
Functionality
FS3
FS2
FS1
FS0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
(MHz)
80.00
75.00
83.31
66.82
103.00
112.01
68.01
100.23
120.00
114.99
109.99
105.00
140.00
150.00
124.00
132.99
PCICLK
(MHz)
40.00
37.50
41.65
33.41
34.33
37.34
34.01
33.41
40.00
38.33
36.66
35.00
35.00
37.50
31.00
33.25
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
ICS94211
General Description
The ICS94211 is a single chip clock solution for desktop designs using the BX/Apollo Pro133/ALI 1631 style chipset. It provides all
necessary clock signals for such a system.
The ICS94211 belongs to ICS new generation of programmable system clock generators. It employs serial programming I2C interface
as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring output to output skew,
changing spread spectrum amount, changing group divider ratio and dis/enabling individual clocks. This device also has ICS
propriety 'Watchdog Timer' technology which will reset the frequency to a safe setting if the system become unstable from over
clocking.
Pin Configuration
PIN NUMBER
1
P I N NA M E
VDDREF
REF0
2
3, 9, 16, 22,
33, 39, 45
PCI_STOP#
TYPE
PWR
OUT
1
GND
IN
PWR
4
X1
IN
5
X2
OUT
VDDPCI
PWR
PCICLK_F
6, 14
7
8
13, 12, 11, 10
DESCRIPTION
Ref, XTAL power supply, nominal 3.3V
14.318 Mhz reference clock.
Halts PCICLK(0:4) clocks at logic 0 level, when input low (In mobile
mode, MODE=0)
Ground
Crystal input, has internal load cap (36pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (36pF)
Supply for PCICLK_F and PCICLK (0:4), nominal 3.3V
OUT
Free running PCI clock not affected by PCI_STOP# for power management.
MODE1, 2
IN
Pin 7 function select pin, 1=Desktop Mode, 0=Mobile Mode. Latched Input.
FS3
IN
Frequency select pin. Latched Input. Internal Pull-down to GND
PCI clock outputs. Syncheronous to CPU clocks with 1-48ns skew
(CPU early)
PCI clock outputs. Syncheronous to CPU clocks with 1-48ns skew
(CPU early)
Input to Fanout Buffers for SDRAM outputs.
PCICLK0
OUT
PCICLK (4:1)
OUT
15
BUFFER IN
17, 18, 20, 21, 28, 29,
31, 32, 34, 35, 37, 38, SDRAM (12:0)
40
19, 30, 36
VDDSDR
IN
OUT
SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin
(controlled by chipset)
PWR
Supply for SDRAM (0:12) and CPU PLL Core, nominal 3.3V.
23
SDATA
I/O
Data input for I2C serial input, 5V tolerant input
24
SCLK
IN
Clock input of I2C input, 5V tolerant input
24MHz
OUT
FS11, 2
IN
48MHz
OUT
FS01, 2
IN
25
26
24MHz output clock
Frequency select pin. Latched Input.
48MHz output clock
Frequency select pin. Latched Input
27
VDD48
PWR
41
RESET
OUT
42
VDDLCPU
PWR
Power for 24 & 48MHz output buffers and fixed PLL core.
R e a l t i m e s y s t e m r e s e t s i g n a l f o r f r e q u e n cy r a t i o c h a n g e o r w a t c h d o g
timmer timeout. This signal is active low.
Supply for CPU clocks, either 2.5V or 3.3V nominal
43
CPUCLK1
OUT
CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low
44
CPUCLK0
OUT
Free running CPU clock. Not affected by the CPU_STOP#
REF1
OUT
14.318 MHz reference clock.
46
FS21, 2
IN
Frequency select pin. Latched Input
47
I OA P I C
OUT
IOAPIC c l o c k o u t p u t . 1 4 . 3 1 8 M H z P ow e r e d b y V D D L .
48
VDDL
PWR
Supply for IOAPIC, either 2.5 or 3.3V nominal
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
2
ICS94211
General I2C serial interface information for the ICS94211
How to Write:
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending Byte 0 through Byte 20
(see Note)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
Controller (host) will send start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends Byte 0 through byte 8 (default)
ICS clock sends Byte 0 through byte X (if X(H) was
written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
How to Read:
How to Write:
Controller (Host)
Start Bit
Address D2(H)
Controller (Host)
Start Bit
Address D3(H)
ICS (Slave/Receiver)
ICS (Slave/Receiver)
ACK
Byte Count
ACK
Dummy Command Code
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
If 7H has been written to B6
ACK
Dummy Byte Count
Byte 0
Byte 0
Byte 1
Byte 1
Byte 2
Byte 2
Byte 3
Byte 3
Byte 4
Byte 4
Byte 5
Byte 5
Byte 6
Byte 6
ACK
Byte 7
Byte 18
ACK
If 12H has been written to B6
ACK
If 13H has been written to B6
ACK
If 14H has been written to B6
ACK
Stop Bit
Byte 19
ACK
Byte 20
ACK
Stop Bit
*See notes on the following page.
3
Byte18
Byte 19
Byte 20
ICS94211
Brief I2C registers description for ICS94211
Programmable System Frequency Generator
Register Name
Byte
Description
PWD Default
2
Functionality & Frequency
Select Register
0
Output frequency, hardware / I C
frequency select, spread spectrum &
output enable control register.
See individual
byte description
Active / inactive output control
registers/latch inputs read back.
See individual
byte description
Output Control Registers
1-6
Vendor ID & Revision ID
Registers
7
Byte 11 bit[7:4] is ICS vendor id - 1001.
Other bits in this register designate device
revision ID of this part.
See individual
byte description
Byte Count
Read Back Register
8
Writing to this register will configure
byte count and how many byte will be
read back. Do not write 00 H to this byte.
08 H
Watchdog Timer
Count Register
9
Writing to this register will configure the
number of seconds for the watchdog
timer to reset.
10 H
Watchdog Control Registers 10 Bit [6:0]
Watchdog enable, watchdog status and
programmable 'safe' frequency' can be
configured in this register.
000,0000
VCO Control Selection Bit
10 Bit [7]
This bit select whether the output
frequency is control by hardware/byte 0
configurations or byte 11&12
programming.
0
VCO Frequency Control
Registers
11-12
These registers control the dividers ratio
into the phase detector and thus control
the VCO output frequency.
Depended on
hardware/byte 0
configuration
Spread Spectrum Control
Registers
13-14
These registers control the spread
percentage amount.
Depended on
hardware/byte 0
configuration
Group Skews Control
Registers
15-16
Increment or decrement the group skew
amount as compared to the initial skew.
See individual
byte description
Output Rise/Fall Time
Select Registers
17-20
These registers will control the output
rise and fall time.
See individual
byte description
Notes:
1.
2.
3.
4.
5.
6.
7.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.
Readback will support standard SMBUS controller protocol. The number of bytes to readback is defined by writing to
byte 8.
When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte 14 is written
but not 15, neither byte 14 or 15 will load into the receiver.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only Block-Writes from the controller. The bytes
must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been
transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes.
The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
4
ICS94211
Byte 0: Functionality and frequency select register (Default=0)
Bit
PWD
Description
Bit7 Bit6 Bit5 Bit4 VCO/REF VCO
CPUCLK
MHz
MHz
FS3 FS2 FS1 FS0 Divider
0
0
0
0
0
447/40
160.01
80.00
0
0
0
0
1
440/42
150.00
75.00
0
0
0
1
0
512/44
166.61
83.31
0
0
0
1
1
392/42
133.64
66.82
0
0
1
0
0
446/31
206.00
103.00
0
0
1
0
1
485/31
224.01
112.01
0
0
1
1
0
513/54
136.02
68.01
0
0
1
1
1
518/37
200.45
100.23
0
1
0
0
0
352/21
240.00
120.00
0
1
0
0
1
514/32
229.99
114.99
0
1
0
1
0
507/33
219.98
109.99
0
1
0
1
1
484/33
210.00
105.00
0
1
1
0
0
352/18
280.00
140.00
0
1
1
0
1
440/21
300.00
150.00
0
1
1
1
0
433/25
247.99
124.00
0
1
1
1
1
483/26
265.99
132.99
1
0
0
0
0
396/21
270.00
135.00
1
0
0
0
1
345/19
259.99
129.99
1
0
0
1
0
440/25
252.00
126.00
1
0
0
1
1
478/29
236.00
118.00
1
0
1
0
0
486/30
231.95
115.98
1
0
1
0
1
491/37
190.01
95.00
1
0
1
1
0
440/35
180.00
90.00
1
0
1
1
1
463/39
169.98
85.01
1
1
0
0
0
371/16
332.00
166.00
1
1
0
0
1
447/20
320.01
160.01
1
1
0
1
0
433/20
309.99
154.99
1
1
0
1
1
310/15
295.91
147.95
1
1
1
0
0
469/23
291.97
145.98
1
1
1
0
1
362/18
287.95
143.98
1
1
1
1
0
476/24
283.98
141.99
1
1
1
1
1
347/18
276.02
138.01
0-Frequency is selected by hardware select, latched inputs
1- Frequency is selected by Bit 2,7:4
0- Normal
1- Spread spectrum enable ± 0.35% Center Spread
0- Running
1- Tristate all outputs
Bit2
Bit
(2,7:4)
Bit 3
Bit 1
Bit 0
PCICLK
MHz
40.00
37.50
41.65
33.41
34.33
37.34
34.01
33.41
40.00
38.33
36.66
35.00
35.00
37.50
31.00
33.25
33.75
32.50
31.50
39.33
38.66
31.67
30.00
28.34
41.50
40.00
38.75
36.99
36.50
35.99
35.50
34.50
Note 1
0
1
0
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
5
ICS94211
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
BIT
PIN#
PWD
BIT
PIN#
PWD
Bit 7
-
X
Latched FS2#
DESCRIPTION
Bit 7
-
1
(Reserved)
Bit 6
-
1
(Reserved)
Bit 6
7
1
PCICLK_F
DESCRIPTION
Bit 5
-
1
(Reserved)
Bit 5
-
1
(Reserved)
Bit 4
-
1
(Reserved)
Bit 4
13
1
PCICLK4
Bit 3
17
1
SDRAM12
Bit 3
12
1
PCICLK3
Bit 2
-
1
(Reserved)
Bit 2
11
1
PCICLK2
Bit 1
43
1
CPUCLK1
Bit 1
10
1
PCICLK1
Bit 0
44
1
CPUCLK0
Bit 0
8
1
PCICLK0
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
Byte 4: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
BIT
PIN#
PWD
Bit 7
-
1
(Reserved)
DESCRIPTION
Bit 7
-
1
Bit 6
-
X
Latched FS0#
Bit 6
-
1
(Reserved)
-
1
(Reserved)
BIT
PIN# PWD
DESCRIPTION
(Reserved)
Bit 5
26
1
48MHz
Bit 5
Bit 4
25
1
24 MHz
Bit 4
-
1
(Reserved)
1
(Reserved)
Bit 3
-
X
Latched FS1#
Bit 2
-
1
(Reserved)
1
SDRAM (8:11)
Bit 1
-
X
Latched FS3#
1
SDRAM (4:7)
Bit 0
-
1
(Reserved)
1
SDRAM (0:3)
Bit 3
Bit 2
Bit 1
Bit 0
28, 21,
20, 18
34, 32,
31, 29,
40, 38,
37, 35
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT
PIN# PWD
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
DESCRIPTION
Bit 7
-
1
(Reserved)
Bit 6
-
1
(Reserved)
Bit 5
-
1
(Reserved)
Bit 4
47
1
IOAPIC
Bit 3
-
1
(Reserved)
Bit 2
-
1
(Reserved)
Bit 1
46
1
REF1
Bit 0
2
1
REF0
PIN#
-
PWD
0
0
0
0
0
1
1
0
DESCRIPTION
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
Note: This is an unused register writing to this register will not
affect device performance or functinality.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
6
ICS94211
Byte 7: Vendor ID and Revision ID Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
0
0
1
X
X
X
X
X
Byte 8: Byte Count and Read Back Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Description
Vendor ID
Vendor ID
Vendor ID
Revision ID
Revision ID
Revision ID
Revision ID
Revision ID
Byte 9: VCO Control Selection Bit &
Watchdog Timer Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
0
0
0
0
0
0
0
0
PWD
0
0
0
0
1
0
0
0
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 10: Watchdog Timer Count Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Description
0=Hw/B0 freq / 1=B14&15 freq
WD Enable 0=disable / 1=enable
WD Status 0=normal / 1=alarm
WD Safe Frequency, Byte 0 bit 2
WD Safe Frequency, FS3
WD Safe Frequency, FS2
WD Safe Frequency, FS1
WD Safe Frequency, FS0
PWD
0
0
0
1
0
0
0
0
Description
The decimal representation of these
8 bits correspond to 290ms or 1ms
the watchdog timer will wait before
it goes to alarm mode and reset the
frequency to the safe setting. Default
at power up is 16X 290ms = 4.6
seconds.
Note: FS values in bit [0:4] will correspond to Byte 0 FS
values. Default safe frequency is same as 00000 entry in
byte0.
Byte 12: VCO Frequency Control Register
Byte 11: VCO Frequency Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
X
X
X
X
X
X
X
X
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Description
VCO Divider Bit0
REF Divider Bit6
REF Divider Bit5
REF Divider Bit4
REF Divider Bit3
REF Divider Bit2
REF Divider Bit1
REF Divider Bit0
PWD
X
X
X
X
X
X
X
X
Description
VCO Divider Bit8
VCO Divider Bit7
VCO Divider Bit6
VCO Divider Bit5
VCO Divider Bit4
VCO Divider Bit3
VCO Divider Bit2
VCO Divider Bit1
Note: The decimal representation of these 9 bits (Byte 12 bit
[7:0] & Byte 11 bit [7] ) + 8 is equal to the VCO divider value.
For example if VCO divider value of 36 is desired, user need
to program 36 - 8 = 28, namely, 0, 00011100 into byte 12 bit
& byte 11 bit 7.
Note: The decimal representation of these 7 bits (Byte 11
[6:0]) + 2 is equal to the REF divider value .
Notes:
1. PWD = Power on Default
7
ICS94211
Byte 13: Spread Sectrum Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
X
X
X
X
X
X
X
X
Byte 14: Spread Sectrum Control Register
Description
Spread Spectrum Bit7
Spread Spectrum Bit6
Spread Spectrum Bit5
Spread Spectrum Bit4
Spread Spectrum Bit3
Spread Spectrum Bit2
Spread Spectrum Bit1
Spread Spectrum Bit0
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
X
X
X
X
X
X
X
X
Description
Reserved
Reserved
Reserved
Spread Spectrum Bit12
Spread Spectrum Bit11
Spread Spectrum Bit10
Spread Spectrum Bi 9
Spread Spectrum Bit8
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread spectrum.
Incorrect spread percentage may cause system failure.
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread spectrum.
Incorrect spread percentage may cause system failure.
Byte 15: Output Skew Control
Byte 16: Output Skew Control
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
Description
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PCICLK_F Skew Control
PCICLK [0:4} Skew Control
SDRAM_F Skew Control
SDRAM [0:7} Skew Control
Byte 17: Output Rise/Fall Time Select Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
PWD
Description
SDRAM [8:11] Skew Control
X
X
X
X
X
X
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 18: Output Rise/Fall Time Select Register
Description
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CPUCLK_F: Slew Rate Control
CPUCLK1: Slew Rate Control
SDRAM_F: Slew Rate Control
SDRAM [0:11] Slew Rate Control
PWD
Description
PCI {0:4]: Slew Rate Control
PCI_F Slew Rate Control
48MHz: Slew Rate Control
24MHz: Slew Rate Control
Notes:
1. PWD = Power on Default
2. The power on default for byte 13-20 depends on the harware (latch inputs FS[0:4]) or I2C (Byte 0 bit [1:7]) setting. Be sure to read
back and re-write the values of these 8 registers when VCO frequency change is desired for the first pass.
8
ICS94211
Byte 19: Reserved Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
X
X
X
X
X
X
X
X
Byte 20: Reserved Register
Description
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PWD
X
X
X
X
X
X
X
X
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Note: Byte 19 and 20 are reserved registers, these are
unused registers writing to these registers will not
affect device performance or functinality.
VCO Programming Constrains
VCO Frequency ...................... 150MHz to 500MHz
VCO Divider Range ................ 8 to 519
REF Divider Range ................. 2 to 129
Phase Detector Stability .......... 0.3536 to 1.4142
Useful Formula
VCO Frequency = 14.31818 x VCO/REF divider value
Phase Detector Stabiliy = 14.038 x (VCO divider value)-0.5
To program the VCO frequency for over-clocking.
0. Before trying to program our clock manually, consider using ICS provided software utilities for easy programming.
1. Select the frequency you want to over-clock from with the desire gear ratio (i.e. CPU:SDRAM:3V66:PCI ratio) by writing
to byte 0, or using initial hardware power up frequency.
2. Write 0001, 1001 (19H) to byte 8 for readback of 21 bytes (byte 0-20).
3. Read back byte 11-20 and copy values in these registers.
4. Re-initialize the write sequence.
5. Write a '1' to byte 9 bit 7 and write to byte 11 & 12 with the desired VCO & REF divider values.
6. Write to byte 13 to 20 with the values you copy from step 3. This maintains the output spread, skew and slew rate.
7. The above procedure is only needed when changing the VCO for the 1st pass. If VCO frequency needed to be changed
again, user only needs to write to byte 11 and 12 unless the system is to reboot.
Note:
1. User needs to ensure step 3 & 7 is carried out. Systems with wrong spread percentage and/or group to group skew relation
programmed into bytes 13-16 could be unstable. Step 3 & 7 assure the correct spread and skew relationship.
2. If VCO, REF divider values or phase detector stability are out of range, the device may fail to function correctly.
3. Follow min and max VCO frequency range provided. Internal PLL could be unstable if VCO frequency is too fast or too slow.
Use 14.31818MHz x VCO/REF divider values to calculate the VCO frequency (MHz).
4. ICS recommends users, to utilize the software utility provided by ICS Application Engineering to program the VCO frequency.
5. Spread percent needs to be calculated based on VCO frequency, spread modulation frequency and spreadamount desired. See
Application note for software support.
9
ICS94211
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient Operating Temperature . . . . . . . . . . . . . .
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .
7.0 V
GND –0.5 V to VDD +0.5 V
0°C to +70°C
115°C
–65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections
of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Input High Voltage
VIH
2
VSS-0.3
Input Low Voltage
VIL
VIN = VDD
-5
Input High Current
IIH
VIN = 0 V; Inputs with no pull-up resistors
-5
IIL1
Input Low Current
VIN = 0 V; Inputs with pull-up resistors
-200
IIL2
CL = max cap loads;
124
IDD3.3OP
Operating Supply
CPU=66-133 MHz, SDRAM=100 MHz
CPU=133 MHz, SDRAM=133 MHz
135
Current
CL = max cap loads;
IDD2.5OP
18
IDD3.3PD
CL = 0 pF; Input address to VDD or GND
Powerdown Current
Input Frequency
Pin Inductance
Input Capacitance1
1
Transition time
1
Settling time
Clk Stabilization1
Delay1
Skew1
1
MAX
VDD+0.3
0.8
5
UNITS
V
V
µA
µA
350
500
70
600
mA
7
5
6
45
µA
MHz
nH
pF
pF
pF
To 1st crossing of target frequency
3
ms
Ts
From 1st crossing to 1% target frequency
3
ms
TSTAB
tPZH,tPZL
tPHZ,tPLZ
From VDD = 3.3 V to 1% target frequency
Output enable delay (all outputs)
Output disable delay (all outputs)
VT = 1.5V; VTL=1.25V
3
10
10
ms
ns
ns
4
ns
Fi
Lpin
CIN
COUT
CINX
VDD = 3.3 V
Ttrans
tcpu-pci
14.318
Logic Inputs
Output pin capacitance
X1 & X2 pins
Guaranteed by design, not 100% tested in production.
10
27
1
1
2.45
ICS94211
Electrical Characteristics - CPU
TA = 0 - 70º C;VDD = 3.3V; VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
1
Output Impedance
RDSP2B
Vo=VDD*(0.5)
13.5
1
Output Impedance
RDSN2B
Vo=VDD*(0.5)
13.5
Output High Voltage
VOH2B
IOH = -1 mA
2
Output Low Voltage
VOL2B
IOL = 1 mA
VOH@MIN = 1 V
IOH2B
Output High Current
VOH@MAX = 2.375V
-27
27
VOL@MIN = 1.2 V
IOL2B
Output Low Current
VOL@MAX =0.3V
Rise Time1
tr2B
VOL = 0.4 V, VOH = 2.0 V
0.4
1
Fall Time
tf2B
VOH = 2.0 V, VOL = 0.4 V
0.4
Duty Cycle1
dt2B
VT = 1.25 V
45
1
Skew
tsk2B
VT = 1.25 V
1
tjcyc-cyc2B
VT = 1.25 V, CPU 66, SDRAM 100
Jitter, Cycle-to-cycle
TYP
15
16.5
2.48
0.04
-60
-7
63
20
1.2
0.9
46.9
12.7
150
MAX UNITS
45
Ω
45
Ω
V
0.4
V
-27
mA
30
1.6
1.6
55
175
250
mA
ns
ns
%
ps
ps
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCI
TA = 0 - 70º C; VDD = 3.3 V +/-5%, CL = 40 pF for PCI0-1, CL = 10 - 30 pF for other PCIs (unless otherwise stated)
PARAMETER
Output Impedance1
Output Impedance1
SYMBOL
RDSP1
RDSN1
Output High Voltage
Output Low Voltage
VOH1
VOL1
Output High Current
IOH1
Output Low Current
IOL1
Rise Time1
tr1
VOL = 0.4 V, VOH = 2.4 V,
0.5
1.5
2
ns
1
tf1
VOL = 2.4 V, VOH = 0.4 V, PCI0-3
0.5
1.5
2
ns
dt1
tsk1
VT = 1.5 V
VT = 1.5 V
45
52.5
49
55
500
%
ps
tjcyc-cyc1
VT = 1.5 V
200
500
ps
Fall Time
Duty Cycle
1
1
Skew
Jitter, cycle-to-cycle1
1
CONDITIONS
Vo=VDD*(0.5)
Vo=VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
VOH@MIN = 1 V
VOH@MAX = 3.135V
VOL@MIN = 1.95 V
VOL@MAX =0.4V
MIN
12
12
2.4
TYP
-33
30
MAX UNITS
55
Ω
55
Ω
V
0.55
V
-33
mA
38
Guaranteed by design, not 100% tested in production.
11
mA
ICS94211
Electrical Characteristics - IOAPIC
TA = 0 - 70º C; VDD = 3.3V; VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output Impedance1
Output Impedance1
SYMBOL
RDSP4B
RDSN4B
Output High Voltage
Output Low Voltage
VOH4B
VOL4B
Output High Current
IOH4B
Output Low Current
IOL4B
Rise Time1
tr4B
VOL = 0.4 V, VOH = 2.0 V
0.4
0.7
1.6
ns
1
tf4B
VOH = 2.0 V, VOL = 0.4 V
0.4
1.1
1.6
ns
dt4B
VT = 1.25 V
45
53.7
55
%
MIN
10
10
2.4
TYP
Fall Time
Duty Cycle1
1
CONDITIONS
Vo=VDD*(0.5)
Vo=VDD*(0.5)
IOH = -5.5 mA
IOL = 9 mA
VOH@MIN = 1.4 V
VOH@MAX = 2.5V
VOL@MIN = 1.0 V
VOL@MAX =0.2V
MIN
9
9
2
TYP
-36
36
MAX UNITS
3
Ω
30
Ω
V
0.4
V
-21
mA
31
mA
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70º C; VDD = 3.3 V +/-5%, CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
Output Impedance1
Output Impedance1
SYMBOL
RDSP3
RDSN3
Output High Voltage
Output Low Voltage
VOH3
VOL3
Output High Current
IOH3
Output Low Current
IOL3
Rise Time1
tr3
VOL = 0.4 V, VOH = 2.4 V
0.4
0.8
1.6
ns
1
tf3
VOH = 2.4 V, VOL = 0.4 V
0.4
0.8
1.6
ns
dt3
VT = 1.5 V
45
51.7
55
%
tsk3
Tprop
VT = 1.5 V
VT = 1.5 V
166
3.1
250
5
ps
ns
Fall Time
Duty Cycle
1
1
Skew
Propagation Delay
1
CONDITIONS
Vo=VDD*(0.5)
Vo=VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
VOH@MIN = 2 V
VOH@MAX = 3.135V
VOL@MIN = 1 V
VOL@MAX =0.4V
-54
54
MAX UNITS
24
Ω
24
Ω
V
0.4
V
-46
mA
53
Guaranteed by design, not 100% tested in production.
12
mA
ICS94211
Electrical Characteristics - REF, 24_48MHz, 48MHz
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
Output Impedance1
RDSP5
VO = VDD*(0.5)
Output Impedance1
RDSN5
VO = VDD*(0.5)
1
IOH = -1 mA
IOL = 1 mA
VOH @ MIN = 1.0 V
VOH @ MAX = 3.135 V
VOL @ MIN = 1.95 V
VOL @ MAX = 0.4 V
MIN
20
20
TYP
2.4
Output High Voltage
Output Low Voltage
VOH5
VOL5
Output High Current
IOH5
Output Low Current
IOL5
Rise Time1
tr5
VOL = 0.4 V, VOH = 2.4 V
0.4
Fall Time1
tf5
dt5
VOH = 2.4 V, VOL = 0.4 V
0.4
Duty Cycle1
VT = 1.5 V
45
Jitter, cycle-to-cycle1
tjcyc-cyc5
VT = 1.5 V, Fixed clocks
VT = 1.5 V, Ref clocks
200
1032
-29
29
MAX UNITS
60
Ω
60
Ω
V
0.4
V
-23
mA
27
Guaranteed by design, not 100% tested in production.
13
2
mA
4
ns
2
4
ns
53
55
%
500
1250
ps
ICS94211
Shared Pin Operation Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.
The I/O pins designated by (input/output) on the ICS94211
serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage) that
is present on these pins at this time is read and stored into a 5bit internal data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In this
mode the pins produce the specified buffered clocks to external
loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K Via to Gnd
Device
Pad
8.2K Clock trace to load
Series Term. Res.
Fig. 1
14
ICS94211
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS94211. It is used to turn off the PCICLK clocks for low power operation. PCI_STOP#
is synchronized by the ICS94211 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# high pulse) is at least
10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK clock on
latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94211 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS94211.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
15
ICS94211
c
N
L
E1
INDEX
AREA
E
1 2
h x 45°
D
A
In Millimeters
SYMBOL COMMON DIMENSIONS
MIN
MAX
A
2.41
2.80
A1
0.20
0.40
b
0.20
0.34
c
0.13
0.25
D
SEE VARIATIONS
E
10.03
10.68
E1
7.40
7.60
e
0.635 BASIC
h
0.38
0.64
L
0.50
1.02
N
SEE VARIATIONS
0°
8°
α
A1
-Ce
b
SEATING
PLANE
.10 (.004) C
N
48
In Inches
COMMON DIMENSIONS
MIN
MAX
.095
.110
.008
.016
.008
.0135
.005
.010
SEE VARIATIONS
.395
.420
.291
.299
0.025 BASIC
.015
.025
.020
.040
SEE VARIATIONS
0°
8°
VARIATIONS
D mm.
MIN
MAX
15.75
16.00
D (inch)
MIN
.620
MAX
.630
R ef erence D o c .: J E D E C P ub lic at io n 9 5, M O -118
10 -0 0 3 4
Ordering Information
ICS94211yF-T
Example:
ICS XXXX y F - T
Designation for tape and reel packaging
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS, AV = Standard Device
16
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.