ICS ICS950227

ICS950227
Integrated
Circuit
Systems, Inc.
Programmable Timing Control Hub™ for P4™
Recommended Application:
CK-408 clock Intel® 845 with P4 processor.
Output Features:
•
3 Differential CPU Clock Pairs @ 3.3V
•
7 PCI (3.3V) @ 33.3MHz
•
3 PCI_F (3.3V) @ 33.3MHz
•
1 USB (3.3V) @ 48MHz
•
1 DOT (3.3V) @ 48MHz
•
1 REF (3.3V) @ 14.318MHz
•
5 3V66 (3.3V) @ 66.6MHz
•
1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
Features/Benefits:
•
Programmable output frequency.
•
Programmable output divider ratios.
•
Programmable output rise/fall time.
•
Programmable output skew.
•
Programmable spread percentage for EMI control.
•
Watchdog timer technology to reset system
if system malfunctions.
•
Programmable watch dog safe frequency.
•
Support I2C Index read/write and block read/write
operations.
•
Uses external 14.318MHz crystal.
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
ICS950227
VDDREF
X1
X2
GND
PCICLK_F0
PCICLK_F1
PCICLK_F2
VDDPCI
GND
PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
PCICLK6
VDD3V66
GND
3V66_2
3V66_3
3V66_4
3V66_5
*PD#
VDDA
GND
Vtt_PWRGD#
REF
FS1
FS0
CPU_STOP#*
CPUCLKT0
CPUCLKC0
VDDCPU
CPUCLKT1
CPUCLKC1
GND
VDDCPU
CPUCLKT2
CPUCLKC2
MULTSEL0*
IREF
GND
FS2
48MHz_USB
48MHz_DOT
VDD48
GND
3V66_1/VCH_CLK
PCI_STOP#*
3V66_0
VDD3V66
GND
SCLK
SDATA
56-Pin 300-mil SSOP
Key Specifications:
•
CPU Output Jitter <150ps
•
3V66 Output Jitter <250ps
•
CPU Output Skew <100ps
* These inputs have 150K internal pull-up resistor to VDD.
Block Diagram
Frequency Table
PLL2
48MHz_USB
48MHz_DOT
X1
XTAL
OSC
3V66_1/VCH_CLK
REF
PLL1
Spread
Spectrum
WDEN
PD#
CPU_STOP#
PCI_STOP#
MULTSEL0
FS (2:0)
SDATA
SCLK
Vtt_PWRGD#
0641D—07/03/03
CPU
DIVDER
3
3
PCI
DIVDER
Stop
7
3
Control
Logic
Stop
3V66
DIVDER
5
CPUCLKT (2:0)
CPUCLKC (2:0)
PCICLK (6:0)
PCICLK_F (2:0)
3V66 (5:2,0)
Config.
Reg.
I REF
FS2 FS1 FS0
CPU
(MHz)
3V66
(MHz)
66Buff[2:0]
3V66[4:2]
(MHz)
PCI_F
PCI
(MHz)
0
0
0
66.66
66.66
66.66
33.33
0
0
1
100.00
66.66
66.66
33.33
0
1
0
200.00
66.66
66.66
33.33
0
1
1
133.33
66.66
66.66
33.33
Mid
0
0
Tristate
Tristate
Tristate
Tristate
Mid
0
1
TCLK/2
TCLK/4
TCLK/4
TCLK/8
Mid
1
0
Reserved Reserved Reserved
Reserved
Mid
1
1
Reserved Reserved Reserved
Reserved
ICS950227
Integrated
Circuit
Systems, Inc.
Pin Description
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1, 8, 14, 19, 26,
32, 37, 46, 50
VDD
PWR
2
X1
X2 Cr ystal
14.318MHz Cr ystal input
Input
3
X2
X1 Cr ystal
14.318MHz Cr ystal output
Output
7, 6, 5
PCICLK_F (2:0)
OUT
Free running PCI clock not affected by PCI_STOP#
for power management.
4, 9, 15, 20, 27,
31, 36, 41, 47
GND
PWR
Ground pins for 3.3V supply
18, 17, 16, 13,
12,11, 10
PCICLK (6:0)
OUT
PCI clock outputs
24, 23, 22, 21
3V66 (5:2)
OUT
66MHz reference clocks, from internal VCO
25
PD#
IN
Invokes power-down mode. Active Low.
3.3V power supply
28
Vtt_PWRGD#
IN
This 3.3V LVTTL input is a level sensitive strobe used to
determine when FS(2:0) and MULTISEL0 inputs are valid
and are ready to be sampled
(active low)
29
SDATA
I/O
Data pin for I2C circuitr y 5V tolerant
30
SCLK
IN
Clock pin of I2C circuitr y 5V tolerant
33
3V66_0
OUT
66MHz reference clocks, from internal VCO
Halts PCICLK clocks at logic 0 level, when input low except
PCICLK_F which are free running
34
PCI_STOP#
IN
35
3V66_1/VCH_CLK
OUT
3.3V output selectable through I2C to be 66MHz from internal VCO
or
48MHz (non-SSC)
38
48MHz_DOT
OUT
48MHz output clock for DOT
39
48MHz_USB
OUT
40
FS2
IN
48MHz output clock for USB
42
I REF
OUT
This pin establishes the reference current for the CPUCLK pairs.
This pin requires a fixed precision resistor tied to ground in order to
establish the appropriate current.
43
MULTSEL0
IN
3.3V LVTTL input for selecting the current multiplier for CPU outputs
44, 48, 51
CPUCLKC (2:0)
OUT
"Complementor y" clocks of differential pair CPU outputs. These are
current outputs and external resistors are required for voltage bias.
45, 49, 52
CPUCLKT (2:0)
OUT
"True" clocks of differential pair CPU outputs. These are current
outputs and external resistors are required for voltage bias.
53
CPU_STOP#
IN
55, 54
FS (1:0)
IN
56
REF
OUT
Special 3.3V input for Mode selection, cannot be logic 1
Halts CPUCLK clocks at logic 0 level, when input low
Frequency select pins
14.318MHz reference clock.
Power Groups
(Analog)
(Digital)
VDDA = Analog Core PLL1
VDDREF = REF, Xtal
VDD48 = 48MHz, PLL
VDDPCI
VDD3V66
VDDCPU
0641D—07/03/03
2
ICS950227
Integrated
Circuit
Systems, Inc.
Truth Table
CPU
(MHz)
3V66 (5:0)
(MHz)
PCI_F
PCI
(MHz)
REF0
(MHz)
USB/DOT
(MHz)
0
66.66
66.66
33.33
14.318
48.00
1
100.00
66.66
33.33
14.318
48.00
0
200.00
66.66
33.33
14.318
48.00
FS2
FS1
FS0
0
0
0
0
0
1
0
1
1
133.33
66.66
33.33
14.318
48.00
Mid
0
0
Tristate
Tristate
Tristate
Tristate
Tristate
TCLK/2
TCLK/4
Mid
0
1
TCLK/8
TCLK
TCLK/2
Mid
1
0
Reserved Reserved
Reserved
Reserved
Reserved
Mid
1
1
Reserved Reserved
Reserved
Reserved
Reserved
Maximum Allowed Current
Condition
Max 3.3V supply consumption
Max discrete cap loads,
Vdd = 3.465V
All static inputs = Vdd or GND
Powerdown Mode
(PWRDWN# = 0)
40mA
Full Active
360mA
Host Swing Select Functions
MULTISEL0
Board Target
Trace/Term Z
Reference R,
Iref =
VDD/(3*Rr)
Output
Current
Voh @ Z
1
50 ohms
Rr = 475 1%,
Iref = 2.32mA
Ioh = 6* I REF
0.7V @ 50
0641D—07/03/03
3
ICS950227
Integrated
Circuit
Systems, Inc.
General I2C serial interface information
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
Controller (host) will need to acknowledge each
byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D2(H)
WR
WRite
Controller (Host)
T
starT bit
Slave Address D2(H)
WR
WRite
ICS (Slave/Receiver)
ICS (Slave/Receiver)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
Byte N + X - 1
ACK
X Byte
ACK
P
stoP bit
Byte N + X - 1
N
P
0641D—07/03/03
4
Not acknowledge
stoP bit
ICS950227
Integrated
Circuit
Systems, Inc.
2
I C Table: Frequency Select Register
Byte 0
Pin #
-
Bit 7
-
Bit 6
Name
Control Function
Frequency H/W IIC
SPREAD ENABLE
Select
CENTER/DOWNSP CENTER/DOWNSPRE
READ SELECT
AD SELECT
3V66/VCH SELECT 48MHz/66.66MHz SEL
Bit 5
35
Bit 4
53
CPU_STOP#
Bit 3
34
PCI_STOP#
HW/SW SELECT
Bit 2
40
FS2
Bit 1
55
FS1
Bit 0
54
FS0
CPU STOP Read Back
Freq Select Bit 3
Type
RW
RW
RW
1
PWD
OFF
ON
0
DOWN
SPREAD
66.66MHz
CENTER
SPREAD
48.00MHz
READBACK
R
RW/R
Freq Select 2 Read
Back
Freq Select 1 Read
Back
Freq Select 0 Read
Back
0
PCI STOP
0
0
X
PCI
RUNNING
R
1
X
READBACK
R
X
R
X
2
I C Table: Spreading and Device Behavior Control Register
Byte 1
Pin #
Name
Bit 7
43
MULTSEL0
Bit 6
-
WD ALARM
Bit 5
45, 44
CPU2/CPUC2
Bit 4
49, 48
CPU1/CPUC1
Bit 3
52, 51
CPU0/CPUC0
Bit 2
Bit 1
Bit 0
45, 44
49, 48
52, 51
CPU2/CPUC2
CPU1/CPUC1
CPU0/CPUC0
Control Function
MULTSEL0
READBACK
Watchdog Alarm Read
Back
CPU FREE-RUN NING
CONTROL
Type
0
1
PWD
R
READBACK
X
R
NO ALARM ALARM SET
0
RW
STOPPABLE FREE-RUN
0
RW
STOPPABLE FREE-RUN
0
RW
STOPPABLE FREE-RUN
0
Output Control
Output Control
Output Control
RW
RW
RW
Disable
Disable
Disable
Enable
Enable
Enable
1
1
1
Control Function
Reserved
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Disable
Disable
Disable
Disable
Disable
Disable
Disable
1
Enable
Enable
Enable
Enable
Enable
Enable
Enable
PWD
0
1
1
1
1
1
1
1
Control Function
Output Control
Output Control
Type
RW
RW
0
Disable
Disable
1
Enable
Enable
PWD
1
1
2
I C Table: Output Control Register
Byte 2
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Pin #
18
17
16
13
12
11
10
7
6
5
4
3
2
1
0
Name
Reserved
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
2
I C Table: Output Control Register
Byte 3
Bit 7
Bit 6
38
39
Pin #
Name
48MHz_DOT
48MHz_USB
Bit 5
7
PCIF2
Bit 4
6
PCIF1
Bit 3
5
PCIF0
Bit 2
Bit 1
Bit 0
7
6
5
PCICLK_F2
PCICLK_F1
PCICLK_F0
CPU FREE-RUN NING
CONTROL
Output Control
Output Control
Output Control
RW
FREE-RUN STOPPABLE
0
RW
FREE-RUN STOPPABLE
0
RW
FREE-RUN STOPPABLE
0
RW
RW
RW
0641D—07/03/03
5
Disable
Disable
Disable
Enable
Enable
Enable
1
1
1
ICS950227
Integrated
Circuit
Systems, Inc.
2
I C Table: Output Control Register
Byte 4
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Pin #
33
35
24
23
22
21
7
6
5
4
3
2
1
0
Name
RESERVED
RESERVED
3V66_0
3V66_1/VHC_CLK
3V66_5
3V66_4
3V66_3
3V66_2
Control Function
RESERVED
RESERVED
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Type
`
RW
RW
RW
RW
RW
RW
0
Disable
Disable
Disable
Disable
Disable
Disable
1
Enable
Enable
Enable
Enable
Enable
Enable
PWD
0
0
1
1
1
1
1
1
Type
RW
0
-
1
-
PWD
0
0
0
0
0
2
I C Table: Output Control and Fix Frequecy Register
Byte 5
Bit
Bit
Bit
Bit
Bit
7
6
5
4
3
Bit 2
-
Pin #
Name
RESERVED
RESERVED
RESERVED
RESERVED
Control Function
-
38
48MHz_DOT
DOT CLOCK EDGE
RATE CONTROL
39
48MHz_USB
USB EDGE RATE
CONTROL
RW
RW
Bit 1
Bit 0
RW
00= MEDIUM (DEFAULT)
10= LOW
01= HIGH
00= MEDIUM (DEFAULT)
01= LOW
10= HIGH
0
0
0
2
I C Table: Vendor & Revision ID Register
Byte 6
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Pin #
-
7
6
5
4
3
2
1
0
Name
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
Control Function
Name
Control Function
REVISION ID
VENDOR ID
Type
R
R
R
R
R
R
R
R
0
-
1
-
PWD
1
1
1
1
1
1
1
1
Type
R
R
R
R
R
R
R
R
0
-
1
-
PWD
0
0
0
0
0
0
0
1
2
I C Table: DEVICE ID
Byte 7
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
Pin #
-
0641D—07/03/03
6
ICS950227
Integrated
Circuit
Systems, Inc.
2
I C Table: Byte Count Register
Byte 8
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Pin #
-
7
6
5
4
3
2
1
0
Name
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
Control Function
Writing to this register
will configure how
many bytes will be read
back, default is 0F = 15
bytes.
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
1
-
PWD
0
0
0
0
1
1
1
1
Type
RW
RW
RW
RW
RW
RW
RW
0
-
1
-
PWD
0
0
0
0
1
0
1
RW
-
-
0
Type
0
1
PWD
RW
RW
RW
RW
RW
Latched
Input
OFF
Latched
FS/Byte0
-
IIC Prog.
B(11:17)
ON
WD B10
b(4:0)
-
0
0
0
0
0
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
1
-
PWD
X
X
X
X
X
X
X
X
2
I C Table: Watchdog Timer Register
7
6
5
4
3
2
1
Byte 9
-
Name
RESERVED
RESERVED
RESERVED
WD4
WD3
WD2
WD1
Bit 0
-
WD0
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Pin #
Control Function
RESERVED
RESERVED
RESERVED
These bits represent
X*290ms the watchdog
timer will wait before it
goes to alarm mode.
Default is10X 290ms
=2.9seconds
2
I C Table: VCO Control Select Bit & WD Timer Control Register
Byte 10
Pin #
Name
Bit 7
-
Bit 6
-
WDEN
Bit 5
-
WDFSEN
Bit
Bit
Bit
Bit
Bit
-
WD SS EN
WD MultSEL
WD FS2
WD FS1
WD FS0
4
3
2
1
0
M/NEN
Control Function
M/N Programming
Enable
Watchdog Enable
WD Safe Frequency
Mode
Writing to these bit will
configure the safe
frequency configuration
RW
RW
RW
0
0
0
2
I C Table: VCO Frequency Control Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Byte 11
7
6
5
4
3
2
1
0
Pin #
-
Name
N Div8
M Div6
M Div5
M Div4
M Div3
M Div2
M Div1
M Div0
Control Function
N Divider Bit 8
The decimal
representation of M Div
(6:0) is equal to
reference divider value.
Default at power up =
latch-in or Byte 0 Rom
table.
0641D—07/03/03
7
ICS950227
Integrated
Circuit
Systems, Inc.
2
I C Table: VCO Frequency Control Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Byte 12
7
6
5
4
3
2
1
0
Pin #
-
Name
N Div7
N Div6
N Div5
N Div4
N Div3
N Div2
N Div1
N Div0
Control Function
The decimal
representation of N Div
(8:0) is equal to VCO
divider value. Default
at power up = latch-in
or Byte 0 Rom table.
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
1
-
PWD
X
X
X
X
X
X
X
X
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
1
-
PWD
X
X
X
X
X
X
X
X
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
1
-
PWD
0
0
X
X
X
X
X
X
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
1
-
PWD
0
0
0
0
X
X
X
X
2
I C Table: Spread Spectrum Control Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Byte 13
7
6
5
4
3
2
1
0
Pin #
-
Name
SSP7
SSP6
SSP5
SSP4
SSP3
SSP2
SSP1
SSP0
Control Function
These Spread
Spectrum bits will
program the spread
pecentage. It is
recommended to use
ICS Spread % table for
spread programming.
2
I C Table: Spread Spectrum Control Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Byte 14
7
6
5
4
3
2
1
0
Pin #
-
Name
Reserved
Reserved
SSP13
SSP12
SSP11
SSP10
SSP9
SSP8
Control Function
Reserved
Reserved
It is recommended to
use ICS Spread %
table for spread
programming.
2
I C Table: Output Divider Control Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Byte 15
7
6
5
4
3
2
1
0
Pin #
-
Name
Reserved
Reserved
Reserved
Reserved
CPU Div3
CPU Div2
CPU Div1
CPU Div0
Control Function
Reserved
Reserved
Reserved
Reserved
CPU divider ratio can
be configured via these
4 bits individually.
See Table 3: Divider Ratio
Combination Table 2-3-5-7
2
I C Table: Output Divider Control Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Byte 16
7
6
5
4
3
2
1
0
Pin #
-
Name
Reserved
Reserved
Reserved
Reserved
3V66 Div3
3V66 Div2
3V66 Div1
3V66 Div0
Control Function
Reserved
Reserved
Reserved
Reserved
3V66 divider ratio can
be configured via these
4 bits individually.
0641D—07/03/03
8
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
1
-
See Table 3: Divider Ratio
Combination Table
PWD
0
0
0
0
X
X
X
X
ICS950227
Integrated
Circuit
Systems, Inc.
2
I C Table: Output Divider Control Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Byte 17
7
6
5
4
3
2
1
0
Pin #
-
Name
Reserved
Reserved
Reserved
CPUINV
Reserved
Reserved
Reserved
Reserved
Control Function
Reserved
Reserved
Reserved
CPU Phase Invert
Reserved
Reserved
Reserved
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Default
-
1
Inverse
-
PWD
0
0
0
0
0
0
0
0
Control Function
Reserved
Reserved
Reserved
Reserved
CPUCLKT/C (2:0)
Skew Control
Reserved
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
1
-
PWD
0
0
0
0
0
1
0
0
Control Function
Reserved
Reserved
Reserved
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
16-Steps Skew Control.
This byte will advance or
delay the skew by 100ps
per step
PWD
0
0
0
0
0
1
0
0
Type
RW
0
1
Skew Control This byte
will advance or delay the
skew by 250 ps per step
PWD
0
2
I C Table: Group Skew Control Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Byte 18
7
6
5
4
3
2
1
0
Pin #
-
Name
Reserved
Reserved
Reserved
Reserved
CPUSkw1
CPUSkw0
Reserved
Reserved
2
I C Table: Group Skew Control Register
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Byte 19
7
6
5
4
3
2
1
0
Pin #
-
Name
Reserved
Reserved
Reserved
Reserved
PCISkw3
PCISkw2
PCISkw1
PCISkw0
PCI (6:1) AND
PCIF(2:0) Skew
Control
2
I C Table: Slew Rate Control Register
Byte 20
Bit 7
-
Name
3V66ISkw
Bit 6
-
3V66ISkw
3V66 (5:0) Skew
Control
Bit
Bit
Bit
Bit
Bit
Bit
-
Reserved
Reserved
RESERVED
RESERVED
RESERVED
RESERVED
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
5
4
3
2
1
0
Pin #
Control Function
RW
RW
RW
-
0641D—07/03/03
9
-
-
1
0
0
0
0
0
0
ICS950227
Integrated
Circuit
Systems, Inc.
2
I C Table: Slew Rate Control Register
Byte 21
Bit 7
Bit 6
Pin #
Name
Control Function
Type
-
PCISlw
PCICLK_F2 Slew Rate
Control
RW
-
PCISlw
PCICLK_F1:0 Slew
Rate Control
RW
-
3V66SLW
3V66 (5:2) Slew Rate
Control
RW
3V66SLW
3V66 (1:0) Slew Rate
Control
RW
Control Function
Type
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
0
1
10=STRONG
00= MEDIUM
01= WEAK
10=STRONG
00= MEDIUM
01= WEAK
10=STRONG
00= MEDIUM
01= WEAK
10=STRONG
00= MEDIUM
01= WEAK
PWD
1
0
1
10=STRONG
00= MEDIUM
01= WEAK
10=STRONG
00= MEDIUM
01= WEAK
10=STRONG
00= MEDIUM
01= WEAK
10=STRONG
00= MEDIUM
01= WEAK
PWD
0
1
0
1
0
1
0
2
I C Table: Slew Rate Control Register
Byte 22
Pin #
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Name
PCISlw
REF Slew Rate Control
RW
RW
PCISlw
PCISlw
PCISlw
1
0
PCICLK (6:4) Slew
Rate Control
RW
PCICLK (3:1) Slew
Rate Control
RW
PCICLK0 Slew Rate
Control
RW
Control Function
Type
0
1
PWD
RW
-
-
1
RW
RW
RW
-
-
0
0
1
RW
RW
RW
1
0
1
0
1
0
2
I C Table: Slew Rate Control Register
Byte 23
Pin #
Name
Bit 7
-
PCISlw1
Bit 7
Bit 6
Bit 5
-
Reserved
Reserved
Bit 4
-
Bit
Bit
Bit
Bit
-
3
2
1
0
PCI (6:4) Slew Rate
Control
Reserved
Reserved
VCSLW
VCH Slew Rate
Control
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0641D—07/03/03
10
RW
RW
RW
RW
RW
10=STRONG
00= MEDIUM
01= WEAK
-
0
0
0
0
0
ICS950227
Integrated
Circuit
Systems, Inc.
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
V IH
2
V DD + 0.3
V
Input Low Voltage
Input High Current
V IL
IIH
VSS - 0.3
-5
0.8
5
V
mA
I IL1
Input Low Current
V IN = VDD
VIN = 0 V; Inputs with no pull-up
resistors
-5
mA
I IL2
VIN = 0 V; Inputs with pull-up
resistors
Operating Supply Current
IDD3.3OP
CL = Full load
283
360
mA
Powerdown Current
Input Frequency
Pin Inductance
IDD3.3PD
Fi
Lpin
CIN
COUT
CINX
IREF=2.32 mA
VDD = 3.3 V
23
14.32
25
7
5
6
45
mA
MHz
nH
pF
pF
pF
1.8
ms
Input Capacitance1
Clk Stabilization1,2
-200
Logic Inputs
Output pin capacitance
X1 & X2 pins
From PowerUp or deassertion of
PowerDown to 1st clock.
27
tPZH,tPZL
Output enable delay (all outputs)
1
10
ns
tPHZ,tPLZ
Output disable delay (all outputs)
1
10
ns
TSTAB
Delay 1
1
2
Guaranteed by design, not 100% tested in production.
See timing diagrams for buffered and un-buffered timing requirements.
0641D—07/03/03
11
ICS950227
Integrated
Circuit
Systems, Inc.
Electrical Characteristics - CPU 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF
PARAMETER
Current Source Output
Impedance
SYMBOL
CONDITIONS
MIN
Zo1
VO = Vx
3000
Voltage High
VHigh
Statistical measurement on single
ended signal using oscilloscope
math function.
Measurement on single ended
signal using absolute value.
660
Voltage Low
VLow
Max Voltage
Min Voltage
Crossing Voltage (abs)
Vovs
Vuds
Vcross(abs)
Crossing Voltage (var)
d-Vcross
Long Accuracy
ppm
Average period
Tperiod
Absolute min period
Tabsmin
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
tr
tf
d-tr
d-tf
Variation of crossing over all
edges
see Tperiod min-max values
200MHz nominal
200MHz spread
166.66MHz nominal
166.66MHz spread
133.33MHz nominal
133.33MHz spread
100.00MHz nominal
100.00MHz spread
200MHz nominal
166.66MHz nominal/spread
133.33MHz nominal/spread
100.00MHz nominal/spread
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
TYP
770
MAX
UNITS
NOTES
Ω
1
850
1
mV
-150
5
150
756
-7
350
1150
-300
250
550
mV
1
1
1
12
140
mV
1
300
5.0015
5.0266
6.0018
6.0320
7.5023
5.4000
10.0030
10.0533
ppm
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
1,2
2
2
2
2
2
2
2
2
1,2
1,2
1,2
1,2
1
1
1
1
-300
4.9985
4.9985
5.9982
5.9982
7.4978
7.4978
9.9970
9.9970
4.8735
5.8732
7.3728
9.8720
175
175
332
344
30
30
700
700
125
125
1
mV
Measurement from differential
45
49
55
%
wavefrom
tsk3
VT = 50%
Skew
8
100
ps
Measurement from differential
tjcyc-cyc
60
150
ps
Jitter, Cycle to cycle
wavefrom
1
Guaranteed by design, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at
14.31818MHz
Duty Cycle
dt3
0641D—07/03/03
12
1
1
1
ICS950227
Integrated
Circuit
Systems, Inc.
Electrical Characteristics - 3V66 [5:0]
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
Output Frequency
FO
Output Impedance
VO = VDD*(0.5)
RDSP11
1
Output High Voltage
I OH = -1 mA
VOH
Output Low Voltage
VOL1
Output High Current
I OH1
Output Low Current
I OL1
Rise Time
t r11
t f11
dt11
t sk11
Fall Time
Duty Cycle
Skew
Jitter
1
t jcyc-cyc
I OL = 1 mA
V [email protected] = 1.0 V,
V [email protected] = 3.135 V
VOL @MIN = 1.95 V,
VOL @MAX = 0.4 V
1
MIN
TYP
66.66
12
MAX
55
2.4
-33
30
UNITS
MHz
Ω
V
-110
-20
110
37
0.55
V
-33
mA
38
mA
VOL = 0.4 V, VOH = 2.4 V
0.5
1.8
2
ns
VOH = 2.4 V, VOL = 0.4 V
0.5
1.3
2
ns
VT = 1.5 V
45
51.2
55
%
VT = 1.5 V
136
250
ps
VT = 1.5 V 3V66
241
250
ps
TYP
33.33
MAX
UNITS
MHz
Ω
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
Output Frequency
FO
Output Impedance
VO = VDD*(0.5)
RDSP11
1
Output High Voltage
I OH = -1 mA
VOH
0.55
V
-33
-110
-20
-33
mA
[email protected] = 1.95 V,
VOL @MAX = 0.4 V
30
110
37
38
mA
VOL = 0.4 V, VOH = 2.4 V
0.5
1.51
2
ns
VOH = 2.4 V, VOL = 0.4 V
0.5
1.32
2
ns
VT = 1.5 V
45
51.1
55
%
VT = 1.5 V
101
500
ps
VT = 1.5 V
226
250
ps
I OH1
Output Low Current
I OL1
t r11
t f11
dt11
t sk11
Duty Cycle
Skew
Jitter,cycle to cyc
1
0.08
[email protected] = 1.0 V,
V [email protected] = 3.135 V
Output High Current
Fall Time
t jcyc-cyc
55
3.28
I OL = 1 mA
Rise Time
12
2.4
VOL1
Output Low Voltage
MIN
1
Guaranteed by design, not 100% tested in production.
0641D—07/03/03
13
V
ICS950227
Integrated
Circuit
Systems, Inc.
Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
Output Frequency
FO
Output Impedance
VO = VDD*(0.5)
RDSP11
1
IOH = -1 mA
Output High Voltage
VOH
1
Output Low Voltage
VOL
Output High Current
I OH1
Output Low Current
I OL1
48DOT Rise Time
tr11
48DOT Fall Time
tf11
tr11
tf11
dt11
dt11
VCH 48 USB Rise Time
VCH 48 USB Fall Time
48 DOT Duty Cycle
VCH 48 USB Duty Cycle
48 DOT Jitter
tjcyc-cyc
USB to DOT Skew
tsk11
VCH Jitter
tjcyc-cyc
IOL = 1 mA
V [email protected] = 1.0 V,
V [email protected] = 3.135 V
MIN
TYP
48.008
20
2.4
-29
MAX
60
3.27
-61
-12
UNITS
MHz
Ω
V
0.4
V
-23
mA
27
mA
VOL @MIN = 1.95 V, VOL @MAX =
0.4 V
VOL = 0.4 V, V OH = 2.4 V
0.5
0.84
1
ns
VOH = 2.4 V, V OL = 0.4 V
0.5
0.92
1
ns
VOL = 0.4 V, V OH = 2.4 V
1
1.74
2
ns
VOH = 2.4 V, V OL = 0.4 V
1
1.84
2
ns
VT = 1.5 V
45
53.2
55
%
VT = 1.5 V
45
29
52.5
55
%
VT = 1.5 V
151
350
ps
V T = 1.5 V (0 OR 180 degrees)
0.53
1
ns
VT = 1.5 V
187
350
ps
TYP
14.318
MAX
UNITS
MHz
Ω
1
1
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
Output Frequency
FO1
Output Impedance
V O = V DD*(0.5)
RDSP11
1
I OH = -1 mA
Output High Voltage
VOH
Output Low Voltage
VOL
Output High Current
IOH1
20
2.4
60
3.28
IOL = 1 mA
V
0.4
V
-33
mA
37
38
mA
V [email protected] = 1.0 V
V [email protected] = 3.135 V
-33
-110
-20
VOL @MIN = 1.95 V
30
110
Output Low Current
IOL1
VOL @MAX = 0.4 V
Rise Time
t r11
t f11
dt11
VOL = 0.4 V, VOH = 2.4 V
1
1.38
2
ns
VOH = 2.4 V, VOL = 0.4 V
1
1.31
2
ns
VT = 1.5 V
45
54.7
55
%
276
1000
ps
Fall Time
Duty Cycle
Jitter
1
1
MIN
tjcyc-cyc
1
VT = 1.5 V
Guaranteed by design, not 100% tested in production.
0641D—07/03/03
14
ICS950227
Integrated
Circuit
Systems, Inc.
3V66 & PCI Phase Relationship
All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no defined
phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard skew described
below as Tpci.
3V66 (1:0)
3V66 (4:2)
3V66_5
Tpci
PCICLK_F (2:0) PCICLK (6:0)
Group Skews at Common Transition Edges
1
GROUP
3V66
SYMBOL
3V66
PCI
PCI
3V66 to PCI
S3V66-PCI
CONDITIONS
3V66 (5:0) pin to pin skew
PCI_F (2:0) and
PCI (6:0) pin to pin skew
3V66 (5:0) leads 33MHz PCI
MIN
0
TYP
136
MAX
250
UNITS
ps
0
101
500
ps
1.5
2.08
3.5
ns
Guarenteed by design, not 100% tested in production.
PD# Functionality
CPU_STOP#
CPUT
CPUC
3V66
66MHz_OUT
PCICLK_F
PCICLK
PCICLK
USB/DOT
48MHz
1
Normal
Normal
66MHz
66MHz_IN
66MHz_IN
66MHz_IN
48MHz
0
iref * Mult
Float
Low
Low
Low
Low
Low
0641D—07/03/03
15
ICS950227
Integrated
Circuit
Systems, Inc.
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low
in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising
edge.
Assertion of PCI_STOP# Waveforms
PCI_STOP#
PCI_F[2:0] 33MHz
PCI[6:0] 33MHz
tsu
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable via assertion
of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown. The final state
of the stopped CPU signals is CPUT=High and CPUC=Low. There is to be no change to the output drive current values. The
CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven.
Assertion of CPU_STOP# Waveforms
CPU_STOP#
CPUT
CPUC
CPU_STOP# Functionality
CPU_STOP#
CPUT
CPUC
1
Normal
Normal
0
iref * Mult
Float
0641D—07/03/03
16
ICS950227
Integrated
Circuit
Systems, Inc.
c
N
SYMBOL
L
E1
INDEX
AREA
A
A1
b
c
D
E
E1
e
h
L
N
α
E
1 2
α
h x 45°
D
A
N
A1
-Ce
SEATING
PLANE
b
56
In Millimeters
COMMON DIMENSIONS
MIN
MAX
2.41
2.80
0.20
0.40
0.20
0.34
0.13
0.25
SEE VARIATIONS
10.03
10.68
7.40
7.60
0.635 BASIC
0.38
0.64
0.50
1.02
SEE VARIATIONS
0°
8°
VARIATIONS
D mm.
MIN
MAX
18.31
18.55
In Inches
COMMON DIMENSIONS
MIN
MAX
.095
.110
.008
.016
.008
.0135
.005
.010
SEE VARIATIONS
.395
.420
.291
.299
0.025 BASIC
.015
.025
.020
.040
SEE VARIATIONS
0°
8°
D (inch)
MIN
.720
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
.10 (.004) C
300 mil SSOP Package
Ordering Information
ICS950227yFT
Example:
ICS XXXXXX y F - T
Designation for tape and reel packaging
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0641D—07/03/03
17
MAX
.730