ICS952802 Advance Information Integrated Circuit Systems, Inc. Programmable Timing Control Hub™ for P4™ processor Recommended Application: SiS755/760 style chipset for AMD K8 Processor Features/Benefits: • Selectable synchronous/asynchronous AGP/PCI/ZCLK frequency • Linear Programmable output frequency. • Programmable output divider ratios. • Programmable output rise/fall time. • Programmable output skew. • Programmable spread percentage for EMI control. • Watchdog timer technology and system reset function • Programmable watch dog safe frequency. • Support I2C Index read/write and block read/write operations. • Uses external 14.318MHz reference input. Output Features: • 2 - Pairs of differential push-pull K8CPU outputs • 10 - PCICLK @ 3.3V • 2 - AGPCLK @ 3.3V • 3 - REF @ 3.3V • 2 - ZCLK @ 3.3V • 1 - 24_48MHz @ 3.3V • 1 - 12_48MHz @ 3.3V • 1 - PCI_12MHz @ 3.3V Key Specifications: • CPU Output Jitter <250ps • AGP Output Jitter <250ps Bit4 FS4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit3 FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Pin Configuration Bit2 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit0 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU MHz 160.00 200.00 200.00 200.00 186.66 233.33 233.33 233.33 213.34 266.67 266.67 266.67 133.34 166.67 166.67 166.67 206.00 210.00 202.00 202.00 240.33 245.00 235.66 235.66 106.66 133.33 133.33 133.33 171.67 175.00 168.34 168.34 ZCLK MHz 106.66 133.33 133.33 160.00 106.67 133.33 133.33 155.55 106.66 133.33 133.33 160.00 106.66 133.33 133.33 166.66 137.33 140.00 134.66 161.60 137.33 140.00 134.67 157.11 106.66 133.33 133.33 177.77 137.33 140.00 134.66 168.33 AGP MHz 53.33 66.67 66.67 66.67 53.33 66.67 66.67 66.67 53.33 66.67 66.67 66.67 53.33 66.67 66.67 66.67 68.67 70.00 67.33 67.33 68.67 70.00 67.33 67.33 53.33 66.67 66.67 66.67 68.67 70.00 67.33 67.33 PCI MHz 26.66 33.33 33.33 33.33 26.66 33.33 33.33 33.33 26.66 33.33 33.33 33.33 26.66 33.33 33.33 33.33 34.33 35.00 33.66 33.66 34.33 35.00 33.66 33.66 26.66 33.33 33.33 33.33 34.33 35.00 33.66 33.66 VDDREF 1 48 CPU_STOP#/Reset#* *FS0/REF0 2 47 GNDCPU **FS1/REF1 3 46 CPUCLK8T1 **FS2/REF2 4 45 CPUCLK8C1 44 VDDCPU GNDREF 5 X1 6 43 VDDCPU X2 7 42 CPUCLK8T0 GNDZ 8 41 CPUCLK8C0 40 GNDCPU ZCLK0 9 ZCLK1 10 VDDZ 11 *PCI_STOP#/PCICLK8 12 **FS3/PCICLK_F0 13 **FS4/PCICLK_F1 14 VDDPCI 15 ICS952802 Functionality GNDPCI 16 39 AGND 38 AVDD 37 PD#* 36 GNDAGP 35 AGPCLK0 34 AGPCLK1 33 VDDAGP 32 SCLK 31 AVDD48 PCICLK0 17 PCICLK1 18 30 12_48MHz/SEL12_48#** 29 24_48MHz/SEL24_48#*~ PCICLK2 19 PCICLK3 20 PCICLK5 22 28 GND48 27 SDATA GNDPCI 23 26 PCICLK7/12MHz/SELPCI_12#** PCICLK4 21 VDDPCI 24 25 PCICLK6/SEL_Reset#* 48-SSOP * Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ This Output has 1.5X Drive Strength 0731—09/18/02 ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners. Integrated Circuit Systems, Inc. ICS952802 Advance Information General Description The ICS952802 is a two chip clock solution for desktop designs using SIS 755/760 style chipsets. When used with a zero delay buffer such as the ICS9179-16 for PC133 or the ICS93735 for DDR applications it provides all the necessary clocks signals for such a system. The ICS952802 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). ICS is the first to introduce a whole product line which offers full programmability and flexibility on a single clock device. Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment. Block Diagram 12_48MHz Frequency Dividers PLL2 24_48MHz PCI7_12MHZ X1 X2 XTAL REF (2:0) CPUCLK8T (1:0) CPUCLK8C (1:0) PD# CPU_STOP# PCI_STOP# FS (4:0) SEL24_48# SEL12_48# SELPCI_12# Programmable Spread PLL1 Programmable Frequency Dividers Control Logic STOP Logic AGPCLK (1:0) PCICLK (8,6:0) PCICLKF (1:0) RESET# 0731—09/18/02 2 Integrated Circuit Systems, Inc. ICS952802 Advance Information Pin Description PIN # 1 PIN NAME PIN TYPE DESCRIPTION VDDREF PWR Ref, XTAL power supply, nominal 3.3V 2 3 4 5 6 7 8 9 10 11 *FS0/REF0 **FS1/REF1 **FS2/REF2 GNDREF X1 X2 GNDZ ZCLK0 ZCLK1 VDDZ I/O I/O I/O PWR IN OUT PWR OUT OUT PWR 12 *PCI_STOP#/PCICLK8 13 14 15 16 17 18 19 20 21 22 23 24 **FS3/PCICLK_F0 **FS4/PCICLK_F1 VDDPCI GNDPCI PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5 GNDPCI VDDPCI I/O I/O PWR PWR OUT OUT OUT OUT OUT OUT PWR PWR Frequency select latch input pin / 14.318 MHz reference clock. Frequency select latch input pin / 14.318 MHz reference clock. Frequency select latch input pin / 14.318 MHz reference clock. Ground pin for the REF outputs. Crystal input,nominally 14.318MHz. Crystal output, nominally 14.318MHz. Ground pin for the ZCLK outputs 3.3V Hyperzip clock output. 3.3V Hyperzip clock output. Power supply for ZCLK clocks, nominal 3.3V Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low. This input is selected by IIC. Frequency select latch input pin / 3.3V PCI free running clock output. Frequency select latch input pin / 3.3V PCI free running clock output. Power supply for PCI clocks, nominal 3.3V Ground pin for the PCI outputs PCI clock output. PCI clock output. PCI clock output. PCI clock output. PCI clock output. PCI clock output. Ground pin for the PCI outputs Power supply for PCI clocks, nominal 3.3V 25 PCICLK6/SEL_Reset#* I/O PCI clock output / Latch input pin to select pin 48 function; 0 = Reset#. 1 = CPU_Stop# I/O PCICLK/12MHz clock output / Latched select input for PCI/12MHz output. 0 = 12MHz, 1 = PCICLK. 27 SDATA I/O Data pin for I2C circuitry 5V tolerant 28 GND48 PWR Ground pin for the 48MHz outputs 24/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 = 29 24_48MHz/SEL24_48#*~ I/O 24MHz. 12/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 = 30 12_48MHz/SEL12_48#** I/O 12MHz. 31 AVDD48 PWR Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V 32 SCLK IN Clock pin of I2C circuitry 5V tolerant 33 VDDAGP PWR Power supply for AGP clocks, nominal 3.3V 34 AGPCLK1 OUT AGP clock output 35 AGPCLK0 OUT AGP clock output 36 GNDAGP PWR Ground pin for the AGP outputs Asynchronous active low input pin used to power down the device into a low power 37 PD#* IN state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. 38 AVDD PWR 3.3V Analog Power pin for Core PLL 39 AGND PWR Analog Ground pin for Core PLL 40 GNDCPU PWR Ground pin for the CPU outputs 41 CPUCLK8C0 OUT "Complementary" clocks of differential 3.3V push-pull K8 pair. 42 CPUCLK8T0 OUT "True" clocks of differential 3.3V push-pull K8 pair. 43 VDDCPU PWR Supply for CPU clocks, 3.3V nominal 44 VDDCPU PWR Supply for CPU clocks, 3.3V nominal 45 CPUCLK8C1 OUT "Complementary" clocks of differential 3.3V push-pull K8 pair. 46 CPUCLK8T1 OUT "True" clocks of differential 3.3V push-pull K8 pair. 47 GNDCPU PWR Ground pin for the CPU outputs 48 CPU_STOP#/Reset#* I/O Slectable real time CPU_Stop# (Input) or Reset# (Output) * Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ This Output has 1.5X Drive Strength 26 PCICLK7/12MHz/SELPCI_12#** I/O 0731—09/18/02 3 Integrated Circuit Systems, Inc. ICS952802 Advance Information General I2C serial interface information for the ICS952802 How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit • • • • • • • • • • • • • • • • • • • • • • Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Read Operation Index Block Write Operation Controller (Host) starT bit T Slave Address D2(H) WR WRite Controller (Host) T starT bit Slave Address D2(H) WR WRite ICS (Slave/Receiver) ICS (Slave/Receiver) ACK ACK Beginning Byte = N Beginning Byte = N ACK ACK RT Repeat starT Slave Address D3(H) RD ReaD Data Byte Count = X ACK Beginning Byte N ACK X Byte ACK Data Byte Count = X ACK Beginning Byte N Byte N + X - 1 ACK X Byte ACK P stoP bit Byte N + X - 1 N P 0731—09/18/02 4 Not acknowledge stoP bit Integrated Circuit Systems, Inc. Table1: Frequency Selection Table Bit4 Bit3 Bit2 Bit1 Bit0 FS4 FS3 FS2 FS1 FS0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 ICS952802 Advance Information CPU MHz 160.00 200.00 200.00 200.00 186.66 233.33 233.33 233.33 213.34 266.67 266.67 266.67 133.34 166.67 166.67 166.67 206.00 210.00 202.00 202.00 240.33 245.00 235.66 235.66 106.66 133.33 133.33 133.33 171.67 175.00 168.34 168.34 ZCLK MHz 106.66 133.33 133.33 160.00 106.67 133.33 133.33 155.55 106.66 133.33 133.33 160.00 106.66 133.33 133.33 166.66 137.33 140.00 134.66 161.60 137.33 140.00 134.67 157.11 106.66 133.33 133.33 177.77 137.33 140.00 134.66 168.33 AGP MHz 53.33 66.67 66.67 66.67 53.33 66.67 66.67 66.67 53.33 66.67 66.67 66.67 53.33 66.67 66.67 66.67 68.67 70.00 67.33 67.33 68.67 70.00 67.33 67.33 53.33 66.67 66.67 66.67 68.67 70.00 67.33 67.33 PCI MHz 26.66 33.33 33.33 33.33 26.66 33.33 33.33 33.33 26.66 33.33 33.33 33.33 26.66 33.33 33.33 33.33 34.33 35.00 33.66 33.66 34.33 35.00 33.66 33.66 26.66 33.33 33.33 33.33 34.33 35.00 33.66 33.66 0731—09/18/02 5 Spread % 0.3% Center 0-0.5% Down 0.3% Center 0.3% Center 0.3% Center 0-0.5% Down 0.3% Center 0.3% Center 0.3% Center 0-0.5% Down 0.3% Center 0.3% Center 0.3% Center 0-0.5% Down 0.3% Center 0.3% Center 0.3% Center 0.3% Center 0.3% Center 0.3% Center 0.3% Center 0.3% Center 0.3% Center 0.3% Center 0.3% Center 0-0.5% Down 0.3% Center 0.3% Center 0.3% Center 0.3% Center 0.3% Center 0.3% Center Integrated Circuit Systems, Inc. ICS952802 Advance Information 2 I C Table: Reserved Register Byte 0 Bit Bit Bit Bit Bit Bit Bit Bit Pin # - 7 6 5 4 3 2 1 0 Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved - Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type 0 1 PWD RW RW RW RW RW RW RW RW - - 1 1 1 1 1 1 1 0 Type 0 1 PWD R R R R R R - - 0 0 0 0 0 0 R - - 0 R - - 1 Type 0 1 PWD RW Disable Enable 0 RW RW RW RW RW RW RW PCI_Stop# Disable Disable Disable Disable Disable Disable PCICLK8 Enable Enable Enable Enable Enable Enable 1 1 1 1 1 1 1 Type 0 1 PWD RW RW RW RW RW RW RW RW Disable Disable 48MHz 48MHz Disable Disable Disable - Enable Enable 12MHz 24MHz Enable Enable Enable - 1 1 Latch Latch 1 1 1 1 2 I C Table: Revision & Vendor ID Register Byte 1 Pin # Name 7 6 5 4 3 2 - RID3 RID2 RID1 RID0 VID3 VID2 Bit 1 - VID1 Bit 0 - VID0 Bit Bit Bit Bit Bit Bit Control Function REVISION ID VENDOR ID 2 I C Table: Output Control Register Byte 2 Bit 7 Bit Bit Bit Bit Bit Bit Bit 6 5 4 3 2 1 0 Pin # Name - GSR_EN 37 30 29 4 3 2 PCIFNSEL PD#_EN 12_48MHz 24_48MHz REF2 REF1 REF0 Control Function Gear Shift Reset Enable PCI_Stop/PCI Select PD# Pin Control Output Control Output Control Output Control Output Control Output Control 2 I C Table: Output Control Register Byte 3 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # 34 35 25 26 12 - Name AGPCLK1 AGPCLK0 12_48MHz 24_48MHz PCICLK6 PCICLK7/12MHz PCICLK8 Reserved Control Function Output Control Output Control Output Select Output Select Output Control Output Control Output Control Reserved 0731—09/18/02 6 Integrated Circuit Systems, Inc. ICS952802 Advance Information 2 I C Table: Frequency Select Register Byte 4 Pin # Name 7 6 5 4 - FS3 FS2 FS1 FS0 Bit 3 - FS Source Bit 2 Bit 1 Bit 0 - FS4 SS_EN Outputs Bit Bit Bit Bit Control Function Freq Select Bit 3 Freq Select Bit 2 Freq Select Bit 1 Freq Select Bit 0 Frequency HW/IIC Select Freq Select Bit 4 Spread Enable Output Control Type RW RW RW RW RW RW RW RW 0 1 See Table1: Frequency Selection Table Latch Input IIC See Table1 OFF ON Running Tri-state PWD 0 0 0 0 0 0 1 0 2 I C Table: Read Back Register Byte 5 Pin # Name Control Function Type 0 1 PWD Bit 7 Bit 6 - SEL12_48#RB SEL Read Back R 48MHz 12MHz X SEL24_48#RB R 48MHz 24MHz X Bit 5 - WDHRB R Normal Alarm X Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - FS4RB SEL Read Back WD Hard Alarm Status Read back FS4 Read back R - - X FS3RB FS3 Read back R - - X FS2RB FS2 Read back R - - X FS1RB FS1 Read back R - - X FS0RB FS0 Read back R - - X Type 0 1 PWD 2 I C Table: Output Control Register Byte 6 Pin # 10 9 14 13 42/41 46/45 42/41 46/45 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name ZCLK_1 ZCLK_0 PCICLK_F1 Control Function Output Control Output Control PCI_STOP# Control RW RW RW Disable Enable Disable Enable Stop Disable Stop Enable 1 1 0 PCICLK_F0 PCI_STOP# Control RW Stop Disable Stop Enable 0 CPUCLK8T0/C0 CPU_STOP# Control RW Stop Disable Stop Enable 1 CPUCLK8T1/C1 CPU_STOP# Control RW Stop Disable Stop Enable 1 CPUCLK8T0/C0 Output Control RW Disable Enable 1 CPUCLK8T1/C1 Output Control RW Disable Enable 1 Type 0 1 PWD RW RW RW RW RW RW RW RW Disable Disable Disable Disable Disable Disable Disable Disable Enable Enable Enable Enable Enable Enable Enable Enable 1 1 1 1 1 1 1 1 2 I C Table: Output Control Register Byte 7 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # 14 13 22 21 20 19 18 17 Name PCICLK_F1 PCICLK_F0 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 Control Function Output Control Output Control Output Control Output Control Output Control Output Control Output Control Output Control 0731—09/18/02 7 Integrated Circuit Systems, Inc. ICS952802 Advance Information 2 I C Table: Byte Count Register Byte 8 Bit Bit Bit Bit Bit Bit Bit Bit Pin # - 7 6 5 4 3 2 1 0 Name BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Control Function Type 0 1 PWD Writing to this register will configure how many bytes will be read back, default is 0F = 15 bytes. RW RW RW RW RW RW RW RW - - 0 0 0 0 1 1 1 1 Control Function Type 0 1 PWD These bits represent X*290ms the watchdog timer will wait before it goes to alarm mode. Default is 16 X 290ms =4.64 seconds RW RW RW RW RW RW RW RW - - 0 0 0 1 0 0 0 0 2 I C Table: Watchdog Timer Register Byte 9 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Name WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0 2 I C Table: VCO Control Select Bit & WD Timer Control Register Byte 10 Pin # Name Control Function Type 0 1 PWD M/N Programming Enable RW Disable Enable 0 RW RW RW RW RW RW RW Disable - Enable - 0 0 0 0 0 0 1 Type 0 1 PWD RW RW RW RW RW RW RW RW - - X X X X X X X X Bit 7 - M/NEN Bit Bit Bit Bit Bit Bit Bit - WDEN Reserved WD SF4 WD SF3 WD SF2 WD SF1 WD SF0 6 5 4 3 2 1 0 Watchdog Enable Reserved Writing to these bit will configure the safe frequency as Byte 4 bit 2, (7:4) 2 I C Table: VCO Frequency Control Register Byte 11 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Name N Div8 M Div6 M Div5 M Div4 M Div3 M Div2 M Div1 M Div0 Control Function N Divider Bit 8 The decimal representation of M Div (6:0) + 2 is equal to reference divider value. Default at power up = latch-in or Byte 0 Rom table. 0731—09/18/02 8 Integrated Circuit Systems, Inc. ICS952802 Advance Information 2 I C Table: VCO Frequency Control Register Byte 12 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Name Control Function Type 0 1 PWD N Div7 N Div6 N Div5 N Div4 N Div3 N Div2 N Div1 N Div0 The decimal representation of N Div (8:0) + 8 is equal to VCO divider value. Default at power up = latch-in or Byte 0 Rom table. RW RW RW RW RW RW RW RW - - X X X X X X X X 2 I C Table: Spread Spectrum Control Register Byte 13 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Name Control Function Type 0 1 PWD SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0 These Spread Spectrum bits will program the spread pecentage. It is recommended to use ICS Spread % table for spread programming. RW RW RW RW RW RW RW RW - - X X X X X X X X Type 0 1 PWD R R R RW RW RW RW RW - - 0 0 X X X X X X Type 0 1 PWD 2 I C Table: Spread Spectrum Control Register Byte 14 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # Name Reserved Reserved SSP13 SSP12 SSP11 SSP10 SSP9 SSP8 - Control Function Reserved Reserved It is recommended to use ICS Spread % Table for Spread Programming 2 I C Table: Output Divider Control Register Byte 15 Pin # Name 7 6 5 4 3 2 - PCI Div3 PCI Div2 PCI Div1 PCI Div0 CPU Div3 CPU Div2 Bit 1 - CPU Div1 Bit 0 - CPU Div0 Bit Bit Bit Bit Bit Bit Control Function PCI divider ratio can be configured via these 4 bits individually. CPU divider ratio can be configured via these 4 bits individually. RW RW RW RW RW RW RW RW 0731—09/18/02 9 See Table 2: Divider Ratio Combination Table See Table 2: Divider Ratio Combination Table X X X X X X X X Integrated Circuit Systems, Inc. ICS952802 Advance Information Table2: Divider Ratio Combination Table Divider (3:2) Divider (1:0) Bit 00 0000 0001 0010 0011 Address 00 01 10 11 LSB 01 1 2 3 5 7 Div 10 2 4 6 10 14 Div 0100 0101 0110 0111 Address 1000 1001 1010 1011 Address 11 4 8 12 20 28 Div 1100 1101 1110 1111 Address MSB 8 16 24 40 56 Div 2 I C Table: Output Divider Control Register Byte 16 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # Name AGPDiv3 AGPDiv2 AGPDiv1 AGPDiv0 ZCLKDiv3 ZCLKDiv2 ZCLKDiv1 ZCLKDiv0 - Control Function AGP divider ratio can be configured via these 4 bits individually. ZCLK divider ratio can be configured via these 4 bits individually. Type RW RW RW RW RW RW RW RW 0 1 See Table 2: Divider Ratio Combination Table See Table 2: Divider Ratio Combination Table PWD X X X X X X X X 2 I C Table: Output Divider Control Register Byte 17 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # Name AGPINV ZCLKSDINV Reserved CPUINV Reserved Reserved Reserved Reserved - Control Function AGPPhase Invert ZCLK Phase Invert Reserved CPU Phase Invert Reserved Reserved Reserved Reserved Type 0 1 PWD RW RW RW RW RW RW RW RW Default Default Default - Inverse Inverse Inverse - X X X X X X X X Type 0 1 PWD 2 I C Table: Group Skew Control Register Byte 18 Pin # 7 6 5 4 3 2 1 - Bit 0 - Bit Bit Bit Bit Bit Bit Bit Name CPUSkw1 CPUSkw0 Reserved Reserved Reserved ASYNC3 ASYNC1 ASYNC0 Control Function CPU-CPU Skew Control Reserved Reserved Reserved Async Freq Fix PLL RW RW RW RW RW RW RW RW 0731—09/18/02 10 See Table 3: 4-Steps Skew Programming Table See Table 4: Asynchronous Frequency Programming Table 1 1 0 0 0 0 0 0 Integrated Circuit Systems, Inc. ICS952802 Advance Information Table 3: 4-Steps Skew Programming Table 4 Step 0 1 MSB 0 0ps 500ps - 1 250ps 750ps - LSB - Table 4: Asynchronous Frequency Selection Table B18 bit2 0 0 0 0 1 1 1 1 B18 bit1 0 0 1 1 0 0 1 1 B18 bit0 0 1 0 1 0 1 0 1 VCO Main PLL 528 528 528 528 528 528 528 ZCLK Main PLL Main PLL Main PLL Main PLL 132 132 132 132 AGP Main PLL 66 75.4 88 Main PLL 66 75.4 88 PCI Main PLL 33 37.7 44 Main PLL 33 37.7 44 2 I C Table: Group Skew Control Register Byte 19 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # Name ZCLKSkw3 ZCLKSkw2 ZCLKSkw1 ZCLKSkw0 AGPSkw3 AGPSkw2 AGPSkw1 AGPSkw0 - Control Function CPU-ZCLK Skew Control CPU-AGP Skew Control Type RW RW RW RW RW RW RW RW 0 1 16-Steps Skew Control. This byte will advance or delay the skew by 100ps per step 16-Steps Skew Control. This byte will advance or delay the skew by 100ps per step PWD 0 0 1 1 0 0 1 1 2 I C Table: Group Skew Control Register Byte 20 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Name PCISkw3 PCISkw2 PCISkw1 PCISkw0 Reserved Reserved Reserved Reserved Control Function CPU-PCI Skew Control Reserved Reserved Reserved Reserved 0731—09/18/02 11 Type RW RW RW RW RW RW RW RW 0 1 16-Steps Skew Control. This byte will advance or delay the skew by 100ps per step - - PWD 0 0 0 0 0 0 0 0 Integrated Circuit Systems, Inc. ICS952802 Advance Information 2 I C Table: Slew Rate Control Register Pin # Byte 21 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Name 24/48Slw1 24/48Slw0 AGPSlw1 AGPSlw0 ZCLKSlw1 ZCLKSlw0 REFSlw1 REFSlw0 - Control Function 24/48 Slew Rate Control AGP Slew Rate Control ZCLK Slew Rate Control REF Slew Rate Control Type 0 1 PWD RW RW RW RW RW RW RW RW - - 0 0 0 0 0 0 0 0 Type 0 1 PWD RW RW RW RW RW RW RW - - 0 0 0 0 0 0 0 RW - - 0 Type 0 1 PWD RW RW RW RW RW RW RW RW - - 0 0 0 0 0 0 0 0 Type 0 1 PWD RW RW RW RW RW RW RW RW - - 0 0 0 0 0 0 0 0 2 I C Table: Slew Rate Control Register Byte 22 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Name Reserved Reserved Reserved Reserved PCI_FSlw1 PCI_FSlw0 PCISlw1 PCISlw0 Control Function Reserved Reserved Reserved Reserved PCI_F Slew Rate Control PCI Slew Rate Control 2 I C Table: Output Control Register Byte 23 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 2 I C Table: Reserved Register Byte 24 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # - Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0731—09/18/02 12 Integrated Circuit Systems, Inc. ICS952802 Advance Information Absolute Maximum Ratings Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 4.6 V 3.6V GND –0.5 V to VDD +0.5 V 0°C to +70°C –65°C to +150°C 115°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency Input Capacitance1 1 Transition Time Clk Stabilization1 Skew1 SYMBOL CONDITIONS MIN VIH 2 VSS - 0.3 VIL VIN = VDD IIH VIN = 0 V; Inputs with no pull-up resistors -5 IIL1 VIN = 0 V; Inputs with pull-up resistors -200 IIL2 IDD(op) IDDPD Fi CIN CINX Ttrans TSTAB TCPU-PCI CL = 0 pF; Select @ 100MHz CL = 0 pF; With input address to Vdd or GND VDD = 3.3 V; Logic Inputs X1 & X2 pins To 1st crossing of target Freq. From VDD = 3.3 V to 1% target Freq. VT = 1.5 V 1 Guaranteed by design, not 100% tested in production. 0731—09/18/02 13 11 27 1.5 TYP MAX UNITS VDD + 0.3 V 0.8 V 5 mA mA mA 180 mA 40 mA 16 5 45 3 3 4 MHz pF pF ms ms ns Integrated Circuit Systems, Inc. ICS952802 Advance Information Electrical Characteristics - ZCLK TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER Output Frequency SYMBOL FO1 Output Impedance RDSP11 Output High Voltage Skew VOH1 VOL1 IOH1 IOL1 tr11 tf11 dt11 tsk11 Jitter tjcyc-cyc 1 Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle CONDITIONS MIN TYP MAX UNITS MHz 55 Ω VO = VDD*(0.5) 12 IOH = -1 mA 2.4 IOL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V -33 30 0.55 -33 38 V mA mA VOL = 0.4 V, VOH = 2.4 V 0.5 2 ns VOH = 2.4 V, V OL = 0.4 V VT = 1.5 V 0.5 45 2 55 ns % V VT = 1.5 V VT = 1.5 V 3V66 250 ps 250 ps Electrical Characteristics - AGPCLK, ZCLK TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER Output Frequency SYMBOL FO1 Output Impedance RDSP11 Output High Voltage VOH1 VOL1 IOH1 IOL1 tr11 tf11 dt11 tsk11 Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter tjcyc-cyc 1 CONDITIONS MIN VO = VDD*(0.5) 12 IOH = -1 mA 2.4 IOL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V TYP MAX UNITS MHz 55 Ω V -33 30 0.55 -33 38 V mA mA VOL = 0.4 V, VOH = 2.4 V 0.5 2 ns VOH = 2.4 V, V OL = 0.4 V VT = 1.5 V 0.5 45 2 55 ns % 250 ps 250 ps VT = 1.5 V VT = 1.5 V 3V66 0731—09/18/02 14 Integrated Circuit Systems, Inc. ICS952802 Advance Information Electrical Characteristics - PCICLK TA = 0 - 70°C; VDD = 3.3 V,+/-5%; CL = 30 pF PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 SYMBOL VOH1 VOL1 I OH1 IOL1 CONDITIONS IOH = -18 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V tr1 VOL = 0.4 V, VOH = 2.4 V tf1 VOH = 2.4 V, V OL = 0.4 V Duty Cycle1 dt1 VT = 1.5 V Skew Jitter tsk1 tjcyc-cyc tjabs1 1 TYP 16 Fall Time1 1 MIN 2.1 MAX UNITS V 0.4 V -22 mA 57 mA 2 ns 2 ns 55 % VT = 1.5 V 500 ps VT = 1.5 V VT = 1.5 V 500 500 ps ps 45 1 Guaranteed by design, not 100% tested in production. Electrical Characteristics - 48MHz, 24_48MHz TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN 1 Output Impedance V O = V DD*(0.5) 20 RDSP1 1 Output High Voltage IOH = -1 mA 2.4 VOH Output Low Voltage V OL1 Output High Current IOH1 Output Low Current IOL1 Rise Time tr11 tf11 dt11 Fall Time Duty Cycle Jitter tjcyc-cyc IOL = 1 mA V OH@MIN = 1.0 V V OH@MAX = 3.135 V VOL @MIN = 1.95 V TYP MAX 60 UNITS Ω V 0.4 V -23 mA mA ns -29 29 V OL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V 0.5 27 1 VOH = 2.4 V, VOL = 0.4 V 0.5 1 ns VT = 1.5 V 45 55 % 350 ps 1 VT = 1.5 V 1 Guaranteed by design, not 100% tested in production. 0731—09/18/02 15 Integrated Circuit Systems, Inc. ICS952802 Advance Information Electrical Characteristics - REF TA = 0 - 70°C; VDD = 3.3 V , +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 SYMBOL VOH5 VOL5 I OH5 I OL5 tr5 VOL = 0.4 V, VOH = 2.4 V 4 ns Fall Time1 tf5 VOH = 2.4 V, V OL = 0.4 V 4 ns Duty Cycle dt5 Jitter1 tjcyc-cyc5 tjabs5 VT = 1.5 V VT = 1.5 V VT = 1.5 V 55 1000 800 % ps ps 1 CONDITIONS IOH = -12 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V MIN 2.6 16 45 0731—09/18/02 16 TYP MAX UNITS V 0.4 V -22 mA mA Integrated Circuit Systems, Inc. ICS952802 Advance Information Electrical Characteristics - CPUCLK TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output Impedance Output High Voltage Output Low Voltage Output Low Current CONDITIONS VO = VX MIN 15 1 V OL = 0.3 V 18 Rise Edge Rate Measured from 20-80% 1 Measured from 80-20% 1 Fall Edge Rate VDIFF DVDIFF VCM DVCM SYMBOL ZO V OH2B V OL2B IOL2B Differential Voltage, Measured @ the Hammer test load (single-ended measurement) Change in VDIFF_DC magnitude, Measured @ the Hammer test load (single-ended measurement) Common Mode Voltage, Measured @ the Hammer test load (single-ended measurement) Change in Common Mode Voltage, Measured @ the Hammer test load (singleended measurement) TYP MAX 55 1.2 0.4 UNITS Ω V V mA 2 7 V/ns 2 7 V/ns 0.4 2.3 V -150 150 mV 1.05 1.45 V -200 200 mV dt2B V T = 50% 45 53 % Duty Cycle1 1 t V = V 0 200 ps Jitter, Cycle-to-cycle jcyc-cyc2B T X Notes: 1 - Guaranteed by design, not 100% tested in production. 2 - VDIF specifies the minimum input differential voltages (V TR-V CP) required for switching, where VTR is the "true" input level and VCP is the "complement" input level. 3 - Vpullup(external) = 1.5V, Min = Vpullup(external)/2-150mV; Max=(Vpullup(external)/2)+150mV 0731—09/18/02 17 Integrated Circuit Systems, Inc. ICS952802 Advance Information Shared Pin Operation Input/Output Pins Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Via to VDD Programming Header 2K Via to Gnd Device Pad 8.2K Clock trace to load Series Term. Res. Fig. 1 0731—09/18/02 18 Integrated Circuit Systems, Inc. ICS952802 Advance Information c N SYMBOL L E1 E INDEX AREA 1 2 α h x 45° D A A A1 b c D E E1 e h L N α A1 -Ce b SEATING PLANE .10 (.004) C N 48 In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0° 8° In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0° 8° VARIATIONS D mm. MIN MAX 15.75 16.00 Reference Doc.: JEDEC Publication 95, MO-118 10-0034 Ordering Information ICS952802yFT Example: ICS XXXX y F - T Designation for tape and reel packaging Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 0731—09/18/02 19 D (inch) MIN .620 MAX .630