ICS ICS950905

ICS950905
Advance Information
Integrated
Circuit
Systems, Inc.
Programmable Timing Control Hub™ for P4™
Output Features:
•
2 - Pair of differential CPU clocks @ 3.3V
•
1 - Pair of differential push pull CPU_CS clocks @ 2.5V
•
3 - AGP @ 3.3V
•
9 - PCI @ 3.3V
•
1- IOAPIC @ 2.5V
•
1 - 48MHz @ 3.3V fixed
•
1 - 24_48MHz @ 3.3V
•
1 - REF @ 3.3V, 14.318MHz
Features/Benefits:
•
Programmable output frequency.
•
Programmable output divider ratios.
•
Programmable output rise/fall time.
•
Programmable output skew.
•
Programmable spread percentage for EMI control.
•
Watchdog timer technology to reset system
if system malfunctions.
•
Programmable watch dog safe frequency.
•
Support I2C Index read/write and block read/write
operations.
•
For DDR and or PC133 SDRAM system use ICS93718
as the memory buffer.
•
Uses external 14.318MHz crystal.
Key Specifications:
•
CPU_CS - CPU0: <±250ps
•
CPU_CS - AGP: <±250ps
•
PCI - PCI: <500ps
•
CPU - PCI: Min = 1.0ns, Typ = 2.0ns, Max = 4.0ns
Block Diagram
PLL2
48MHz
24_48MHz
/2
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
REF0
CPU
DIVDER
Stop
CPUCLKT_(1:0)
CPUCLKC_(1:0)
CPU
DIVDER
Stop
CPUCLK_PPT
CPUCLK_PPC
SEL24_48
SDATA
SCLK
Control
FS (3:0)
Logic
PD#
PCI_STOP#
CPU_STOP#
MULTI_SEL
Vtt_PWRGD#
WDEN
WDTB
IOAPIC
DIVDER
PCI
DIVDER
IOAPIC
Pin Configuration
1
**SEL24_48/REF0
VDDREF
GND
X1
X2
VDD48
*FS3/48MHz
*FS2/24_48MHz
GND
*FS0/PCICLK_F
**FS1/PCICLK0
*MULTI_SEL/PCICLK1
GND
*WDTB/PCICLK2
**WDEN/PCICLK3
VDDPCI
PCICLK4
PCICLK5
PCICLK6
GND
PCICLK7
*PD#
AGPCLK0
VDDAGP
VDDLAPIC
GND
N/C
IOAPIC
GND
VDDCPU_PP (2.5V)
CPUCLK_PPT
CPUCLK_PPC
CPUCLKT_0
CPUCLKC_0
VDDCPU (3.3V)
I REF
GND
CPUCLKT_1
CPUCLKC_1
Vtt_PWRGD#
CPU_STOP#*
PCI_STOP#*
RESET#
SDATA
SCLK
AGPCLK2
AGPCLK1
GND
48-Pin 300-mil SSOP
1. These outputs have 2X drive strength.
* These inputs have a internal Pull-up resistor
of 120K to VDD
** These inputs have a internal pull-down to GND
Frequency Table
FS 3
FS 2
FS 1
FS 0
CPUCLK
MHz
AGP
MHz
PCICLK
MHz
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
160.00
164.00
166.60
170.00
175.00
180.00
185.00
190.00
66.80
100.90
133.60
200.40
66.60
100.00
200.00
133.30
80.00
82.00
66.60
68.00
70.00
72.00
74.00
76.00
66.80
67.27
66.80
66.80
66.60
66.60
68.60
68.60
40.00
41.00
33.30
34.00
35.00
36.00
37.00
38.00
33.40
33.63
33.40
33.40
32.30
33.30
33.30
33.30
PCICLK_F
Reg.
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
PCICLK (7:0)
Stop
Config.
AGP
DIVDER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ICS950905
Recommended Application:
VIA P4X266 chipset with PC133 or DDR memory.
3
AGPCLK (2:0)
RESET#
MULTISEL0
Board Target
Trace/Term Z
Reference R,
Iref =
VDD/(3*Rr)
Output
Current
Voh @ Z
0
50 ohms
Rr = 221 1%,
Iref = 5.00mA
Ioh = 4* I REF
1.0V @ 50
1
50 ohms
Rr = 475 1%,
Iref = 2.32mA
Ioh = 6* I REF
0.7V @ 50
I REF
950905 Rev - 11/26/01
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
ICS950905
Advance Information
Integrated
Circuit
Systems, Inc.
General Description
The ICS950905 is a single chip clock solution for desktop designs using the VIA P4X266 chipset with PC133 or DDR memory.
with PC133 or DDR memory. When used with a fanout buffer such as the ICS93712, ICS93715 or the ICS93718 provides all
the necessary clock signals for such a system.
The ICS950905 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This part
incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a
serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output
divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Pin Description
P IN NUM BE R
P IN NAM E
SEL 2 4 _ 4 8
T YPE
IN
DE S CRIP T IO N
Lat hc input t o select s eit her 24 or 48M Hz out put . 0 = 24M Hz; 1 = 68M Hz.
1
2, 6, 16, 24, 38
REF0
O UT
3. 3V, 14. 318M Hz r ef er ence clock out put .
VDD
PW R
3. 3V pow er supply.
4
X1
IN
5
X2
O UT
F S3
IN
Cr yst al input , has int er nal load cap ( 33pF) and f eedback r esist or f r om X2.
Cr yst al out put , nominally 14. 318M Hz. Has int er nal load cap ( 33pF) .
Logic input f r equency select bit . I nput lat ched at pow er on.
7
48M Hz
FS2
O UT
IN
3. 3V Fixed 48M Hz clock out put . .
Logic input f r equency select bit . I nput lat ched at pow er on.
8
3, 9, 13, 20, 25,
36, 44, 47
10
24_48M Hz
O UT
G ND
PW R
FS0
IN
PCI CLK_F
11
FS1
PCI CLK0
14
15
21, 19, 18, 17
22
27, 26, 23
WDTB
PCI CLK2
WDEN
O UT
IN
O UT
IN
O UT
IN
Select able 24 or 48M Hz out put .
G r ound pins f or 3. 3V supply.
Logic input f r equency select bit . I nput lat ched at pow er on.
3. 3V Fr ee r unning PCI clock out put
Logic input f r equency select bit . I nput lat ched at pow er on.
3. 3V PCI clock out put .
Wat ch dog t ime base select input . 1 = 290 ms/ st ep; 0 = 580 ms/ st ep.
3. 3V PCI clock out put .
Har dw ar e enable of w at ch dog cir cuit . Def ault saf e f r equency is 100M Hz. 0 = WD Disable; 1 = WD
Enable. This is a lat ch input .
PCI CLK3
O UT
3. 3V PCI clock out put .
PCI CLK ( 7: 4)
O UT
3. 3V PCI clock out put s.
PD#
AG P ( 2 : 0 )
IN
O UT
Asynchr onous act ive low input pin used t o pow er dow n t he device int o a low pow er st at e. The
int er nal clocks ar e disabled and t he VCO and t he cr yst al ar e st opped. The lat ency of t he pow er
dow n w ill not be gr eat er t han 3ms.
AG P out put s def ined as 2X PCI . These may not be st opped.
28
SCLK
IN
Clock pin for I2C circuitry 5V tolerant.
29
SDATA
I/O
Data pin for I2C circuitry 5V tolerant.
30
RESET#
O UT
33
Vtt_PWRGD#
IN
34, 39
CPUCLKC_(1:0)
O UT
35, 40
CPUCLKT_(1:0)
O UT
37
I REF
OUT
Real time system reset signal for frequency value or watchdog timmer timeout. This signal is active low.
This 3.3V LVTTL input is a level sensitive strobe used to determine when FS (3:0) and MULTSEL inputs
are valid and are ready to be sampled (active low).
"Complementory" clocks of differential pair CPU outputs. These are current outputs and external
resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current outputs and external resistors are
required for voltage bias.
This pin est ablishes t he r ef er ence cur r ent f or t he CPUCLK pair s. This pin r equir es a f ixed pr ecision
r esist or t ied t o gr ound in or der t o est ablish t he appr opr iat e cur r ent .
41
CPUCLK_PPC
OUT
42
CPUCLK_PPT
OUT
Complementory"" clocks of differential pair CPU outputs. These are 2.5V push-pull outputs.
True"" clocks of differential pair CPU outputs. These are 2.5V push-pull outputs.
43
VDDCPU_PP (2.5V)
PWR
Power for CPUCLK_CS outputs 2.5V.
45
46
48
IOAPIC
N/ C
VDDLAPI C
OUT
PWR
2.5V clock outputs
No connections to this pin.
Power for APIC clocks 2.5V.
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2
ICS950905
Advance Information
Integrated
Circuit
Systems, Inc.
General I2C serial interface information
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D2(H)
WR
WRite
Controller (Host)
T
starT bit
Slave Address D2(H)
WR
WRite
ICS (Slave/Receiver)
ICS (Slave/Receiver)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
Byte N + X - 1
ACK
X Byte
ACK
P
stoP bit
Byte N + X - 1
N
P
*See notes on the following page.
Third party brands and names are the property of their respective owners.
3
Not acknowledge
stoP bit
ICS950905
Advance Information
Integrated
Circuit
Systems, Inc.
Byte 0: Functionality and frequency select register (Default=0)
Description
Bit
Bit2
Bit
(2,7:4)
Bit 3
Bit 1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
010101-
PWD
Bit7 Bit6 Bit5 Bit4 CPUCLK AGPCLK PCICLK
MHz
MHz
MHz
FS3 FS2 FS1 FS0
Spread %
0
0
0
0
102.00
68.00
34.00
+/- 0.30% Center Spread
0
0
0
1
105.00
70.00
35.00
+/- 0.30% Center Spread
0
0
1
0
108.00
72.00
36.00
+/- 0.30% Center Spread
0
0
1
1
111.00
74.00
27.00
+/- 0.30% Center Spread
0
1
0
0
114.00
76.00
38.00
+/- 0.30% Center Spread
0
1
0
1
117.00
78.00
39.00
+/- 0.30% Center Spread
0
1
1
0
120.00
80.00
40.00
+/- 0.30% Center Spread
0
1
1
1
123.00
82.00
41.00
+/- 0.30% Center Spread
1
0
0
0
126.00
72.00
36.00
+/- 0.30% Center Spread
1
0
0
1
130.00
74.30
37.10
+/- 0.30% Center Spread
1
0
1
0
133.90
66.95
33.48
+/- 0.30% Center Spread
1
0
1
1
140.00
70.00
35.00
+/- 0.30% Center Spread
1
1
0
0
144.00
72.00
36.00
+/- 0.30% Center Spread
1
1
0
1
148.00
74.00
37.00
+/- 0.30% Center Spread
1
1
1
0
152.00
76.00
38.00
+/- 0.30% Center Spread
1
1
1
1
156.00
78.00
39.00
+/- 0.30% Center Spread
0
0
0
0
160.00
80.00
40.00
+/- 0.30% Center Spread
0
0
0
1
164.00
82.00
41.00
+/- 0.30% Center Spread
0
0
1
0
166.60
66.60
33.30
+/- 0.30% Center Spread
0
0
1
1
170.00
68.00
34.00
+/- 0.30% Center Spread
0
1
0
0
175.00
70.00
35.00
+/- 0.50% Center Spread
0
1
0
1
180.00
72.00
36.00
+/- 0.50% Center Spread
0
1
1
0
185.00
74.00
37.00
+/- 0.50% Center Spread
0
1
1
1
190.00
76.00
38.00
+/- 0.30% Center Spread
1
0
0
0
66.80
66.80
33.40
+/- 0.30% Center Spread
1
0
0
1
100.90
67.27
33.63
+/- 0.30% Center Spread
1
0
1
0
133.60
66.80
33.40
+/- 0.30% Center Spread
1
0
1
1
200.40
66.80
33.40
+/- 0.30% Center Spread
1
1
0
0
66.60
66.60
32.30
0 to - 0.6% Down Spread
1
1
0
1
100.00
66.60
33.30
0 to - 0.6% Down Spread
1
1
1
0
200.00
68.60
33.30
0 to - 0.6% Down Spread
1
1
1
1
133.30
68.60
33.30
0 to - 0.6% Down Spread
Frequency is selected by hardware select, latched inputs and Bit2 setting.
Frequency is selected by Bit 2,7:4
Normal
Spread spectrum enable
Watch dog safe frequency will be selected by latch inputs
Watch dog safe frequency will be programmed by Byte 10 bit (4:0)
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
Third party brands and names are the property of their respective owners.
4
1xxxx
0
1
0
ICS950905
Advance Information
Integrated
Circuit
Systems, Inc.
Byte 1: CPU Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Pin#
10
35, 34
40, 39
42, 41
PWD
1
1
1
1
0
1
1
1
Description
(Reserved)
PCICLK_F (Active/Inactive)
(Reserved)
(Reserved)
CPUCLKT/C_CS 1x/2x Strength(1 = 2x, 0 = 1x)
CPUCLKT/C1 (Active/Inactive)
CPUCLKT/C0 (Active/Inactive)
CPUCLKT/C_CS (Active/Inactive)
Byte 2: PCI Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Pin#
21
19
18
17
15
14
12
11
PWD
1
1
1
1
1
1
1
1
Description
PCICLK7
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Byte 3: Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Pin#
1
45
23
26
27
PWD
1
1
1
1
1
1
1
Description
Reserved
SEL 24_48, 0=24Mhz 1=48MHz
(Reserved)
(Reserved)
IOAPIC 1
AGPCLK 0
AGPCLK 1
AGPCLK 2
Byte 4: Frequency Select Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Pin#
7
8
1
PWD
X
X
X
X
1
1
X
1
Description
Latched FS3#
Latched FS2#
Latched FS1#
Latched FS0#
48MHz (Active/Inactive)
24_48MHz (Active/Inactive)
WDEN (Readback)
REF (Active/Inactive)
Third party brands and names are the property of their respective owners.
5
ICS950905
Advance Information
Integrated
Circuit
Systems, Inc.
Byte 5: Peripheral Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Pin#
X
X
X
X
X
X
X
X
PWD
-
Description
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Byte 6: Vendor ID Register
(1 = enable, 0 = disable)
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
Revision ID Bit3
Revision ID Bit2
Revision ID Bit1
Revision ID Bit0
Vendor ID Bit3
Vendor ID Bit2
Vendor ID Bit1
Vendor ID Bit0
PWD
X
X
X
X
0
0
0
1
Description
Revision ID values will be based on individual device's revision
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Byte 7: Revision ID and Device ID Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
Device ID7
Device ID6
Device ID5
Device ID4
Device ID3
Device ID2
Device ID1
Device ID0
PWD
Description
1
0
0
Device ID values will be based on individual device
1
"01h" in this case.
1
0
1
0
Byte 8: Byte Count Read Back Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
Byte7
Byte6
Byte5
Byte4
Byte3
Byte2
Byte1
Byte0
PWD
Description
0
0
0
Note: Writing to this register will configure byte count and how
0
many bytes will be read back, default is 0FH = 15 bytes.
1
1
1
1
Third party brands and names are the property of their respective owners.
6
ICS950905
Advance Information
Integrated
Circuit
Systems, Inc.
Byte 9: Watchdog Timer Count Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
WD7
WD6
WD5
WD4
WD3
WD2
WD1
WD0
PWD
Description
0
0
0
The decimal representation of these 8 bits correspond to X •
0
290ms the watchdog timer will wait before it goes to alarm mode
and reset the frequency to the safe setting. Default at power up is
1
16 • 290ms = 4.6 seconds.
0
0
0
Byte 10: Programming Enable bit 8 Watchdog Control Register
Bit
Name
PWD
Bi t 7
Program
Enable
0
Bi t 6
WD Enable
0
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
WD Alarm
S F4
S F3
S F2
S F1
S F0
0
0
1
0
0
0
Description
Programming Enable bit
0 = no programming. Frequencies are selected by HW latches or Byte0 1
= enable all I2C programing.
Watchdog Enable bit.
This bit will over write WDEN latched value. 0 = disable, 1 = Enable.
Watchdog Alarm Status 0 = normal 1= alarm status
Watchdog safe frequency bits. Writing to these bits will configure the safe
frequency corrsponding to Byte 0 Bit 2, 7:4 table
Byte 11: VCO Frequency M Divider (Reference divider) Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
Ndiv 8
Mdiv 6
Mdiv 5
Mdiv 4
Mdiv 3
Mdiv 2
Mdiv 1
Mdiv 0
PWD
X
X
X
X
X
X
X
X
Description
N divider bit 8
The decimal respresentation of Mdiv (6:0) corresposd to the
reference divider value. Default at power up is equal to the
latched inputs selection.
Byte 12: VCO Frequency N Divider (VCO divider) Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Ndiv 7
Ndiv 6
Ndiv 5
Ndiv 4
Ndiv 3
Ndiv 2
Ndiv 1
Ndiv 0
PWD
Description
X
X
X
The decimal representation of Ndiv (8:0) correspond to the
X
VCO divider value. Default at power up is equal to the
latched inputs selecton. Notice Ndiv 8 is located in Byte 11.
X
X
X
X
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7
ICS950905
Advance Information
Integrated
Circuit
Systems, Inc.
Byte 13: Spread Spectrum Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
SS 7
SS 6
SS 5
SS 4
SS 3
SS 2
SS 1
SS 0
PWD
Description
X
X
The Spread Spectrum (12:0) bit will program the spread
X
precentage. Spread precent needs to be calculated based on the
X
VCO frequency, spreading profile, spreading amount and spread
X
frequency. It is recommended to use ICS software for spread
X
programming. Default power on is latched FS divider.
X
X
Byte 14: Spread Spectrum Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reserved
Reserved
Reserved
SS 12
SS 11
SS 10
SS 9
SS 8
PWD
X
X
X
X
X
X
X
X
Description
Reserved
Reserved
Reserved
Spread Spectrum Bit 12
Spread Spectrum Bit 11
Spread Spectrum Bit 10
Spread Spectrum Bit 9
Spread Spectrum Bit 8
Byte 15: Output Divider Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
B it 1
B it 0
Name
CPU 0/1 Div 3
CPU 0/1 Div 2
CPU 0/1 Div 1
CPU 0/1 Div 0
CPU_CS Div 3
CPU_CS Div 2
CPU_CS Div 1
CPU_CS Div 0
PWD
0
1
0
1
0
1
0
1
Description
CPU 0/1 clock divider ratio can be configured via these
4 bits individually. For divider selection table refer to
Table 1. Default at power up is latched FS divider.
CPU_CS clock divider ratio can be configured via
these 4 bits individually. For divider selection table refer
to Table 1. Default at power up is latched FS divider.
Byte 16: Output Divider Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
AGP Div 3
AGP Div 2
AGP Div 1
AGP Div 0
APIC Div 3
APIC Div 2
APIC Div 1
APIC Div 0
PWD
0
1
0
1
0
1
0
1
Description
AGP clock divider ratio can be configured via these 4
bits individually. For divider selection table refer to
Table 1. Default at power up is latched FS divider.
IOAPIC clock divider ratio can be configured via these
4 bits individually. For divider selection table refer to
Table 1. Default at power up is latched FS divider.
Third party brands and names are the property of their respective owners.
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Byte 17: Output Divider Control Register
B it
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
N ame
PC I_INV
AGP
C PU 0/1_INV
C PU_C S_INV
PWD
0
0
0
0
PCI Div 3
PCI Div 2
PCI Div 1
PCI Div 0
1
0
0
1
D escription
PC IC LK Phase Inversi on bi t
AGP Phase Inversi on bi t
C PU 0/1 Phase Inversi on bi t
C PU_C S Phase Inversi on bi t
PCI clock divider ratio can be configured via these 4 bits
individually. For divider selection table refer to Table 2.
Default at power up is latched FS divider.
Table 1
Div (3:2)
Div (1:0)
Table 2
00
01
10
11
Div (3:2)
Div (1:0)
00
01
10
11
00
/2
/4
/8
/16
00
/4
/8
/16
/32
01
/3
/6
/12
/24
01
/3
/6
/12
/24
10
/5
/10
/20
/40
10
/5
/10
/20
/40
11
/7
/14
/28
/56
11
/9
/18
/36
/72
Byte 18: Group Skew Control Register
Bit
Name
PWD
Bi t 7
CPU_Skew 1
0
Bi t 6
Bi t 5
Bi t 4
Bi t 3
CPU_Skew 0
Reserved
Reserved
CPU_Skew 1
0
0
0
0
Bi t 2
Bi t 1
Bi t 0
CPU_Skew 0
Reserved
Reserved
0
0
0
Description
These 2 bits delay the CPUCLKC/T_CS with respect to
CPUCLKC/T (1:0)
00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps
Reserved
Reserved
These 2 bits delay the CPUCLKC/T (1:0) clock with respect to
CPUCLKC/T_CS
00 = 0ps 01 = 250ps 10 = 500ps 11 = 750ps
Reserved
Reserved
Byte 19: Group Skew Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
AGP_Skew 1
AGP_Skew 0
Reserved
Reserved
AGP_Skew 1
AGP_Skew 0
Reserved
Reserved
PWD
1
0
0
0
0
1
0
0
Description
These 2 bits delay the AGP (2:1) with respect to CPUCLK
00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps
Reserved
Reserved
These 2 bits delay the AGP_0 with respect to CPUCLK
00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps
Reserved
Reserved
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Byte 20: Group Skew Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
PCI_Skew 3
PCI_Skew 2
PCI_Skew 1
PCI_Skew 0
PCIF_Skew 3
PCIF_Skew 2
PCIF_Skew 1
PCIF_Skew 0
PWD
1
0
0
0
1
0
0
0
Description
These 4 bits can change the CPU to PCI (7:0) skew from 1.4ns 2.9ns. Default at power up is - 2.5ns. Each binary increment or
decrement of Bits (3:0) will increase or decrease the delay of the
PCI clocks by 100ps.
These 4 bits can change the CPU to PCIF skew from 1.4ns 2.9ns. Default at power up is - 2.5ns. Each binary increment or
decrement of Bit (3:0) will increase or decrease the delay of the
PCI clocks by 100ps.
Byte 21: Slew Rate Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
PCIF_1_Slew 1
PCIF_1_Slew 0
PCIF_0_Slew 1
PCIF_0_Slew 0
AGP (2:1)_Slew 1
AGP (2:1)_Slew 1
AGP_0_Slew 1
AGP_0_Slew 0
PWD
0
1
0
1
0
1
0
1
Description
PCIFclock slew rate control bits.
01 = strong:11 = normal; 10 = weak
PCI clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
AGP (2:1) clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
AGP_0 clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
Byte 22: Slew Rate Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
REF Slew 1
REF Slew 0
PCI (7:4) Slew 1
PCI (7:4) Slew 0
PCI (3:1) Slew 1
PCI (3:1) Slew 0
PCI0 Slew 1
PCI0 Slew 0
PWD
0
1
0
1
0
1
0
1
Description
REF clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
PCI (6:4) clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
PCI (3:1) clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
PCI0 clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
Byte 23: Slew Rate Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
Reserved
Reserved
Reserved
Reserved
48-24 Slew 1
48-24 Slew 0
48-24 Slew 1
48-24 Slew 0
PWD
X
X
X
X
0
1
0
1
Description
Reserved
Reserved
48-24 clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
48-24 clock slew rate control bits.
01 = strong: 11 = normal; 10 = weak
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10
ICS950905
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Integrated
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Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VD D = 3.3 V +5%
PAR AMETER
Input High Voltage
Input Low Voltage
SYMBOL
Input High Current
Input Low C urrent
Input Low C urrent
IIH
IIL1
IIL2
Operating
Supply C urrent
Power Down
Supply C urrent
Input frequency
Pin Inductance
Input C apacitance 1
Trans ition Tim e 1
IDD 3.3OP
IDD 3.3PD
Fi
VIN = VDD
VIN = 0 V; Inputs with no pull-up res is tors
VIN = 0 V; Inputs with pull-up res is tors
MIN
MAX
UN ITS
2
VSS-0.3
VD D +0.3
0.8
V
V
-5
-5
-200
5
mA
mA
mA
100
280
20
37
mA
mA
mA
mA
MHz
7
5
nH
pF
6
45
pF
pF
C L = 0 pF; Select @ 66M
C L = Full load
IR EF=2.32
IR EF= 5m A
VDD = 3.3 V;
TYP
L pin
C IN
Logic Inputs
C out
C INX
Out put pin capacitance
X1 & X2 pins
Ttrans
To 1s t cros s ing of target Freq.
3
mS
From 1s t cros s ing to 1% target Freq.
3
mS
3
10
10
mS
nS
nS
Settling Tim e 1
Ts
Clk Stabilization 1
TSTAB
tPZH ,tPZH
tPLZ ,tPZH
D elay
COND ITIONS
VIH
VIL
From VDD = 3.3 V to 1% target Freq.
output enable delay (all outputs )
output dis able delay (all outputs )
1
Guarenteed by des ign, not 100% tes ted in production.
Third party brands and names are the property of their respective owners.
11
27
1
1
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Electrical Characteristics - CPUCLKC/T
TA = 0 - 70º C; VDD = 3.3 V +/-5%; (unless otherwise stated)
PARAMETER
Current Source Output
Impedance
Output High Voltage
Output High Current
SYMBOL
ZO
CONDITIONS
VO = VX
VOH
IOH
tr
MIN
TYP
MAX
Ω
3000
0.71
-13.92
VR = 475W +1%; IREF = 2.32mA; IOH = 6*IREF
VOL = 20%, VOH = 80%
Rise Time1
Differential Crossover
VX
Note 3
Voltage1
dt
VT = 50%
Duty Cycle1
1
VT = 50%
tsk
Skew , CPU to CPU
1
t
VT = VX
Jitter, Cycle-to-cycle
jcyc-cyc
Notes:
1 - Guaranteed by design, not 100% tested in production.
UNITS
175
1.2
700
V
mA
ps
45
50
55
%
45
51
55
150
200
%
ps
ps
MIN
2
TYP
Electrical Characteristics - CPUCLKTC_CS
TA = 0 - 70º C; VDD = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
VOH2B
IOH = -12.0 mA
Output High Voltage
MAX UNITS
V
Output Low Voltage
VOL2B
IOL = 12 mA
0.4
V
Output High Current
IOH2B
VOH = 1.7 V
-19
mA
Output Low Current
IOL2B
VOL = 0.7 V
Rise Time
tr2B1
VOL = 0.4 V, VOH = 2.0 V
Differential Crossover
Voltage1
Duty Cycle
VX
55
%
dt2B1
VT = 1.25 V
45
55
%
1
VT = 1.25 V
175
ps
VT = 1.25 V
250
ps
VT = 1.25 V
VT = 1.25 V
150
ps
+250
ps
Jitter, Cycle-to-cycle
tjcyc-cyc2B
1
1
tj1s2B
tjabs2B1
-250
1
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
12
50
ns
45
tsk2B
Jitter, Absolute
mA
1.6
Note 3
Skew
Jitter, One Sigma
19
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Integrated
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Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = 3.3 V +/-5%; C L = 10-30 pF (unles s otherwis e s tated)
PARAMETER
SYMBOL
CONDITIONS
TYP
MAX
33.33
Output Frequency
F0
Output Im pedance
Output High Voltage
R DSN11
VOH1
Output Low Voltage
Output High Current
Output Low Current
VOL1
IOH1
IOL1
IOL = 1 m A
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
Ris e Tim e
tr11
Fall Tim e
Skew
tf11
d t11
tsk11
Jitter
tjcyc-cyc1
Duty Cycle
MIN
1
UNITS
MHz
55
Ω
V
-33
30
0.55
-33
38
V
mA
mA
VOL = 0.4 V, VOH = 2.4 V
0.5
2
ns
VOH = 2.4 V, VOL = 0.4 V
0.5
2
ns
VT = 1.5 V
45
55
%
500
ps
250
ps
MAX
UNITS
MHz
12
2.4
55
Ω
V
VO = VDD *(0.5)
IOH = -1 m A
12
2.4
VT = 1.5 V
VT = 1.5 V
1
Guarenteed by des ign, not 100% tes ted in production.
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V +/-5%; C L =10-30 pF (unles s otherwis e s tated)
PARAMETER
Output Frequency
SYMBOL
FO1
Output Im pedance
Output High Voltage
R DSP11
VOH1
CONDITIONS
VO = VDD *(0.5)
IOH = -1 m A
MIN
TYP
66.66
Output Low Voltage
VOL1
IOL = 1 m A
0.4
V
Output High Current
Output Low Current
IOH1
IOL1
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
-33
30
-33
38
mA
mA
Ris e Tim e
tr11
VOL = 0.4 V, VOH = 2.4 V
0.5
2
ns
Fall Tim e
VOH = 2.4 V, VOL = 0.4 V
0.5
2
ns
VT = 1.5 V
45
55
%
Skew
tf11
d t11
tsk11
VT = 1.5 V
500
ps
Jitter
tjcyc-cyc 1
VT = 1.5 V
250
ps
Duty Cycle
1
Guarenteed by des ign, not 100% tes ted in production.
Third party brands and names are the property of their respective owners.
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Electrical Characteristics - 48MHz
TA = 0 - 70C; VDD = 3.3 V +/-5%; C L = 10-30 pF (unles s otherwis e s tated)
PARAMETER
SYMBOL
Output Frequency
F O1
Output Im pedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
R DSN11
48DOT Ris e Tim e
48DOT Fall Tim e
VCH 48 USB
Ris e Tim e
VCH 48 USB
Fall Tim e
48 DOT to 48 USB
Skew
Duty Cycle
Jitter
CONDITIONS
MHz
-29
29
VOL = 0.4 V, VOH = 2.4 V
0.5
1
ns
VOH = 2.4 V, VOL = 0.4 V
0.5
1
ns
VOL = 0.4 V, VOH = 2.4 V
1
2
ns
VOH = 2.4 V, VOL = 0.4 V
1
2
ns
1
ns
1
tf1
12
2.4
55
VT=1.5V
VT = 1.5 V
VT = 1.5 V
tjcyc-cyc1
UNITS
0.55
-23
27
tf11
d t11
MAX
Ω
V
V
mA
mA
tr11
ts kew 1
TYP
48
VO = VDD *(0.5)
IOH = -1 m A
IOL = 1 m A
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
VOH1
VOL1
IOH1
IOL1
tr
MIN
VO = VDD *(0.5)
45
55
%
350
ps
MAX
UNITS
MHz
60
1
Guarenteed by des ign, not 100% tes ted in production.
Electrical Characteristics -
REF
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL =10-20 pF (unless otherwise stated)
PARAMETER
Output Frequency
SYMBOL
FO1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSP1
VOH1
VOL1
IOH1
IOL1
Rise Time
tr11
VOL = 0.4 V, VOH = 2.4 V
Fall Time
1
tf1
dt11
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
VT = 1.5 V
Duty Cycle
Jitter
1
1
tjcyc-cyc
CONDITIONS
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
14
MIN
TYP
-29
29
0.4
-23
27
Ω
V
V
mA
mA
1
4
ns
1
4
ns
45
55
500
%
ps
20
2.4
ICS950905
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Shared Pin Operation Input/Output Pins
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming
resistors should be located close to the series termination
resistor to minimize the current loop area. It is more important
to locate the series termination resistor close to the driver
than the programming resistor.
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm (10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Figure 1 shows a means of implementing this function when
Via to
VDD
Programming
Header
2K Via to Gnd
Device
Pad
8.2K Clock trace to load
Series Term. Res.
Fig. 1
Third party brands and names are the property of their respective owners.
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Integrated
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Power Down Waveform
0ns
25ns
1
50ns
2
VCO Internal
CPU 100MHz
3.3V 66MHz
PCI 33MHz
APIC 16.7MHz
PD#
SDRAM 100MHz
REF 14.318MHZ
48MHZ
Note
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all
the output clocks are driven Low on their next High to Low tranistiion.
2. Power-up latency <3ms.
3. Waveform shown for 100MHz
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0ns
10ns
20ns
30ns
Cycle Repeats
CPU 66MHz
CPU 100MHz
CPU 133MHz
SDRAM 100MHz
SDRAM 133MHz
3.5V 66MHz
PCI 33MHz
APIC 16.7MHz
REF 14.318MHz
USB 48MHz
Group Offset Waveforms
Third party brands and names are the property of their respective owners.
17
40ns
ICS950905
Advance Information
Integrated
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c
N
SYMBOL
L
E1
INDEX
AREA
E
1 2
h x 45°
D
A
A
A1
b
c
D
E
E1
e
h
L
N
α
A1
-Ce
SEATING
PLANE
b
.10 (.004) C
N
48
In Millimeters
COMMON DIMENSIONS
MIN
MAX
2.41
2.80
0.20
0.40
0.20
0.34
0.13
0.25
SEE VARIATIONS
10.03
10.68
7.40
7.60
0.635 BASIC
0.38
0.64
0.50
1.02
SEE VARIATIONS
0°
8°
VARIATIONS
D mm.
MIN
MAX
15.75
16.00
In Inches
COMMON DIMENSIONS
MIN
MAX
.095
.110
.008
.016
.008
.0135
.005
.010
SEE VARIATIONS
.395
.420
.291
.299
0.025 BASIC
.015
.025
.020
.040
SEE VARIATIONS
0°
8°
D (inch)
MIN
.620
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
300 mil SSOP Package
Ordering Information
ICS950904yFT
Example:
ICS XXXX y F - T
Designation for tape and reel packaging
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
Registered Company
9001
For more information on Integrated Circuit Systems Inc. or any of our products please visit our web site at:
http://www.icst.com
18
MAX
.630