ICS94229 Integrated Circuit Systems, Inc. Advance Information Programmable System Clock Chip for AMD - K7™ processor Features: • Programmable output frequency. • Programmable output rise/fall time. • Programmable slew and skew control for CPUCLK, PCICLK, AGP, REF, 48MHz and 24_48MHz. • Real time system reset output. • Spread spectrum for EMI control typically by 7dB to 8dB, with programmable spread percentage. • Watchdog timer technology to reset system if over-clocking causes malfunction. • Uses external 14.318MHz crystal. Pin Configuration PLL2 2 48MHz (1:0) 24_48MHz /2 XTAL OSC 2 REF (1:0) REF_F CPU DIVDER Stop CPUCLKT0 CPUCLKC0 CPU DIVDER Stop CPUCLK_CST0 CPUCLK_CSC0 PCI DIVDER Stop AGP DIVDER Stop SEL24_48# PCICLK9_E SDATA SCLK Control FS (3:0) Logic PD# PCI_STOP# CPU_STOP# AGP_STOP# Config. Reg. REF0/FS0* REF1/FS1* REF_F RATIO AGP_STOP#* GND CPUCLKT0 CPUCLKC0 VDDL CPUCLK_CST0 CPUCLK_CSC0 GND CPU_STOP#* PCI_STOP#* PD#* AVDD AGND SDATA SCLK GND AGP2 AGP1 AGP0 VDDAGP 48-Pin 300mil SSOP Functionality Block Diagram PLL1 Spread Spectrum 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 * Internal Pull-up Resistor of 120K to VDD Skew Specifications: • CPU - CPU: <175ps • PCI - PCI: <500ps • CPU (early - PCI: min=1.0ns, max=2.0ns • CPU cycle to cycle jitter: <250ps X1 X2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 VDDREF GND X1 X2 AVDD48 *FS2/48MHz *FS3/24_48MHz GND *WDEN/PCICLK_F *SEL24_48#/PCICLK0 PCICLK1 GND PCICLK2 PCICLK3 VDDPCI PCICLK4 PCICLK5 PCICLK6 GND PCICLK7 PCILCK8 PCICLK9_E VDDPCI SRESET# ICS94229 Recommended Application: VIA KT266 style chipset Output Features: • 1 - Differential pair open drain CPU clocks @ 2.5V • 1 - Differential pair push-pull CPU clocks @ 2.5V • 11 - PCI including 1 free running and 1 early @ 3.3V • 1 - 48MHz, @ 3.3V fixed • 1 - 24/48MHz @ 3.3V • 3 - REF @ 3.3V, 14.318MHz. 9 PCICLK (8:0) PCICLK_F 3 AGP (2:0) SRESET# FS3 FS2 FS1 FS0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU (MHz) 233.33 220.00 210.00 200.00 190.00 180.00 170.00 150.00 140.00 120.00 110.00 66.67 200.00 166.67 100.00 133.33 AG P (MHz) 77.78 73.33 70.00 66.67 76.00 72.00 68.00 75.00 70.00 60.00 66.00 66.67 66.67 66.67 66.67 66.67 PCICLK (MHz) 38.88 36.67 35.00 33.33 38.00 36.00 34.00 37.50 35.00 30.00 33.00 33.33 33.33 33.33 33.33 33.33 RATIO 94229 Rev - 05/31/01 Third party brands and names are the property of their respective owners. ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. ICS94229 Advance Information Pin Descriptions PIN NUMBER 1, 15, 23, 25, 2, 8, 12, 19, 29, 37, 43 3 4 5 6 7 9 10 21, 20, 18, 17, 16, 14, 13, 11 22 24 28, 27, 26 30 31 32 33 34 P I N NA M E VDD TYPE PWR Power supply, nominal 3.3V GND PWR Ground X1 X2 AVDD48 FS21, 2 48MHz FS31, 2 24_48MHz WDEN PCICLK_F SEL24_48#1, 2 PCICLK0 IN OUT PWR IN OUT IN OUT IN OUT IN OUT Crystal input, has internal load cap (36pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Has internal load cap (36pF) Power supply, nominal 3.3V Frequency select pin. Latched Input 48MHz output clock Frequency select pin. Latched Input 24 or 48MHz clock output Hardware enable of watch dog circuit. Default safe frequency is 100MHz. Free running PCI clock not affected by PCI_STOP# for power management. Logic input to select 24 or 48MHz for pin 7 output PCI clock output PCICLK (8:1) OUT PCI clock outputs. PCICLK9_E SRESET#1 AGP (2:0) SCLK SDATA AGND AVDD OUT OUT OUT IN I/O PWR PWR Early PCI clock. Leads general PCI clocks by 2ns. Can be stopped by PCI_STOP#. Real time system reset signal for watchdog tmer timeout. This signal is active low. AGP clock outputs Clock input of I2C input, 5V tolerant input Data pin for I2C circuitry 5V tolerant Analog ground Power supply, nominal 3.3V Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low This asynchronous input halts CPUCLKT, CPUCLKC & CUCLKC_CS clocks at logic "0" level when driven low. "Complementary" clock of differential pair CPU output. These push-pull outputs need an external 1.5V pull-up (push-pull) "True" clock of differential pair CPU output. These push-pull outputs need an external 1.5V pull-up (push-pull). Power supply for CPUCLKs, nominal 2.5V "True" clock of differential pair CPU output. These open drain outputs need an external 1.5V pull-up (open drain). "Complementary" clock of differential pair CPU output. These open drain outputs need an external 1.5V pull-up (open drain). Stops all AGP clocks at logic 0 level, when input low PD# IN 35 PCI_STOP# IN 36 CPU_STOP#1, 2 IN 38 CPUCLK_CSC0 OUT 39 CPUCLK_CST0 OUT 40 VDDL PWR 42 CPUCLKT0 OUT 41 CPUCLKC0 OUT 44 AGP_STOP# 45 RATIO OUT Outputs a "0" for 100MHz or "1" for 133MHz to the South Bridge 46 REF_F OUT 14.318 MHz free running reference clock., not afftected by REF_STOP# 47 48 IN DESCRIPTION FS11, 2 IN REF1 OUT FS01, 2 IN REF0 OUT Frequency select pin. Latched Input 14.318 MHz reference clock. Frequency select pin. Latched Input 14.318 MHz reference clock. Notes: 1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low. Third party brands and names are the property of their respective owners. 2 ICS94229 Advance Information General Description The ICS94229 is a main clock synthesizer chip for AMD-K7 based systems with VIA KT266 style chipset. This provides all clocks required for such a system. The ICS94229 belongs to ICS new generation of programmable system clock generators. It employs serial programming I2C interface as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring output to output skew, changing spread spectrum amount, changing group divider ratio and dis/enabling individual clocks. This device also has ICS propriety 'Watchdog Timer' technology which will reset the frequency to a safe setting if the system become unstable from over clocking. SRESET# Signal Description The SRESET# signal from ICS94229 system clock generator is a real time active low pulse that can be used to reset the system. The Open-Drain Nch output Reset# pin needs to be tied to the system reset line which has a pull-up resistor. When activated, the SRESET# output will be driven to a low with a 288ms pulse width. Third party brands and names are the property of their respective owners. 3 ICS94229 Advance Information General I2C serial interface information How to Write: How to Read: • • • • • • • • • • • • • • • Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending Byte 0 through Byte 16 (see Note 2) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends Byte 0 through byte 6 (default) ICS clock sends Byte 0 through byte X (if X(H) was written to byte 6). • Controller (host) will need to acknowledge each byte • Controller (host) will send a stop bit How to Read: How to Write: Controller (Host) Start Bit Address D2(H) Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver) ICS (Slave/Receiver) ACK Byte Count ACK Dummy Command Code ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK If 7H has been written to B6 ACK Dummy Byte Count Byte 0 Byte 0 Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4 Byte 5 Byte 5 Byte 6 Byte 6 ACK Byte 7 Byte 14 ACK If 1AH has been written to B6 ACK If 1BH has been written to B6 ACK If 1CH has been written to B6 ACK Stop Bit Byte 15 ACK Byte 16 ACK Stop Bit *See notes on the following page. Third party brands and names are the property of their respective owners. 4 Byte 14 Byte 15 Byte 16 ICS94229 Advance Information Brief I2C registers description for Programmable System Frequency Generator Register Name Byte Description PWD Default 2 Functionality & Frequency Select Register 0 Output frequency, hardware / I C frequency select, spread spectrum & output enable control register. See individual byte description Output Control Registers 1, 2, 3 Active / inactive output control registers/latch inputs read back. See individual byte description Vendor ID & Revision ID Registers 5, 6, 7 Byte 11 bit[7:4] is ICS vendor id - 1001. Other bits in this register designate device revision ID of this part. See individual byte description Byte Count Read Back Register 8 Writing to this register will configure byte count and how many byte will be read back. Do not write 00 H to this byte. 08 H Watchdog Enable Register 4 Writing to this register will configure the number of seconds for the watchdog timer to reset. 10 H Watchdog Control Registers Watchdog enable, watchdog status and programmable 'safe' frequency' can be configured in this register. 000,0000 VCO Control Selection Bit 4, 5 This bit select whether the output frequency is control by hardware/byte 0 configurations or byte 11&12 programming. 0 VCO Frequency Control Registers 9, 10 These registers control the dividers ratio into the phase detector and thus control the VCO output frequency. Depended on hardware/byte 0 configuration Spread Spectrum Control Registers 11, 12 These registers control the spread percentage amount. Depended on hardware/byte 0 configuration Group Skews Control Registers 13, 14 Increment or decrement the group skew amount as compared to the initial skew. See individual byte description Output Rise/Fall Time Select Registers 15, 16 These registers will control the output rise and fall time. See individual byte description Notes: 1. 2. 3. 4. 5. 6. 7. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Readback will support standard SMBUS controller protocol. The number of bytes to readback is defined by writing to byte 8. When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte 14 is written but not 15, neither byte 14 or 15 will load into the receiver. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only Block-Writes from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. Third party brands and names are the property of their respective owners. 5 ICS94229 Advance Information Serial Configuration Command Bitmap Byte0: Functionality and Frequency Select Register (default = 0) Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CPUCLK AGPCLK PCICLK Spre a d Pe rce nta ge SSB1 SSB0 FS3 FS2 FS1 FS0 0 0 0 0 0 0 233.33 77.78 38.88 +/- 0.25% Center Spread 0 0 0 0 0 1 220.00 73.33 36.67 +/- 0.25% Center Spread 0 0 0 0 1 0 210.00 70.00 35.00 +/- 0.25% Center Spread 0 0 0 0 1 1 200.00 66.67 33.33 +/- 0.25% Center Spread 0 0 0 1 0 0 190.00 76.00 38.00 +/- 0.25% Center Spread 0 0 0 1 0 1 180.00 72.00 36.00 +/- 0.25% Center Spread 0 0 0 1 1 0 170.00 68.00 34.00 +/- 0.25% Center Spread 0 0 0 1 1 1 150.00 75.00 37.50 +/- 0.25% Center Spread 0 0 1 0 0 0 140.00 70.00 35.00 +/- 0.25% Center Spread 0 0 1 0 0 1 120.00 60.00 30.00 +/- 0.25% Center Spread 0 0 1 0 1 0 110.00 66.00 33.00 +/- 0.25% Center Spread 0 0 1 0 1 1 66.67 66.67 33.33 +/- 0.25% Center Spread 0 0 1 1 0 0 200.00 66.67 33.33 +/- 0.25% Center Spread 0 0 1 1 0 1 166.67 66.67 33.33 +/- 0.25% Center Spread 0 0 1 1 1 0 100.00 66.67 33.33 +/- 0.25% Center Spread 0 0 1 1 1 1 133.33 66.67 33.33 +/- 0.25% Center Spread 1 0 0 0 0 0 200.00 66.67 33.33 0 to -0.5% Down Spread 1 0 0 0 0 1 166.67 66.67 33.33 0 to -0.5% Down Spread 1 0 0 0 1 0 100.00 66.67 33.33 0 to -0.5% Down Spread 1 0 0 0 1 1 133.33 66.67 33.33 0 to -0.5% Down Spread 1 0 0 1 0 0 200.00 66.67 33.33 +/- 0.50% Center Spread 1 0 0 1 0 1 166.67 66.67 33.33 +/- 0.50% Center Spread 1 0 0 1 1 0 100.00 66.67 33.33 +/- 0.50% Center Spread 1 0 0 1 1 1 133.33 66.67 33.33 +/- 0.50% Center Spread 1 1 1 0 0 0 200.00 66.67 33.33 +/- 0.75% Center Spread 1 1 1 0 0 1 166.67 66.67 33.33 +/- 0.75% Center Spread 1 1 1 0 1 0 100.00 66.67 33.33 +/- 0.75% Center Spread 1 1 1 0 1 1 133.33 66.67 33.33 +/- 0.75% Center Spread 1 1 1 1 0 0 200.00 66.67 33.33 0 to +0.5% Up Spread 1 1 1 1 0 1 166.67 66.67 33.33 0 to +0.5% Up Spread 1 1 1 1 1 0 100.00 66.67 33.33 0 to +0.5% Up Spread 1 1 1 1 1 1 133.33 66.67 33.33 0 to +0.5% Up Spread Bit 6: 0 = Hardware select; 1 = I2 C select. Default is OFF. Bit 7: 0 = Spread off; 1 = Spread spectrum enable. Default is OFF Third party brands and names are the property of their respective owners. 6 RATIO N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 0 1 N/A N/A 0 1 N/A N/A 0 1 N/A N/A 0 1 N/A N/A 0 1 ICS94229 Advance Information Byte 1: CPU, Active/Inactive Register (1= enable, 0 = disable) BIT PIN# PWD Byte 2: PCI, Active/Inactive Register (1= enable, 0 = disable) DESCRIPTION BIT PIN# PWD DESCRIPTION Bit 7 42, 41 1 CPUCLKT0, CPUCLKC0 Bit 7 20 1 PCICLK7 Bit 6 39, 38 1 CPUCLK_CST0, CPUCLK_CSC0 Bit 6 18 1 PCICLK6 17 1 PCICLK5 Bit 5 6 1 48MHz Bit 5 Bit 4 7 1 24_48MHz Bit 4 16 1 PCICLK4 Bit 3 - 1 FS0 (readback) Bit 3 14 1 PCICLK3 Bit 2 28 1 AGP2 Bit 2 13 1 PCICLK2 Bit 1 27 1 AGP1 Bit 1 11 1 PCICLK1 Bit 0 26 1 AGP0 Bit 0 10 1 PCICLK0 Byte 4: Watch Dog Register (1= enable, 0 = disable) Byte 3: PCI, REF, Active/Inactive Register (1= enable, 0 = disable) BIT PIN# PWD Bit 7 9 1 PCICLK_F DESCRIPTION Bit 6 22 1 PCICLK9_E BIT PIN# PWD Bit 7 - 0 Bit 5 - 1 FS1 (readback) Bit 6 - 0 Bit 4 21 1 PCICLK8 Bit 5 - 0 Bit 3 46 1 REF_F Bit 4 - 0 Bit 2 - 1 FS2 (readback) Bit 3 - 0 Bit 1 47 1 REF1 Bit 2 - 1 Bit 0 48 1 REF0 Bit 1 - 0 Bit 0 - 0 Byte 5: Vendor Specific Feature, Active/Inactive Register (1= enable, 0 = disable) BIT PIN# PWD - 0 SEL24_48# (readback) Bit 6 - 0 Bit 5 - 0 Bit 4 - 1 FS3 (readback) Watchdog status: 0=Normal 1=Alarm SSB1 Bit 3 - 1 FS3 Bit 2 - 1 FS2 Bit 1 - 1 FS1 Bit 0 - 0 FS0 The decimal representation of these 8 bits correspond to 290ms or 1ms the watchdog timer will wait before it goes to alarm mode and reset the frequency to the safe setting. Default at power up is 4X 580ms = 2.3 seconds. Byte 6: Vendor ID1 , Active/Inactive Register (1= enable, 0 = disable) DESCRIPTION Bit 7 DESCRIPTION Watch dog enable 0: stop 1: start M/N program enable BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Notes: PIN# - PWD DESCRIPTION 0 0 Device ID 0 1 0 0 Vendor ID 0 1 Note: Don’t write into this register, writing into this register can cause malfunction 1. Inactive means outputs are held LOW and are disabled from switching. 2. Watch dog timer is enabled or disabled via latch input WDEN during power up. User can change watch dog state with Byte 4 bit 7 after power up condition is established. Third party brands and names are the property of their respective owners. 7 ICS94229 Advance Information Byte 7: Vendor ID2, Active/Inactive Register (1= enable, 0 = disable) BIT PIN# PWD Bit 7 - X Byte 8: Byte Count Register (1= enable, 0 = disable) DESCRIPTION BIT PIN# PWD WDEN (readback) Bit 7 - 0 Reserved DESCRIPTION Bit 6 - 0 Revision ID Bit 6 - 0 Reserved Bit 5 - 0 Revision ID Bit 5 - 0 Reserved Bit 4 - 0 Revision ID Bit 4 - 0 Reserved Bit 3 - 0 Revision ID Bit 3 - 1 Reserved Bit 2 - 1 Revision ID Bit 2 - 0 Reserved Bit 1 - 0 Revision ID Bit 1 - 0 Reserved Bit 0 - 1 Revision ID Bit 0 - 0 Reserved Byte 9: VCO Frequency Control Register (1= enable, 0 = disable) Byte 10: VCO Frequency Control Register (1= enable, 0 = disable) BIT PIN# PWD BIT PIN# PWD Bit 7 - X VCO Divder Bit 0 DESCRIPTION Bit 7 - X VCO Divider Bit 8 Bit 6 - X REF Divder Bit 6 Bit 6 - X VCO Divider Bit 7 Bit 5 - X REF Divder Bit 5 Bit 5 - X VCO Divider Bit 6 Bit 4 - X REF Divder Bit 4 Bit 4 - X VCO Divider Bit 5 Bit 3 - X REF Divder Bit 3 Bit 3 - X VCO Divider Bit 4 Bit 2 - X REF Divder Bit 2 Bit 2 - X VCO Divider Bit 3 Bit 1 - X REF Divder Bit 1 Bit 1 - X VCO Divider Bit 2 Bit 0 - X REF Divder Bit 0 Bit 0 - X VCO Divider Bit 1 Byte 11: VCO Spread Spectrum Control Register (1= enable, 0 = disable) BIT PIN# PWD DESCRIPTION Byte 12: VCO Spread Spectrum Control Register (1= enable, 0 = disable) DESCRIPTION BIT PIN# PWD DESCRIPTION Bit 7 - X Spread Spectrum Bit 7 Bit 7 - X Reserved Bit 6 - X Spread Spectrum Bit 6 Bit 6 - X Reserved Bit 5 - X Spread Spectrum Bit 5 Bit 5 - X Reserved Bit 4 - X Spread Spectrum Bit 4 Bit 4 - X Spread Spectrum Bit 12 Bit 3 - X Spread Spectrum Bit 3 Bit 3 - X Spread Spectrum Bit 11 Bit 2 - X Spread Spectrum Bit 2 Bit 2 - X Spread Spectrum Bit 10 Bit 1 - X Spread Spectrum Bit 1 Bit 1 - X Spread Spectrum Bit 9 Bit 0 - X Spread Spectrum Bit 0 Bit 0 - X Spread Spectrum Bit 8 Third party brands and names are the property of their respective owners. 8 ICS94229 Advance Information Byte 13: Output Skew Control Register (1= enable, 0 = disable) Byte 14: Output Skew Control Register (1= enable, 0 = disable) BIT PIN# PWD Bit 7 - 0 DESCRIPTION Bit 6 - 0 Bit 5 - 0 Bit 4 - 0 Bit 4 - 0 Bit 3 - 0 Bit 3 - 0 Bit 2 - 0 Bit 2 - 0 Bit 1 - 0 Bit 0 - 0 CPUCLKC0/T0 Skew Control CPUCLKC_CST/C Skew Control Byte 15: Output Rise/Fall Time Select Register (1= enable, 0 = disable) BIT PIN# PWD Bit 7 - 0 Bit 6 - 0 Bit 5 - 1 Bit 1 - 0 Bit 0 - 0 BIT PIN# PWD BIT PIN# PWD - 0 CPUCLKT0 Bit 7 - 0 Bit 6 - 0 CPUCLKC0 Bit 6 - 0 Bit 5 - 0 CPUCLKT_CST Bit 5 - 1 Bit 4 - 0 CPUCLKC_CSC Bit 4 - 0 Bit 3 - 1 Bit 2 - 0 Bit 1 - 0 - 0 PCICLK(8:0) Skew Control AGP(2:0) Skew Control PCICLK9_E: Slew Rate Control Byte 16: Output Rise/Fall Time Select Register (1= enable, 0 = disable) Bit 7 Bit 0 DESCRIPTION DESCRIPTION AGP(2:0): Slew Rate Control REF(2:0): Slew Rate Control Third party brands and names are the property of their respective owners. 9 Bit 3 - 0 Bit 2 - 0 Bit 1 - 0 Bit 0 - 0 DESCRIPTION PCICLK(3:0): Slew Rate Control PCICLK(8:4): Slew Rate Control 48MHz: Slew Rate Control 24_48MHz: Slew Rate Control ICS94229 Advance Information Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating SYMBOL VIH VIL IIH IIL1 IIL2 IDD3.3OP66 VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; Select @ 66MHz Supply Current IDD3.3OP100 CL = 0 pF; Select @ 100MHz IDD3.3OP133 CL = 0 pF; Select @ 133MHz Power Down Input frequency Input Capacitance1 Clk Stabilization 1 CONDITIONS PD Fi CIN CINX VDD = 3.3 V; Logic Inputs X1 & X2 pins TSTAB From VDD = 3.3 V to 1% target Freq. Guaranteed by design, not 100% tested in production. Third party brands and names are the property of their respective owners. 10 TYP -5 -200 12 tCP U-P CI tCPU-AGP 1 MIN 2 VSS-0.3 14.318 MAX UNITS VDD+0.3 V 0.8 V µA 5 µA µA 180 mA 600 µA MHz pF pF 27 16 5 45 -100 -500 3 100 500 ms ICS94229 Advance Information Electrical Characteristics - REF TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time 1 1 Duty Cycle 1 1 SYMBOL VOH5 VOL5 IOH5 IOL5 CONDITIONS MIN 2.4 IOH = -12 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V 16 TYP MAX UNITS V 0.4 V -22 mA mA tr5 VOL = 0.4 V, VOH = 2.4 V 4 ns tf5 VOH = 2.4 V, VOL = 0.4 V 4 ns d t5 VT = 50% 55 % 45 Guaranteed by design, not 100% tested in production. Electrical Characteristics - CPUCLK (Open Drain) TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output Impedance SYMBOL ZO Output High Voltage VOH2B Output Low Voltage VOL2B Output Low Current IOL2B CONDITIONS VO = VX Termination to Vpull-up(external) Termination to Vpull-up(external) VOL = 0.3 V tr2B VOL = 0.3 V, VOH = 1.2 V 0.9 ns Fall Time1 tf2B VOH = 1.2 V, VOL = 0.3 V 0.9 ns Differential voltage-AC1 VDIF Note 2 0.4 Differential voltage-DC1 VDIF Note 2 0.2 VX Note 3 550 1100 mV dt2B tsk2B VT = 50% VT = 50% VT = VX VT = 50% 45 55 200 250 +250 % ps ps ps Rise Time 1 Differential Crossover Voltage1 Duty Cycle1 Skew1 Jitter, Cycle-to-cycle1 Jitter, Absolute1 tjcyc-cyc2B tjabs2B MIN 1 TYP MAX UNITS Ω 1.2 V 0.4 V 18 -250 mA Vpullup(external) + 0.6 Vpullup(external) + 0.6 Notes: 1 - Guaranteed by design, not 100% tested in production. 2 - VDIF specifies the minimum input differential voltages (VTR-VCP) required for switching, where VTR is the "true" input level and VCP is the "complement" input level. 3 - Vpullup(external) = 1.5V, Min = Vpullup (external)/2-150mV; Max=(Vpullup (external)/2)+150mV Third party brands and names are the property of their respective owners. 11 V V ICS94229 Advance Information Electrical Characteristics - PCICLK TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time 1 1 Duty Cycle 1 1 Skew (window) 1 SYMBOL VOH1 VOL1 IOH1 IOL1 CONDITIONS IOH = -11 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V MIN 2.6 TYP 19 MAX UNITS V 0.4 V -16 mA mA tr1 VOL = 0.4 V, VOH = 2.4 V 2 ns tf1 VOH = 2.4 V, VOL = 0.4 V 2 ns 55 % 500 ps d t1 Tsk 1 VT = 50% 45 VT = 1.5V Guaranteed by design, not 100% tested in production. Electrical Characteristics - PCICLK_F TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time 1 1 Duty Cycle 1 1 Skew (window) 1 SYMBOL VOH1 VOL1 IOH1 IOL1 CONDITIONS IOH = -11 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V MIN 2.6 12 TYP MAX UNITS V 0.4 V -12 mA mA tr1 VOL = 0.4 V, VOH = 2.4 V 2 ns tf1 VOH = 2.4 V, VOL = 0.4 V 2 ns 55 % 200 ps d t1 Tsk 1 VT = 50% 45 VT = 1.5V Guaranteed by design, not 100% tested in production. Third party brands and names are the property of their respective owners. 12 ICS94229 Advance Information Electrical Characteristics - 24MHz, 48MHz TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time 1 1 Duty Cycle 1 Jitter, One Sigma Jitter, Absolute 1 1 1 SYMBOL VOH5 VOL5 IOH5 IOL5 CONDITIONS IOH = -16 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V MIN 2.4 16 TYP MAX UNITS V 0.4 V -22 mA mA tr5 VOL = 0.4 V, VOH = 2.4 V 4 ns tf5 VOH = 2.4 V, VOL = 0.4 V 4 ns d t5 VT = 50% 55 % tj1s5 VT = 1.5 V 0.5 ns tjabs5 VT = 1.5 V 1 ns 45 -1 Guaranteed by design, not 100% tested in production. Third party brands and names are the property of their respective owners. 13 ICS94229 Advance Information Shared Pin Operation Input/Output Pins Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. The I/O pins designated by (input/output), serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Via to VDD Programming Header 2K Via to Gnd Device Pad 8.2K Clock trace to load Series Term. Res. Fig. 1 Third party brands and names are the property of their respective owners. 14 ICS94229 Advance Information AGP_STOP# Timing Diagram AGP_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the AGP clocks. for low power operation. AGP_STOP# is synchronized by the ICS94229. The AGPCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. AGPCLK on latency is less than AGPCLK and AGPCLK off latency is less than 3 AGPCLKs. This function is available only with MODE pin latched low. Notes: 1. All timing is referenced to the internal CPUCLK. 2. AGP_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside the ICS4229. 3. All other clocks continue to run undisturbed. 4. PD# and PCI_STOP# are shown in a high (true) state. 5. Only applies if MODE pin latched 0 at power up. CPU_STOP# Timing Diagram CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation. CPU_STOP# is synchronized by the ICS94229. All other clocks will continue to run while the CPUCLKs clocks are disabled. The CPUCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs. INTERNAL CPUCLK PCICLK CPU_STOP# PD# (High) CPUCLKT CPUCLKT_CST CPUCLKC CPUCLKC_CSC Notes: 1. All timing is referenced to the internal CPUCLK. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside the ICS94229. 3. All other clocks continue to run undisturbed. 4. PD# and PCI_STOP# are shown in a high (true) state. Third party brands and names are the property of their respective owners. 15 ICS94229 Advance Information PD# Timing Diagram The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete. PD# CPUCLKT CPUCLKC PCICLK VCO Crystal Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94229 device). 2. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz. PCI_STOP# Timing Diagram PCI_STOP# is an asynchronous input to the ICS94229. It is used to turn off the PCICLK clocks for low power operation. PCI_STOP# is synchronized by the ICS94229 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock. CPUCLK (Internal) PCICLK_F (Internal) PCICLK_F (Free-running) CPU_STOP# PCI_STOP# PCICLK Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94229 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS94229. 3. All other clocks continue to run undisturbed. 4. CPU_STOP# is shown in a high (true) state. Third party brands and names are the property of their respective owners. 16 ICS94229 Advance Information c N SYMBOL L E1 INDEX AREA E 1 2 h x 45° D A A A1 b c D E E1 e h L N α A1 -Ce SEATING PLANE b .10 (.004) C N 48 In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0° 8° VARIATIONS D mm. MIN MAX 15.75 16.00 In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0° 8° D (inch) MIN .620 MAX .630 Reference Doc.: JEDEC Publication 95, MO-118 10-0034 300 mil SSOP Package Ordering Information ICS94229yF-T Example: ICS XXXX y F - T Designation for tape and reel packaging Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS, AV = Standard Device Third party brands and names are the property of their respective owners. 17 ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice.