ICSSSTV16859 Integrated Circuit Systems, Inc. Preliminary Product Preview DDR 13-Bit to 26-Bit Registered Buffer Recommended Application: DDR Memory Modules Product Features: • Differential clock signals • Meets SSTL_2 signal data • Supports SSTL_2 class II specifications on outputs • low-voltage operation - VDD = 2.3V to 2.7V • Available in 64 pin TSSOP and 56 pin MLF2 packages Q13A Q12A Q11A Q10A Q9A VDDQ GND Q8A Q7A Q6A Q5A Q4A Q3A Q2A GND Q1A Q13B VDDQ Q12B Q11B Q10B Q9B Q8B Q7B Q6B GND VDDQ Q5B Q4B Q3B Q2B Q1B Truth Table1 Inputs Q Outputs RESET# CLK CLK# D Q L X or Floating X or Floating X or Floating L ¯ ¯ H H H L L H L or H L or H X Q0(2) H Notes: 2. H = High Signal Level L = Low Signal Level ↑ = Transition LOW-to-HIGH ↓ = Transition HIGH -to LOW X = Irrelevant 64-Pin TSSOP D1 VREF 48 49 51 35 45 43 56 Block Diagram RESET# R 16 Q1A CLK D1 32 Q1B Q7A 1 Q6A Q5A Q4A Q3A Q2A Q1A Q13B VDDQ Q12B Q11B Q10B Q9B Q8B 14 42 D10 D9 D8 D7 RB GND CLKB CLK VDDQ VDDI VREF D6 D5 29 D4 ICSSTV16859 15 28 Q7B Q6B VDDQ Q5B Q4B Q3B Q2B Q1B VDDQ D1 D2 VDDI VDDQ D3 To 12 Other Channels VDDQ GND D13 D12 VDD VDDQ GND D11 D10 D9 GND D8 D7 RESET# GND CLK# CLK VDDQ VDD VREF D6 GND D5 D4 D3 GND VDDQ VDD D2 D1 GND VDDQ 6.10 mm. Body, 0.50 mm. pitch Output level before the indicated steady state input conditions were established. CLK CLK# 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Q8A VDDQ Q9A Q10A Q11A Q12A Q13A VDDQ GND D13 D12 VDDI VDDQ D11 1. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ICSSSTV16859 Pin Configurations 56 pin MLF2 16859 Rev B 06/22/01 Third party brands and names are the property of their respective owners. PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. ICSSSTV16859 Preliminary Product Preview General Description The 13-bit to 26-bit ICSSTV16859 is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2 I/O Levels except for the RESET# input which is LVCMOS. Data flow from D to Q is controlled by the differential clock, CLK, CLK# and RESET#. Data is triggered on the positive edge of CLK. CLK# must be used to maintain noise margins. RESET# must be supported with LVCMOS levels as VREF may not be stable during power-up. RESET# is asynchronous and is intended for power-up only and when low assures that all of the registers reset to the Low State, Q outputs are low, and all input receivers, data and clock are switched off. The ICSSSTV16859 supports low-power standby operation. When RESET# is LOW, the differential input receivers are disabled, and are allowed. In addition, when RESET# is LOW, all registers are reset, and all outputs are forced LOW. The LVCMOS RESET# input must always be held at a valid logic HIGH or LOW level. To ensure defined outputs from the register before a stable clock has been supplied, RESET# must be held in the LOW state during power up. In the DDR DIMM application RESET# is specified to be completely asynchronous with respect to CK and CK#. Therefore, no timing relationship can be guaranteed between the two. When entering RESET#, the register will be cleared and the outputs will be driven LOW quickly, relative to the time to disable the differential input receivers, thus ensuring no glitches on the output. However, when coming out of RESET#, the register will become active quickly, relative to the time to enable the differential input receivers. When the data inputs are LOW, and the clock is stable, during the time from the LOW-to-HIGH transition of RESET# until the input receivers are fully enabled, the design must ensure that the outputs will remain LOW. Pin Configuration PIN NAME Q (13:1) GND VDDQ D (13:1) CLK CLK# VDD RESET# VREF Center PAD TYPE OUTPUT PWR PWR INPUT INPUT INPUT PWR INPUT INPUT PWR DESCRIPTION Data output Ground Output supply voltage, 2.5V nominal Data input Positive master clock input Negative master clock input Core supply voltage, 2.5V nominal Reset (active low) Input reference voltage, 2.5V nominal Ground (MLF2 package only) Third party brands and names are the property of their respective owners. 2 ICSSSTV16859 Preliminary Product Preview Absolute Maximum Ratings Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Voltage 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Voltage 1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Clamp Current . . . . . . . . . . . . . . . . . . . . . . . Output Clamp Current . . . . . . . . . . . . . . . . . . . . . Continuous Output Current . . . . . . . . . . . . . . . . . VDD, VDDQ or GND Current/Pin . . . . . . . . . . . . –65°C to +150°C -0.5 to 3.6V -0.5 to VDD +0.5 -0.5 to VDDQ +0.5 ±50 mA ±50mA ±50mA ±100mA Package Thermal Impedance3 55°C/W .................... Notes: 1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. This current will flow only when the output is in the high state level V0 >VDDQ. 3. The package thermal impedance is calculated in accordance with JESD 51. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Recommended Operating Conditions PARAM ETER VDD V DDQ VREF VTT VI VIH VIH VIL VIL VIH VIL VICR VID 1 DESCRIPTION Supply Voltage I/O Supply Voltage Reference Voltage VREF = 0.5X VDDQ Termination Voltage Input Voltage DC Input High Voltage AC Input High Voltage DC Input Low Voltage AC Input Low Voltage Input High Voltage Level Input Low Voltage Level Common mode Input Range Differential Input Voltage Data Inputs RESET# CLK, CLK# V IX Cross Point Voltage of Differential Clock Pair IOH IOL TA High-Level Output Current Low-Level Output Current Operating Free-Air Temperature M IN 2.3 2.3 1.15 VREF -0.04 0 VREF +0.15 VREF +0.31 Third party brands and names are the property of their respective owners. 3 M AX 2.7 2.7 1.35 V REF -0.04 VDD UNITS V REF -0.15 V REF -0.31 V 1.7 0.97 0.36 (VDDQ/2) -0.2 0 Guarenteed by design, not 100% tested in production. TYP 2.5 2.5 1.25 VREF 0.7 1.53 (VDDQ/2) +0.2 -20 20 70 mA °C ICSSSTV16859 Preliminary Product Preview Electrical Characteristics - DC T A = 0 - 70º C; VDD = 2.5 V +/-200mV, VDDQ=2.5V 200mV; (unless otherwise stated) SYMBOL VIK VOH VOL II IDD IDDD rOH rOL rO(∆ ) Ci PARAMETERS CONDITIONS VDD II = -18mA IOH = -100µA IOH = -16mA IOL = 100µA IOL = 16mA All Inputs VI = VDD or GND Standby (Static) RESET# = GND VI = VIH (AC#) or VIL (AC), Operating (Static) RESET# = VDD RESET = VDD, VI = VIH(AC) Dynamic operating or VIL (AC), CK and CK# clock only switching 50% duty cycle. I = 0 O RESET# = VDD, VI = VIH(AC) or VIL (AC), CK and CK# Dynamic Operating switching 50% duty cycle. per each data input One data input switching at half clock frequency, 50% duty cycle IOH = 20mA Output High I Output Low OL = 20mA [rOH - rOL] each separate bit Data Inputs CK and CK# 2.3V 2.3V-2.7 2.3V 2.3-2.7V 2.3V 2.7V UNITS -1.2 VDD -0.2 1.95 V 0.2 0.35 ±5 .01 µA µA TBD mA TBD µ/clock MHz TBD µA/ clock MHz/data 7 20 Ω 2.3-2.7V 7 20 Ω 4 Ω 3.5 3.5 pF VI = VREF ±350Mv VICR = 1.25V, VI(PP) = 360mV 2.5V 4 MAX 2.3-2.7V 2.5V Third party brands and names are the property of their respective owners. TYP 2.7V IO = 20mA, T A = 25° C Notes: 1 - Guaranteed by design, not 100% tested in production. MIN 2.5 2.5 ICSSSTV16859 Preliminary Product Preview Timing Requirements (over recommended operating free-air temperature range, unless otherwise noted) VDD = 2.5V ±0.2V SYM BOL PARAM ETERS M IN M AX fclo ck Clock frequency 200 t PD Clock to output time TBD t RST Reset to output time 5 t SL Output slew rate 1 4 0.75 Setup time, fast slew rate 2, 4 Data before CK↑ , CK# ↓ t SU 0.9 Setup time, slow slew rate 3 , 4 0.75 Hold time, fast slew rate 2 , 4 Th Data after CK↑ , CK# ↓ 0.9 Hold time, slow slew rate 3 , 4 1 - Guaranteed by design, not 100% tested in production. Note s: 2 - For data signal input slew rate =≥ 1V/ns. 3 - For data signal input slew rate =≥=0.5V/ns and < 1V/ns. 4 - CLK, CLK# signals input slew rates are =≥=1V/ns. Switching Characteristics (over recommended operating free-air temperature range, unless otherwise noted) From To V DD = 2.5V ±0.2V UNITS SYM BOL M IN TYP M AX (Input) (Output) fmax 200 M Hz t PD CLK, CLK# Q 1.1 2.8 ns CLK, CLK# Q 5 ns t ph 1 Third party brands and names are the property of their respective owners. 5 UNITS M Hz ns ns V/ns ns ns ns ns ICSSSTV16859 Preliminary Product Preview VTT RL=50Ω From Output Under Test Test Point CL = 30 pF (see Note 1) Load Circuit LVCMOS RESET# Input VDD VDD/2 VDD/2 tinact VI(pp) 0V Timing Input tact IDD (see note 2) tPHL 90% IDDH 10% VICR VICR IDDL tPHL VTT Voltage and Current Waveforms Inputs Active and Inactive Times VTT VOH VOL Output Voltage Waveforms - Propagation Delay Times tw VIH VREF Input VREF VIL Voltage Waveforms - Pulse Duration LVCMOS RESET# Input VI(pp) Timing Input VIL VICR tPHL tSU Input VIH VDD/2 VREF VOH Output th VTT VOL VIH VREF Voltage Waveforms - Propagation Delay Times VIL Voltage Waveforms - Setup and Hold Times Parameter Measurement Information (VDD = 2.5V ±0.2V) Notes: 1. CL incluces probe and jig capacitance. 2. IDD tested with clock and data inputs held at VDD or GND, and Io = 0mA. 3. All input pulses are supplied by generators having the following chareacteristics: PRR ≤10 MHz, Zo=50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified). 4. The outputs are measured one at a time with one transition per measurement. 5. VTT = VREF = VDDQ/2 6. VIH = VREF + 310mV (ac voltage levels) for differential inputs. VIH = VDD for LVCMOS input. 7. VIL = VREF -310mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input. 8. tPLH and tPHL are the same as tpd Third party brands and names are the property of their respective owners. 6 ICSSSTV16859 Preliminary Product Preview c N In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS D 8.10 BASIC 0.319 BASIC E E1 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC e L 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS N 0° 8° 0° 8° α aaa -0.10 -.004 L E1 INDEX AREA E 1 2 D A A2 A1 -Ce VARIATIONS SEATING PLANE b N 64 aaa C D mm. MIN 16.90 D (inch) MAX 17.10 MIN .665 MAX .673 R ef erenc e D o c .: J E D E C P ub lic at io n 9 5, M O -153 10 -0 0 3 9 6.10 mm. Body, 0.50 mm. pitch TSSOP (0.020 mil) (240 mil) Ordering Information ICSSSTV16859yG-T Example: ICS XXXX y G - PPP - T Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type G=TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device Third party brands and names are the property of their respective owners. 7 PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. ICSSSTV16859 Preliminary Product Preview Symbol Common Dime ns ions A - 0.85 1.00 A1 0.00 0.01 0.05 A2 - 0.65 0.80 A3 56 pin MLF2 0.20 BSC D 8.00 BSC D1 7.75 BSC E 8.00 BSC E1 7.75 BSC Q 12 P 0.24 0.42 0.60 R 0.13 0.17 0.23 Pitch Varation D e 0.50 BSC N 56 Nd 14 Ne Ordering Information ICSSSTV16859yK 14 L 0.30 0.40 0.50 b 0.18 0.23 0.30 Q 0.00 0.20 0.45 D2 5.95 6.10 6.25 E2 5.95 6.10 6.25 Example: ICS XXXX y K - PPP - T Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device Third party brands and names are the property of their respective owners. 8