PI74SSTV32852 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 24-Bit to 48-Bit Registered Buffer Product Features Product Description • PI74 SSTV32852 is designed for low-voltage operation, VDD = VDDQ = 2.3V to 2.7V Pericom Semiconductor’s PI74SSTV32852 logic circuit is produced using the Company’s advanced 0.35 micron CMOS technology, achieving industry leading speed. • Supports SSTL_2 Class II specifications on outputs All inputs are compatible with the JEDEC standard for SSTL_2, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible. • All Inputs are SSTL_2 Compatible, except RESET which is LVCMOS. • Designed for DDR Memory The device operates from a differential clock (CK and CK). Data registered at the crossing of CK going HIGH, and CK going LOW. • Packaging (Pb-free available): 114-Ball LFBGA The PI74SSTV32852 supports low-power standby operation. When RESET is LOW, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW, all registers are reset, and all outputs are forced LOW. The LVCMOS RESET input must always be held at a valid logic HIGH or LOW level. Logic Block Diagram A3 A4 CLK CLK D1 VREF A2 R3 R V RESET T2 R4 CLK D Q1A A5 To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the LOW state during power up. Q1B In the DDR DIMM application, RESET is specified to be completely asynchronous with respect to CK and CK. Therefore, no timing relationship can be guaranteed between the two. When entering RESET, the register will be cleared and the outputs will be driven LOW quickly, relative to the time to disable the differential input receivers, thus ensuring no glitches on the output. However, when coming out of RESET, the register will become active quickly, relative to the time to enable the differential input receivers. When the data inputs are LOW, and the clock is stable, during the time from the LOW-to-HIGH transition of RESET until the input receivers are fully enabled, the design must ensure that the outputs will remain LOW. TO 23 OTHER CHANNELS Product Pin Description Pin Name RESET De s cription Reset (Active Low) LVCMOS CLK Clock Input, Positive Differential Input CLK Clock Input, Negative Differential Input D Data Input Q Data Output Pericom’s PI74SSTV32852 is characterized for operation from 0° to 70°C. GND Ground VDD Core Supply Voltage, 2.5V Nominal VDDQ Output Supply Voltage, 2.5V Nominal VREF Input Reference Voltage, 1.25V Nominal Truth Table(1) Inputs Outputs RESET CLK CLK D Q L X or Floating X or Floating X or Floating L H ↑ ↓ H H Η ↑ ↓ L L H L or H L or H X Qo(2) Notes: 1. H = High Signal Level; L = Low Signal Level; ↑ = Transition LOW-to-HIGH; ↓ = Transition HIGH-to-LOW X = Irrelevant or floating 2. Output level before the indicated steady state input conditions were established. 1 PS8615A 06/23/02 PI74SSTV32852 24-Bit to 48-Bit Registered Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Product Pin Configuration 1 2 3 4 5 6 A Q 2A Q1A CLK CLK Q 1B Q 2B B Q 3A VDDQ GND GND VDDQ Q 3B C Q 5A Q 4A VDDQ VDDQ Q 4B Q 5B D Q 7A Q 6A GND GND Q 6B Q 7B E Q 8A GND VDDQ VDDQ GND Q 8B F Q 10 A Q 9A VDDQ VDDQ Q 9B Q10B G Q12A Q11A GND GND Q11B Q12B H Q 13 A VCC VDDQ VDDQ VCC Q13B J Q 14 A Q15A GND GND Q15B Q14B K Q17A Q16A VDDQ VDDQ Q16B Q17B L Q 18 A Q19A GND GND Q19B Q18B M Q 20A VDDQ GND GND VDDQ Q 20B N Q 22A Q21A VDDQ VDDQ Q21B Q 22B P Q 23A VDDQ GND GND VDDQ Q 23B R Q 24A VCC RESET VREF VCC Q 24B T D2 D1 D6 D18 D13 D14 U D4 D3 D10 D22 D15 D16 V D5 D7 D11 D23 D19 D17 W D8 D9 D12 D24 D21 D20 NB Package (Top View) 1 2 3 4 5 6 A B C D E F G H J K L M N P R T U V W 2 PS8615A 06/23/02 PI74SSTV32852 24-Bit to 48-Bit Registered Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Ite m Symbol/Conditions Ratings Units Tstg –65 to 150 °C VDD or VDDQ –0.5 to 3.6 VI –0.5 to VDD +0.5 VO –0.5 to VDDQ +0.5 Input clamp current IIK , VI <0 or VI >VDD –50 Output clamp current IO K , VO <0 or VO >VDDQ ± 50 IO , VO = 0 to VDDQ ± 50 IDD, IDDQ or IGN D ±100 θJA 36 Storage temperature Supply voltage Input voltage(1,2) Output voltage(1,2) Continuous output current VDD, VDDQ or GND current/pin Package Thermal Impedance(3) V mA °C/W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. This value is limited to 3.6V Maximum. 3. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions(4) Parame te rs De s cription M in. Nom. M ax. VDD Supply Voltage 2.3 2.5 2.7 VDDQ I/O Supply Voltage 2.3 2.5 2.7 VREF Reference Voltage VREF = 0.5X VDDQ 1.15 1.25 1.35 VTT Termination Voltage VREF –0.04 VREF VREF +0.04 VI Input Voltage 0 Units VDD VIH AC High - Level Input Voltage VREF +310mV VIL AC Low - Level Input Voltage VIH DC High - Level Input Voltage VIL DC Low - Level Input Voltage VIH High - Level Input Voltage VIL Low - Level Input Voltage VICR Common- mode input range VID Differential Input Voltage IOH High- Level Output Current –20 IOL Low- Level Output Current 20 TA Operating Free- Air Temperature Data Inputs VREF – 310mV V VREF +150mV VREF –150mV Reset CK , CK 1.7 0.7 0.97 1.53 360 0 70 mA ºC Note: 4. The RESET input of the device must be held at VDD or GND to ensure proper device operation. The differential inputs must not be floating, unless RESET is LOW. 3 PS8615A 06/23/02 PI74SSTV32852 24-Bit to 48-Bit Registered Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Electrical Characteristics (Over the Operating Range, TA = 0°C to +70°C, VDD = 2.5V ± 200mV, VDDQ = 2.5V ± 200mV) Parame te rs VIK 2.3V M ax. Units –1.2 IO H = –16mA 2.3V 1.95 IO L = 100µA 2.3V- 2.7V 0.2 IO H =16mA 2.3V 0.35 All Inputs VI = VDD or GND 2.7V ±5 Standby (Static) RESET = GND 10 Operating (Static) RESET = VDD, VI = VIH(AC ) or VIL (AC ) 35 mA Dynamic operating clock only RESET = VDD, VI = VIH(AC ) or VIL(AC ), CK and CK switching 50% duty cycle. 46 µA/ MHz Dynamic Operating per each data input RESET = VDD, VI = VIH(AC ) or VIL(AC ), CK and CK switching 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle. 12 µA/ clock MHz/ data input ROH Output High Ci Typ.(1) VDD –0.2 IDDD ROL II = –18mA M in. 2.3V- 2.7V VO L IDD VDD IO H = –100µA VO H II Te s t Conditions IO = 0 IO = - 20mA 2.7V 2.3V to 2.7V Output Low IO = 20mA Data Inputs VI = VREF ±350mV CK and CK VIC R =1.25V, VI(P P ) = 360mV RESET VI = VDD or GND V 2.5 7.0 20 7.0 20 3.0 4.0 5.5 6.5 8.0 9.5 3.5 4.35 5.0 µA Ohm pF Note: 1. All typical values are at VDD = 2.5V, T A = 25°C. 4 PS8615A 06/23/02 PI74SSTV32852 24-Bit to 48-Bit Registered Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Timing Requirements (over recommended operating free-air temperature range, unless otherwise noted) VDD = 2.5V ±0.2V M in. fclock tw Clock frequency 200 Pulse Duration, CK, CK high or low Differential Inputs active time, data inputs must be low after RESET high. tinact† Differential Inputs inactive time, data and clock inputs must be held at valid levels (not floating) after RESET Low. Setup time, fast slew rate(5,7) Setup time, slow slew rate(6,7) Hold time, fast slew rate(5,7) th Hold time, slow slew rate(6,7) Units MHz 2.5 tact† tsu M a x. 22 ns 0.75 Data before CK↑, CK↓ 0.9 0.75 Data after CK↑, CK↓ 0.9 Notes: 5. For data signal input slew rate ≥1V/ns. 6. For data signal input slew rate ≥0.5V/ns and <1V/ns. 7. CLK, CLK signals input slew rates are ≥1V/ns. † This parameter is not necessarily production tested. Switching Characteristics (Over recommended operating free-air temperature range, unless otherwise noted.) (See test circuits and switching waveforms). Parame te r From (Input) VD D = 2.5V ±0.2V To (Output) M in. fmax Typ. Units M a x. 200 tpd CLK, CLK Q tphl RESET Q 1.1 MHz 3.3 ns 5.0 5 PS8615A 06/23/02 PI74SSTV32852 24-Bit to 48-Bit Registered Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Test Circuit and Switching Waveforms LVCMOS RESET Input VTT VDD VDD/2 RL = 50 ohms 0V t inact From Output Under Test tact IDD(9) IDDL Load Circuit Voltage and Current Waveforms Input Active and Inactive Times Timing Input tw VIH VREF CL = 30pF(8) IDDH 90% 10% Input Test Point Output VREF VICR VICR VI(PP) t PLH t PHL VTT VTT VOL VIL Voltage Waveforms - Propagation Delay Times Voltage Waveforms - Pulse Duration Timing Input VICR tsu LVCMOS RESET Input VI(PP) VREF VIH VDD/2 VIL t PHL th VIH Input VOH Output VREF VOH VTT VOL VIL Voltage Waveforms - Propagation Delay Times Voltage Waveforms - Setup and Hold Times Parameter Measurement Information (VDD = 2.5V ±0.2V) Notes: 8. CL includes probe and jig capacitance. 9. IDD tested with clock and data inputs held at VDD or GND, and IO = 0mA. 10. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 ohms. Input slew rate = 1V/ns ±20% (unless otherwise specified). 11. The outputs are measured one at a time with one transition per measurement. 12. VTT = VREF = VDDQ/2 13. VIH = VREF + 310mV (ac voltage levels) for SSTL inputs. VIH = VDD for LVCMOS input. 14. VIL = VREF + 310mV (ac voltage levels) for SSTL inputs. VIL = GND for LVCMOS input. 15. tPLH and tPHL are the same as tpd. 6 PS8615A 06/23/02 PI74SSTV32852 24-Bit to 48-Bit Registered Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 114-Ball LFBGA (NB) Package 0.80 0.39 ± 0.05 0.75 0.31 BSC 0.87mm. Min. (2 layer) 0.90mm. Min. (4 layer) 1.40 Max. (2 layer) 1.45 Max. (4 layer) Ordering Information Orde ring Code Package Code Package Type PI74SSTV32852NB NB 114- Ball LFBGA PI74SSTV32852NBE NB Pb- free, 114- Ball LFBGA Notes: 1. Thermal characteristics can be found on the company web site at http://www.pericom.com/packaging/mechanicals.php Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 7 PS8615A 06/23/02