MK3722 VCXO PLUS AUDIO CLOCK FOR STB Description Features The MK3722 is a low cost, low jitter, high performance VCXO and PLL clock synthesizer designed to replace expensive discrete VCXOs and multipliers. The patented on-chip Voltage Controlled Crystal Oscillator accepts a 0 to 3.3 V input voltage to cause the output clocks to vary by ±115 ppm. Using ICS’ analog/digital Phase-Locked Loop (PLL) techniques, the device uses an inexpensive 27 MHz pullable crystal input to produce a reference output and a selectable audio clock. • • • • • • Packaged in 16 pin TSSOP Replaces a VCXO and oscillator Operating voltage of 3.3V Provides output of 27 MHz plus audio clock Uses an inexpensive 27 MHz pullable crystal On-chip patented VCXO with pull range of 230 ppm (minimum) • VCXO tuning voltage of 0 to 3.3 V • Advanced, low power, sub-micron CMOS process ICS manufactures the largest variety of VCXO based timing devices for all applications. Consult ICS to eliminate VCXOs, crystals, and oscillators from your board. The frequency of the on-chip VCXO is adjusted by an external control voltage connected to VIN. Because VIN is a high impedance input, it can be driven directly from an PWM RC integrator circuit. Block Diagram VDD 3 PLL/Clock Synthesis Circuitry 3 S2:S0 VIN X1 27 MHz Pullable Crystal X2 ACLK Voltage Controlled Crystal Oscillator 27MHz 3 GND 1 MDS 3722 B In tegr ated C ir cu it S yst ems PDTS ● 5 25 Ra ce Str eet, San Jose, C A 95 126 Revision 092502 ● tel ( 408) 2 95-9 800 ● www. i c s t. c om MK3722 VCXO PLUS AUDIO CLOCK FOR STB Pin Assignment Audio Clock Select Table X2 1 16 S1 S2 S1 S0 ACLK (MHz) X1 2 15 NC 0 0 0 8.192 VD D 3 14 VDD 0 0 1 11.2896 VD D 4 13 S0 0 1 0 12.288 VIN 5 12 27M 0 1 1 16.9344 GND 6 11 GND GND 7 10 AC LK 1 0 0 18.432 PD TS 8 9 1 0 1 16.384 1 1 0 22.5792 1 1 1 24.576 S2 16 Pin 4.40m m body, 0.65m m pitch TSSO P Pin Descriptions Pin Number Pin Name Pin Type 1 X2 Output Crystal connection. Connect to a 27MHz fundamental mode pullable crystal. 2 X1 Input Crystal connection. Connect to a 27MHz fundamental mode pullable crystal. 3 VDD Power Connect to +3.3 V. 4 VDD Power Connect to +3.3 V. 5 VIN Input 6 GND Power Connect to ground. 7 GND Power Connect to ground. 8 PDTS Power Power Down Tri-state. This pin powers down entire chip and tri-states the outputs when low. Internal pull-up. 9 S2 Input 10 ACLK Output Audio clock output per table above. 11 GND Power Connect to ground. 12 27M Output 27MHz reference clock output. 13 S0 Input 14 VDD Power 15 NC -- 16 S1 Input Voltage input to VCXO. Zero to 3.3V signal which controls the VCXO frequency. Select input S2. Selects ACLK per table above. Internal pull-up. Select input S0. Selects ACLK per table above. Internal pull-up. Connect to +3.3V. No connect. Do not connect anything to this pin. Select input S1. Selects ACLK per table above. Internal pull-up. 2 MDS 3722 B Int egrat ed C ircuit Syste ms Pin Description ● 525 R ace S tr eet, San Jose, CA 95126 Revision 092502 ● t el (40 8) 295 -9800 ● w ww. ic s t .c o m MK3722 VCXO PLUS AUDIO CLOCK FOR STB External Component Selection Crystal Tuning Load Capacitors The MK3722 requires a minimum number of external components for proper operation. The crystal traces should include pads for small fixed capacitors, one between X1 and ground, and another between X2 and ground. Stuffing of these capacitors on the PCB is optional. The need for these capacitors is determined at system prototype evaluation, and is influenced by the particular crystal used (manufacture and frequency) and by PCB layout. The typical required capacitor value is 1 to 4 pF. Decoupling Capacitors Decoupling capacitors of 0.01µF should be connected between VDD and GND on pins 3 and 4, pins 6 and 7, and pins 11 and 14 as close to the MK3722 as possible. For optimum device performance, the decoupling capacitors should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit. Series Termination Resistor To determine the need for and value of the crystal adjustment capacitors, you will need a PC board of your final layout, a frequency counter capable of about 1 ppm resolution and accuracy, two power supplies, and samples of the crystals which you plan to use in production. You will also need measured initial accuracy for each crystal at the specified crystal load capacitance (CL). When the PCB traces between the clock outputs and the loads are over 1 inch, series termination should be used. To series terminate a 50Ω trace (a commonly used trace impedance) place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. To determine the value of the crystal capacitors: Quartz Crystal 2. Adjust the voltage on pin 5 to 3.3V. Measure and record the frequency of the same output. The MK3722 VCXO function consists of the external crystal and the integrated VCXO oscillator circuit. To assure the best system performance (frequency pull range) and reliability, a crystal device meeting ICS’ recommended parameters must be used, and the layout guidelines discussed in the following section must be followed. To calculate the centering error: See Application Note MAN05 for a full list of crystal parameters. ftarget = nominal crystal frequency The frequency of oscillation of a quartz crystal is determined by its “cut” and by the load capacitors connected to it. The MK3722 incorporates on-chip variable load capacitors that “pull” (change) the frequency of the crystal. The crystal specified for use with the MK3722 is designed to have zero frequency error when the total of on-chip + stray capacitance is 14pF. The external crystal must be connected as close to the chip as possible and should be on the same side of the PCB as the MK3722. There should be no via’s between the crystal pins and the X1 and X2 device pins. There should be no signal traces underneath or close to the crystal. 6 ( f 3.3 ( 3.0 )V – f t arg et ) + ( f 0V – f t arg et ) Error = 10 x ---------------------------------------------------------------------------------------- – errorxtal f t arg et Where: errorxtal =actual initial accuracy (in ppm) of the crystal being measured If the centering error is less than ±25 ppm, no adjustment is needed. If the centering error is more than 25ppm negative, the PC board has excessive stray capacitance and a new PCB layout should be considered to reduce stray capacitance. (Alternately, the crystal may be re-specified to a higher load capacitance. Contact ICS for details.) If the centering error is more than 25ppm positive, add identical fixed centering capacitors from each crystal pin to ground. The value for each of these caps (in pF) is given by: 3 MDS 3722 B Int egrat ed C ircuit Syste ms 1. Connect VDD to 3.3V. Connect pin 5 to the second power supply. Adjust the voltage on pin 5 to 0V. Measure and record the frequency of the CLK output. ● 525 R ace S tr eet, San Jose, CA 95126 Revision 092502 ● t el (40 8) 295 -9800 ● w ww. ic s t .c o m MK3722 VCXO PLUS AUDIO CLOCK FOR STB External Capacitor = assume it is 30 ppm/pF. After any changes, repeat the measurement to verify that the remaining error is acceptably low (typically less than ±25ppm). 2 x (centering error)/(trim sensitivity) Trim sensitivity is a parameter which can be supplied by your crystal vendor. If you do not know the value, Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK3722. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7V All Inputs and Outputs -0.5V to VDD+0.5V Ambient Operating Temperature 0 to +70°C Storage Temperature -65 to +150°C Soldering Temperature 260°C Recommended Operation Conditions Parameter Min. Max. Units 0 +70 °C +3.15 +3.45 V Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) Typ. Reference crystal parameters Refer to page 3 DC Electrical Characteristics VDD=3.3V ±5% , Ambient temperature 0 to +70°C, unless stated otherwise Parameter Symbol Conditions Operating Voltage VDD Output High Voltage VOH IOH = -12 mA Output Low Voltage VOL IOL = 12 mA Output High Voltage (CMOS Level) VOH IOH = -4 mA Input High Voltage (S1:S0) Min. Typ. 3.15 Max. Units 3.45 V 2.4 V 0.4 V VDD-0.4 V VIH 2.0 V Input High Voltage (S2) VIH 2.5 V Input Low Voltage (S1:S0) VIL 0.8 V Input Low Voltage (S2) VIL 0.5 V 4 MDS 3722 B Int egrat ed C ircuit Syste ms ● 525 R ace S tr eet, San Jose, CA 95126 Revision 092502 ● t el (40 8) 295 -9800 ● w ww. ic s t .c o m MK3722 VCXO PLUS AUDIO CLOCK FOR STB Parameter Symbol Conditions Min. Typ. Units Operating Supply Current IDD Short Circuit Current IOS VIN, VCXO Control Voltage VIA On Chip Pull-up Resistor, inputs RPU S0, S1, S2 150 kΩ Input Capacitance CIN S0, S1, S2 5 pF 20 Ω Nominal Output Impedance No load, 2 outputs Max. 11 mA ±50 mA 0 3.3 ZOUT V AC Electrical Characteristics VDD = 3.3V ±5%, Ambient Temperature 0 to +70° C, unless stated otherwise Parameter Symbol Crystal Pullability fP Conditions Min. 0V< VIN < 3.3V, Note 1 Max. Units + 100 VIN = VDD/2 + 1V, Note 1 VCXO Gain Typ. ppm 80 ppm/V Output Rise Time tOR 0.8 to 2.0V, CL=15pF 0.75 1.5 ns Output Fall Time tOF 2.0 to 0.8V, CL=15pF 0.75 1.5 ns Output Clock Duty Cycle tD Measured at 1.65V, CL=15pF 50 60 % Maximum Output Jitter, short term tJ CL=15pF 40 +150 ps Note 1: External crystal device must conform with Pullable Crystal Specifications listed on page 3. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Conditions Min. Typ. Max. Units θJA Still air 78 °C/W θJA 1 m/s air flow 70 °C/W θJA 3 m/s air flow 68 °C/W 37 °C/W θJC 5 MDS 3722 B Int egrat ed C ircuit Syste ms Symbol ● 525 R ace S tr eet, San Jose, CA 95126 Revision 092502 ● t el (40 8) 295 -9800 ● w ww. ic s t .c o m MK3722 VCXO PLUS AUDIO CLOCK FOR STB Package Outline and Package Dimensions (16 pin TSSOP, 4.40 mm Body, 0.65 mm Pitch) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters 16 Symbol E1 A A1 A2 b C D E E1 e L α E INDEX AREA 1 2 D A 2 Min Inches Max -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 5.1 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0° 8° Min Max -0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.193 0.201 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0° 8° A A 1 c -Ce SEATING PLANE b α L .10 (.004) C Ordering Information Part / Order Number Marking Shipping packaging Package Temperature MK3722G MK3722GTR MK3722G MK3722G Tubes Tape and Reel 16 pin TSSOP 16 pin TSSOP 0 to +70° C 0 to +70° C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 6 MDS 3722 B Int egrat ed C ircuit Syste ms ● 525 R ace S tr eet, San Jose, CA 95126 Revision 092502 ● t el (40 8) 295 -9800 ● w ww. ic s t .c o m