ICS552-03 LOW SKEW 1 TO 8 CLOCK BUFFER (4 AT 1X, 4 AT 1/2X) Description Features The ICS552-03 is a low skew, single input to eight output clock buffer. Four of the outputs are exact copies of the input, while the other four are divide by 2 copies of the input. It is part of ICS’ Clock BlocksTM family. See the ICS553 for a 1 to 4 low skew buffer, or the ICS552-02 for a 1 to 8 low skew buffer without divide by 2. For more than 8 outputs see the MK74CBxxx BuffaloTM series of clock drivers. • • • • • • Low skew outputs (50 ps maximum) ICS makes many non-PLL and PLL based low skew output devices as well as Zero Delay Buffers to synchronize clocks. Contact us for all of your clocking needs. • • • • One bank of 4 outputs at 1X Packaged in 16 pin TSSOP Low power CMOS technology Operating Voltages of 2.5 V to 5 V Output Enable pin tri-states outputs Low skew between 1X and 1/2X outputs (100 ps maximum) One bank of 4 outputs at 1/2X 5V tolerant input clocks Input clock multiplexer Block Diagram Q0 IN A 1 Q1 IN B 0 Q2 Q3 P0 P1 D ivid e by 2 P2 P3 S E LA 1 MDS 552-03 B In tegr ated C ir cu it S yst ems OE ● 5 25 Ra ce Str eet, San Jose, C A 95 126 Revision 052501 ● tel ( 408) 2 95-9 800 ● www. i c s t. c om ICS552-03 LOW SKEW 1 TO 8 CLOCK BUFFER (4 AT 1X, 4 AT 1/2X) Pin Assignment OE VDD Q0 Q1 Q2 Q3 GND INB Input Source Select 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SELA VDD P3 P2 P1 P0 GND INA SELA Input 0 INB 1 INA 16 Pin 173 Mil (0.65mm) TSSOP Pin Descriptions Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name Pin Type OE VDD Q0 Q1 Q2 Q3 GND INB INA GND P0 P1 P2 P3 VDD SELA Input Power Output Output Output Output Power Input Input Power Output Output Output Output Power Input Pin Description Output Enable. Tri-states outputs when low.Internal Pull-up resistor Connect to +2.5 V, +3.3 V or +5.0 V. Must be the same as pin 15 Clock Output Q0 Clock Output Q1 Clock Output Q2 Clock Output Q3 Ground Clock Input B. 5 V tolerant input Clock Input A. 5 V tolerant input Ground Clock Output P0 Clock Output P1 Clock Output P2 Clock Output P3 Connect to +2.5 V, +3.3 V or +5.0 V. Must be the same as pin 2 Selects either INA or INB. Internal pull-up resistor External Components A minimum number of external components are required for proper operation. Decoupling capacitors of 0.01 µF should be connected between VDD on pin 2 and GND on pin 7,and between VDD on pin 15 and GND on pin 10, as close to the device as possible. A 33 Ω series terminating resistor should be used on each clock output if the trace is longer than 1 inch. To achieve the low output skews that the ICS552-03 is capable of, careful attention must be paid to board layout. Essentially, all 8 outputs must have identical terminations, identical loads, and identical trace geometries. If they do not, the output skew will be degraded. For example, using a 30 Ω series termination on one output (with 33Ω on the others) will cause at least 15 ps of skew. 2 MDS 552-03 B Int egrat ed C ircuit Syste ms ● 525 R ace S tr eet, San Jose, CA 95126 Revision 052501 ● t el (40 8) 295 -9800 ● w ww. ic s t .c o m ICS552-03 LOW SKEW 1 TO 8 CLOCK BUFFER (4 AT 1X, 4 AT 1/2X) Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS552-03. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature 0 to +70 °C Storage Temperature -65 to +150 °C Junction Temperature 175 °C Soldering Temperature 260 °C Recommended Operation Conditions Parameter Min. Typ. Max. Units 0 – +70 °C +5.25 V Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) +2.375 DC Electrical Characteristics VDD=2.5V ±5%, Ambient temperature 0 to +70°C, unless stated otherwise Parameter Symbol Operating Voltage Conditions Min. Max. Units 2.375 2.625 V VDD/2+0.5 5.5 V VDD/2-0.5 V VDD V 0.4 V VDD Typ. Input High Voltage, INA, INB VIH Note 1 Input Low Voltage, INA, INB VIL Note 1 Input High Voltage, OE, SELA VIH Input Low Voltage, OE, SELA VIL Output High Voltage VOH IOH = -16 mA Output Low Voltage VOL IOL = 16 mA Operating Supply Current IDD No load, 100 MHz 20 mA Short Circuit Current IOS Each output 60 mA 2.4 V 0.8 3 MDS 552-03 B Int egrat ed C ircuit Syste ms 2 ● 525 R ace S tr eet, San Jose, CA 95126 V Revision 052501 ● t el (40 8) 295 -9800 ● w ww. ic s t .c o m ICS552-03 LOW SKEW 1 TO 8 CLOCK BUFFER (4 AT 1X, 4 AT 1/2X) DC Electrical Characteristics (continued) VDD=3.3V ±5%, Ambient temperature 0 to +70°C, unless stated otherwise Parameter Symbol Operating Voltage Conditions Min. Max. Units 3.135 3.465 V VDD/2+0.7 5.5 V VDD/2-0.7 V VDD V 0.4 V VDD Typ. Input High Voltage, INA, INB VIH Note 1 Input Low Voltage, INA, INB VIL Note 1 Input High Voltage, OE, SELA VIH Input Low Voltage, OE, SELA VIL Output High Voltage VOH IOH = -25 mA Output Low Voltage VOL IOL = 25 mA Operating Supply Current IDD No load, 100 MHz 25 mA Short Circuit Current IOS Each output 80 mA 2 2.4 V 0.8 V VDD=5V ±5%, Ambient temperature 0 to +70°C, unless stated otherwise Parameter Symbol Operating Voltage Conditions Min. Max. Units 4.75 5.25 V VDD/2+1 5.5 V VDD/2-1 V VDD V 0.4 V VDD Typ. Input High Voltage, INA, INB VIH Note 1 Input Low Voltage, INA, INB VIL Note 1 Input High Voltage, OE, SELA VIH Input Low Voltage, OE, SELA VIL Output High Voltage VOH IOH = -45 mA Output Low Voltage VOL IOL = 45 mA Operating Supply Current IDD No load, 100 MHz 45 mA Short Circuit Current IOS Each output 100 mA 2 2.4 V 0.8 V Notes: 1. Nominal switching threshold is VDD/2 AC Electrical Characteristics VDD = 2.5V ±5%, Ambient Temperature 0 to +70° C, unless stated otherwise Parameter Symbol Conditions Min. Input Frequency Typ. 0 Max. Units 160 MHz Output Rise Time tOR 0.8 to 2.0 V, CL=15 pF 1.5 ns Output Fall Time tOF 2.0 to 0.8 V, CL=15 pF 1.5 ns 6.5 ns Propagation Delay Note 1 Output to output skew. Between any two Q outputs Note 2 Rising edges at VDD/2 0 50 ps Output to output skew. Between any two P outputs Note 2 Rising edges at VDD/2 0 50 ps Output to output skew. Between any P to any Q output Note 2 Rising edges at VDD/2 0 100 ps Input A to Input B skew. Note 3 0 50 ps 4 MDS 552-03 B Int egrat ed C ircuit Syste ms ● 525 R ace S tr eet, San Jose, CA 95126 Revision 052501 ● t el (40 8) 295 -9800 ● w ww. ic s t .c o m ICS552-03 LOW SKEW 1 TO 8 CLOCK BUFFER (4 AT 1X, 4 AT 1/2X) AC Electrical Characteristics (continued) VDD = 3.3V ±5%, Ambient Temperature 0 to +70° C, unless stated otherwise Parameter Symbol Conditions Min. Input Frequency Typ. 0 Max. Units 200 MHz Output Rise Time tOR 0.8 to 2.0 V, CL=15 pF 1.0 ns Output Fall Time tOF 2.0 to 0.8 V, CL=15 pF 1.0 ns 5 ns Propagation Delay Note 1 Output to output skew. Between any two Q outputs Note 2 Rising edges at VDD/2 0 50 ps Output to output skew. Between any two P outputs Note 2 Rising edges at VDD/2 0 50 ps Output to output skew. Between any P to any Q output Note 2 Rising edges at VDD/2 0 100 ps Input A to Input B skew Note 3 0 50 ps VDD = 5.0V ±5%, Ambient Temperature 0 to +70° C, unless stated otherwise Parameter Symbol Conditions Min. Input Frequency Typ. 0 Max. Units 160 MHz Output Rise Time tOR 0.8 to 2.0 V, CL=15 pF 0.7 ns Output Fall Time tOF 2.0 to 0.8 V, CL=15 pF 0.7 ns 4 ns Propagation Delay Note 1 Output to output skew. Between any two Q outputs Note 2 Rising edges at VDD/2 0 50 ps Output to output skew. Between any two P outputs Note 2 Rising edges at VDD/2 0 50 ps Output to output skew. Between any P to any Q output Note 2 Rising edges at VDD/2 0 100 ps Input A to Input B skew Note 3 0 50 ps Notes: 1. With rail to rail input clock 2. Between any two outputs with equal loading 3. Propagation delay matching through the part 4. Duty cycle on outputs will match incoming clock duty cycle. Consult ICS for tight duty cycle clock generators. 5 MDS 552-03 B Int egrat ed C ircuit Syste ms ● 525 R ace S tr eet, San Jose, CA 95126 Revision 052501 ● t el (40 8) 295 -9800 ● w ww. ic s t .c o m ICS552-03 LOW SKEW 1 TO 8 CLOCK BUFFER (4 AT 1X, 4 AT 1/2X) Package Outline and Package Dimensions (16 pin TSSOP, 173 Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters Index Area E H Symbol Min Max Min Max A -- 1.20 -- 0.047 a 0.05 0.15 0.002 0.006 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.0035 0.008 D 4.90 5.10 0.193 0.201 E 4.30 4.50 0.169 0.177 e 0.65 Basic 0.0256 Basic H 6.40 Basic 0.252 Basic L Pin 1 Inches 0.45 0.75 0.018 0.030 D a A c e b L Ordering Information Part / Order Number Marking (both) Shipping packaging Package Temperature ICS552G-03 ICS552G-03T ICS (top line) 552G-03 (2nd line) Tubes Tape and Reel 16 pin TSSOP 16 pin TSSOP 0 to +70 °C 0 to +70 °C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 6 MDS 552-03 B Int egrat ed C ircuit Syste ms ● 525 R ace S tr eet, San Jose, CA 95126 Revision 052501 ● t el (40 8) 295 -9800 ● w ww. ic s t .c o m