MK2069-01 VCXO-Based Line Card Clock Synchronizer Description Features The MK2069-01 is a VCXO (Voltage Controlled Crystal Oscillator) based clock generator that offers system synchronization, jitter attenuation, and frequency multiplication or translation. It can accept an unstable, jittery input clock and provide a de-jittered, low phase noise output clock at a user determined frequency. The device’s clock multiplication ratios are user selectable since all major PLL divider blocks can be configured through device pin settings. External PLL loop filter components allow tailoring of the VCXO PLL loop response and therefore the clock jitter attenuation characteristics. • Input clock frequency of 1kHz to 170MHz • Output clock frequency of 500kHz to 160MHz • Jitter attenuation of input clock provided by VCXO • • • • The MK2069-01 is ideal for line card applications. Its three input MUX enables selection of the master or slave (backup) system clocks, as well as a backup local line card clock. The lock detector (LD) output serves as a clock status monitor. The clear (CLR) input enables rapid synchronization to the phase of a newly selected input clock, while eliminating the generation of extra clock cycles and wander caused by memory in the PLL feedback divider. CLR also serves as a temporary holdover function when kept low. • • • • • circuit. Jitter transfer characteristics user configured through selection of external loop filter components. 3:1 Input MUX for input reference clocks PLL lock status output PLL Clear function allows seamless synchronizing to an altered input clock phase, virtually eliminating the generation of wander or extra clock cycles. VCXO-based clock generation offers very low jitter and phase noise generation, even with a low frequency or jittery input clock. 2nd PLL provides translation of VCXO PLL output (VCLK) to higher or alternate clock frequencies (TCLK). Device will free-run in the absence of an input clock based on the VCXO crystal frequency. 56 pin TSSOP package Single 3.3V power supply 5V tolerant inputs on ICLK0 and ICLK1 Block Diagram P u lla b le x ta l R V 1 :0 2 S V 2 :0 IS E T LF LFR X1 3 X2 R T 1 :0 S T 1 :0 2 VDD 2 4 VCLK IC L K 0 0X IC L K 1 10 IC L K 2 01 RV D iv id e r Phase D etector O EV VCXO 1 ,2 ,4 ,1 2 8 2 M X 1 :0 Charge P um p SV D iv id e r 1 ,2 ,4 ,6 ,8 , 1 0 ,1 2 ,1 6 RT D iv id e r VCO 1 -4 TCLK 2 ,4 ,8 ,1 6 O ET F T D iv id e r F V D iv id e r 1 -4 0 9 6 VCXO PLL ST D iv id e r T ra n s la to r PLL 1 -6 4 RCLK L o c k D e te c to r O ER LD CLR O EL LDC 12 LDR F V 1 1 :0 4 F T 5 :0 GND 1 MDS 2069-01 H Integrated Circuit Systems 6 l 5 25 Race Street, San Jose, CA 9 512 6 Revision 050203 l tel (40 8) 2 95-98 00 l www.icst.com MK2069-01 Line Card Clock Synchronizer Pin Assignment VCXO PLL Feedback Divider Selection ST0 1 56 SV2 2 55 SV1 3 54 SV0 RT1 4 53 RV1 FT0 5 52 MX0 FT1 6 51 IC L K 1 FT2 7 50 OEL FT3 8 49 OET FT4 9 48 OEV FT5 10 47 OER RV0 11 46 VDD VDDT 12 45 LD 44 TCLK 43 VDDP 42 VCLK 41 GNDP 40 RCLK 39 LDR 38 GND M K 2 0 6 9 -0 1 ST1 RT0 GNDT 13 X1 14 VDDV 15 X2 16 GNDV 17 LFR 18 LF 19 IS E T 20 37 LDC FV0 21 36 CLR FV1 22 35 IC L K 0 FV2 23 34 IC L K 2 FV3 24 33 MX1 FV4 25 32 FV11 FV5 26 31 FV10 FV6 27 30 FV9 28 29 FV8 FV7 FV11:0 FV Divider Ratio Notes 0...00 2 For FV addresses 0 to 4094, 0...01 3 FV Divide = Address + 2 : : 1...10 4096 1...11 1 VCXO PLL Scaling Divider Selection Table SV2 SV1 SV0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Translator PLL Reference Divider Selection Table RT1 RT0 0 0 0 1 1 0 1 1 Input Selection Tables 000000 000001 : 111110 111111 Input Mux Selection Table Input Selection ICLK0 ICLK0 ICLK1 ICLK2 RV Divider Ratio 4 128 2 1 Notes For FT addresses 0 to 62, FT Divide = Address + 2 ST1 ST0 0 0 0 1 1 0 1 1 ST Divider Ratio 2 4 8 16 2 MDS 2069-01 H Integrated Circuit Systems FT Divider Ratio 2 3 : 64 1 Translator PLL Scaling Divider Selection Table VCXO PLL Reference Divider Selection Table RV1 RV0 0 0 0 1 1 0 1 1 RT Divider Ratio 2 3 4 1 Translator PLL Feedback Divider Selection FT5:0 MX1 MX0 0 0 0 1 1 0 1 1 SV Divider Ratio 4 6 8 10 12 2 16 1 l 525 Ra ce Stree t, Sa n Jose, CA 951 26 Revision 050203 l te l (4 08) 295 -9 800 l www.icst.com MK2069-01 Line Card Clock Synchronizer Pin Descriptions Pin Number Pin Name Pin Type Pin Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 ST0 ST1 RT0 RT1 FT0 FT1 FT2 FT3 FT4 FT5 RV0 VDDT GNDT X1 VDDV X2 GNDV LFR LF ISET FV0 FV1 FV2 FV3 FV4 FV5 FV6 FV7 FV8 FV9 FV10 FV11 MX1 ICLK2 ICLK0 CLR LDC Input Input Input Input Input Input Input Input Input Input Input Power Ground Power Ground Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input - Scaling Divider bit 0 input, Translator PLL (internal pull-up). Scaling Divider bit 1 input, Translator PLL (internal pull-up). Reference Divider bit 0 input, Translator PLL (internal pull-up). Reference Divider bit 1 input, Translator PLL (internal pull-up). Feedback Divider bit 0 input, Translator PLL (internal pull-up). Feedback Divider bit 1 input, Translator PLL (internal pull-up). Feedback Divider bit 2 input, Translator PLL (internal pull-up). Feedback Divider bit 3 input, Translator PLL (internal pull-up). Feedback Divider bit 4 input, Translator PLL (internal pull-up). Feedback Divider bit 5 input, Translator PLL (internal pull-up). Reference Divider bit 0 input, VCXO PLL (internal pull-up). Power Supply connection for translator PLL. Ground connection for translator PLL. Crystal oscillator input. Connect this pin to the external reference crystal. Power Supply connection for VCXO PLL. Crystal oscillator output. Connect this pin to the external reference crystal. Ground connection for VCXO PLL. Loop filter connection, reference node. Refer to loop filter circuit on page 6. Loop filter connection, active node. Refer to loop filter circuit on page 6. Charge pump current setting input. Refer to loop filter circuit on page 6. Feedback Divider bit 0 input, VCXO PLL (internal pull-up). Feedback Divider bit 1 input, VCXO PLL (internal pull-up). Feedback Divider bit 2 input, VCXO PLL (internal pull-up). Feedback Divider bit 3 input, VCXO PLL (internal pull-up). Feedback Divider bit 4 input, VCXO PLL (internal pull-up). Feedback Divider bit 5 input, VCXO PLL (internal pull-up). Feedback Divider bit 6 input, VCXO PLL (internal pull-up). Feedback Divider bit 7 input, VCXO PLL (internal pull-up). Feedback Divider bit 8 input, VCXO PLL (internal pull-up). Feedback Divider bit 9 input, VCXO PLL (internal pull-up). Feedback Divider bit 10 input, VCXO PLL (internal pull-up). Feedback Divider bit 11 input, VCXO PLL (internal pull-up). Input MUX selection bit 1 (internal pull-up). Reference clock input 2. Reference clock input 0. 5V tolerant input. Clear input, clears VCXO PLL dividers when low (internal pull-up). Lock detector threshold setting circuit connection. Refer to circuit on page 10. 38 GND Ground Digital ground connection. 39 40 41 LDR RCLK GNDP Output Ground Lock detector threshold setting circuit connection. Refer to circuit on page 10. VCXO PLL phase detector Reference Clock output. Ground connection for output drivers (VCLK, TCLK, RCLK, LD, LDR). 3 MDS 2069-01 H Integrated Circuit Systems l 525 Ra ce Stree t, Sa n Jose, CA 951 26 Revision 050203 l te l (4 08) 295 -9 800 l www.icst.com MK2069-01 Line Card Clock Synchronizer Pin Number Pin Name Pin Type Pin Description 42 43 44 VCLK VDDP TCLK Output Power Output Clock output from VCXO PLL Power Supply connection for output drivers (VCLK, TCLK, RCLK, LD, LDR). Clock output from Translator PLL 45 46 47 48 49 LD VDD OER OEV OET Output Power Input Input Input 50 51 52 53 54 55 56 OEL ICLK1 MX0 RV1 SV0 SV1 SV2 Input Input Input Input Input Input Input Lock detector output. Power Supply connection for digital circuitry. Output enable for RCLK. RCLK is tri-stated when low (internal pull-up). Output enable for VCLK. VCLK is tri-stated when low (internal pull-up). Output enable for TCLK. TCLK is tri-stated and the translator PLL is disabled when low (internal pull-up). Output enable for LD and LDR. Both are tri-stated when low (internal pull-up). Reference clock input 1. 5V tolerant input. Input MUX selection bit 0 input (internal pull-up). Reference Divider bit 1 input, VCXO PLL (internal pull-up). Scaler Divider bit 0 input, VCXO PLL (internal pull-up). Scaler Divider bit 1 input, VCXO PLL (internal pull-up). Scaler Divider bit 2 input, VCXO PLL (internal pull-up). Functional Description The MK2069-01 is a PLL (phase locked loop) based clock generator that generates output clocks synchronized to an input reference clock. It contains two cascaded PLL’s with user selectable divider ratios. The first PLL is VCXO-based and uses an external pullable crystal as part of the normal “VCO” (voltage controlled oscillator) function of the PLL. The use of a VCXO assures a low phase noise clock source even when a low PLL loop bandwidth is implemented. A low loop bandwidth is needed when the input reference frequency is low, or when jitter attenuation of the input reference is desired. The second PLL is used to translate or multiply the frequency of the VCXO PLL which has a maximum output frequency of 27 MHz. This second PLL, or Translator PLL, uses an on-chip VCO circuit that can provide an output clock up to 160 MHz. The Translator PLL uses a high loop bandwidth (typically greater than 1 MHz) to assure stability of the VCO clock output. It requires a stable, high frequency input reference which is provided by the VCXO PLL. • • • • • Input clock frequency VCXO crystal frequency VCLK output frequency RCLK output frequency, which is also the phase detector frequency of the VCXO PLL. TCLK output frequency Any unused clock or logic outputs can be tri-stated to reduce interference (jitter, phase noise) on other clock outputs. Outputs can also be tri-stated for system testing purposes. External components are used to configure the VCXO PLL loop response. This serves to maximize loop stability and to achieve the desired input clock jitter attenuation characteristics. 4 MDS 2069-01 H Integrated Circuit Systems The divide values of the divider blocks within both PLLs are set by device pin configuration. This enables the system designer to define the following: l 525 Ra ce Stree t, Sa n Jose, CA 951 26 Revision 050203 l te l (4 08) 295 -9 800 l www.icst.com MK2069-01 Line Card Clock Synchronizer Application Information The MK2069-01 is a mixed analog / digital integrated circuit that is sensitive to PCB (printed circuit board) layout and external component selection. Used properly, the device will provide the same high performance expected from a canned VCXO-based hybrid timing device, but at a lower cost. To help avoid unexpected problems, the guidance provided in the sections below should be followed. Setting VCLK Output Frequency The frequency of the VCLK output is determined by the following relationship: FV Divider f(VCLK) = ---------------------------- × f(ICLK) RV Divider Where: FT Divider = 1 to 64 RT Divider = 1 to 4 The frequency range of TCLK is set by the operational range of the internal VCO circuit and the output divider selections: f(VC0) = ---------------------ST Divider A higher VCO frequency will generally produce lower phase noise and therefore is preferred. f ( VCXO ) ---------------------SV Divider Where: F(VCXO) = F(External Crystal) = 8 to 27 MHz SV Divider = 1,2,4,6,8,10,12 or 16 A higher crystal frequency will generally produce lower phase noise and therefore is preferred. A crystal frequency between 13.5 MHz and 27 MHz is recommended. Because VCLK is generated by the external crystal, the frequency range of VCLK in a given configuration is limited to the pullable range of the crystal. This is guaranteed to be +/-115 ppm minimum. This frequency range in ppm also applies to the input clock and other clock outputs if the device is to remain frequency locked to the input, which is required for normal operation. MK2069-01 Loop Response and JItter Attenuation Characteristics The MK2069-01 will reduce the transfer of phase jitter existing on the input reference clock to the output clock. This operation is known as jitter attenuation. The low-pass frequency response of the VCXO PLL loop is the mechanism that provides input jitter attenuation. Clock jitter, more accurately called phase jitter, is the overall instability of the clock period which can be measured in the time domain using an oscilloscope, for instance. Jitter is comprised of phase noise which can be represented in the frequency domain. The phase noise of the input reference clock is attenuated according to the VCXO PLL low-pass frequency response curve. The response curve, and thus the jitter attenuation characteristics, can be established through the selection of external MK2069-01 passive components and other device setting as explained in the following section. 5 MDS 2069-01 H Integrated Circuit Systems FT Divider f(TCLK) = ---------------------------- × f(VCLK) RT Divider Where: f(VCO) = 40 to 320 MHz ST Divider = 2,4,8 or 16 The operational frequency range of VCLK is set by the allowable frequency range of the external VCXO crystal and by the internal VCXO divider selections: = The clock frequency of TCLK is determined by: f(TCLK) Where: FV Divider = 1 to 4096 RV Divider = 1,2,4 or 128 f(VCLK) Setting TCLK Output Frequency l 525 Ra ce Stree t, Sa n Jose, CA 951 26 Revision 050203 l te l (4 08) 295 -9 800 l www.icst.com MK2069-01 Line Card Clock Synchronizer Setting the VCXO PLL Loop Response. External VCXO PLL Components The VCXO PLL loop response is determined both by fixed device characteristics and by other characterizes set by the user. This includes the values of RS, CS, CP and RSET as shown in the External VCXO PLL Components figure on this page. DON'T STUFF Refer to "Crystal Tuning Load Capacitors" Section The VCXO PLL loop bandwidth is approximated by: R S × I CP × K O NBW(VCXO PLL) = -------------------------------------------------------------------------2π × SV Divider × FV Divider CL XTAL X2 CL CS CP RS The above equation calculates the “normalized” loop bandwidth (denoted as “NBW”) which is approximately equal to the - 3dB bandwidth. NBW does not take into account the effects of damping factor or the second pole imposed by CP. It does, however, provide a useful approximation of filter performance. To prevent jitter on VCLK due to modulation of the VCXO PLL by the phase detector frequency, the following general rule should be observed: NBW(VCO PLL) X1 RSET LFR LF ISET MK2069 Where: RS = Value of resistor RS in loop filter in Ohms ICP = Charge pump current in amps (see table on page 7) KO = VCXO Gain in Hz/V (see table on page 8) SV Divider = 1,2,4,6,8,10,12 or 16 FV Divider = 1 to 4096 Optional Crystal Tuning Capacitors 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 In general, the loop damping factor should be 0.7 or greater to ensure output stability. A higher damping factor will create less peaking in the passband and will further ensure output stability with the presence of system and power supply noise. A damping factor of 4 will ensure a passband peak less then 0.2dB which may be required for network clock wander transfer compliance. A higher damping factor may also increase output clock jitter when there is excess digital noise in the system application, due to the reduced ability of the PLL to respond to and therefore compensate for phase noise ingress. f(Phase Detector) 20 ≤ --------------------------------------- . The PLL loop damping factor is determined by: RS I CP × C S × K O DF(VCLK) = ------ × ------------------------------------------------------------2 SV Divider × FV Divider Where: CS = Value of capacitor CS in loop filter in Farads Notes on setting the value of CP As another general rule, the following relationship should be maintained between components CS and CP in the loop filter: C CP 20 6 MDS 2069-01 H Integrated Circuit Systems = -----S- l 525 Ra ce Stree t, Sa n Jose, CA 951 26 Revision 050203 l te l (4 08) 295 -9 800 l www.icst.com MK2069-01 Line Card Clock Synchronizer hit the supply or ground rail resulting in non-linear loop response. CP establishes a second pole in the VCXO PLL loop filter. For higher damping factors (> 1), calculate the value of CP based on a CS value that would be used for a damping factor of 1. This will minimize baseband peaking and loop instability that can lead to output jitter. The best way to set the value of CP is to use the filter response software available from ICS (please refer to the following section). CP should be increased in value until it just starts affecting the passband peak. CP also dampens VCXO input voltage modulation by the charge pump correction pulses. A CP value that is too low will result in increased output phase noise at the phase detector frequency due to this. In extreme cases where input jitter is high, charge pump current is high, and CP is too small, the VCXO input voltage can Loop Filter Response Software Online tools to calculate loop filter response can be found at www.icst.com. Graph of Charge Pump Current vs. Value of RSET (external resistor) ICP, Amps 1E-3 100E-6 10E-6 100E+3 1E+6 Recommended Range of Operation RSET, ohms Charge Pump Current, Example Settings from Above Graph RSET 5 MΩ 3 MΩ 2 MΩ 1 MΩ 480 kΩ 400 kΩ 10E+6 problems, output clock cycle slips, or low frequency phase noise. As can be seen in the loop bandwidth and damping factor equations or by using the filter response software available from ICS, increasing charge pump current (ICP) increases both bandwidth and damping factor. Charge Pump Current (ICP) 25 µA 42 µA 65 µA 125 µA 255 µA 300 µA Notes on Setting Charge Pump Current The recommended range for the charge pump current is 25 µA to 300 µA. Below 25 µA, loop filter charge leakage, due to PCB or capacitor leakage, can become a problem. This loop filter leakage can cause locking 7 MDS 2069-01 H Integrated Circuit Systems l 525 Ra ce Stree t, Sa n Jose, CA 951 26 Revision 050203 l te l (4 08) 295 -9 800 l www.icst.com MK2069-01 Line Card Clock Synchronizer VCXO Gain (KO) vs. XTAL Frequency Notes on Setting the RV, FV and SV Divider Values V C X O G a in (K O ), H z p e r V o lt 6000 As shown in the loop bandwidth and damping factor equations on page 6, or by using the filter response software available from ICS, increasing FV or SV decreases both bandwidth and damping factor. Many applications require that SV = 1. In these cases, one way to decrease loop bandwidth is to increase the value of FV, which is accompanied by an increase in the value of RV to maintain the same PLL frequency multiplication ratio. 5000 4000 3000 However, the phase detector frequency, FPD, also needs to be considered. FPD is equal to the input frequency divided by the value of the RV divider. FPD should be typically at least 20x the loop bandwidth to prevent loop modulation (phase noise) by the phase detector frequency. The phase detector jitter tolerance limit (use 0.4UI) and input phase noise frequency aliasing should be considerations as well. 2000 1000 10 15 20 25 30 C ry s ta l F re q u e n c y , M H z Example Loop Filter Component Value RSET RS CS CP Input Clock Xtal Freq (MHz) VCLK (MHz) RV Div FV Div SV Div Passband Peaking Note 8 kHz 19.44 19.44 1 2430 1 1 MΩ 560 kΩ 4.7 nF 22 Hz 4.0 0.15dB at 1Hz 1 8 kHz 19.44 19.44 1 2430 1 1 MΩ 560 kΩ 0.1 µF 4.7 nF 27 Hz 1.4 1.2dB at 6Hz 2 8 kHz 22.368 22.368 1 2796 1 1 MΩ 680 kΩ 1 µF 4.7 nF 20 Hz 4.5 0.12dB at 1Hz 3 19.44 MHz 19.44 19.44 128 128 1 1 MΩ 1 µF 47 nF 0.85 1.8dB at 8Hz 4 27 kΩ 1 µF Loop Loop BW Damp. (-3dB) 25 Hz Notes: 1) This filter configuration assures a passband ripple compliant with Bellcore GR-1244 to satisfy wander transfer requirements (<0.2 dB ripple is required) of a network node. It can be used following a system synchronizer such as the MT9045 to provide clock jitter attenuation while maintaining Stratum 3 compliance. A 155.52 MHz TCLK output generated with the VCXO PLL configuration will be OC-3 and OC-12 timing jitter compliant. 2) This is a reduced cost and size variant of the above filter, due to the decreased size of CS. It is useful when GR-1244 compliance is not needed, such as in a network access application. 3) This configuration is used to generate a DS3 clock of 44.768 MHz at the TCLK output. This configuration is GR-1244 compliant. 4) The MK2069-02 or MK2069-04 may be more suitable for this application since the VCXO feedback divider can be increased (>128), enabling a lower bandwidth for improved jitter attenuation. 8 MDS 2069-01 H Integrated Circuit Systems l 525 Ra ce Stree t, Sa n Jose, CA 951 26 Revision 050203 l te l (4 08) 295 -9 800 l www.icst.com MK2069-01 Line Card Clock Synchronizer Loop Filter Capacitor Type Loop filters must use specific types of capacitors. Recommendations for these capacitors can be found at www.icst.com. Input MUX The MK2069-01 incorporates an input clock multiplexer or ‘mux’ that allows selection between one of three alternate reference inputs supplied to the device. The mux input selection pins are asynchronous and non-latched. Please refer to the Input MUX Selection Table on page 2. Note that inputs ICLK0 and ICLK1 are 5V tolerant, whereas ICLK2 is not. Input Phase Compensation Circuit The VCXO PLL includes a special input clock phase compensation circuit. It is used when selecting a new reference input that has a clock phase differing from the previously selected input. The phase compensation circuit allows the VCXO PLL to quickly lock to the new input phase without producing extra clock cycles or clock wander, assuming the new clock is at the same frequency. Input pin CLR controls the phase compensation circuit. CLR must remain high for normal operation. When used in conjunction with the input MUX select pins, CLR should be brought low prior to MUX reselection, then returned high after MUX reselection. This prevents the VCXO PLL from attempting to lock to the new input clock phase associated with the input clock. When CLR is high, the VCXO PLL operates normally. When CLR is low, the VCXO PLL charge pump output is inactivated which means that no charge pump correction pulses are provided to the loop filter. During this time, the VCXO frequency is held constant by the residual charge or voltage on the PLL loop filter, regardless of the input clock condition. However, the VCXO frequency will drift over time, eventually to the minimum pull range of the crystal, due to leak-off of the loop filter charge. This means that CLR can provide a holdover function, but only for a very short duration, typically in milliseconds. Upon bringing CLR high, the FV Divider is reset and begins counting upon with the first positive edge of the new input clock, and the charge pump is re-activated. By resetting the FV Divider, the memory of the previous input clock phase is removed from the feedback divider, By using CLR in this fashion VCLK will align to the input clock phase with only one or two VCLK cycle slips resulting. When CLR is not used, the number of VCLK cycle slips can be as high the FV Divider value. TCLK is always locked to VCLK regardless of the state of the CLR input. Lock Detection The MK2069-01 includes a lock detection feature that indicates lock status of VCLK relative to the selected input reference clock. When phase lock is achieved (such as following power-up), the LD output goes high. When phase lock is lost (such as when the input clock stops, drifts beyond the pullable range of the crystal, or suddenly shifts in phase), the LD output goes low. The definition of a “locked” condition is determined by the user. LD is high when the VCXO PLL phase detector error is below the user-defined threshold. This threshold is set by external components RLD and CLD shown in the Lock Detection Circuit Diagram, below. To help guard against false lock indications, the LD pin will go high only when the phase error is below the set threshold for 8 consecutive phase detector cycles. The LD pin will go low when the phase error is above the set threshold for only 1 phase detector cycle. The lock detector threshold (phase error) is determined by the following relationship: (LD Threshold) = 0.6 x R x C Where: 1 kΩ < R < 1 MΩ (to avoid excessive noise or leakage) C > 50 pF (to avoid excessive error due to stray capacitance, which can be as much as 10 pF including Cin of LDC) Lock Detector Application example: The desired maximum allowable loop phase error for a generated 19.44MHz clock is 100UI which is 5.1 µs. Solution: 5.1 µs = (0.001 µF) x (8.5 kΩ) 9 MDS 2069-01 H Integrated Circuit Systems eliminating the generation of extra VCLK clock cycle that would occur if the loop was to re-lock under normal means. Lock time is also reduced, as is the generation of clock wander. l 525 Ra ce Stree t, Sa n Jose, CA 951 26 Revision 050203 l te l (4 08) 295 -9 800 l www.icst.com MK2069-01 Line Card Clock Synchronizer Under ideal conditions, where the VCXO is phaselocked to a low-jitter reference input, loop phase error is typically maintained to within a few nanoseconds. • Only one connection is made to the PCB power L o c k D e te ctio n C irc u it plane. Lock Q u a lific a tio n C o u n te r (8 u p , 1 d o w n ) • The capacitors and ferrite chip (or ferrite bead) on LD RESET VCXO Phase D e te c to r E rro r O u tp u t OEL LDR the PCB power plane or system EMI problems may result. This above set of requirements is served by the circuit illustrated in the Recommended Power Supply Connection (next page). The main features of this circuit are as follows: Lock Detection Circuit Diagram FV D iv id e r O u tp u t • Clock noise from device VDD pins must not get onto the common device supply form a lowpass ‘pi’ filter that remove noise from the power supply as well as clock noise back toward the supply. The bulk capacitor should be a tantalum type, 1 µF minimum. The other capacitors should be ceramic type. • The power supply traces to the individual VDD pins should fan out at the common supply filter to reduce interaction between the device circuit blocks. LDC In p u t T h res h o ld se t to V D D /2 • The decoupling capacitors at the VDD pins should be RLD ceramic type and should be as close to the VDD pin as possible. There should be no via’s between the decoupling capacitor and the supply pin. CLD If the lock detection circuit is not used, the LDR output may remain unconnected, however the LDC input should be tied high or low. If the PCB was designed to accommodate the RLD and CLD components but the LD output will not be used, RLD can remain unstuffed and CLD can be replaced with a resistor (< 10 kohm). Power Supply Considerations As with any integrated clock device, the MK2069-01 has a special set of power supply requirements: • The feed from the system power supply must be filtered for noise that can cause output clock jitter. Power supply noise sources include the system switching power supply or other system components. The noise can interfere with device PLL components such as the VCO or phase detector. • Each VDD pin must be decoupled individually to prevent power supply noise generated by one device circuit block from interfering with another circuit block. 10 MDS 2069-01 H Integrated Circuit Systems l 525 Ra ce Stree t, Sa n Jose, CA 951 26 Revision 050203 l te l (4 08) 295 -9 800 l www.icst.com MK2069-01 Line Card Clock Synchronizer 0.01 µF Recommended Power Supply Connection Connection Via to 3.3V Power Plane 0.01 µF 0.01 µF 0.01 µF 1 nF BULK 0.1 µF Ferrite Chip VDD Pin Recommended Crystal Parameters: Crystal parameters can be found in application note MAN05 on www.icst.com. Approved crystals can be found at www.icst.com (search “crystal”). VDD Pin Crystal Tuning Load Capacitors VDD Pin VDD Pin Series Termination Resistor Output clock PCB traces over 1 inch should use series termination to maintain clock signal integrity and to reduce EMI. To series terminate a 50Ω trace, which is a commonly used PCB trace impedance, place a 33Ω resistor in series with the clock line as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. Quartz Crystal The MK2069-01 operates by phase-locking the VCXO circuit to the input signal at the selected ICLK input. The VCXO consists of the external crystal and the integrated VCXO oscillator circuit. To achieve the best performance and reliability, a crystal device with the recommended parameters must be used, and the layout guidelines discussed in the following section must be followed. The frequency of oscillation of a quartz crystal is determined by its cut and by the load capacitors connected to it. The MK2069-01 incorporates variable load capacitors on-chip which “pull” or change the frequency of the crystal. The crystals specified for use with the MK2069-01 are designed to have zero frequency error when the total of on-chip + stray The crystal traces should include pads for small capacitors from X1 and X2 to ground, shown as CL in the External VCXO PLL Components diagram on page 6. These capacitors are used to center the total load capacitor adjustment range imposed on the crystal. The load adjustment range includes stray PCB capacitance that varies with board layout. Because the typical telecom reference frequency is accurate to less than 32 ppm, the MK2069-01 may operate properly without these adjustment capacitors. However, ICS recommends that these capacitors be included to minimize the effects of variation in individual crystals, including those induced by temperature and aging. The value of these capacitors (typically 0-4 pF) is determined once for a given board layout, using the procedure described in MAN05. PCB Layout Recommendations For optimum device performance and lowest output phase noise, the following guidelines should be observed. Please refer to the Recommended PCB Layout drawing on the following page. 1) Each 0.01µF decoupling capacitor (CD) should be mounted on the component side of the board as close to the VDD pin as possible. No via’s should be used between the decoupling capacitor and VDD pin. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. Distance of the ferrite chip and bulk decoupling from the device is less critical. 2) The loop filter components must also be placed close to the CHGP and VIN pins. CP should be closest to the device. Coupling of noise from other system signal traces should be minimized by keeping traces short and away from active signal traces. Use of vias should be avoided. 3) The external crystal should be mounted as close to the device as possible, on the component side of the 11 MDS 2069-01 H Integrated Circuit Systems capacitance is 14pF. To achieve this, the layout should use short traces between the MK2069-01 and the crystal. l 525 Ra ce Stree t, Sa n Jose, CA 951 26 Revision 050203 l te l (4 08) 295 -9 800 l www.icst.com MK2069-01 Line Card Clock Synchronizer board. This will keep the crystal PCB traces short which will minimize parasitic load capacitance on the crystal and as well as noise pickup. The crystal traces should be spaced away from each other and should use minimum trace width. There should be no signal traces near the crystal or the traces. Also refer to the Optional Crystal Shielding section that follows. 4) To minimize EMI the 33Ω series termination resistor, if needed, should be placed close to the clock output. 5) All components should be on the same side of the board, minimizing vias through other signal layers (the ferrite bead and bulk decoupling capacitor may be mounted on the back). Other signal traces should be routed away from the MK2069-01. This includes signal traces on PCB traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. evaluation. The crystal is less sensitive to system noise interference when the case is grounded. 4) Add a ground trace around the crystal circuit to shield from other active traces on the component layer. The external crystal is particularly sensitive to other system clock sources that are at or near the crystal frequency since it will try to lock to the interfering clock source. The crystal should be keep away from these clock sources. The ICS Applications Note MAN05 may also be referenced for additional suggestions on layout of the crystal section. 6) Because each input selection pin includes an internal pull-up device, those inputs requiring a logic high state (“1”) can be left unconnected. The pins requiring a logic low state (“0”) can be grounded. Optional Crystal Shielding The crystal and connection traces to pins X1 and X2 are sensitive to noise pickup. In applications that are especially sensitive to noise, such as SONET or G-Bit ethernet transceivers, some or all of the following crystal shielding techniques should be considered. This is especially important when the MK2069-01 is placed near high speed logic or signal traces. The following techniques are illustrated on the Recommended PCB Layout drawing. 1) The metal layer underneath the crystal section should be the ground layer. Remove all other layers that are above. This ground layer will help shield the crystal circuit from other system noise sources. As an alternative, all layers underneath the crystal can be removed, however this is not recommended if there are adjacent PCBs that can induce noise into the unshielded crystal circuit. 2) Cut a channel in the PCB ground plane around the crystal area as shown. This will eliminate high frequency ground currents that can couple into to crystal circuit. 3) Add a through-hole for the optional third lead offered by the crystal manufacturer (case ground). The requirement for this third lead can be made at prototype 12 MDS 2069-01 H Integrated Circuit Systems l 525 Ra ce Stree t, Sa n Jose, CA 951 26 Revision 050203 l te l (4 08) 295 -9 800 l www.icst.com MK2069-01 Line Card Clock Synchronizer Recommended PCB Layout Diagram SUPPLY SOURCE TO DEVICE (SUCH AS VIA TO SUPPLY PLANE) OPTIONAL CRYSTAL SHIELDING V SHIELD TRACE (TOP LAYER) CUT CHANNEL IN GROUND PLANE CE 603 CBD A G FC A G 1 2 G G CL 603 G G CD 603 XTAL G CL 603 G 5 6 52 51 7 50 8 49 9 48 10 47 11 46 12 45 G CD 603 G RS 603 RSET 603 41 39 G 38 20 37 21 22 36 35 23 24 34 33 25 26 32 31 27 28 G RT 603 RT 603 40 19 CP 805 CS 1206 42 G 18 G CD 603 43 16 17 G 44 MK2069 15 G 56 55 G 54 53 14 G G 3 4 13 G CBB 603 CD 603 THRU HOLE FOR 3RD LEAD (XTAL CASE GROUND) G G RLD 603 CLD 603 G 30 29 Components are identified by function (top line) and by typical package type (bottom line) which may vary. Legend: G = Via to PCB Ground plane V = Via to PCB Power Plane CE = EMI suppression cap, typical value 0.1 µF (ceramic) FC = Ferrite chip CBD = Bulk decoupling capacitor for chip power supply, 1 µF minimum (tantalum) CBB = Bulk bypass cap for chip power supply, typical value 1000 nF (ceramic) CD = Decoupling capacitor for VDD pin (ceramic) CL = Optional load capacitor for crystal tuning (do not stuff) *Note: If output LD is not used, RLD and CLD may be omitted. See text on page 10. 13 MDS 2069-01 H Integrated Circuit Systems CS = External loop capacitor CS (film type) CP = External loop capacitor CP (film type) RS = External loop resistor RS RSET = Resistor RSET used to set charge pump current RT = Series termination resistor for clock output, typical value 33 Ω RLD* = External resistor for lock detector circuit CLD* = External capacitor for lock detector circuit l 525 Ra ce Stree t, Sa n Jose, CA 951 26 Revision 050203 l te l (4 08) 295 -9 800 l www.icst.com MK2069-01 Line Card Clock Synchronizer Circuit Troubleshooting 1) IF TCLK or VCLK does not lock to ICLK 2.3) VCLK and TCLK jitter can also be caused by poor power supply decoupling. Ensure a bulk decoupling capacitor is in place. First check VCLK to ICLK. It is best to display and trigger the scope with RCLK, especially if a non-integer VCXO PLL multiplication ratio is used. 2.4) Ensure that the VCXO PLL loop bandwidth is sufficiently low. It should be at least 1/20th of the phase detector frequency. If VCLK is not locked to ICLK: 2.5) Ensure that the VCXO PLL loop damping is sufficient. If should be at least 0.7, preferably 1.0 or higher. 1.1) Ensure the proper ICLK input is selected. 1.2) Check RV, SV, FV Divider settings 1.3) Ensure ICLK is within lock range (within about 100 ppm of the nominal input frequency, limited by pull range of the external crystal). If in doubt, tweak the ICLK frequency up and down to see if VCLK locks. 1.4) Ensure ICLK jitter is not excessive. If ICLK jitter is excessive device may not lock. Also see item 2.1 below. 1.5) Clean the PCB. The VCXO PLL loop filter is very sensitive to board leakage, especially when the VCXO PLL phase detector frequency is in the low kHz. If organic solder flux is used (most common today) scrub the PCB board with detergent and water and then blow and bake dry. Inorganic solder flux (Rosen core) requires solvent. See also section 3 below. 2) If There is Excessive Jitter on VCLK or TCLK 2.1) The problem may be an unstable input reference clock. An unstable ICLK will not appear to jitter when ICLK is used as the oscilloscope trigger source. In this condition, VCLK and TCLK may appear to be unstable since the jitter from ICLK (the trigger source) has been removed by the trigger circuit of the scope. 2.2) The instability may be caused by VCXO PLL loop filter leakage. Refer to item 1.5 above. 3) If There is Excessive Input to Output Skew 3.1) TCLK should track VCLK. The rising edge of TCLK should be within a few nanoseconds of VCLK. 3.1) VCLK should track RCLK. The rising edge of VCLK should be within 5-10 nsec of RCLK (VCLK leads). 3.3) The biggest cause of input to output skew is VCXO PLL loop filter leakage. Skew is best observed by comparing ICLK to RCLK. When no leakage is present the rising edge of RCLK should lag the rising edge of ICLK by about 10 usec. Loop filter leakage can greatly increase this lag time or cause the loop to not lock. Refer to item 1.5, above. 3.4) Another way to view the loop filter leakage is to observe LDR pin. Use RCLK as the scope trigger. LDR will produce a negative pulse equal in length to the charge pump pulse. 3.5) Filter leakage can also be caused by the use of improper loop capacitors. Refer to the section titled ‘Loop Filter Capacitor Type’ on page 9. 14 MDS 2069-01 H Integrated Circuit Systems 2.6) Ensure that the 2nd pole in the VCXO PLL loop filter is set sufficiently. In general, CP should be equal to CS/20. If CP is too high, passband peaking will occur and loop instability may occur. If CP is set too low, excessive VCXO modulation by the charge correction pulses may occur. l 525 Ra ce Stree t, Sa n Jose, CA 951 26 Revision 050203 l te l (4 08) 295 -9 800 l www.icst.com MK2069-01 Line Card Clock Synchronizer Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK2069-01. These ratings are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7V All Inputs and Outputs -0.5V to VDD+0.5V Ambient Operating Temperature -40 to +85°C Storage Temperature -65 to +150°C Junction Temperature 175°C Soldering Temperature 260°C Recommended Operation Conditions Parameter Min. Ambient Operating Temperature -40 Power Supply Voltage (measured in respect to GND) +3.15 +3.3 Max. Units +85 °C +3.45 V 15 MDS 2069-01 H Integrated Circuit Systems Typ. l 525 Ra ce Stree t, Sa n Jose, CA 951 26 Revision 050203 l te l (4 08) 295 -9 800 l www.icst.com MK2069-01 Line Card Clock Synchronizer DC Electrical Characteristics Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature -40 to +85°C Parameter Symbol Conditions Min. Typ. Max. Units 3.15 3.3 3.45 V 20 30 mA Operating Voltage VDD Supply Current IDD Input High Voltage, MX1:0, RV1:0, FV11:0, SV2:0, RT1:0, FT5:0, ST1:0 VIH 2 VDD + 0.4 V Input Low Voltage, MX1:0, RV1:0, FV11:0, SV2:0, RT1:0, FT5:0, ST1:0 VIL -0.4 0.8 V Input Pull-Up Resistor (Note 1) RPU Input High Voltage, ICLK2, CLR VIH VDD/2+1 VDD + 0.4 V Input High Voltage, ICLK1:0 VIH VDD/2+1 5.5 V Input Low Voltage, ICLK2:0, CLR VIL -0.4 VDD/2-1 V Input High Current (Note 1) IIH VIH = VDD -10 +10 µA Input Low Current (Note 1) IIL VIL = 0 -10 +10 µA Input Capacitance, except X1 CIN Output High Voltage (CMOS Level) VOH IOH = -4 mA VDD-0.4 Output High Voltage VOH IOH = -8 mA 2.4 Output Low Voltage VOL IOL = 4 mA Output Short Circuit Current, TCLK IOS ±50 mA Output Short Circuit Current, VCLK, RCLK and LD IOS ±20 mA VIN, VCXO Control Voltage VXC All clock outputs loaded with 15 pF, VCLK = 19.44 MHz, TCLK = 155.52 MHz 200 kΩ 7 pF V V 0.4 0 VDD V V Note 1: All logic select inputs (MX1:0, RV1:0, FV11:0, SV2:0, RT1:0, FT5:0, ST1:0, CLR) have an internal pull-up resistor. 16 MDS 2069-01 H Integrated Circuit Systems l 525 Ra ce Stree t, Sa n Jose, CA 951 26 Revision 050203 l te l (4 08) 295 -9 800 l www.icst.com MK2069-01 Line Card Clock Synchronizer AC Electrical Characteristics Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature -40 to +85° C Parameter Symbol VCXO Crystal Frequency Range (Note 1) fXTAL Using recommended crystal 13.5 VCXO Crystal Pull Range fXP Using recommended crystal ±115 ±150 ppm VCXO Crystal Free-Run Frequency (Note 2) fXF Input reference = 0 Hz -300 -150 ppm Input Clock Frequency (Note 2) fI Input Clock Pulse Width tID VCXO PLL Phase Detector Frequency (Note 3) fPD VCXO PLL Phase Detector Jitter Tolerance tJT Translator PLL VCO Frequency fV Conditions Min. Typ. Max. Units 27 0.001 Positive or Negative Pulse 170 10 MHz nsec 0.001 1 UI = phase detector period MHz 27 0.4 MHz UI 40 320 MHz Timing Jitter, Filtered 500Hz-1.3MHz (OC-3) tOJf Derived from phase noise characteristics, peak-to-peak 6 sigma 95 ps Timing Jitter, Filtered 65kHz-5MHz (OC-3) tOJf Derived from phase noise characteristics, peak-to-peak 6 sigma 85 ps Timing Jitter, Filtered 1kHz-5MHz (OC-12) tOJf Derived from phase noise characteristics, peak-to-peak 6 sigma 105 ps Timing Jitter, Filtered 250kHz-5MHz (OC-12) tOJf Derived from phase noise characteristics, peak-to-peak 6 sigma 80 ps Output Duty Cycle (% high time), VCLK when SV Divider = 1 tOD Measured at VDD/2, CL=15pF 40 50 60 % Output Duty Cycle (% high time), VCLK when SV Divider > 1, TCLK tOD Measured at VDD/2, CL=15pF 44 50 65 % Output High Time, RCLK (Note 4) tOH Measured at VDD/2, CL=15pF 0.5 VCLK Period Output Rise Time, VCLK and RCLK tOR 0.8 to 2.0V, CL=15pF 1.5 2 ns Output Fall Time, VCLK and RCLK tOF 2.0 to 0.8V, CL=15pF 1.5 2 ns 17 MDS 2069-01 H Integrated Circuit Systems l 525 Ra ce Stree t, Sa n Jose, CA 951 26 Revision 050203 l te l (4 08) 295 -9 800 l www.icst.com MK2069-01 Line Card Clock Synchronizer Parameter Symbol Conditions Min. Typ. Max. Units Output Rise Time, TCLK tOR 0.8 to 2.0V, CL=15pF 0.75 1 ns Output Fall Time, TCLK tOF 2.0 to 0.8V, CL=15pF 0.75 1 ns Skew, ICLK to VCLK (Note 5) tIV Rising edges, CL=15pF -5 2.5 +10 ns Skew, ICLK to RCLK (Note 5) tIV Rising edges, CL=15pF +5 10 +20 ns Skew, ICLK to TCLK (Note 5) tVT Rising edges, CL=15pF -5 1.5 +10 ns Nominal Output Impedance ZOUT Ω 20 Note 1: This is the recommended crystal operating range. A crystal as low as 8 MHz can be used, although this may result in increased output phase noise. Note 2: The VCXO crystal will be pulled to its minimum frequency when there is no input clock (CLR = 1) due to the attempt of the PLL to lock to 0 Hz. Note 3: The minimum practical input frequency is 1 kHz. Through proper loop filter design lower input frequencies may be possible. Note 4: The output of RCLK is a positive pulse with a duration equal to VCLK high time, or half the VCLK period. Note 5: Referenced to ICLK, the skews of VCLK, RCLK and TCLK increase together when leakage is present in the external VCXO PLL loop filter. 18 MDS 2069-01 H Integrated Circuit Systems l 525 Ra ce Stree t, Sa n Jose, CA 951 26 Revision 050203 l te l (4 08) 295 -9 800 l www.icst.com MK2069-01 Line Card Clock Synchronizer Package Outline and Package Dimensions 56 pin TSSOP 6.10 mm (240 mil) body, 0.50 mm. (20 mil) pitch Package dimensions are kept current with JEDEC Publication No. 95 56 Millimeters Symbol E1 E IN D EX AR EA 1 2 D A 2 Min A A1 A2 b C D E E1 e L α aaa Inches Max Min -1.20 0.05 0.15 0.80 1.05 0.17 0.27 0.09 0.20 13.90 14.10 8.10 BASIC 6.00 6.20 0.50 Basic 0.45 0.75 0° 8° -0.10 Max -0.047 0.002 0.006 0.032 0.041 0.007 0.011 0.0035 0.008 0.547 0.555 0.319 BASIC 0.236 0.244 0.020 Basic 0.018 0.030 0° 8° -0.004 A A 1 c -C e S E A T IN G P LA N E b L aaa C Ordering Information Part / Order Number Marking Shipping packaging Package Temperature MK2069-01GI MK2069-01GI Tubes 56 pin TSSOP -40 to +85° C MK2069-01GITR MK2069-01GI Tape and Reel 56 pin TSSOP -40 to +85° C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 19 MDS 2069-01 H Integrated Circuit Systems l 525 Ra ce Stree t, Sa n Jose, CA 951 26 Revision 050203 l te l (4 08) 295 -9 800 l www.icst.com