MK3725 DUAL OUTPUT 3.3 VOLT VCXO Description Features The MK3725 is a low cost, high-performance, two output 3.3 Volt VCXO and PLL clock synthesizer designed to replace expensive VCXOs and crystals. The patented on-chip Voltage Controlled Crystal Oscillator accepts a 0 to 3.3 V input voltage to cause the output clocks to vary by ±115 ppm minimum. Using our analog Phase Locked Loop (PLL) techniques, the device uses an external, fundamental mode pullable crystal input to produce output clocks of 2x the input frequency. • • • • The frequency of the on-chip VCXO is adjusted by an external control voltage input into pin VIN. Because VIN is a high impedance input, it can be driven directly from an PWM RC integrator circuit. Packaged in 8-pin SOIC Operating voltage of 3.3 V (±5%) Two pullable output clocks of 24-36 MHz Uses a fundamental mode 12-18 MHz pullable crystal • On-chip patented VCXO with pull range of 230 ppm (minimum) • VCXO tuning voltage of 0 to 3.3 V • 12 mA output drive capability at TTL levels • Advanced, low power, sub-micron CMOS process Block Diagram VD D VIN X1 X2 12-18 M H z Pullable C rystal V oltage C ontrolled C rystal O scillator F requency C lock D oubler 2 24-36 M H z GND MDS 3725 A 1 Revision 100803 Integrated Circuit Systems z 525 Race Street, San Jose, CA 95126 z t e l ( 4 0 8 ) 2 9 7 - 1 2 0 1 z www.i cst.com MK3725 DUAL OUTPUT 3.3 VOLT VCXO Pin Assignment X1 1 8 X2 VDD 2 7 VDD VIN 3 6 CLK GND 4 5 CLK 8 Pin (150 mil) SOIC Pin Descriptions Pin Number Pin Name Pin Type 1 X1 Input Crystal connection. Connect to a 12-18 MHz external pullable crystal. 2 VDD Power Connect to +3.3 V. 3 VIN Input Voltage input to VCXO. Zero to 3.3 V analog input which controls the oscillation frequency of the VCXO. 4 GND Input Connect to ground. 5 CLK Output VCXO clock output. 2x input frequency. 6 CLK Output VCXO clock output. 2x input frequency. 7 VDD Power Connect to +3.3 V. 8 X2 Output Crystal connection. Connect to a 12-18 MHz external pullable crystal. MDS 3725 A Pin Description 2 Revision 100803 Integrated Circuit System s z 525 Race Street, S an Jose, CA 9 5126 z tel (4 08) 29 7-12 01 z w w w. ic s t . c o m MK3725 DUAL OUTPUT 3.3 VOLT VCXO External Component Selection The MK3725 requires a minimum number of external components for proper operation. Decoupling Capacitor A decoupling capacitor of 0.01µF must be connected between VDD (pin 2 & 7) and GND (pin 4), as close to these pins as possible. For optimum device performance, the decoupling capacitor should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit. Series Termination Resistor Use series termination when the PCB trace between the clock outputs and the loads are over 1 inch. To series terminate a 50Ω trace (a commonly used trace impedance), place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. between X2 and ground. Stuffing of these capacitors on the PCB is optional. The need for these capacitors is determined at system prototype evaluation, and is influenced by the particular crystal used (manufacture and frequency) and by PCB layout. The typical required capacitor value is 1 to 4 pF. To determine the need for and value of the crystal adjustment capacitors, you will need a PC board of your final layout, a frequency counter capable of about 1 ppm resolution and accuracy, two power supplies, and some samples of the crystals which you plan to use in production, along with measured initial accuracy for each crystal at the specified crystal load capacitance, CL. To determine the value of the crystal capacitors: 1. Connect VDD of the MK3725 to 3.3 V. Connect pin 3 of the MK3725 to the second power supply. Adjust the voltage on pin 3 to 0V. Measure and record the frequency of the CLK output. 2. Adjust the voltage on pin 3 to 3.3 V. Measure and record the frequency of the same output. Quartz Crystal The MK3725 VCXO function consists of the external crystal and the integrated VCXO oscillator circuit. To assure the best system performance (frequency pull range) and reliability, a crystal device with the recommended parameters (as described in application note MAN05) must be used, and the layout guidelines discussed in the following section must be followed. The frequency of oscillation of a quartz crystal is determined by its “cut” and by the load capacitors connected to it. The MK3725 incorporates on-chip variable load capacitors that “pull” (change) the frequency of the crystal. The crystal specified for use with the MK3725 is designed to have zero frequency error when the total of on-chip + stray capacitance is 14 pF. The external crystal must be connected as close to the chip as possible and should be on the same side of the PCB as the MK3725. There should be no vias between the crystal pins and the X1 and X2 device pins. There should be no signal traces underneath or close to the crystal. To calculate the centering error: 6 ( f 3.0V – f t arg et ) + ( f 0V – f t arg et ) Error = 10 x ------------------------------------------------------------------------------ – error xtal f t arg et Where: ftarget = nominal crystal frequency errorxtal =actual initial accuracy (in ppm) of the crystal being measured If the centering error is less than ±25 ppm, no adjustment is needed. If the centering error is more than 25ppm negative, the PC board has excessive stray capacitance and a new PCB layout should be considered to reduce stray capacitance. (Alternately, the crystal may be re-specified to a higher load capacitance. Contact ICS MicroClock for details.) If the centering error is more than 25 ppm positive, add identical fixed centering capacitors from each crystal pin to ground. The value for each of these caps (in pF) is given by: Crystal Tuning Load Capacitors External Capacitor = The crystal traces should include pads for small fixed capacitors, one between X1 and ground, and another 2 x (centering error)/(trim sensitivity) MDS 3725 A 3 Revision 100803 Integrated Circuit System s z 525 Race Street, S an Jose, CA 9 5126 z tel (4 08) 29 7-12 01 z w w w. ic s t . c o m MK3725 DUAL OUTPUT 3.3 VOLT VCXO Trim sensitivity is a parameter which can be supplied by your crystal vendor. If you do not know the value, assume it is 30 ppm/pF. After any changes, repeat the measurement to verify that the remaining error is acceptably low (typically less than ±25 ppm). Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK3725. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature 0 to +70°C Storage Temperature -65 to +150°C Soldering Temperature 260°C Recommended Operation Conditions Parameter Min. Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) Reference crystal parameters MDS 3725 A Typ. Max. Units 0 +70 °C +3.15 +3.45 V Refer to MAN05 4 Revision 100803 Integrated Circuit System s z 525 Race Street, S an Jose, CA 9 5126 z tel (4 08) 29 7-12 01 z w w w. ic s t . c o m MK3725 DUAL OUTPUT 3.3 VOLT VCXO DC Electrical Characteristics VDD=3.3 V ±5% , Ambient temperature 0 to +70°C, unless stated otherwise Parameter Symbol Conditions Operating Voltage VDD Output High Voltage VOH IOH = -12 mA Output Low Voltage VOL IOL = 12 mA Output High Voltage (CMOS Level) VOH IOH = -4 mA Operating Supply Current IDD No load Short Circuit Current IOS VIN, VCXO Control Voltage VIA Nominal output impedance ZOUT Min. Typ. 3.15 Max. Units 3.45 V 2.4 V 0.4 VDD-0.4 V V 12 mA ±50 mA 0 3.3 V Ω 20 AC Electrical Characteristics VDD=3.3 V ±5%, Ambient Temperature 0 to +70° C, unless stated otherwise Parameter Symbol Crystal Pullability FP VCXO Gain Conditions 0V< VIN < 3.3 V, Note 1 Min. Typ. Max. Units + 115 ppm VIN = VDD/2 + 1 V, Note 1 120 ppm/V Output Rise Time tOR 20% to 80%, CL=15 pF 1.0 ns Output Fall Time tOF 80% to 20%, CL=15 pF 1.0 ns Output Clock Duty Cycle tD Measured at VDD/2, CL=15 pF Maximum Output Jitter, short term tJ CL=15 pF 45 55 ±60 % ps Note 1: External crystal device must conform with Pullable Crystal Specifications listed in MAN05 Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case MDS 3725 A Symbol Conditions Min. Typ. Max. Units θJA Still air 150 °C/W θJA 1 m/s air flow 140 °C/W θJA 3 m/s air flow 120 °C/W 40 °C/W θJC 5 Revision 100803 Integrated Circuit System s z 525 Race Street, S an Jose, CA 9 5126 z tel (4 08) 29 7-12 01 z w w w. ic s t . c o m MK3725 DUAL OUTPUT 3.3 VOLT VCXO Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters Inches 8 Symbol E A A1 B C D E e H h L α H INDEX AREA 1 2 D A Min Max 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 0° 8° Min Max .0532 .0688 .0040 .0098 .013 .020 .0075 .0098 .1890 .1968 .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 0° 8° h x 45 A1 C -Ce SEATING PLANE B L .10 (.004) C Ordering Information Part / Order Number Marking Shipping packaging Package Temperature MK3725S MK3725STR MK3725 MK3725 Tubes Tape and Reel 8-pin SOIC 8-pin SOIC 0 to +70° C 0 to +70° C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. MDS 3725 A 6 Revision 100803 Integrated Circuit System s z 525 Race Street, S an Jose, CA 9 5126 z tel (4 08) 29 7-12 01 z w w w. ic s t . c o m