INNOVASIC IA63484

IA63484
Advanced CRT Controller
Data Sheet
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
High-speed graphics
- Drawing rate: 200 ns/pixel max (color drawing)
- Commands: 38 commands including 23 graphic drawing commands:
Dot, Line, Rectangle, Poly-line, Polygon, Circle, Ellipse, Paint, Copy, etc.
- Colors: 16 bits/word: 1,2,4,8,16 bits/pixel (5 types) monochrome to 64k colors max
- Pattern RAM: 32 bytes
- Converts logical X-Y coordinate to physical address
- Color operation and conditional drawing
- Drawing area control for hardware clipping and hitting
Large frame-memory space
- Maximum 2 Mbytes graphic memory and 128 kbytes character memory separate from
MPU memory.
- Maximum Resolution: 4096 x 4096 pixels (1 bit/pixel mode)
CRT display control
- Split Screens: three displays and one window
Zoom: 1 to 16 times
Scroll: vertical and horizontal
Interleaved access mode for flashless display and superimposition
External synchronization between ARTCs or between ACRTC and external device (TV system
or other controller.
DMA interface
Two programmable cursors
Three Scan modes
- Non-interlaced
- Interlace sync
- Interlace sync and video
Interrupt request to MPU
256 characters/line 32 raster/ line, 4096 rasters/screen
Maximum clock frequency: 25MHz
CMOS, single +5V power supply
The IA63484 is a "plug-and-play" drop-in replacement for the original Hitachi© HD63484. This
replacement IC has been developed using innovASIC’s MILESTM, or Managed IC Lifetime
Extension System, cloning technology. This technology produces replacement ICs far more complex
than "emulation" while ensuring they are compatible with the original IC. MILESTM captures the
design of a clone so it can be produced even as silicon technology advances. MILESTM also verifies
the clone against the original IC so that even the "undocumented features" are duplicated. This data
sheet documents all necessary engineering information about the IA63484 including functional and
I/O descriptions, electrical characteristics, and applicable timing.
Copyright  2001
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The End of Obsolescence
ENG 21101041200
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IA63484
Advanced CRT Controller
Data Sheet
68 Pin Package: ACRTC PLCC PINOUT
dreq_n
done_n(O,D)
res_n
rs
cs_n
rw_n
cud2_n
cud1_n
Vcc
lpstb
disp1_n
disp2_n
mad0(T)
mad1(T)
mad2(T)
mad3(T)
mad4(T)
Pin Arrangement:
9
dack_n
dtack_n(T)
irq(O,D)
hsync_n
vsync_n
Vcc
exsync_n
Vss
Vss
d0(T)
d1(T)
d2(T)
d3(T)
d4(T)
d5(T)
d6(T)
d7(T)
1
68
60
IA63484
44
d8(T)
d9(T)
d10(T)
d11(T)
d12(T)
d13(T)
d14(T)
d15(T)
Vss
ra4
ma_ra19_3
ma_ra18_2
ma_ra17_1
ma_ra16_0
mad15(T)
mad14(T)
mad13(T)
27
chr
mrd
draw_n
as_n
mcyc
Vss
Vss
clk_2
Vcc
mad5(T)
mad6(T)
mad7(T)
mad8(T)
mad9(T)
mad10(T)
mad11(T)
mad12(T)
O,D: Open Drain
T: Three State
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IA63484
Advanced CRT Controller
Data Sheet
BLOCK DIAGRAM
Figure 1: System Block Diagram
Figure 2 illustrates the ACRTC system environment. The following paragraphs will further describe
the system block diagram and design in more detail.
res_n
ma[19:16]
irq_n
MPU
(8/16b)
as_n
d[15:0]
L
FRAME
BUFFER
2MB, MAX
dtack_n
mrd
cs_n
rs
mad[15:0]
rw_n
disp2_n
SYSTEM
MEMORY
ACRTC
dreq_n
disp1_n
cud2_n
CONTROL
DATA
ADDRESS
dack_n
DOT SHIFTER
cud1_n
done_n
lpstb
clk_2
exsync_n
Vss
vsync_n
Vcc
hsync_n
CRT
DMAC
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VIDEO
SIGNAL
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Advanced CRT Controller
Data Sheet
I/O SIGNAL DESCRIPTION:
The diagram below describes the I/O characteristics for each signal on the IC. The signal names
correspond to the signal names on the pinout diagrams provided.
I/O Characteristics:
Signal Name
res_n
d[15,0]
rw_n
cs_n
rs
dtack_n
irq_n
dreq_n
dack
done_n
clk_2
mad[15,0]
as_n
MA16/R 0-*
I/O
Group
I
I/O
I
I
I
MPU
Interface
O
O
I
I/O
I
DMAC
Interface
I/O
O
O
O
MA 19/RA3
RA4
chr
mcyc
mrd
draw_n
disp1, disp2
cud1, cud2
vsync_n
hsync_n
exsync_n
lpstb
O
O
O
O
CRT
Interface
O
O
O
I/O
I
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Description
ACRTC reset:
Data bus (three state): are the bidirectional data bus to the host mpu or dmac. D 0 -D
are used in 8-bit data bus mode.
Read/write strobe: controls the direction of host/ACRTC transformers.
Chip Select: enables transfers between the host and the ACRTC.
Register Select: selects the ACRTC register to be accessed. It is usually connected to
the least significant bit of the host address bus.
Data transfer acknowledge (three state): output provides asynchronous bus cycle
timing. It is compatible with the HD68000 mpu dtack output.
Interrupt request (open drain): output generates interrupt service requests to the
host MPU.
DMA request: recieves DMA acknowledge timing from the host DMAC.
DMA acknoledge:
DMA done: terminates DMA transfer. It is compatible with the HD68450 DMAC
DONE signal.
ARTC clock: is the baasic operating clock, twice the frequency of the dot clock.
Multiplexed frame buffer address/data bus: are the multiplexed frame buffer
address/data bus.
Address strobe: output demultiplexes the address/data bus.
Higer-order address bits/character screen rastar address:MA16/R0- MA19/RA3 are
the upper bits of the graphics screen ddress multiplexed with th lower bits of the
character screen raster address.
Higer-order character screen rastar address bit: is the high bit of the character screen
raster address (up to 32 rasters.)
Graphic or character screen access: output indicates whether a graphic or character
screen is being accessed.
Frame buffer memory acess timing signal: is the frame buffer access timing output,
1/2 the frequency of clk_2.
Frame buffer memory read: output controls the frame buffer data bus direction.
Draw/refresh signal: output differentiates between drawing and CRT displayrefresh
cycles.
Display enable: programmable display enable outputs can enable, disable, and blanck
logical screens.
Coursor Display: outputs provides cursor timing programmed by ACRTC parameters
such as cursor definition, cursor mode, cursor address, etc.
CRT vertical sync pulse: outputs the crt vertical synchronization pulse.
CRT horizontal sync pulse: outputs the crt horizontal synchronization pulse.
External sync:allows synchronization between multiple ACRTSs and other videro
signal generators.
Lightpen strobe: is the lightpen input
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Data Sheet
Figure 2: ACRTC Block Diagram
res_n
dreq_n
draw_adrs[19:0]
DMA
Control
Unit
dack_n
Register
Address
Data
done_n
20
Drawing
Processor
draw_data[15:0]
16
draw_en
draw_n
write
mrd
Interrupt
Control
Unit
irq_n
mad[15:0]
16
ma19_16_ra[3:0]
4
disp_adrs[19:0]
ra4
20
raster_adrs[4:0]
Display
Processor
16
d[15:0]
CRT
Interface
15
chr_int
chr
ccud
cs_n
lpstb
rs_n
lpstb
MPU
Interface
cud1_n, cud2_n
2
rw_n
gcud[1:0]
2
hsync
hsync_n
dtack_n
vsync
vsync_n
exsync
Timing
Processor
exsync_n
disp[1:0]
disp1_n, disp2_n
2
2
m_cyc
mcyc
as
clk2
23
V cc
as_n
clk_2
25
V SS
ACRTC System Description:
Some CRT controllers provide a single bus interface to the frame buffer that must be shared with the host
MPU. However, refreshing large frame buffers, and accessing the frame buffer for drawing operations can
quickly saturate the shared bus.
The ACRTC uses separate host MPU and frame buffer interfaces. This allows the ACRTC full access to the
frame buffer for display refresh and drawing operations and minimizes the use of the MPU system bus by the
ACRTC. A related benefit is that a large frame buffer (2 MB for each ACRTC) can be used, even if the host
MPU has a smaller address space or segment size restriction.
The ACRTC can use an external Direct Memory Access Controller (DMAC) to increase system throughput
when many commands, parameters and data must be transferred to the ACRTC. Advanced DMAC features
such as the HD68450 “chaining” modes can be used to develop powerful graphics system architectures.
More cost-sensitive or less performance-sensitive applications might not require a DMAC. In these cases, the
interface to the ACRTC can be handled under MPU software control.
While both ACRTC bus interfaces (host MPU and frame buffer) are 16 bits wide, the ACRTC also offers an
8 bit MPU mode for easy connection to popular 8 bit busses.
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Advanced CRT Controller
Data Sheet
FUNCTIONAL REQUIREMENTS:
Drawing Processor:
The Drawing Processor performs drawing operations on the frame buffer memory upon interpreting
commands and command parameters issued by the host bus (MPU or DMAC). The drawing
processor then executes ACRTC drawing algorithms and converts logical X-Y addresses to physical
frame buffer addresses.
The drawing processor uses three operation control units; the Drawing Algorithm Control unit, the
Drawing Address Generation unit and the Logical Operation unit.
The Drawing Algorithm Control Unit interprets graphic commands and parameters and executes the
appropriate micro-programmed drawing algorithm. This control unit calculates coordinates using
logical pixel X-Y addressing.
The Drawing Address Generation Unit converts logical X-Y addresses from the Drawing Algorithm
Control unit to a bit address in the frame buffer. The frame buffer is organized as sequential 16 bit
words. The bit address consists of 20 bits and bits 0-4 specifying the logical pixel bit address within
the physical frame buffer word.
Logical Operation Unit, using the address calculated in the drawing algorithm control and drawing
address generation units, performs logical operations between the existing read data in the frame
buffer and the drawing pattern in the pattern RAM, and rewrites the results into the frame buffer. A
detailed description of the Drawing Processor is contained in its module specification.
Display Processor:
The display processor manages frame buffer refresh addressing based on the user specified display
screen organization. It combines and displays as many as 4 independent screen segments (3
horizontal split screens and 1 window) using an internal high-speed address calculation unit. It
controls display refresh outputs in graphic (physical frame buffer address) or character (physical
refresh memory address and row address) modes.
Display Functions:
The ACRTC allows the frame buffer to be divided into four separate logical screens:
•
Upper
•
Base
•
Lower
•
Window
In the simplest case, only the base screen parameters must be defined. Other screens may be
selectively enabled, disabled, and blanked under software control.
The background screens (upper, base, and lower) split the screen into three horizontal partitions
whose positions are fully programmable. The window screen is unique, since the ACRTC usually
gives it higher priority than the background screens. A typical application might be to use the base
screen for the bulk of the user interaction, while using the upper screen for pull-down menus and the
lower screen for status line indicators. The exception is in the ACRTC superimpose mode, in which
the window has the same priority as the background screens. In this mode, the window and
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Data Sheet
background screens are superimposed on the display.
combinations.
Figure 3 is an example of the screen
Figure 3: Screen Combination Examples
Screen Number
0
1
2
3
Screen Name
Upper Screen
Base Screen
Lower Screen
Window Screen
Screen Group
Background Screen
Upper
Base
Base
Window
Window
Lower
Upper
Upper
Base
Base
Window
Lower
Window
Lower
Display Control:
The ACRTC can have two types of external frame memory: 2 Mbyte frame buffer and 128 kbyte
refresh memory. The chr signal controls which memory is accessed.
Each screen has its own memory width, vertical display width, and character/graphic attribution set
by the control registers. Horizontal display control registers are set in units of memory cycles.
Vertical display control registers are set in units of rasters. Figure 4 illustrates the relation between the
frame memory and the display screens, while Figure 5 illustrates the timing.
Note that display width of registers marked with an (*) in Figure 4 is:
Display width = Register value + 1 memory cycle.
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Data Sheet
Figure 4: Frame Memory and Display Screens
Frame Memory Image
Refresh Memory
(Character)
MW0
$0000
SA0
File Name: MOS
MW2
SA2
$FFFF
Frame Buffer
(Graphic)
Left
Right
:
:
Layout
Symbol
MW1
$00000
SA1
File Name: MOS
MW3
SA3
Left
Right
:
:
Layout
Symbol
$FFFFF
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Advanced CRT Controller
Data Sheet
Figure 5: Display Screen Specification
HC*
HSW
HDS*
HWW*
vsync_n
HWS*
HDW*
hsync_n
VWS
VDS
Display Screen Period
SP0
(Upper)
(Base)
VWW
(Window)
SP1
(Base)
VC
SP2
(Lower)
VSW
Timing Processor:
The Timing Processor generates the CRT synchronization signals and signals used internally
by the ACRTC. The details for this block are contained in the module specification for the
Display Processor.
CRT Interface:
The CRT Interface manages the communication between the frame buffer, the light pen and the
CRT. The frame buffer interface manages the frame buffer bus and selects display drawing or
refreshes address outputs. The light pen interface uses a 20-bit address register and a strobe input pin
(lpstb).
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Advanced CRT Controller
Data Sheet
Frame Buffer Interface:
The ACRTC allows for two types of independent frame memories. The first type is up to a 2 Mbyte
frame buffer and the second is a 128 Kbytes refresh memory. The chr output pin can access either
the Graphic or Character screen.
The width of the frame memory is defined by setting-up the memory width register (mwr) and
independently, the horizontal display width is defined by the horizontal display register (hdr). This
allows for the frame buffer area to be bigger than the display area; reference Figure 6.
Figure 6: Frame Memory and Display Screen Area
Memory Width
Start Address
Display Screen Area
Vertical
Display
Width
text
Horizontal Display Width
The ACRTC has two ways to access the frame memory (or buffer); (1) Display Memory Access
(three types) and (2) Graphic Address Increment mode.
Display Memory Access Modes:
In Single Access Mode, a display or drawing cycle is defined as two cycles of clk_2. During the first
cycle, the frame buffer display or drawing address is output. During the second clk_2 cycle, the
frame buffer data is read (display cycles and/or drawing cycles) or written (drawing cycles).
Display and drawing cycles contend for access to the frame buffer. The ACRTC allows the priority
to be defined as display priority or drawing priority. If display has priority, drawing cycles are only
allowed to occur during the horizontal or vertical fly back periods (a ‘flash less’ display is obtained).
If drawing has priority, drawing may occur during display (display may flash).
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In Interleaved Access Mode (dual access mode 0), display cycles and drawing cycles are interleaved.
A display or drawing cycle is defined as four cycles of clk_2.
•
During the first clk_2 cycle, the ACRTC outputs the frame buffer display address.
•
During the second clk_2 cycle, the display data is output from the frame buffer.
•
During the third clk_2, the ACRTC outputs the frame buffer drawing address.
•
During the fourth clk_2 cycle, the ACRTC reads or writes the drawing data.
In Superimposed Access Mode (dual access mode 1), two separate logical screens are accessed during
each display cycle. The display cycle is defined as four clk_2 cycles. If the third and fourth cycles are
not used for window display, they can be used for drawing; similar to the Interleaved Mode.
•
During the first clk_2 cycle, the ACRTC outputs the background screen frame buffer address.
•
During the second clk_2 cycle, the background screen displays data.
•
During the third clk_2 cycle, the ACRTC outputs the window screen frame buffer address or the
drawing frame buffer address.
•
During the fourth clk_2 cycle, the ACRTC reads (display or drawing) or writes (drawing) the
window screen display or drawing data.
Graphic Address Increment (GAI) Mode:
The ACRTC can be programmed to control the graphic display address in one of six ways, by
incrementing by 1, 2, 4, 8, and 16 words, 1 word every two display cycles, and no increment. Setting
GAI to increment by 2, 4, 8, or 16 words per display cycle achieves 2, 4, 8, or 16 times the video data
rate corresponding to GAI = 1. This allows the number of bits/logical pixel and logical pixel
resolution to be increased while meeting the clk_2 maximum frequency constraint.
When the frame buffer memory uses dynamic RAMs (DRAMs), the ACRTC automatically provides
DRAM refresh addressing.
During hsync_n low, the ACRTC outputs the values of an 8-bit DRAM refresh counter on the
multiplexed frame buffer address and data bus mad[15:0]. The counter is decremented on each
frame buffer access. The refresh address pin assignment (mad[15:0]) depends on the GAI mode.
The remaining mad and ma19_16_ra outputs not used for refresh addressing are cleared to a low
value.
Table 1: GAI and DRAM Refresh Addressing
Address Increment Mode
Refresh Address Output Terminal
+1 (GAI = 000)
mad[7:0]
+2 (GAI = 001)
mad[8:1]
+4 (GAI = 010)
mad[9:2]
+8 (GAI = 011)
mad[10:3]
+16 (GAI = 100)
mad[11:4]
+0 (GAI = 101)
mad[7:0]
+1/2 (GAI = 11X)
mad[7:0]
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Data Sheet
Address Space:
The ACRTC allows the host to issue commands in logical X-Y coordinates. The ACRTC then
converts the physical linear word addresses with bit field offsets in the frame buffer. Figure 7 shows
the relationship between the logical X-Y screen address and the frame buffer memory. The frame
buffer memory is organized as sequential 16 bit words. The host may specify 1, 2, 4, 8, or 16 physical
bits in the frame buffer. The system in the figure uses 4 bit logical pixels, allowing for 16 colors or
tones.
Figure 7: Logical/Physical Addressing
SAD
Display Screen
Y
(x,y)
Physical Addressing
(Frame Buffer)
bit
bit
15
0
Origin
X
Logical Addressing
1 pixel data
MW
Y
(x,y)
X
Origin
SAD
MW
Up to 4 logical screens may be mapped onto the ACRTC physical address space. The four screens
are the upper, base, lower, and window screens. The host first specifies the following:
•
A logical screen starting address.
•
A logical screen physical memory width (memory words per raster).
•
A logical pixel physical memory width (bit per pixel).
•
A logical origin physical address.
Then the ACRTC converts the logical pixel X-Y addresses issued by the host MPU or the drawing
processor to physical frame buffer addresses. The device also performs bit extraction and masking
to map logical pixel operations to 16 bit word frame buffer addresses.
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Data Sheet
Memory Map:
The ACTRC has over 200 bytes of accessible registers organized as Hardware, Direct, and FIFO
Access. Figure 8 illustrates the programming memory map model.
•
The ACRTC registers are initialized by res_n as follows:
•
Drawing and display operations are stopped
•
Status register (SR) is initialized to $FF23
•
Command control register (CCR) is initialized to $8000.
•
Operation mode register bits MS and STR are reset to 0.
•
All other registers are unaffected by res_n.
•
The FIFO Entry (FE) pointer is cleared, and the written command/parameter and the read
data are lost.
•
The DRAM refresh address is placed on the mad lines determined by graphic address
increment (GAI). Refresh continues to function until the start bit (STR) is set to 1. hsync_n
is also held low during the period from res_n until str is set by the MPU.
For directly accessible registers, the register address is shown as ‘rXX’, and FIFO accessible registers
are shown as ‘PrXX’, where XX is interpreted as an 8 bit hexadecimal value. Hexadecimal numbers
are denoted by a leading ‘$’.
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Data Sheet
Figure 8: Programming Model
Address Register
Status Register
Write FIFO
FIFO Entry
Command Control Register
Operation Mode Register
Display Control Register
Raster Counter
Read FIFO
Horizontal Sync
Horizontal Display
Vertical Sync
Vertical Display
Split Screen Width
Command Register
Blink Control
Horizontal Window Display
Vertical Window Display
Graphic Cursor
Pattern
RAM
16 x 16
Split Screen 0
(Upper Screen)
Split Screen 1
(Base Screen)
Color 0
Split Screen 2
(Lower Screen)
Color Comparison
Edge Color
Split Screen 3
(Window Screen)
Mask
Pattern RAM Control
Block Cursor
Drawing
Parameter
Register
Area Definition
Cursor Definition
Zoon Factor
Read/Write Pointer
Light Pen Address
Drawing Pointer
Current Pointer
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Hardware Access:
The ACRTC is connected to the host MPU as a standard memory-mapped peripheral that occupies
two word locations of the host’s address space. When rs=0, read operations access the status
register, and write operations access the address register.
The status register summarizes the ACRTC State; it monitors the overall state of the ACRTC for the
host MPU. When the MPU wants to access a direct access register, it puts the register’s address into
the ACRTC address register.
Direct Access:
The MPU accesses the direct access registers by loading the register address into the address register.
Then, when the MPU accesses the ACRTC with rs=1, the chosen register is accessed. The FIFO
entry register enables the MPU to access FIFO access registers using the ACRTC read and write
FIFOs.
The command control register controls overall ACRTC operations, such as aborting or pausing
commands, defining DMA protocols, and enabling/disabling interrupt sources.
The operation mode register defines basic parameters of ACRTC operation, such as frame buffer
access mode, display or drawing priority, cursor and display timing skew factors, and raster scan
mode.
The display control register independently enables and disables the four ACRTC logical address
screens (upper, base, lower, and window). It also contains 8 user-defined video attribute bits.
The timing control RAM registers define ACRTC timing, including timing specifications for CRT
control signals (hsync_n, vsync_n, etc.), logical display screen size and display period, and blink
period.
The display control RAM contains registers that define logical screen display parameters, such as start
address, raster address, and memory width. It also includes the cursor definition, zoom factor, and
lightpen registers.
FIFO Access:
For high-performance drawing, key drawing processor registers are coupled to the host MPU via the
ACRTC’s 16-byte read and write FIFOs. Figure and Figure illustrate the hardware and direct access
register information.
ACRTC commands are sent from the MPU via the write FIFO to the command register. As the
ACRTC completes a command, the next command is automatically fetched from the write FIFO and
put into the command register.
The pattern RAM defines drawing and painting patterns. It is accessed with the ACRTC’s Read
Pattern RAM (RPTN) and Write Pattern RAM (WPTN) register access commands.
The drawing parameter registers define detailed parameters of the drawing process, such as color
data, area control (hitting/clipping), and pattern RAM pointers. The drawing parameter registers are
accessed using the ACRTC’s Read Parameter Register (RPR) and Write Parameter Register (WPR)
commands. Figure illustrates the drawing parameter registers.
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Data Sheet
Figure 9: Hardware Access and Direct Access Registers
Reg Name
Address
Reg(AR)
Status
Reg(SR)
FIFO
Entry(FE)
Command
Control
(CCR)
Reg #
15
14
13
12
11
AR
$0
ST
$0
$00
7
6
5
4
3
2
1
0
ARD
CED
LPD
RFF
DDM
CDM
Operation
Mode (OMR)
$04
MS
STR
ACP
WSS
Display
Control
(DCR)
$06
DSP
SE1
Undefined
$08-$7E, $9E$BE, $F0-$FE
Raster
Count(RCR)
$80
Horizontal
Sync(HSR)
$82
HC
Horizontal
Display
(HDR)
$84
HDS
$86
GBM
DRC
SE0
CSK
DSK
SE2
SE3
CRE
RFR
WFR
WFE
ARE
CEE
LPE
RFE
GAI
RAM
RRE
ACM
WRE
$8A
$8C
$8E
$0
$0
$0
Blink Control
(BCR)
$90
BON1
Horz.
Window
Disp(HWR)
$92
0, 1, 0/1
0, 1, 0/1
RC
0, 1, 1
$0
HSW
HDW
0, 1, 0/1
$0
VSW
SP1
SP0
SP2
0, 1, 0/1
0, 1, 0/1
0, 1, 0/1
0, 1, 0/1
BON2
HWS
0, 1, 0/1
0, 1, 0/1
VC
BOFF1
0, 1, 0/1
0, 1, 0/1
$0
Split Screen
Width(SSW)
WEE
RSM
ATR
$0
VDS
0, 0, 0
0, 1, 0/1
$0
$88
cs_n, rs,
rw_n
0, 0, 0
FIFO Entry
PSE
BOFF2
HWW
0, 1, 0/1
0, 1, 0/1
$94
$0
VWS
0, 1, 0/1
$96
$0
VWW
0, 1, 0/1
$98
Graphic
Cursor
(GCR)
8
CER
ABT
Vert. Window
Disp(VDR)
9
Address
$02
Vertical
Sync(VSR)
Vertical
Display
(VDR)
10
CXE
CXS
0, 1, 0/1
$9A
$0
CSY
0, 1, 0/1
$9C
$0
CYE
0, 1, 0/1
Copyright  2001
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The End of Obsolescence
ENG 21101041200
Page 16 of 32
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Data Sheet
Figure 10: Hardware Access and Direct Access Registers (cont.)
Reg Name
Raster
Addr 0
(RAR0)
Memry
Wdth 0
(MWR0)
Strt Addr 0
(SAR0)
Raster
Addr 1
(RAR1)
Mem
Width 1
(MWR1)
Strt Addr 1
(SAR1)
Raster
Addr 2
(RAR2)
Memry
Wdth 2
(MWR2)
Strt Addr 2
(SAR2)
Raster
Addr 3
(RAR3)
Memry
Wdth 3
(MWR3)
Strt Addr 3
(SAR3)
Blk Cursor
1 (BCUR1)
Blk Cursor
2 (BCUR2)
Reg #
$C0(Upper
Scrn)
$C2(Upper
Scrn)
14
9
4
3
2
1
0
FRA0
$0
0, 0, 0
$0
SA0H/SRA0
0, 1, 0/1
0, 1, 0/1
$0
SDA1
FRA1
0, 1, 0/1
0, 1, 0/1
$0
SA1H/SRA1
0, 1, 0/1
SA1L
$0
0, 1, 1
LRA2
CH
R
$0
$0
FRA2
0, 1, 0/1
MW2
$0
SDA2
0, 1, 0/1
$0
SA2H/SRA2
0, 1, 0/1
SA2L
$0
cs_n,
0, 1,rs,0/1
rw_n
LRA3
CH
R
$0
$0
FRA3
0, 1, 0/1
MW3
$0
SDA3
0, 1, 0/1
$0
SA3H/SRA3
0, 1, 0/1
SA3L
BCW1
cs_n,
0, 1,rs,0/1
rw_n
BCSR1
$0
BCER1
0, 1, 0/1
BCA1
BCW2
0, 1, 0/1
BCSR2
$0
BCER2
0, 1, 0/1
BCA2
CM
CON1
COFF1
HZF
$EC
$0
CON2
LPAL
ENG 21101041200
Page 17 of 32
COFF2
$0
CH
R
$EE
Copyright  2001
innovASIC
The End of Obsolescence
0, 1, 0/1
VZF
$0
cs_n, rs, rw_n
0, 0, 0
MW1
$E5
$EA
5
$0
$0
$E2
Zoom
Factor
(ZFR)
6
LRA1
CH
R
$DC(Wndw
Scrn)
$DE(Wndw
Reg #
Scrn)
$E8
7
SDA0
$0
$D8(Wndw
Scrn)
$E4
8
SA0L
$D4(Lower
Scrn)
$D6(Lower
Reg #
Scrn)
$E0
10
MW0
$0
$D0(Lower
Scrn)
$DA(Wndw
Scrn)
11
$0
$CC(Base
Scrn)
$CE(Base
Scrn)
$D2(Lower
Scrn)
12
LRA0
CH
R
$C8(Base
Scrn)
$CA(Base
Scrn)
13
$0
$C4(Upper
Scrn)
$C6(Upper
Scrn)
Cursor Def.
(CDR)
Lightpen
Addr
(LPAR)
15
$0
0, 1, 0/1
0, 1, 0/1
FRA3
0, 1, 0/1
0, 1, 0/1
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Data Sheet
Figure 11: Drawing Parameter Registers
Reg Name
Reg #
Color 0 (CL0)
Pr00
CL0
R/W
Color 1 (CL1)
Pr01
CL1
R/W
Color Cmpr
(CCMP)
Pr02
CCMP
R/W
Edge Color
(EDG)
Pr03
EDG
R/W
Mask
(MASK)
Pr04
MASK
R/W
Pattern RAM
Control
(PRC)
Area
Def(ADR)->
Set 2's Comp.
for neg.
values of X
and Y axis.
Read Write
Pntr (RWP)
Undefined
Drawing Pntr
(DP)
Current
Pntr(CP)->
Set 2's Comp.
for neg.
values
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read/Write
Pr05
PPY
PZCY
PPX
PZCX
R/W
Pr06
PSY
$0
PSX
$0
R/W
Pr07
PEY
PZY
PEX
PZX
R/W
Pr08
XMIN
R/W
Pr09
YMIN
R/W
Pr0A
XMAX
R/W
YMAX
cs_n,
rs, rw_n
R/W
Reg #
Pr0C
Pr0C
15
DN
$0
Pr0D
RWPH
RWPL
Pr0E-Pr0F,
Pr14-Pr15
Pr10
R/W
$0
$0
DN
Pr11
$0
R/W
DPAH
DPAL
R/W
R
DPD
R
Pr12
X
R
Pr13
Y
R
Copyright  2001
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ENG 21101041200
Page 18 of 32
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Data Sheet
COMMAND TRANSFER MODES:
Program Transfer and DMA Transfer are the two modes used to transfer commands and associated
parameters issued by the MPU to the ACRTC.
Program Transfer:
Program transfer occurs when the MPU specifies the FIFO entry address and then writes operation
code/parameters to the write FIFO under program control. The MPU writes are normally
synchronized with ACRTC FIFO status by software polling or interrupts.
Software Polling (WFR, WFE interrupts disabled):
•
MPU program checks the SR for WFR=1, and then writes 1-word operation code/parameters, or
•
MPU program checks the SR for write WFE=1, and the writes 1- to 8-word operation
code/parameters.
Interrupt Driven (WFR, WFE interrupts enabled):
•
MPU WFR interrupt service routine writes 1-word operation code/parameters, or
•
MPU WFE interrupt service routine writes 1- to 8-word operation code/parameters.
DMA Transfer:
Commands and parameters can be transferred from MPU system memory by an external DMAC.
The MPU initiates and terminates command DMA transfer mode under software control.
Command DMA can also be terminated by assertion of the done_n input.
Using command DMA transfer, the ACRTC will issue cycle stealing DMA requests to the DMAC
when the write FIFO is empty. The DMA data is automatically sent from system memory to the
ACRTC write FIFO regardless of the contents of the address register.
Command Function:
The ACRTC commands are divided into three groups, register access commands, data transfer
commands, and graphic drawing commands.
Register access commands:
Access to the drawing processor drawing parameter registers and the pattern RAM is through the
read/write FIFOs using register access commands. When writing register access commands to an
initially empty write FIFO, the MPU does not have to synchronize to write FIFO status. The
ACRTC can fetch and execute these commands faster than the MPU can issue them.
Data transfer commands:
Data is moved between the host system memory and the frame buffer, or within the frame buffer
using the data transfer commands. Before issuing these commands, a physical 20-bit frame buffer
address must be specified in the RWP (read/write pointer) drawing parameter register.
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The End of Obsolescence
ENG 21101041200
Page 19 of 32
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Data Sheet
Graphic Drawing Commands:
The graphic drawing commands cause the ACRTC to draw. Graphic drawing is performed by
modifying the contents of the frame buffer based on micro coded drawing algorithms in the ACRTC
drawing processor. Parameters for these commands are specified using logical X-Y addressing. The
display processor performs the complex task of translating a logical pixel address to a linear frame
buffer word address, and further, selecting the proper sub field of the word.
Many instructions allow specification in either absolute or relative X-Y coordinates. In both cases,
two’s compliment numbers represent both positive and negative values.
Table 2 and Table 3 tabulate the ACRTC drawing commands and Op-Codes available.
Table 2: ACRTC Command Table
Type
Register Access Command
Data Transfer Command
Graphic Drawing Command
# (words)
CLK_2 Cycles
ORG
WPR
Mnemonic
Origin
Write Parameter Reg
3
2
8
6
RPR
Read Parameter Reg
1
6
WPTN
RPTN
Write Pattern RAM
Read Pattern RAM
n+2
2
4n+8
4n+10
DRD
DMA Read
3
(4x+8)y+12(x*y/8 )+(62~68)
DWT
DMA Write
3
(4x+8)y+16(x*y/8
DMOD
RD
DMA Modify
Read
3
1
(4x+8)y+16(x*y/8
12
WT
Write
2
8
MOD
Modify
2
8
CLR
Clear
4
(2x+8)y+12
SCLR
CPY
Selective Clear
Copy
4
5
(4x+8)y+12
(6x+8)y+12
SCPY
Selective Copy
5
(6x+8)y+12
AMOVE
RMOVE
Absolute Move
Relative Move
3
3
56
56
ALINE
Absolute Line
3
P*L+18
RLINE
Relative Line
3
P*L+18
ARCT
RRCT
Absolute Rectangle
Relative Rectangle
3
3
2P(A+B)+54
2P(A+B)+54
APLL
Absolute Polyline
2n+2
RPLL
Relative Polyline
2n+2
APLG
RPLG
Absolute Polygon
Relative Polygon
2n+2
2n+2
CRCL
Circle
2
8d+66
ELPS
Ellipse
4
10d+90
AARC
RARC
Absolute Arc
Relative Arc
5
5
8d+18
8d+18
AEARC
Absolute Ellipse Arc
7
10d+96
REARC
Relative Ellipse Arc
7
10d+96
AFRCT
RFRCT
Absolute Filled Rectangle
Relative Filled Rectangle
3
3
(P*A+8)B+18
(P*A+8)B+18
PAINT
Paint
1
DOT
Dot
1
8
PTN
AGCPY
Pattern
Absolute Graphic Copy
2
5
(P*A+10)B+20
((P+2)A+10)B+70
RGCPY
Relative Graphic Copy
5
((P+2)A+10)B+70
Copyright  2001
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The End of Obsolescence
Command Name
ENG 21101041200
Page 20 of 32
∑
∑
∑
∑
↑
↑)+34
↑)+34
( P * L + 16 ) + 8
( P * L + 16 ) + 8
( P * L + 16 ) + P * Lo + 20
( P * L + 16 ) + P * Lo + 20
(18A+102)B-58(Applies to rectagular figures, varies for other shapes )
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Data Sheet
Table 3: Opcode Map
Type
Register Access Command
Data Transfer Command
Graphic Drawing Command
Mnemonic
Operation Code
Parameter
ORG
WPR
0000010000000000
0 0 0 0 1 0 0 0 0 0 0 RN
DPH DPL
D
RPR
WPTN
0 0 0 0 1 1 0 0 0 0 0 RN
0 0 0 1 1 0 0 0 0 0 0 0 PRA
n
D1,...,Dn
RPTN
DRD
0 0 0 1 1 1 0 0 0 0 0 0 PRA
0010010000000000
n
AX
AY
DWT
DMOD
RD
0010100000000000
0 0 1 0 1 1 0 0 0 0 0 0 0 0 MM
0100010000000000
AX
AX
AY
AY
WT
MOD
0100100000000000
0 1 0 0 1 1 0 0 0 0 0 0 0 0 MM
D
D
CLR
SCLR
0101100000000000
0 1 0 1 1 1 0 0 0 0 0 0 0 0 MM
D
D
AX
AX
CPY
SCPY
AMOVE
00 1 1 0 S DSD 0 0 0 0 0 0 0 0
01 1 1 1 S DSD 0 0 0 0 0 0 MM
1000000000000000
SAH
SAH
X
SAL
SAL
Y
RMOVE
ALINE
1000010000000000
1 0 0 0 1 0 0 0 AREA COL OPM
dX
X
dY
Y
RLINE
ARCT
1 0 0 0 1 1 0 0 AREA COL OPM
1 0 0 1 0 0 0 0 AREA COL OPM
dX
X
dY
Y
RRCT
APLL
RPLL
1 0 0 1 0 1 0 0 AREA COL OPM
1 0 0 1 1 0 0 0 AREA COL OPM
1 0 0 1 1 1 0 0 AREA COL OPM
dX
n
n
dY
X1,Y1,...XN,YN
dX1,dY1,...dXN,dYN
APLG
RPLG
1 0 1 0 0 0 0 0 AREA COL OPM
1 0 1 0 0 1 0 0 AREA COL OPM
n
n
X1,Y1,...XN,YN
dX1,dY1,...dXN,dYN
CRCL
ELPS
AARC
1 0 1 0 1 0 0 C AREA COL OPM
1 0 1 0 1 1 0 C AREA COL OPM
1 0 1 1 0 0 0 C AREA COL OPM
r
a
Xc
b
Yc
DX
Xe
Ye
RARC
AEARC
1 0 1 1 0 1 0 C AREA COL OPM
1 0 1 1 1 0 0 C AREA COL OPM
dXc
a
dYc
b
dXe
Xc
dYe
Yc
Xe
Ye
REARC
AFRCT
1 0 1 1 1 1 0 C AREA COL OPM
1 1 0 0 0 0 0 0 AREA COL OPM
a
X
b
Y
dXc
dYc
dXe
dYe
RFRCT
PAINT
1 1 0 0 0 1 0 0 AREA COL OPM
1 1 0 0 1 0 0 E AREA 0 0 000
dX
dY
DOT
PTN
AGCPY
1 1 0 0 1 1 0 0 AREA COL OPM
1 1 0 1 SL SD AREA COL OPM
1 1 1 0 S DSD AREA 0 0 OPM
SZ
Xs
Ys
DX
DY
RGCPY
1 1 1 1 S DSD AREA 0 0 OPM
dXs
dYs
dDX
dDY
Copyright  2001
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The End of Obsolescence
ENG 21101041200
Page 21 of 32
AY
AY
AX
AX
AY
AY
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Data Sheet
AC/DC PARAMETERS:
Absolute maximum ratings:
Operating Temp (Comm’l)…….......................………………...…..0°C to +70°C
Storage Temperature.......................................…....……....……...…- 65°C to 150°C
VCC Supply Voltage…………......................................………..…... - 0.3V to +4.6V
Input Voltage Range…...............................................…..................... - 0.3V to +4.6V
Allowable Input Current……………………………………….…………. TBD
Total Allowable Input Current……………………………………………..TBD
Recommended Operating Conditions (@ 9.8 MHz):
Power Supply VCC………………………………………………..4.75V to 5.25V
Input Low Voltage VIL……………………………………………..…0V to 0.8V
Input High Voltage VIH…………………………………………...….2.0V to V CC
Operating Temperature Range…………………………………….....0°C to 70°C
DC Characteristics:
Item
Input High Level
Voltage
Input Low Level
Voltage
Input Leak
Current
Hi-Z Input
Current
Output High
Level Voltage
Output Low
Level Voltage
All Inputs
Symbol
VIH
Min
2.0
Max
-
Unit
V
Test Conditions
9.8 MHz
All Inputs
VIL
-
0.8
V
9.8 MHz
rw_n, cs_n, rs, res_n,
dack_n, clk_2, lpstb
d[15:0], mad[15:0],
exsync_n
d[15:0], mad[15:0],
exsync_n, cud1_n,
cud2_n, dreq_n,
dtack_n, hsync_n,
vsync_n, mrd,
draw_n, as_n,
disp1_n, disp2_n, chr,
mcyc, ra4, ma16/ra0,
ma19/ra3
d[15:0], mad[15:0],
exsync_n, cud1_n,
cud2_n, dreq_n,
dtack_n, hsync_n,
vsync_n, mrd,
draw_n, as_n,
disp1_n, disp2_n, chr,
mcyc, ra4, ma16/ra0,
ma19/ra3
I in
-10
10
uA
VSS to VCC
I TSI
-10
10
uA
VSS to VCC
VOH
0.7Vcc
uA
I OH = -4mA
CMOS Output
VOL
0.3VCC
V
I OL = 4mA
CMOS Output
VOL
0.3VCC
V
I LOD
TBD
uA
I OL = 4mA Open
Drain
VOH = VCC
irq_n, done_n
Output Leak
Current(Hi-Z)
irq_n, done_n
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ENG 21101041200
Page 22 of 32
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Item
Input Capacitance
d[15:0], mad[15:0],
exsync_n, rw_n, cs_n,
rs, res_n, dack_n,
clk_2, lpstb
irq_n, done_n
Data Sheet
Symbol
CIN
Min
Output
COUT
Capacitance
CurrentI CC
Consumption
(VCC = 5.0V+5%, VSS = 0V, Ta = 0 to 70o C, unless otherwise noted.)
Copyright  2001
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The End of Obsolescence
ENG 21101041200
Page 23 of 32
Max
TBD
Unit
pF
Test Conditions
TBD
TBD
pF
TBD
TBD
mA
9.8 MHz
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Data Sheet
AC Characteristics:
Clock Timing:
Item
Symbol
9.8 MHz Version
Unit
Min
Max
f
1
9.8
MHz
tCYC
102
1000
ns
Clock High Level Pulse Width
t PWCH
46
500
ns
Clock Low Level Pulse Width
tPWCL
46
500
ns
Operation Frequency of clk_2
Clock Cycle Time
Clock Rise Time
tcr
5
ns
Clock Fall Time
tc f
5
ns
MPU Read / Write Cycle Timing:
Item
Symbol
9.8 MHz Version
Min
Unit
Max
rw_n Setup Time
tRWS
50
ns
rw_n Hold Time
tRWH
0
ns
rs Setup Time
tRSS
50
ns
rs Hold Time
tRSH
0
ns
cs_n Setup Time
tCSS
40
ns
cs_n High Level Width
tWCSH
60
ns
Read Wait Time
tRWAI
0
ns
Read Data Access Time
tRDAC
Read Data Hold Time
tRDH
Read Data Turn Off Time
t RDZ
60
ns
dtack_n Delay Time (Z to L)
t DTKZL
70
ns
dtack_n Delay Time (D to L)
tDTKDL
dtack_n Release Time (L to H)
tDTKLH
80
ns
dtack_n Turn Off Time (H to Z)
tDTKZ
100
ns
Data Bus 3-State Recovery Time 1
t DBRT1
0
ns
Write Wait Time
tWWAI
0
ns
Write Data Setup Time
tWDS
40
ns
Write Data Hold Time
tWDH
10
ns
Copyright  2001
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ENG 21101041200
Page 24 of 32
80
10
ns
ns
0
ns
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Data Sheet
AC Characteristics (continued):
DMA Read / Write Cycle Timing:
Item
Symbol
9.8 MHz Version
Min
Unit
Max
dreq_n Delay Time 1
t DRQD1
110
ns
dreq_n Delay Time 2
t DRQD2
70
ns
DMA r / w_n Setup Time
tDMRWS
50
ns
DMA r / w_n Hold Time
tDMRWH
0
ns
dack_n Setup Time
t DAKS
40
ns
dack_n Hold Time
tWDAKH
60
ns
tDRW
0
ns
DMA Read Wait Time
DMA Read Data Access Time
t DRDAC
DMA Read Data Hold Time
t DRDH
DMA Read Data Turn Off Time
tDRDZ
60
ns
DMA dtack_n Delay Time (Z to L)
t DDTZL
70
ns
DMA dtack_n Delay Time (D to L)
tDDTDL
DMA dtack_n Release Time (L to H)
tDDTLH
80
ns
DMA dtack_n Turn Off Time (H to Z)
tDDTHZ
100
ns
done_n Output Delay Time
tDND
70
ns
done_n Output Turn Off Time
tDNL2
80
ns
Data Bus 3-State Recovery Time 2
tDBRT2
0
ns
done_n Input Pulse Width
tDNPW
2
tCYC
DMA Write Wait Time
tDWW
0
ns
DMA Write Data Setup Time
t DWDS
40
ns
DMA Write Data Hold Time
t DWDH
10
ns
Copyright  2001
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The End of Obsolescence
ENG 21101041200
Page 25 of 32
80
10
ns
ns
0
ns
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Data Sheet
AC Characteristics (continued):
Frame Memory Read / Write Cycle Timing:
Item
Symbol
9.8 MHz Version
Min
Unit
Max
as_n "Low" Level Pulse Width
t PWASL
20
ns
Memory Address Hold Time 2
tMAH2
5
ns
as_n Delay Time 1
t ASD1
as_n Delay Time 2
t ASD2
Memory Address Delay Time
50
ns
5
40
ns
tMAD
10
50
ns
Memory Address Hold Time 1
tMAH1
15
Memory Address Turn Off Time (A to Z)
tMAAZ
Memory Read Data Setup Time
tMRDS
30
ns
Memory Read Data Hold Time
tMRDH
0
ns
ma_ra Delay Time
tMARAD
ma_ra Delay Time
tMARAH
5
MCYC Delay Time
tMCYCD
5
mrd Delay Time
tMRDD
mrd Hold Time
tMRH
draw_n Delay Time
tDRWD
draw_n Hold Time
tDRWH
Memory Write Data Delay Time
tMWDD
Memory Write Data Hold Time
tMWDH
5
ns
Memory Address Setup Time 1
tMAS1
10
ns
Memory Address Setup Time 2
tMAS2
10
ns
ns
35
60
ns
ns
ns
40
ns
50
ns
5
ns
50
5
ns
ns
50
ns
NOTE: t MAD is independent of clk_2 operation frequency (f) and timing of tASD2 and t MAS1
Copyright  2001
innovASIC
The End of Obsolescence
ENG 21101041200
Page 26 of 32
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Advanced CRT Controller
Data Sheet
AC Characteristics (continued):
Display Control Signal Output Timing:
Item
Symbol
9.8 MHz Version
Min
Unit
Max
hsync_n Delay Time
tHSD
50
ns
vsync_n Delay Time
tVSD
50
ns
disp1_n, disp2_n Delay Time
tDSPD
50
ns
cud1_n, cud2_n Delay Time
tCUDD
50
ns
exsync_n Output Delay Time
tEXD
50
ns
chr delay time
tCHD
50
ns
15
exsync_n Input Timing:
Item
Symbol
9.8 MHz Version
Min
Unit
Max
exsync_n Input Pulse Width
tEXSW
3
tCYC
exsync_n Input Setup Time
t EXS
30
ns
exsync_n Input Hold Time
tEXH
10
ns
lpstb Input Timing:
Item
Symbol
9.8 MHz Version
Min
Unit
Max
lpstb Uncertain Time 1
t LPD1
45
ns
lpstb Uncertain Time 2
t LPD2
10
ns
lpstb Input Hold Time
tLPH
10
ns
lpstb Input Inhibit Time
tLPI
4
tCYC
res_n and dack_n Input Timing:
Item
Symbol
9.8 MHz Version
Min
Unit
Max
dack_n Setup Time for res_n
tDAKSR
100
ns
dack_n Holt Time for res_n
tDAKHR
0
ns
tRES
10
tCYC
res_n Input Pulse Width
Copyright  2001
innovASIC
The End of Obsolescence
ENG 21101041200
Page 27 of 32
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IA63484
Advanced CRT Controller
Data Sheet
Figure 12: DMA Write Cycle Timing
clk_2
tDRQD1
dreq_n
rw_n
tDRQD2
tDAKS
tDMRWS
tDMRWH
dack_n
tDWDS tDWDH
d[15:0]
tDWW
tDDTLH
tDNLZ1
tDDTZL
dtack_n_ready_n
tDDTHZ
tDND
done_n(output)
tDNPW
done_n(input)
Figure 13: Display Cycle Timing
refresh_cycle
attribute_cntl_info_out_cycle
clk_2
tASD2
tPWASL
tASD1
as_n
tMAA2
tMAH1
tMAD
mad[15:0]
refresh_adrs
tATRD1
tMAS1
refresh_adrs
tATRH1
ATR
tATRH2
ma19_16_ra[3:0 ]
tMARAD
tATRD2
ATR
tMCYCD
mcyc
tMRDD
tMRH
tDRWD
tDRWH
mrd
draw_n
Copyright  2001
innovASIC
The End of Obsolescence
ENG 21101041200
Page 28 of 32
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IA63484
Advanced CRT Controller
Data Sheet
Figure 14: Frame Memory Refresh & Video Attributes Output Cycle Timing
Refresh_cycle
Attribute_cntl_info_out_cycle
clk_2
tASD2
tASD1
tPWASL
as_n
mad[15:0]
tMAA2
tMAH1
tMAD
refresh _adrs
tMAS1
refresh_adrs
tATRH1
tATRD1
ATR
tATRH2
tMARAD
ma19_16_ra[3:0]
tATRD2
ATR
tMCYCD
mcyc
tMRDD
tMRH
tDRWD
tDRWH
tHSD
tHSD
mrd
draw_n
hsync_n
Figure 15: Display Control Signal Output Timing
clk_2
tMCYD
mcyc
tHSD
tVSD
hsync_n_vsync_n
tDSPD
disp1_n_disp2_n
tCUDD
cud1_n_cud2_n
tEXD
exsync_n
tCHD
chr
Copyright  2001
innovASIC
The End of Obsolescence
ENG 21101041200
Page 29 of 32
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Customer Support:
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IA63484
Advanced CRT Controller
Data Sheet
Figure 16: Input Timing exsync_n
clk_2
tEXH
tEXSW
tEXS
exsync_n
tHSD
hsync_n
mcyc(phase_shifted)
mcyc(phase_not_shifted)
Figure 17: Input Timing (Single Access Mode) lpstb
Display_Cycle
clk_2
mcyc
tLPD1
mad[15:0]
M
M+1
tLPD2
M+2
tLPH
lpstb
Figure 18: Input Timing (Dual Access Mode) lpstb
Display_Cycle
clk_2
mcyc
mad[15:0]
M
M+1
M+2
tLPD1
tLPD2
tLPH
tLP1
lpstb
tLPD1
tLPD2
tLPH
tLP1
lpstb
Copyright  2001
innovASIC
The End of Obsolescence
ENG 21101041200
Page 30 of 32
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IA63484
Advanced CRT Controller
Data Sheet
PLCC Packaging Dimensions:
PIN 1
IDENTIFIER & ZONE
E
E1
D1
E3
1.22/1.07
2 PLCS
D
D3
TOP VIEW
BOTTOM VIEW
.81 / .66
Lead Count = 68
MIN
MAX
(Millimeters)
(Millimeters)
A1
A
SEATING PLANE
Symbol
0.20 TYP
e
.51 MIN.
.53 / .31
A
4.20
5.08
A1
2.29
3.30
D
25.02
25.27
D1
24.13
24.33
E
25.02
25.27
E1
24.13
24.33
R 1.14 / .64
D2 / E2
SIDE VIEW
e
Copyright  2001
innovASIC
The End of Obsolescence
ENG 21101041200
Page 31 of 32
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Customer Support:
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IA63484
Advanced CRT Controller
Data Sheet
ORDERING INFORMATION:
Table 1:
Part Number
IA63484-PLC68I
Temperature Grade
Industrial
Package
68 lead Plastic Leaded Chip Carrier (PLCC)
Contact innovASIC for other package and processing options.
Copyright  2001
innovASIC
The End of Obsolescence
ENG 21101041200
Page 32 of 32
www.innovasic.com
Customer Support:
1−888−824−4184