UG0567: RTG4 FPGA High Speed Serial Interfaces User Guide

RTG4 FPGA High-Speed Serial Interfaces
UG0567 User Guide
RTG4 FPGA High-Speed Serial Interfaces
Table of Contents
About This Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1 SERDES Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SERDES Block Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SERDES Block Serial Protocols Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
I/O Signal Interface of SERDES Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Using SERDES Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Using SERDES Block in Libero SoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
APB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
APB Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Radiation Hardening . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2 Serializer/De-serializer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SERDES Block Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PMA Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
TX Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
RX Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Clock Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SERDES Testing Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Diagnostic Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pseudo-Random Bit Sequences Pattern Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pseudo-Random Bit Sequences Pattern Checker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Custom Pattern Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
34
36
37
37
Using SmartDebug Utility for SERDES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
SERDES Block–I/O Signal Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Acronym . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3 PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Overview of PCIe in RTG4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
PCIe EP Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Using SERDES Block in PCIe Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
PCIe System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Physical Coding Sublayer Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
PCIe System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Revision 3
2
Table of Contents
Fabric Interface for PCIe System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
PCIe Clocking Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
PCIe Reset Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
PCI Express Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Designing with PCIe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Base Address Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Translation on AXI3 Master Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AXI3 Slave Interface Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCIe System Credit Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User Data Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Setting up Lane Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCIe Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCIe EP implementation supports L0, L1, and a special version of L2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCIe Interrupts for Endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ECRC Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
62
63
65
66
67
68
68
69
70
70
Bridge Register Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Register Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash Bits (Flash) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
APB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fixed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Information Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bridge Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address Mapping Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EP Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCIe Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCIe Bridge Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
71
71
71
71
72
73
74
75
75
76
PCIe Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Common Configuration Space Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
PCIe Extended Capability Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Type 0 Configuration Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
IP Core Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
MSI Capability Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Power Management Capability Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
PCIe Capability Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
PCIe AER Extended Capability Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
TLP Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
C.1 Content of a TLP without a Data Payload
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
C.2 Content of a TLP with a Data Payload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
SERDES Block PCIe Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
4 XAUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Overview of XAUI Implementation in RTG4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XAUI Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RTG4 XAUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
107
108
108
108
Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Using High-Speed Serial Configurator for XAUI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Simulating the SERDES Block with XAUI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Using the XAUI IP Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Reset and Clocks for XAUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
XAUI Mode Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
XAUI Mode Reset Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Using MDIO Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XAUI IP Block Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XAUI Mode Loopback Test Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using MMD Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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120
122
122
RTG4 FPGA High-Speed Serial Interfaces
MDIO Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
SERDES Block System Register Configurations for XAUI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
5 EPCS Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
RTG4 EPCS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Using High-Speed Serial Interfaces Configurator in EPCS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Using SERDES Block in EPCS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simulating the SERDES Block in EPCS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Creating an Application in EPCS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
132
132
132
132
SERDES Block Architecture in EPCS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
SERDES Block in EPCS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
SERDES Block Fabric Interface in EPCS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Reset and Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
EPCS Mode Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
EPCS Mode Reset Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
EPCS SERDES Calibration and External Resistor Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
6 SERDES Block Register Access Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Configuration of SERDES Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
SERDES Block System Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
SERDES Block Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
SERDES Block Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Product Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Customer Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contacting the Customer Technical Support Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
185
185
185
185
185
Email . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
My Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Outside the U.S. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
ITAR Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Revision 3
4
About This Guide
Purpose
This user guide provides details of the high-speed serial interfaces (SERDES) and integrated
functionality support for multiple protocols within the RTG4™ field programmable gate array (FPGA). The
protocols supported in the RTG4 FPGA devices are peripheral component interconnect express (PCIe®)
and ten gigabits attachment unit interface (XAUI). In addition, user defined high serial protocol
implemented in the RTG4 FPGA fabric can access SERDES lanes through the external physical coding
sublayer (EPCS) interface. The flexibility of EPCS can be used to build protocol specific interfaces such
as JESD204B, and 1000 Base-X, and serial gigabit media independent interfaces (SGMII). The
integrated blocks can be configured to support single or multiple serial protocol modes of operation and
connection to the FPGA fabric.
Contents
This user guide contains the following chapters:
•
Chapter 1 - SERDES Block
•
Chapter 2 - Serializer/De-serializer
•
Chapter 3 - PCI Express
•
Chapter 4 - XAUI
•
Chapter 5 - EPCS Interface
•
Chapter 6 - SERDES Block Register Access Map
Additional Documentation
The following is a list of additional documentation available on RTG4 FPGAs:
Table 1 • RTG4 Additional Documents
Document
Description
RTG4 FPGA Product Brief
Provides an overview of RTG4 FPGA family of devices, features and
benefits, and ordering information.
RTG4 FPGA Datasheet
Provides details about RTG4 AC characteristics, DC characteristics,
switching characteristics, and general specifications.
RTG4 FPGA Pin Descriptions
Contains RTG4 pin descriptions, bank location diagrams, packaging
information, and links to pin assignment tables.
RTG4 FPGA Fabric User Guide
Describes the RTG4 FPGA radiation tolerant fabric architecture and
embedded hard blocks like LSRAM, uSRAM, mathblocks and
input/outputs (I/Os).
RTG4 FPGA Clocking Resources User Describes the RTG4 FPGA devices clocking resources that include,
Guide
FPGA fully SET hardened fabric global network, clock conditioning
circuitry (CCCs) with dedicated Radiation-hardened phase-locked loops
(PLLs), and a radiation hardened 50 MHz RC oscillator.
RTG4 FPGA System Controller User Describes the System Controller that manages programming,
Guide
initialization, and configuration of the RTG4 FPGA devices and also the
subsystems and interfaces available in the System Controller.
RTG4 FPGA Programming User Guide
Describes the programming modes that the RTG4 FPGAs support and
provides details about implementation of programming modes that are
validated in the RTG4 devices. The RTG4 device programming security,
debugging features and methods are not discussed in this document.
Revision 3
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RTG4 FPGA High-Speed Serial Interfaces
Table 1 • RTG4 Additional Documents
DirectC User Guide
Provides instructions to make necessary changes to DirectC, a Microsemi
developed programming algorithm based on C code that is used to create
a binary executable, downloaded to the system along with the
programming data file.
Libero SoC User Guide
Describes the usage of the Libero SoC software and the design flow.
rd
3
Party Documentation
•
PCISIG Specifications
•
SERDESIF BFM Simulation Guide
•
SmartDebug Hardware Design Debug Tools Tutorial
Revision 3
6
1 – SERDES Block
Introduction
The high-speed serial interface block of the RTG4 FPGA device, also known as serializer/de-serializer
(SERDES Block), provides support for several serial communication standards. This module integrates
several functional blocks to support multiple high-speed serial protocols within the FPGA.
Features
The SERDES block has the following features:
•
6 SERDES/PCS blocks (Quads/4x Lanes) - Up to 24 total SERDES lanes
•
x1, x2, and x4 PCIe Endpoint protocol support
–
PCIe is compliant with the PCIe Base Specification 1.1 for Gen1 and PCIe Base Specification
2.1 for Gen1 or Gen2 - only supports the 2.5 Gbps variant of the Gen2 specification.
•
10 gigabit attachment unit interface (XAUI) protocol support
•
External physical coding sub-layer (EPCS) interface supports user defined high serial protocols,
such as serial gigabit media independent interface (SGMII)1000-BaseX, and JESD204B protocol
support up to 3 Gbps.
•
Single or multiple serial protocol modes of operation. In multiple serial protocol modes, two
protocols can be implemented on the four physical lanes of the SERDES block.
Revision 3
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SERDES Block
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Figure 1-1 • RTG4 SERDES Block Diagram
Device Support
Table 1-1 shows the total number of SERDES blocks available in each RTG4 device.
Table 1-1 • Available SERDES Blocks in RTG4 Devices
SERDES Lanes/ PCIE Endpoints available
RT4G075
RT4G150
16/2
24/2
Note: The specified number of SERDES blocks varies depending on the device package. PCIe Endpoints support x1,
x2, or x4 PCIe links.
SERDES Block Overview
The RTG4 device family has up to six high-speed serial interface blocks (SERDES Block). Each
SERDES block interfaces with fabric, program control, and four duplex SERDES differential I/O pads.
Individually, the SERDES block. Figure 1-1 on page 8 shows the inclusive high level view of the RTG4
SERDES block. Dependent on the implemented protocol, the SERDES block provides an AXI3 or AHB
(PCIe), XGMII (XAUI), or native SERDES clock and data (EPCS) along with the control plane interface
APB. Not all the SERDES block modules are PCIE capable.
8
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RTG4 FPGA High-Speed Serial Interfaces
As shown in Figure 1-2, two of the SERDES block modules in each device contain PCIE functionality.
PCIE Sub-system (PCIESS) modules include PCIe functionality whereas non-PCIE Sub-system (NPSS)
modules do not include PCIE.
Figure 1-2 shows the number of PCIESS and NPSS modules per device. PCIESS modules are superset
of NPSS modules with all capabilities of NPSS modules and PCIe functionality included.
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Figure 1-2 • SERDES Block Capability Per Device
Note:
1. Each SERDES block supports up to 4 SERDES lanes. The PCIESS SERDES blocks include PCIE
functionality, but the NPSS SERDES blocks do not include PCIe functionality.
2. PCIESS blocks have PCIE x1, x2, or x4 Endpoint capabilities.
Each of these SERDES blocks includes:
•
PCIe System: This block implements the x1, x2, and x4 lane PCIe endpoint (regular and reverse
lanes mode) with an AXI3/AHB interface to the fabric. The RTG4 PCIe is compliant with the PCIe
Base Specification 1.1 for Gen1 and PCIe Base Specification 2.0 for Gen1 or Gen2 - only
supports the 2.5Gbps variant of the Gen2 specification. Refer to the "PCI Express" chapter on
page 41 for more information on the PCIe system block.
Note:This functionality is only included in the 2 PCIESS blocks.
•
XAUI Extender: This block is an XGMII extender to support the XAUI protocol through a FPGA IP
MAC core in the FPGA fabric. Refer to the "XAUI" chapter on page 107 for more information.
•
EPCS: This block is a basic mode used to extend the SERDES for custom support access to the
FPGA fabric. Refer to the "EPCS Interface" chapter on page 129 for more information.
•
SERDES: This block implements up to four channels of high-speed I/O, the physical media
attachment layer (PMA), and a physical coding sub-layer (PCS) of PCIe protocols. This PCS layer
is compliant to the Intel PIPE 2.0 specification. It also implements the PMA calibration and control
logic. The PCIe PCS functionality can be bypassed completely in order to use the SERDES lanes
for protocols other than PCIe. This allows use of the PMA in various PHY modes and allows for
the implementation of various protocols in the RTG4 device. Refer to the "Serializer/De-serializer"
chapter on page 21 for more information on the SERDES block.
•
SERDES Block System Register: The SERDES block system registers control the SERDES
block module for single protocol or multi-protocol support implementation. These registers can be
accessed through the 32-bit APB interface, and the default values of these registers are
configured using Libero® System on-Chip (SoC) software. See Chapter 6 – SERDES Block
Register Access Map for detailed register access descriptions. The SERDES block is initially
configured at power-up with parameters determined during the FPGA design flow using the
Libero SoC software.The SERDES block configuration can subsequently be changed by writing
tho the related control registers through the advanced peripheral bus (APB) interface.
Revision 3
9
SERDES Block
Table 1-2 • SERDES Block Module Single Protocol Usage Overview
Protocol
SERDES Block Description
Data Rate
(Gbps)
Reference Clock
(typ) Input
Frequency
PCIe
SERDES block is configured to use PCIeGen1/2 x4, x2, and x1 link
mode. The PCIe link can be configured in Regular or Reversed modes.
2.5
100 MHz
XAUI
SERDES block is configured to use all four lanes. In XAUI mode, all
lanes are used and the PCIe system is put in RESET state.
4 x 3.125
156.25 MHz
EPCS
In EPCS mode, any serial protocol can be run though the EPCS
interface to fabric using the EPCS interface. EPCS mode is used for
implementing many other standard protocol interfaces such as SGMII.
1 - 3.125
100 - 160 MHz
SERDES Block Serial Protocols Support
The SERDES block supports the implementation of multiple high-speed serial protocols. Although each
of the serial protocols is unique, all of them are layered protocol stacks, and the implementation can vary
greatly from one layer to the next layer. Typically, the physical layer consists of fixed functionality that is
common to multiple packet-based protocols, while the upper layers tend to be more customizable.
The advantage of being able to connect the FPGA logic and the SERDES blocks is that it allows multiple
serial protocols in the RTG4 devices. Figure 1-3 shows the implementation of PCIe, XAUI, and EPCS
protocols using the SERDES block and FPGA fabric. Figure 1-3 shows the fixed modules contained
within the SERDES block per application. As shown in the example, PCIe applications include many
functional blocks within the SERDES block, whereas EPCS requires more FPGA IP blocks for complete
system implementation. Refer to the "PCI Express" chapter on page 41 and "XAUI" chapter on page 107
for details about the fixed protocol modules.
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RTG4 FPGA High-Speed Serial Interfaces
Link Width and Lane
Negotiation
Link Training
and Status
Channel Alignment
(x4)
Physical Layer
CRC Generation
and Checking
Clock Tolerance
Compensation
GbE State Machine/
Auto Negotiation
Channel Alignment
8b/10b
MAC Layer
Reconciliation
XAUI State Machine
A/K/R Translation
Scrambling/
Descrambling
Clock Tolerance
Compensation
Note: Typical SGMII Protocol Stack
MAC Layer
Reconciliation
MAC and Control
Clock Tolerance
Compensation
Physical Coding Sublayer
(PCS)
Framing
MAC and Control
Physical Coding Sublayer
(PCS)
Data Link Layer
(CRC, Control, DLLP)
Data Link Layer
Transaction Layer
Transaction
Layer
Application Layer
8b/10b
8b/10b
Word Alignment/
Link Sync
Word Alignment/
Link Sync
PMA (SERDES)
MDI
PCIe
Express
XAUI
PMA (SERDES)
MDI
Physical Medium
Attachment (PMA)
PMA (SERDES)
Physical Medium
Dependant (PMD)
Word Alignment/
Link Sync
EPCS
- SERDES BLOCK contained functionality
Figure 1-3 • Serial Protocol Using SERDES Block and FPGA Logic
Revision 3
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SERDES Block
I/O Signal Interface of SERDES Block
The SERDES block interfaces with the FPGA fabric and SERDES differential I/O pads. The SERDES
block I/Os can be grouped into a number of interfaces from functional perspective. The SERDES block
I/O signals interface are listed below:
•
Reset Interface
•
Clock Interface
•
AXI3/AHB-Lite Master Interface
•
AXI3 /AHB-Lite - Slave Interface
•
APB Slave Interface
•
EPCS Interface
•
I/O - PAD Interface (refer to Table 2-4 on page 38 for more information)
•
PLL Control and Status Interface
•
SERDES Block-PCI Express Interrupt and Power Management Interface
Refer to protocol specific chapters for I/O details.
Using SERDES Block
Using SERDES Block in Libero SoC
The main SERDES block GUI wizard allows the user to enter customizable design parameters. This
enables the user to step through the options to configure the building blocks to assemble correct-byconstruction SERDES block module.
The High Speed Serial Interface Configurator available in Libero SoC allows generation of the SERDES
block with the user options to configure support for various protocols. It allows module creation of Single
and Multi protocol modes. Refer to the High Speed Serial Configuration and Initialization User Guide (to
be released) for more information on protocol.
SERDES Block Resets
Refer to specific protocol chapters for detailed pin descriptions and information on reset behaviors for
each protocol. Refer to the "PCI Express" chapter on page 41, the "XAUI" chapter on page 107, and the
"EPCS Interface" chapter on page 129 for more information on using the reset signals highlighted in
Table 1-7.
Table 1-3 • Reset Interface
Port
Type
Connected To
Description
CORE_RESET_N
Input
Fabric
PCIe or XAUI mode: Active-low reset for PCIe and XAUI
fundamental core
PHY_RESET_N
Input
Fabric
SERDES-PHY-Active low reset.
APB_S_PRESET_N
Input
Fabric
Asynchronous active-low reset signal for APB slave interface.
EPCS_0_RESET_N
Input
Fabric
External EPCS interface mode: External PCS reset control
lane0 and lane1.
Output
Fabric
External EPCS interface mode (lane0 and lane1): Clean reset
deasserted on rxclk.
Output
Fabric
EPCS_1_TX_RESET_N
External EPCS interface mode (lane0 and lane1): Clean reset
deasserted on txclk.
12
R e visio n 3
EPCS_1_RESET_N
EPCS_0_RX_RESET_N
EPCS_1_RX_RESET_N
EPCS_0_TX_RESET_N
RTG4 FPGA High-Speed Serial Interfaces
Serial Protocols Setting Using the SERDES Block System Registers
The SERDES block is configured to support various modes of operation through high level SERDES
block system registers. These registers are configured using the APB interface. To facilitate the initial
configuration, a GUI in Libero SoC is provided. Figure 6-1 on page 140 describes the settings for the
three SERDES block registers to control the SERDES block into a specific mode of operation. Refer to
Chapter 6 – SERDES Block Register Access Map for more information.
APB Interface
APB Transactions
Advanced peripheral bus (APB) is used to configure and monitor the SERDES block peripheral for PCIe,
XAUI, and EPCS protocols. APB is used for write and read transfers, as shown in Figure 1-4 on
page 14.The APB write transfer starts with the apb_s_paddr, apb_s_prdata, apb_pwrite, and apb_s_psel
all changing after the rising edge of apb_s_pclk, as shown in Figure 1-4 on page 14. In the next clock
edge, the apb_s_penable is asserted, and this indicates that the Access phase is enabled. The address,
data, and control signals remain valid throughout the Access phase. The transfer completes at the end of
this cycle. The apb_s_penable signal is de-asserted at the end of the transfer. The apb_s_psel signal
goes Low unless an another transfer is immediately followed by the same peripheral. During the Access
phase, when apb_s_psel is High, the transfer can be extended by driving apb_s_pready Low. The slave
must provide the data before the end of the read transfer.
Table 1-4 lists the APB slave interfaces of SERDES block.
Table 1-4 • SERDES Block – APB Slave Interface
Port
Type
Description
APB_S_PSEL
Input
APB slave select; select signal for register for reads or writes.
APB_S_PENABLE
Input
APB strobe. This signal indicates the second cycle of an APB transfer.
APB_S_PWRITE
Input
APB write or read. If High, a write occurs when an APB transfer takes place.
If low, a read takes place.
APB_S_PADDR[13:0]
Input
APB address bus.
APB_S_PWDATA[31:0]
Input
APB write data.
APB_S_PREADY
Output
APB ready. Used to insert wait states.
APB_S_PRDATA[31:0]
Output
APB read data.
APB_S_PSLVERR
Output
APB Error.
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SERDES Block
Figure 1-4 shows the APB interface timing diagram.
25ns
0ns
50ns
apb_s_pclk
Thdapb
Tsuapb
Addr R
apb_s_paddr[13:2]
Addr W
apb_s_pwrite
apb_s_psel
apb_s_penable
RDATA
apb_s_prdata[31:0]
Tcqabp
apb_s_pready
Figure 1-4 • APB Interface Transactions Diagram
Radiation Hardening
Within the high-speed SERDES block, radiation hardening techniques are applied to the system
controller, APB, REFCLK, SPLL-used with XAUI and PCIE blocks, path from REFCLKP to
GLOBAL_0_OUT (fabric global clock), path from REFCLKN to GLOBAL_1_OUT. This is done with
several types of mitigation techniques including TMR logic triplication and self-correcting latches as well
as added digital delay buffers. The asynchronous resets are hardened using glitch-suppression filters
and by using special buffers for reset distribution in all areas of the circuit.
The following sections describe each of the serial protocols and their implementation in the RTG4
devices using the SERDES block.
PCIe Protocol
The RTG4 device family supports Gen1 and Gen2 PCIe 2.5 Gbps endpoints. The PCIe endpoint
supports PCIe base specification 1.1 (2.5 Gbps) and PCIe base specification 2.0 (2.5 Gbps) protocol with
x1, x2, and x4 lane configurations. The application interface to the PCIe link is available through the
FPGA fabric, and can be programmed to AXI3 or AHB master and slave interfaces. The RTG4 devices
have PCIe hard IP that is designed for performance and ease-of-use. The hard IP consists of the PMA,
data link, and transaction layers.
Following are the PCIe Protocol Features:
14
•
x1, x2, and x4 lane PCIe support
•
Suitable for Native Endpoint
•
PCIe base specification 2.0 and 1.1 compliant - both specifications at 2.5 Gbps
•
Single-function/Single virtual channel (VC)
•
Three 64-bit base address registers or six 32-bit base address registers
•
2 KB Receive, 1 KB Transmit, 1 KB Retry Buffers with ECC
•
64-bit AXI3/32-bit AHB master and slave interface to the FPGA fabric
R e visio n 3
RTG4 FPGA High-Speed Serial Interfaces
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Figure 1-5 • SERDES Block Configuration for PCIe Protocol (PCIESS Only)
Revision 3
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SERDES Block
Table 1-5 • PCIE Protocol Implementation RTG4 Devices - PCIESS Type Only
PHY Physical Lanes
Serial Protocol
Modes
Lane0
Lane1
Lane2
Lane3
PHY Logical Lanes Vs Logical Lanes
PCIe Protocol only mode
PCIe (x4)
PCIe (x2)
PCIe (x1)
PCIe
PCIe
PCIe
PCIe
Lane 0
Lane 1
Lane 2
Lane 3
–
–
–
–
PCIe
PCIe
Lane 0
Lane 1
PCIe
–
Lane0
PCIe Reversed mode (x4)
PCIe Reversed mode (x2)
PCIe
PCIe
PCIe
PCIe
Lane 3
Lane 2
Lane 1
Lane 0
–
–
PCIe
PCIe
Lane1
Lane 0
PCIe Reversed mode (x1)
–
–
–
PCIe-0
PCIe Reversed mode (x2)
PCIe
PCIe
–
–
Lane 1
Lane 0
–
PCIe
–
–
PCIe Reversed mode (x1)
Lane 0
XAUI only
XAUI (x4 lane)
XAUI-0
XAUI-1
XAUI-2
XAUI-3
EPCS only
All lanes are used for
user-defined protocol
EPCS
EPCS
EPCS
EPCS
EPCS
EPCS
Multi-protocol (PCIe and
EPCS) (See, Note2)
PCIe (x2)
PCIe (x1)
PCIe
PCIe
Lane0
Lane1
PCIe
–
EPCS
EPCS
EPCS
EPCS
EPCS
EPCS
Lane0
PCIe Reversed mode (x2)
PCIe Reversed mode (x1)
PCIe
PCIe
Lane1
Lane0
–
PCIe
Lane0
Notes:
1. Lane Tx-clk is used for lane0 for PCIe protocol purposes.
2. In Multi-protocol mode, EPCS is available only on lane2 and lane3.
3. Refer to Table 1-2 on page 10 for complete device listing with PCIe implementations.
4. SGMII, GbE, JESD204B, and SRIO are supported with EPCS defined protocols.
5. SERDES blocks of PCIESS type include all the functionalities for PCIE, XAUI, and EPCS protocols, whereas NPSS
blocks only support XAUI and EPCS protocols, not PCIE capabilities.
Refer to the RTG4 FPGA Datasheet for specific device speed grade dependencies for protocol IP blocks.
16
R e visio n 3
RTG4 FPGA High-Speed Serial Interfaces
XAUI Protocol
The XAUI implementation is an interface extending the XGMII, 10 gigabit media independent interface.
The XGMII is used to attach the Ethernet MAC to the PHY. The XAUI may be used in place of, or to
extend, the XGMII in chip-to-chip applications typical of most FPGA IP Ethernet MAC-to-PHY
interconnects.
Following are the XAUI Protocol Features:
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•
IEEE 802.3ae- clause 45 MDIO interface
•
IEEE 802.3ae- clause 48 state machines
•
Pseudo AKR random idle insertion (PRBS Polynomial X^7 + X^3 + 1)
•
Reference clock frequency of 156.25 MHz
•
Double-width single data rate (SDR - 64 bit XGMII interface)
•
Comma alignment function
•
PHY-XS and DTE-XS loopback
•
IEEE 802.3ae- annex 48A jitter test pattern support
•
IEEE 802.3 clause 36 8B/10B encoding compliance
•
Tolerance of lane skew up to 16 ns (50 UI)
•
IEEE 802.3 PICs compliance matrix
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Figure 1-6 • SERDES Block Configuration for XAUI Protocol (NPSS or PCIESS)
Note: Contact Microsemi sales for 10 G MAC FPGA IP information.
Revision 3
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SERDES Block
Table 1-6 shows the configuration bandwidth for using XAUI in four physical SERDES lanes. Refer to the
"XAUI" chapter on page 107 for more information on XAUI protocol implementation in the RTG4 devices.
Table 1-6 • Bandwidth for Implementing XAUI in SERDES Block PCIESS and NPSS Type
Lane0
XAUI Protocol
Single Protocol
PHY mode
Lane1
Lane2
Lane3
Protocol
Speed
(bps)
Protocol
Speed
(bps)
Protocol
Speed
(bps)
Protocol
Speed
(bps)
XAUI
3.125 G
XAUI
3.125 G
XAUI
3.125 G
XAUI
3.125 G
EPCS Protocol
By using the EPCS interface, other serial protocols can be implemented in the RTG4 device family. The
SERDES block can be configured to bypass the embedded PCS logic in the SERDES block and expose
the EPCS interface to the fabric. A user-defined IP block in the FPGA fabric can be connected to this
EPCS interface.
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Figure 1-7 • SERDES Block Configuration for EPCS Protocol (NPSS or PCIESS)
Refer to the "EPCS Interface" chapter on page 129 for more information on EPCS implementation in the
RTG4 device families.
18
R e visio n 3
RTG4 FPGA High-Speed Serial Interfaces
Table 1-7 • Options for Implementing EPCS in the SERDES Block - PCIESS Type
Lane0
Lane1
Lane2
Lane3
SGMII Protocol
Protocol
Speed
(Gbps)
Protocol
Speed
(Gbps)
Protocol
Speed
(Gbps)
Protocol
Speed
(Gbps)
Single Protocol
PHY mode
EPCS
1.25
EPCS
1.25
EPCS
1.25
EPCS
1.25
Multi-Protocol
PHY mode
PCIe
2.5
–
–
EPCS
1.25
EPCS
1.25
PCIe
2.5
PCIe
2.5
EPCS
1.25
EPCS
1.25
–
–
PCIe
2.5
EPCS
1.25
EPCS
1.25
PCIe
2.5
PCIe
2.5
EPCS
1.25
EPCS
1.25
(PCIe Link NonReversed mode)
Multi-Protocol
PHY mode
(PCIe Link
Reversed mode)
Notes: 1. These speeds are when mixed with PCIe protocols.
2. In Multi-protocol mode, EPCS is available only on lane2 and lane3.
In summary, the four SERDES physical lanes can be configured to run different serial protocols, resulting
in different modes of operation. Table 1-7 summarizes the various modes of operation of the SERDES
block.
Clocking and Resets
This section describes the clocking and reset scheme for the SERDES block. The SERDES block offers
reset and clocking options that are exposed for the different protocol choices. More details of these
options are found in the specific protocol chapters.
Clocking System for SERDES Block
The clocking system in the SERDES block includes the following:
•
•
SERDES reference clocks
–
Dedicated reference clock input pins
–
Fabric Clock available only for EPCS protocols
Fabric/serial PLL (SPLL) clocking
–
PCIe system block clocking
–
XAUI block clocking
SERDES Reference Clocks
Reference clocks are used to generate the needed internal RX and TX clocks using dedicated PLLs in
the PMA sub-block. Refer to the "Serializer/De-serializer" chapter on page 21 for more information on Tx
and Rx clock generation through PLLs. A dedicated reference clock input is available. The reference
clock inputs can either come from single-ended clock signal sources to provide two reference clocks or
can be sourced from a differential signal source to one reference clock input to the SERDES block. The
fabric clock is only available when using EPCS protocols and the user must assure the clock accuracy
and quality.
The reference clock selection is made using the High Speed Serial Interface Configurator in the Libero
SoC. It sets the MUX selection, depending on the selected reference clocks. Refer to Figure 3-12 on
page 60 for reference clock diagram.
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SERDES Block
Serial PLL (SPLL)
The SPLL manages clock domain data transfers skew between the FABRIC and SERDES block module.
The SPLL is used for PCIe and XAUI protocol implementations.
The SPLL is powered by the VDDPLL supply. This supply requires 3.3 V. Refer to the RTG4 FPGA
Datasheet for more information on the PLL power supply requirement.
Refer to the RTG4 FPGA Fabric User Guide for details on fabric based PLLS.
20
R e visio n 3
2 – Serializer/De-serializer
Introduction
The high-speed serial/de-serializer (SERDES) IP block of the RTG4 FPGA family is included within the
SERDES block module. This chapter describes the physical hardware capabilities of the SERDES and a
description of the fixed hardware blocks of the RTG4 serial physical interface (PHY). For more
Information on serial protocols, refer to the previous protocol chapters in the "SERDES Block" chapter on
page 7.
Features
Following are the main features of SERDES:
•
TX block including differential impedance matching output buffers, serializer logic, transition 
de-emphasis, and receiver detection circuitry
•
RX block including differential CML input buffers, de-serializer logic, on-chip termination, and
continuous-time linear equalization (CTLE)
•
Clock block including clock recovery circuitry and clock management logic
•
Configuration control and status register access
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Figure 2-1 • RTG4 SERDES Block Diagram - SERDES/PMA Module (shown with PCIE, XAUI, and EPCS
Overlays)
Revision 3
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Serializer/De-serializer
Device Support
Table 2-1 lists the total number of SERDES channels available in each RTG4 device.
Table 2-1 • Available SERDES Lanes in RTG4 Devices
RT4G075
16
SERDES Lanes available
RT4G150
24
SERDES Block Overview
The RTG4 devices include up to six integrated high-speed serial interface (SERDES Block) blocks.
Details on SERDES block can be found in "SERDES Block" chapter on page 7. Figure 2-1 on page 21
shows a high level diagram of the fixed SERDES Blocks.
Each SERDES block has a SERDES including four full-duplex differential channels and a fully
implemented physical media attachment (PMA). The PMA includes the TX and RX buffers, SERDES
logic, clocking, and clock recovery circuitry.
Based on application, the datapath includes a peripheral component interface express (PCIe) physical
coding sublayer (PCS), 10 gigabit attachment unit interface (XAUI) extender, or external PCS (EPCS).
Specific to PCIe PCS, the SERDES blocks contain the 8b/10b encoder/decoder, RX detection, and
elastic buffer for the PCI. The PCS layer interface is compliant to the Intel PHY interface for the PCIe
architecture v2.00 specification (PIPE). The PCIe PCS is fully configurable in terms of number of lanes
and number of links. Each link is configurable from x1, x2, or x4 with supporting power management and
wakeup logic.
For XAUI applications, the datapath from the PMA passes through the 8b/10b encoder/decoder, channel
aligner, clock compensation, and XAUI state machine. The XAUI path is terminated to the FPGA fabric
as an XGXS interface. The XAUI extender core also includes an MDIO management interface.
The PCIe PCS functionality can be bypassed completely in order to use the SERDES block for protocols
other than PCIe through an EPCS interface. In addition, the multi-lane instance can be disassociated at
power-up to distinguish between the lanes used for PCIe and the lanes used for other protocols through
the external PCS interface.
The SERDES blocks terminate to the FPGA fabric by the following interfaces.
•
PIPE interface for PCIe protocol (maximum 16 bits), this also includes power management and
wake-up signals.
•
XAUI XGMII with MDIO control interface
•
EPCS interface for implementing any protocol other than PCIe (maximum 20 bits) including
SGMII
•
APB interface for configuration
Each SERDES block can be configured independently at power-up in a specific mode by using the
SERDES block registers. These registers are used to control the multi-function SERDES block
parameters to configure the SERDES in a specific mode. Refer to Chapter 6 – SERDES Block Register
Access Map for details about setting serial protocols. Each SERDES block can interface to several
other modules within the SERDES block.
22
R e visio n 3
RTG4 FPGA High-Speed Serial Interfaces
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Figure 2-2 • SERDES Block Datapath for PCIE Capable Blocks
As shown in Figure 2-2, PCIe, XAUI, and EPCS modes include a specific connectivity through the
SERDES block.
The SERDES block registers allow control of the parameters corresponding to PLL frequency, baud rate,
output voltage, de-emphasis, RX equalization, and parallel data path width for the PCS logic. The initial
setup of these parameters is pre-configured through the Libero SoC software. These registers can be
modified after power-up through the register space interface signals on a per-lane basis or all lanes
together. These registers can be accessed through the APB interface and load the SERDES parameters
after power-up. This run-time capability can be used to simply change specific settings such as the
output voltage amplitude or de-emphasis due to a high bit error rate seen on a specific lane. The Libero
software programs the appropriate registers based on the user design requirements. Any unused
SERDES block resources are configured in a powered down mode via programming from the software.
For unused SERDES, physical I/Os need to be properly terminated based on the recommendations in
RTG4 FPGA Pin Descriptions.
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Serializer/De-serializer
PMA Block
The SERDES PMA block contains high-speed analog front-end logic as well as TX PLL and clock and
data recovery (CDR) PLL, calibration, and the voltage offset cancellation mechanism. Figure 2-3 shows a
simplified functional block diagram of the PMA block. Each of the PMA blocks includes the following
three sub-functions:
•
TX Block
•
RX Block
•
Clock Block
The three blocks have several primary inputs and outputs as well as control and status connections. The
control and status nodes are either ports or registers used in conjunction with the implementation.
Figure 2-3 shows a simple diagram of the functionality fixed within the PMA.
Far End
RX Detect
TX Block
TXDP
Transmitter
TX Amp
Pre-and
Post-Cursor
Settings
TX Data
Serializer
TXDN
TX Clk
TX PLL
REXT
TX Clk
Stable
IMPEDANCE
CALIBRATOR
Clock
Block
Reference
Clock
÷
DIV
CDR PLL
RXDP
Ref Clk
Stable
Receiver
with CTLE
RXDN
RX Clk
÷
Deserializer
Activity
Detect
AD
RX Block
Figure 2-3 • PMA Diagram
24
RX Data
R e visio n 3
Equalization
Control
RTG4 FPGA High-Speed Serial Interfaces
TX Block
The TX macro includes a serializer which receives a 20-bit (maximum) data-word synchronous with a TX
clock, serialized into a single stream of differential transmitted data transmitted to the lane. The TX macro
supports multi-level output drive and multi-level transition (pre-and post-cursor) 3-tap de-emphasis while
maintaining proper impedance. Refer to the "SERDES Block–I/O Signal Interface" listed in Table 2-4 on
page 38 for details. The TX outputs do not support hot-swap.
TX Output Buffer
Figure 2-4 shows the TX block with a high-speed, and differential impedance matching output buffer. It
supports multi-level drive, pre-cursor and post-cursor transition de-emphasis, multi-level common-mode,
and calibrated output impedance. The output driver utilizes the current diversion circuitry to maintain the
programmable amplitude adjustments. These parameters are predefined by the Libero software, but can
be tuned by the designer.
SERDES_#_L[01][23]_VDDAIO
SERDES_PCIE_#_L[01][23]_VDDAIO
Emphasis
Ctrl
Emphasis driver
Pre-cursor
Pre-Driver
Far End Detect
(PCIe)
+
SERDES_#_TXD[3:0]_P
SERDES_PCIE_#_TXD[3:0]_P
Differential
Output Buffer
From Serializer
Pre-Driver
SERDES_#_TXD[3:0]_N
SERDES_PCIE_#_TXD[3:0]_N
Emphasis driver
Post-cursor
Clk
Pre-Driver
Figure 2-4 • TX Output Diagram
The TX output voltage levels, VDIFFp-p and VCM, are nominally set by the Libero software based on key
protocol parameters. The limits of these settings are dependent on the analog SERDES I/O supply. The
output voltage parameters are defined by the following equations:
•
VDIFFp-p = 2*|VD+ – VD-|
•
VCM = 0.5*(VD+ – VD-)
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Serializer/De-serializer
VD+
VDIFF
VCM
VD-
Figure 2-5 • TX Output Signal Parameters
Figure 2-6 • Example TX Output Signal
The main tap of the TX output block is programmable and controlled by the TX_AMP_RATIO setting. The
amplitude can be set as a ratio from 100% (full-swing) to 0%. The ratio is determined as a function of the
initial lane calibration. Thus the device calibrates the link and determines an optimized impedance and
the ratio setting uses this calibration to baseline the needed amplitude. This allows flexibility to match
receiver specifications on the far-end of the link. Valid settings for TX_AMP_RATIO are between 0 and
128, whereas 128 is 100% swing.
Figure 2-7 • TX AMP RATIO Setting as shown in Libero SoC Toolsuite
26
R e visio n 3
RTG4 FPGA High-Speed Serial Interfaces
TX De-Emphasis
The signal quality of a physical channel can be adjusted to match the interconnections and PCB using
the integrated de-emphasis control. The post-cursor and pre-cursor nominally spans 0 dB to 20 dB.
Adjustment to these controls in conjunction with the TX amplitude allows the user to closely match the
interconnect channel.
The pre-cursor and post cursor de-emphasis adjusts the magnitude of the output based on the prior bit
values effectively attenuating the successive bits. This transition emphasis compensates for the channel
losses and opens the signal eye at the far-end receiver. Figure 2-8 shows the de-emphasis settings and
pre-cursor and post-cursor response of the transmit driver.
The pre-cursor and post-cursor attenuation is a function of the TX amplitude ratio setting (see
TX_AMP_RATIO) and the TX pre and post cursor ratio setting (see TX_PRE_RATIO and
TX_PST_RATIO, respectively).
The pre-cursor attenuation (de-emphasis in dB) is calculated using the formula:
dB = 20 * log (1-2*precursor ratio)
where precursor ratio is simply the TX_PRE_RATIO divided by TX_AMP_RATIO.
Similarly, post-cursor attenuation (de-emphasis in dB) is calculated using the formula:
dB = 20 * log (1-2*postcursor ratio)
where postcursor ratio is simply the TX_PST_RATIO divided by TX_AMP_RATIO.
For example, when TX_AMP_RATIO=128 and TX_PST_RATIO=21,
Post Cursor Attenuation= 20*log(1-2*21/128). This yields -3.5dB attenuation.
Post Cursor
De-emphasis
Pre Cursor
De-emphasis
Figure 2-8 • Pre-Cursor and Post-Cursor De-Emphasis
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Serializer/De-serializer
The TX block has many features that can be tuned dynamically when in operation mode. When changing
the TX control registers in real-time, the changes are not updated until the specific UPDATE_SETTINGS
register is written. Refer to Table 6-88 on page 179.
Figure 2-9 • TX DEEMPHASIS RATIO Setting as shown in Libero SoC Toolsuite
RX Block
The RX block receives the serialized data from input receivers. The CDR circuit receives the signal and
extracts a properly timed bit clock from the data stream. The data signal is deserialized down to a lower
speed parallel, 20-bit (maximum) digital data-word (RX data). The deserialized data is synchronous to
the recovered link clock (RX clock).
RX Input Buffer
The RX block includes an analog front-end powered by the SERDES analog power supply. It contains a
current mode, input differential buffer with on-die input impedance control. The input buffer amplifier
receives the incoming differential data signal. It translates the differential signal to internal logic levels,
with no amplitude impairments. The input buffer amplifier rejects common mode noise. The calibrated
input impedance has a typical 100-ohm differential impedance. The input impedance can be configured
as needed to match the system requirements. The RX inputs do not support hot-swap.
Jitter on the incoming data signal transfers through this stage, therefore care must be taken to ensure
both the incoming timing and amplitude are clean from impairments. The integrated linear equalizer
filters extraneous noise from the incoming signals.
SERDES_#_L[01][23]_VDDAIO
SERDES_PCIE_#_L[01][23]_VDDAIO
+
SERDES_#_RXD[3:0]_P
SERDES_PCIE_#_RXD[3:0]_P
Input Impedance
Termination
(On-die)
Differential
Input Buffer
SERDES_#_RXD[3:0]_N
SERDES_PCIE_#_RXD[3:0]_N
Linear Equalization
Figure 2-10 • RX Input Diagram
28
R e visio n 3
RTG4 FPGA High-Speed Serial Interfaces
RX Equalization
The RX block supports a programmable continuous time-linear equalization (CTLE). The equalizer
compensates attenuated interconnections of the system printed circuit board (PCB) by effectively using a
high-pass filter component which attenuates the lower frequency components to a degree greater than
the higher frequency components. The equalizer circuitry can be tuned to compensate for the signal
distortion due to the high frequency attenuation of the physical channel of the PCB and interconnect.
The effective receiver equalization compensates for the channel loss of the board with the added
frequency response of the CTLE. The frequency response can be programmed to maximize the signal
quality of the receiver for achieving the best possible bit-error rate (BER). An under-equalized channel
does not adequately open the eye, whereas over-equalization can produce a channel with high jitter.
Correct equalization has optimal eye opening with low noise and low jitter.
The RX block has many features that can be tuned dynamically when in operation mode. When changing
the TX control registers in real-time, the changes are not updated until the specific UPDATE_SETTINGS
register is written. Refer to Table 6-88 on page 179 for more information.
Figure 2-11 • RX EQ RATIO Setting as shown in Libero SoC Toolsuite
AC Coupling
Each channel must be AC-coupled to remove common mode dependencies. However, AC coupling
generates baseline wander if the high-speed serial data transmission is not DC-balanced. 8B/10B
encoded data is an example of DC-balanced signaling used with PCIe and XAUI protocols. The addition
of external capacitors for AC coupling requires careful consideration. The designer must select a
capacitor knowing the requirements of the system. It is important to minimize the pattern-dependent jitter
associated with the low frequency cutoff of the AC coupling network. When NRZ data containing long
strings of identical 1's or 0's is applied to this high-pass filter, a voltage droop occurs, resulting in 
low-frequency, pattern-dependent jitter (PDJ). Off-chip AC coupling requires recommended capacitor
values such as 10 nF for 8b/10b XAUI and 75-200 nF for PCIe. These example values need to be
reviewed based on specific system requirements. Refer to the AC439: Board Design Guidelines for
RTG4 FPGA Application Note (to be released) for more information.
Clock Block
The Clock block in the PMA contains one transmit PLL (TX PLL) and one CDR PLL. Figure 2-12 shows
the overview of the clock block with some associated signals. The TXPLL and RXCDR use a common
input pin “aRefClk”. The power supply for the TXPLL and CDR PLL is supplied from a dedicated 2.5 V
supply. Figure 2-15 on page 34 shows the required power supply connections for
SERDES_#_L[01][23]_VDDAPLL or SERDES_PCIE_L[01][23]_VDDAPLL. These supplies are specified
and used separately from the SPLL which was mentioned in the PCIE and XAUI sections of this
document.
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Serializer/De-serializer
TXDN
Pre-cursor D/E
Post-cursor D/E
TXDP
aTxD[0]
Serializer
aTxD[19]
2
÷M
aRefClk
LoopBack
Equalizer
RXDP
Equalizer
RXDN
S_CLK
TX
PLL
BIT_CLK
T_CLK
aTxClk
÷N
÷F
÷M
CDR
PLL
÷N
÷F
T_CLK
S_CLK
aLpBkNearEnd
2
aRxClk
aRxDO[19]
DeSerializer
aRxDO[0]
Figure 2-12 • Clock Block Diagram
Note: aRefClk comes from REFCLK or from fabric clock. Fabric clock only available in EPCS modes.
Each of the PLLs (TX PLL and CDR PLL) contains the necessary dividers and output high frequency
(BIT_CLK, S_Clk, and T_Clk) and low frequency (aTXClk and aRXClk) clocks. The TX clock (aTXclk)
and RX clock (aRXClk) are divided down and pipelined versions of the high frequency clocks BIT_CLK
and S_Clk. The TX clock and RX clock are complementary. The exact frequencies of the clocks are
determined by the reference clock (RefClk) and divide ratio settings (M, N, and F). The divide ratio
settings—M, N, and F can be programmed from the APB interface on the SERDES block. Refer to the
RTG4 FPGA Datasheet for the RefClk operating ranges.
30
R e visio n 3
RTG4 FPGA High-Speed Serial Interfaces
The relationships between FREF (from RefClk clock input), FBaudClock, FBusClock, and bus width are
as shown in EQ 1 through EQ 4.
FVCO = (FREF) * M * N * F
EQ 2-1
FBaudClock = FVCO / M = (FREF) * N * F
EQ 2-2
FBusClock = FBaudClock / N = (FREF) * F
EQ 2-3
Bus width = FBaudClock / FBusClock = N
EQ 2-4
Note: FBaudClock in TX PLL is the EPCS_TX_CLK for EPCS mode, FBaudClock in CDR PLL is the
EPCS_RX_CLK for EPCS mode, and bus width is the EPCS bus width.
TX clock does only be present and at the correct frequency if all the following are true:
•
Reference clock is present and at correct frequency
•
M, N, and F are correctly set
•
TX PLL is on
•
TX clock trees are on (internal)
•
Power-down mode is off and initialization is done
The RX clock does only be present and at the correct frequency (with high frequency internal S and T
clocks aligned to the bitstream) if all of the following are true:
•
Reference clock is initially present and at the correct frequency
•
M, N, and F are correctly set
•
RX PLL is on, at correct frequency and Tx clock is present (PMA controlled mode)
•
Serial bitstream is present and valid
•
De-serializer circuitry is on
•
Receivers are on
Note: The Tx clock and Rx clock are not required to be identical in frequency.
Figure 2-13 • M, N, and F Setting as shown in Libero SoC Toolsuite
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Serializer/De-serializer
Reference Clock Inputs
Each SERDES block consists of reference clock input pads. The REFCLK is multiplexed in the clock
Block, It optionally allows the reference clock to be sourced to the TX PLL and/or the CDR PLL These
are dedicated input buffers used for the reference clock input. If unused for SERDES REFCLK, can be
left floating. The REFCLK inputs have a dedicated power supply. VDDI powers the SERDES reference
clock that can be 1.8, 2.5, or 3.3 V. A common SERDES_VDDI supply provides requiring SERDES
reference clocks to use the same voltage supply.
Table 2-2 • Reference Clock Specifications (Typical)
Reference Clock Parameter
Min
Ref Clock Speed
100
Refer to the RTG4 FPGA Datasheet for detailed specifications
Max
160
Unit
MHz
The best performance of the SERDES is based on the selection of a quality clock source. The SERDES
reference clock phase noise contributes to the transmit output phase noise and can decrease receiver
jitter tolerance. Refer to the RTG4 FPGA Datasheet for more specific information.
SERDES Reference Clock Inputs
The PMA in the SERDES block needs a reference clock on each of its lanes for Tx and Rx clock
generation through the PLLs. The reference clock inputs port (REFCLK) is optionally connected to I/O
pads or an additional reference clock source, fab_ref_clk, coming from the fabric.
Each SERDES block includes four lanes, Lane[0:3]. A dedicated reference clock block (REFCLK) is
available for each SERDES block. Two I/O pads are associated with the REFCLK block. The I/O pads
can accept only one differential clock signal. The REFCLK block uses both the I/O pads to supply a
single REFCLK signal to all four lanes of the SERDES block. However, an optional feature is available to
supply two individual single-ended clock signals to the I/O pads. This feature provides two REFCLKs to
the SERDES block and permits clocking of two lanes independently from each other. In this scenario,
Lane 0 and Lane 1 share one of the clock inputs, and Lane 2 and Lane 3 share the other clock input. The
REFCLK is controlled by selection of the input multiplexer to the REFCLK input of the SERDES block, as
shown in Figure 3-12 on page 60. The Libero software correctly sets the input muxes for the REFCLKs
based on the SERDES block configurator settings.
The device includes a multi-standard input reference clock. The reference clock is configured through the
software Configurator to support differential or single-ended signaling standards. Based on the
Reference Clock source selection, the supported I/O standards and other options such as Impedance,
Receiver settings, weak pull-up/pull-down settings are available.
The dedicated clock input pins are recommended to achieve optimal performance. The fabric reference clock is
only available for EPCS modes. Figure 2-14 shows the reference clock selection. The user programmed clock
selection is routed to the SERDES Clock block RefClk input port, as shown in Figure 2-6 on page 26.
32
R e visio n 3
RTG4 FPGA High-Speed Serial Interfaces
The SERDES has four lanes, the two adjacent SERDES lanes share the same reference clock, as
shown in Figure 2-14. In this scheme, lane0 and lane1 share the same reference clock input. Similarly,
lane3 and lane4 share the same reference clock.
5()&/.B,25()&/.B3
5()&/.B,25()&/.B1
5()&/.
5()&/.
(3&6B)$%B5()B&/.
D5HI&ON>@
D5HI&ON>@
/$1(B5()&/.B
6(/>@
5()&/.LVRQO\DYDLODEOHZLWKVLQJOHHQGHGFORFNLQSXW
D5HI&ON>@
D5HI&ON>@
/$1(B5()&/.B6(/>@
Figure 2-14 • SERDES Reference Clock Input Sources
Calibration Resource Sharing
The SERDES PMA block calibration is performed to optimize the SERDES in the system. Calibration is
done for the source impedance at the transmitter and the termination of the receiver. The calibration
circuitry is shared across channels. Each SERDES block contains 2 external reference resistor (REXT)
signals—one for lane0 and lane1, and another for lane2 and lane3. The calibration interaction limits the
combination of protocols/data rates per channel utilization since the adjacent channels are bonded to the
same calibration circuitry. For example, if lane1 and lane0 operate and the PHY is reset on lane0, the
recalibration function which follows the reset disrupts lane1 as a consequence of the shared REXT
calibration resistor.
REXT connections are required to calibrate Tx/Rx termination value and internal elements. A 1.21 k-1%
resistor must be connected on the PCB, as shown in Figure 2-15. This resistor can be a 0201 or 0402
sized component, since the power dissipation through this resistor is less than 1mW during calibration.
Refer to the AC439: Board Design Guidelines for RTG4 FPGA Application Note (to be released) for more
details.
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Serializer/De-serializer
2.5 V
SERDES_(PCIE)_#_VDDAPLL
3.3 Ω
33 uF
0.1 uF
SERDES_(PCIE)_#_L[01][23]_REFRET
1.21 kΩ
SERDES_(PCIE)_#_L[01][23]_REXT
RTG4
Figure 2-15 • Calibration Resistor Connection
Note: Refer to the AC439: Board Design Guidelines for RTG4 FPGA Application Note (to be released)
for correct values on components.
SERDES Testing Operations
This section covers how to configure the SERDES in loopback to test the signal integrity of the SERDES
block. It also details the internal pattern generation and checking capability to assist with system debug.
Following are the sub-sections:
•
Diagnostic Loopbacks
•
Pseudo-Random Bit Sequences Pattern Generator
•
Pseudo-Random Bit Sequences Pattern Checker
•
Custom Pattern Generator
Diagnostic Loopbacks
Serial Loopbacks
Serial loopback modes are specialized configurations of the SERDES datapath where the data is folded
back to the source. Typically, a specific traffic pattern is transmitted and then compared to check for
errors. Loopback test modes fall into two broad categories: Near End and Far End.
SERDES-PMA
PCS - PCIE
Figure 2-16 • Diagnostic Loopbacks
34
R e visio n 3
FPGA Fabric
RTG4 FPGA High-Speed Serial Interfaces
Near End Serial PMA Loopback
The SERDES block provides support for a serial loopback back onto itself for test purposes. When the
LPBK_EN bit (bit1 of the PRBS_CTRL register) is set, the serial data is fed back to the CDR block and
the CDR block extracts the clock and data. Loopback may be operated in full frequency mode (PLLs
active) or bypass mode (PLLs bypassed). This mode is useful when used in conjunction with the on-die
PRBS data generator and checker. In this scenario, the data can be sent and received without going 
off-chip.
PCS
Serializer
PMA
TX
De-emphasis
PRBS
Gen
RX
CDR
Deserializer
CTLE
PRBS
Chk
Figure 2-17 • Near End Serial PMA Loopback
PCS Far End PMA RX to TX Loopback
This loopback mode (also termed meso_lpbk, as shown in Figure 2-18) is where received data is
recaptured by the parallel transmit clock before being sent to the PMA transmitter. The RX is sent back to
the TX and requires no PPM differences between the reference clock used by the transmit and received
data. In this case, data is usually sent to the receiver from test equipment such as a BERT (Bit error-rate
tester) and brought back out of the device TX to the BERT to be checked. Typically the tester provides a
reference clock to the device. This loopback is available for XAUI and EPCS protocols.
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Serializer/De-serializer
PCS
Serializer
PMA
TX
Demphasis
RX
CDR
Deserializer
CTLE
Figure 2-18 • Far End PMA RX to TX Loopback
Note: To activate far end PMA RX to TX loopback program the PCS_LOOPBACK_CTRL[2].
Pseudo-Random Bit Sequences Pattern Generator
Pseudo-random bit sequences (PRBS) are commonly used to test the signal integrity of SERDES. The
SERDES block allows pattern generation using the PRBS_CTRL register. This pattern can be looped
back in the PMA and verified as explained in the "Pseudo-Random Bit Sequences Pattern Checker"
on page 37.
The following bits describe the PRBS pattern generation feature:
•
PRBS_GEN: This signal starts the PRBS pattern transmission.
•
PRBS_TYP[1:0]: This signal defines the type of PRBS pattern which is applied. PRBS7 when set
to 00b, PRBS11 when set to 01b, PRBS23 when set to 10b, and PRBS31 when set to 11b.
Table 2-3 • SERDES Block PRBS Patterns
Name
PRBS-7
Polynomial
1 + X^6 + X^7
PRBS-15
1 + X^14 +
X^15
PRBS-23
1 + X^18 +
X^23
36
Length of
Sequence
Descriptions
27– 1 bits Used to test channels which use 8b/10b encoding. Available for PCIe, XAUI,
and EPCS protocols.
215 – 1 bits ITU-T Recommendation O.150, Section 5.3. PRBS-15 is often used for jitter
measurement because it is the longest pattern the Agilent DCA-J sampling
scope can handle. Available for EPCS protocols.
223 – 1 bits ITU-T Recommendation O.150, Section 5.6. PRBS-23 is often used for 
non-8B/10B encoding scheme. One of the recommended test patterns in
the SONET specification. Available for EPCS protocols.
R e visio n 3
RTG4 FPGA High-Speed Serial Interfaces
Table 2-3 • SERDES Block PRBS Patterns (continued)
Length of
Sequence
Descriptions
231 – 1 bits ITU-T Recommendation O.150, Section 5.8. PRBS-31 is often used for 
non-8b/10b encoding schemes. A recommended PRBS test pattern for 10
GbE. Refer to the IEEE 802.3ae-2002 specification. Available for EPCS
protocols.
Note: ITU-T Recommendation O.150 provides general requirements for instrumentation for performance
measurements on digital transmission equipment.
Name
PRBS-31
Polynomial
1 + X^28 +
X^31
Pseudo-Random Bit Sequences Pattern Checker
The SERDES block includes a built-in PRBS checker to test the signal integrity of the channel. Using the
internal PMA loopback or a complete external path from the transmitter to receiver, this pattern checker
allows SERDES to check the four industry-standard PRBS patterns mentioned in Table 2-3. The
PRBS_CTRL register and PRBS_ERRCNT register allow pattern checking.
•
LPBK_EN: The LPBK_EN signal, bit 1 of the PRBS_CTRL register, puts the PMA block in nearend loopback (serial loopback from TX back to RX). PRBS tests can be done using the nearend loopback of the PMA block or using any far-end loopback implemented in the opposite
component.
•
PRBS_CHK: The PRBS_CHK signal, bit 6 of the PRBS_CTRL register, starts the PRBS pattern
checker. Refer to the PRBS_CTRL register for more information.
•
PRBS_ERRCNT: The PRBS_ERRCNT register reports the number of PRBS errors detected
when the PRBS test is applied. Refer to PRBS_ERRCNT register for more information.
Custom Pattern Generator
The SERDES block allows generation of a user-defined pattern. There is no pattern checking
available for custom patterns, including any of the non-PRBS patterns. The SERDES block allows
pattern generation using PRBS related registers. The following bits describe the custom pattern
generation feature:
•
CUSTOM_PATTERN[7:0]: The custom pattern registers (register offset 0X190to 0X1CC) enable
programming of a custom pattern. Refer to the custom pattern registers (starting with
CUSTOM_PATTERN_7_0) for more information.
•
CUST_SEL (CUSTOM_PATTERN_CTRL[0]): This signal replaces the PRBS data transmitted on
the link by the custom pattern. The PRBS_SEL register must also be set for transmitting the
custom pattern on the link.
•
CUST_TYP (CUSTOM_PATTERN_CTRL[3:1]): This signal defines whether the custom pattern
generated on the link is generated by the custom pattern register or by one of the hard-coded
patterns:
–
00b: Custom pattern register
–
100b: All-zero pattern (0000…00)
–
101b: All-one pattern (1111…11)
–
110b: Alternated pattern (1010…10)
–
111b: Dual alternated pattern (1100…1100)
•
CUST_SKIP (CUSTOM_PATTERN_CTRL[5]): This register is used in RX Word alignment manual
mode.
•
CUST_AUTO (CUSTOM_PATTERN_CTRL[6]): This allows the word alignment to be performed
automatically by a state machine that checks whether the received pattern is word-aligned with
the transmitted pattern and to automatically use the PMA CDR PLL skip bit function to find the
alignment.
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Serializer/De-serializer
•
CUST_ERROR (CUSTOM_PATTERN_CTRL[3:0]): When the custom pattern checker is enabled,
this status register reports the number of errors detected by the logic when the custom word
aligner is in synchronization. It starts counting only after a first matching pattern has been
detected.
•
CUST_SYNC (CUSTOM_PATTERN_CTRL[4]): This bit reports that the custom pattern is 
word- aligned.
•
CUST_STATE (CUSTOM_PATTERN_CTRL[7:5]): This register reports the current state of the
custom pattern word alignment state machine.
Using SmartDebug Utility for SERDES
The SmartDebug utility included with the Libero design software provides SERDES access that assists
FPGA and the board designers to perform SERDES real-time signal integrity testing and tuning in a
system including SERDES control and test capabilities to assist with debugging high-speed serial
designs with no extra steps.
The SmartDebug JTAG interface extends access to configure, control and observe SERDES operations
and is accessible in every SERDES design. Users simply implement their design with the Libero System
Builder to incorporate the SERDES block enabling SERDES access from the SmartDebug tool set. This
quickly enables designers to explore configuration options without going through FPGA recompilation or
making changes to the board. GUI displays real-time system and lane status information. SERDES
configurations are supported with TCL scripting allowing access to the entire register map for real-time
customized tuning.
SmartDebug Hardware Design Debug Tools Tutorial demonstrates the tools capabilities.
SERDES Block–I/O Signal Interface
The RTG4 SERDES block interfaces with differential I/O pads, the PCIe system, and the FPGA. The
following section describes these signals.
Table 2-4 • SERDES Block I/O – PAD Interface
Port Name
SERDES_(PCIE)_#_RXD0_P
Type
Input
SERDES_(PCIE)_#_RXD1_P
Connected
to
Description
I/O Pads Receive data. SERDES differential positive input: 
Each SERDES block consists of 4 RX+ signals.
SERDES_(PCIE)_#_RXD2_P
SERDES_(PCIE)_#_RXD3_P
SERDES_(PCIE)_#_RXD0_N
Input
I/O Pads
Receive data. SERDES differential negative input:
Each SERDES block consists of 4 RX- signals.
SERDES_(PCIE)_#_RXD1_N
SERDES_(PCIE)_#_RXD2_N
SERDES_(PCIE)_#_RXD3_N
SERDES_(PCIE)_#_TXD0_P
Output
I/O Pads
SERDES_(PCIE)_#_TXD1_P
SERDES_(PCIE)_#_TXD2_P
SERDES_(PCIE)_#_TXD3_P
38
Transmit data. SERDES differential positive output:
Each SERDES block consists of 4 TX+ signals.
R e visio n 3
RTG4 FPGA High-Speed Serial Interfaces
Table 2-4 • SERDES Block I/O – PAD Interface (continued)
Port Name
SERDES_(PCIE)_#_TXD0_N
Type
Output
Connected
to
Description
I/O Pads Transmit data. SERDES differential negative output:
Each SERDES block consists of 4 TX- Signals.
SERDES_(PCIE)_#_TXD1_N
SERDES_(PCIE)_#_TXD2_N
SERDES_(PCIE)_#_TXD3_N
SERDES_(PCIE)_#_L01_REXT
Reference
I/O Pads
External reference resistor connection to calibrate
TX/RX termination value. Each SERDES block
consists of 2 REXT signals—one for lanes 0 and 1
and another for lane2 and lane3.
Input
I/O Pads
This pin is used as the positive terminal when used
with a differential clock source. It is limited to driving
only one clock source to the SERDES block when
used differential (REFCLK0).
Input
I/O Pads
SERDES_(PCIE)_#_L23_REXT
SERDES_(PCIE)_#_REFCLK_P
SERDES_(PCIE)_#_REFCLK_IO0
SERDES_(PCIE)_#_REFCLK_N
This pin is used as the negative terminal when used
with a differential clock source. It is limited to driving
only one clock source to the SERDES block when
used differential(REFCLK0). When used with a single
ended clock source, this input pin supplies a
reference clock signal to the REFCLK1 input of the
SERDES block.
Note: Here, x = the SERDES Block_# where # is from 0 through 5 based on device size. The notation
SERDES_(PCIE) indicates the capability of a SERDES block to include PCIE functionality. SERDES without
PCIE capability is noted without PCIE in the pin name. That is, SERDES_3.
SERDES_(PCIE)_#_REFCLK_IO1
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Serializer/De-serializer
Glossary
Acronym
CDR
Clock data recovery
PCS
Physical coding sublayer
PHY
Physical interface
PIPE
PHY interface for the PCI Express architecture v2.0 specification
PMA
Physical media attachment
PRBS
Pseudo-random bit sequence
SERDES Block
Serializer/de-serializer interface block
40
R e visio n 3
3 – PCI Express
Introduction
This chapter describes using peripheral component interconnect express (PCIe) in the RTG4 FPGA
devices. PCIe is a high-speed serial computer expansion bus standard designed to replace the older
PCI, PCI-X, and AGP bus standards. The RTG4 high-speed serial interface (SERDES Block) allows fully
integrated PCIe endpoint (EP) implementation. This chapter provides detailed information on
implementing, verifying, and debugging the PCIe EP design in the RTG4 devices.
SERDES
I/O
PMA
LANE0
SERDES
I/O
PMA
LANE1
LANE[0:1] Calibration
Up to 24 Lanes Multi Protocol 3.125G SERDES
PMA
PMA
PCI Express
x1,x2, x4
2 Per Device
PMA
Standard Cell /
SEL Immune
Flash Based /
SEL Immune
PMA
Native SERDES
EPCS
XAUI
XGXS
PCIe PCS
LANE0
PMA
Control
Logic
PCIe PCS
LANE1
PMA
Control
Logic
AXI/AHB, XGMII, Direct 20 Bit Bus
System
Controller
POR
Generator
Math Blocks
(18x18)
JTAG
RT PLLs
Micro SRAM
(64x18)
462
Math Blocks
(18x18)
210
Micro SRAM
(64x18)
Large SRAM
(1024x18)
uPROM
SERDES
I/O
PMA
LANE2
SERDES
I/O
PMA
LANE3
XAUI
Extender
PCIe PCS
LANE2
PMA
Control
Logic
LANE[2:3] Calibration
209
Large SRAM
(1024x18)
PIPE
Controller
APB Bus
Up to 16 SpaceWire Clock
& Data Recovery Circuits
FPGA Fabric
Up to 150K Logic Elements
EPCS
LANE
0:1
Lane
0:1
AXI/AHB
667 Mb/s DDR
Controller/PHY
AXI/AHB
667 Mb/s DDR
Controller/PHY
PMA
Control
Logic
PCIe PCS
LANE3
Lane
2:3
EPCS
LANE
2:3
RC OSC
Multi-Standard GPIO
FPGA Fabric Interface
(1.2 – 3.3 V, LVTTL, LVCMOS, LVDS, HSTL/SSTL, PCI)
APB Slave
Auxilliary
Register Space Power
Interface
Wake-Up
Logic
AXI/AHB
Master/
Slave
User PCIe
System
Figure 3-1 • RTG4 SERDES Block Diagram
Features
The RTG4 family supports up to six integrated SERDES blocks in one device, and each block supports
up to 4 serialization/deserialization (SERDES) lanes, thus supporting up to 24 SERDES lanes.
Figure 3-1 shows the RTG4 device block diagram with PCIe implementation. Each PCIESS block
contains an integrated PCIe system block, also known as a PCIe system, which implements the PCIe
transaction layer and data link layer. The PCIESS block also has a SERDES PMA block that implements
the physical layer. The RTG4 family includes two PCIESS blocks per device, as shown in Figure 3-1. The
PCIe system block along with the SERDES PMA block provide the complete PCIe EP solution in RTG4.
The RTG4 PCIe implementation is compliant with PCIe Base Specification Revision 2.0 and 1.1.
Following are the main features of PCIe EP implemented in RTG4:
•
x1, x2, or x4 lane support
•
Implements native endpoint
•
Compliant with PCIe Base Specification Revision 2.1 and 1.1 for 2.5 Gbps operation
•
Single-function/Single virtual channel (VC)
•
Receives, transmits, and retries buffer
•
AXI3/AHB master and slave interface to the RTG4 FPGA fabric
•
Supports design time selection of the PCIe lane reversal for flexibility of lane assignments for
board layout.
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PCI Express
Note: A PCIe Endpoint refers to the location of the connection in the PCIe topology. A PCIe Endpoint can
connect to Switches Downstream Port or a Root Complex Downstream Port. As an Endpoint the
PCIe can initiate and respond to transactions in the system.
Device Support
The RTG4 family has a number of devices available. Table 3-1 shows the total number of PCIE Endpoint
blocks available in each RTG4 device that can be configured to support PCIe.
Table 3-1 • PCIE Endpoint Blocks Available in RTG4
PCIE EP available
RT4G075
RT4G150
2
2
Note:
1. The specified number of PCIE EP blocks varies depending on the device package. PCIE EP can implement x1,
x2, or x4 links.
2. Each RTG4 device has a minimum of 2 PCIE Endpoint blocks allowing 2 PCIE variations within an RTG4 device.
Overview of PCIe in RTG4
The PCIe protocol is software backward-compatible with the earlier PCI and PCI-X protocols, but is
significantly different from its predecessors. The performance is scalable based on the number of lanes
and the generation that is implemented. The PCIe protocol specifies 2.5 giga-transfers per second for
Gen1. There is a 20% overhead because the PCIe protocol uses 8b/10b encoding. Table 3-2 shows the
aggregate bandwidth of a PCIe link.
Table 3-2 • Theoretical PCIe Throughput
Link Width
PCI Express 2.5 Gbps (1.x/2.x compliant)
x1
x2
x4
2 Gbps
4 Gbps
8 Gbps
Description
RTG4 supports implementing PCIe endpoints (EPs). The EP in PCIe refers to a type of function that can
be the requester or the completer of a PCIe transaction. The PCIe system and SERDES high-speed
serial interface (SERDES Block) blocks implement the PCIe EP specification for transaction, data link,
and physical layers.
Figure 3-2 shows a simplified view of a PCIe EP implementation in an RTG4 device. The PCIe system
interfaces to the FPGA fabric on one side and the PCS/PMA SERDES block on the other side. The
SERDES block interfaces to the dedicated I/O in the RTG4 device is called a SERDES I/O. Refer to the
"SERDES Block–I/O Signal Interface" listed in Table 2-4 on page 38 for more information. The PCIe
system interface to the FPGA fabric consists of an application interface and a configuration interface. In
addition, it has several signals for clocking, reset, and power management.
•
42
Application Interface: The application interface is used to transfer transaction layer packets
(TLP). It can be AXI3/AHB master only AXI3/AHB slave only, or AXI3/AHB master plus slave
interface.
–
AXI3/AHB Master Interface: The master interface can be a 64-bit AXI3 master or a 32-bit
AHB master. A typical application interface uses a master interface which is used to respond
to data read requests and a slave interface which is used to initiate requests. It is also
possible to use a master and/or the slave interface by itself for specific applications.
–
AXI3/AHB Slave Interface: The slave interface can be a 64-bit AXI3 slave or a 32-bit AHB
slave interface. The RTG4 fabric initiates PCIe transactions using the slave interface (that is,
Memory Write TLP and Memory Read TLP). The data on a read request comes back to this
same interface.
R e visio n 3
RTG4 FPGA High-Speed Serial Interfaces
•
Configuration Interface: The configuration interface uses the APB slave interface.
–
•
6(5'(6
,2
APB Interface: The APB interface has access to various registers, including PCIe
configuration registers, AXI3/AHB bridge register, SERDES block register and so on. The
APB provides access to the memory map of the SERDES block which includes a section for
the PCIe controller.
Other Signals: The PCIe system also has several clocking signals, reset signals, phase-locked
loop (PLL) signals, interrupts, and power management signals to the FPGA fabric.
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Figure 3-2 • SERDES Block Configuration for PCIe Single Protocol Mode
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PCI Express
PCIe EP Application Example
Figure 3-3 shows a relatively simple application with a switch port connected to a PCIe EP implemented
in an RTG4 device.
PCIe/SERDES Configuration Data
FIC_2
Fabric
User Logic
AXI/AHB Master
and Slave Interface
SERDES Block in PCIe Mode
RTG4
APB Slave Interface
PCI Express Connector
PCIe Link
SWITCH
Figure 3-3 • RTG4 PCIe EP Implementation
44
R e visio n 3
RTG4 FPGA High-Speed Serial Interfaces
Getting Started
This section provides an overview of configuring the SERDES block in PCIe mode, simulating the
SERDES block in PCIe mode, and implementing a PCIe EP in an RTG4 device.
Using SERDES Block in PCIe Mode
The SERDES block Configurator in Libero SoC provides the configuration options for the PCIe EP
implementation. It includes options for selecting the protocol for various SERDES lanes, serial rate
settings, fabric interface, PCIe Identification registers, PCIe base address register (BAR). These setting
are implemented during programming using dedicated flash bits for fast configuration or via the APB
interface. These registers can be reviewed by using the APB interface, which can access all the registers
in the SERDES block.
The following sub-sections show how to instantiate PCIe in a design:
•
Configuring High Speed Serial Interface Configurator for PCIe
•
Simulating SERDES Block in PCIe Mode
•
Adding RTG4 PCIe Block to User Design
Configuring High Speed Serial Interface Configurator for PCIe
This section describes configuring and generating the SERDES block for PCIe EP mode using the Libero
SoC software.
The High Speed Serial Interface Configurator (SERDES Block Configurator) in Libero allows
configuration of the SERDES block in PCIe mode. Following is a brief description of the various protocol
configuration options. Refer to the "SERDES Block" chapter on page 7 for details.
Protocol Selection
These settings are used for protocol selection.
•
Protocol Type 1: Protocol settings. Select PCIe from the drop-down menu.
•
Number of Lanes: Select number of lanes used.
•
Protocol 1 PHY Reference Clock: Select the inputs for the PHY reference clock selection.
Refer to the "SERDES Reference Clocks Selection" section on page 60 for details on PHY
reference clock selection.
In addition to the protocol settings, various other options for PCIe implementation can be set.
PCIe SPLL Configuration
These settings are used for SPLL that synchronizes data between the AXI3/AHB interface to the
SERDES block.
•
CLK_BASE: This is an AXI3/AHB clock setting.
•
The SPLL is a PLL embedded in the SERDES block to manage the clock phase used for
transfers across the SERDES block to FPGA fabric interface.
PCIe Fabric Interface (AXI3/AHB-Lite)
CLK_BASE frequency must be set to the same frequency of the APB interface as the operating
frequency. These settings select the PCIe system interfaces to the fabric. It can be AXI3 or AHB-Lite bus
as master only, slave only, or both master and slave.
PCIe Base Address Registers
These settings are used to set six 32-bit or three 64-bit base address registers.
•
Width: Width can be 32-bit or 64-bit. If an even register is selected to be 64-bits wide, the
subsequent (odd) register serves as the upper half of 64 bits. Otherwise, the width of odd
registers is restricted to 32 bits.
•
Size: Ranges from 4 Kbytes to 2 Gbytes, in 4Kbyte increments.
•
Prefetchable: Prefetchable option for memory BAR.
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PCIe Identification Registers
These settings are used to set the six identification registers for PCIe.
•
Vendor ID: 0x11AA is the Vendor ID assigned to Microsemi by PCI-SIG. Contact Microsemi at
www.pcisig.com to allocate subsystems under the Microsemi vendor ID. This default assignment
can be optionally changed by the end-user.
•
Subsystem vendor ID: Card manufacturer’s ID
•
Device ID: Manufacturer’s assigned part number by the vendor
•
Revision ID: Revision number, if available
•
Subsystem Device ID: Assigned by the subsystem vendor
•
Class Code: PCIe device's generic function
PCIe Other Options
These settings are used to set other PCIe options:
•
L2_P2 Entry/Exit: Selecting this option adds PCIE_WAKE_N, PCIE_WAKE_REQ, and
PCIE_PERST_N ports to control the L2/P2 state.
•
PHY Reference Clock Slot: Select this option if the PHY reference clock is sourced from a PCIe
slot or it is generated separately.
Note: Slot refers to a clock source that is shared in the PCIe system between both ends of the link. The
other setting, Independent, is used in a system which uses independent clock sources on either
side of the link. This setting changes the PCIe configuration space register to advertise to the
system root which clocking topology is used. It makes no other functional changes to the endpoint.
•
PCIe Specification Version: Specifies the version
Entry of L2P2 can only be requested by the host and when it is requested, the RTG4 PCIE core responds
to the protocol request and transitions to L2 state. Its response is in conjunction with the
CFGR_L2_P2_ENABLE bit of the CONFIG_PCIE_PM register. If the bit is configured as
CFGR_L2_P2_ENABLE=0 or =1, the device goes into L2, and it needs a fundamental reset
(PCIE_PERST_N) to get out of L2.
If CFGR_L2_P2_ENABLE=1, the device shows much lower power when it enters L2. In either case the
host needs to perform enumeration.
PCIE_WAKE_REQ is an input into the RTG4 PCIE reset controller. When PCIE_WAKE_REQ is
asserted, the PCIe reset controller drives out the PCIE_WAKE to RC as WAKE# side band signal.
Simulating SERDES Block in PCIe Mode
Refer to the SERDESIF BFM Simulation Guide for more information on simulation detail.
Adding RTG4 PCIe Block to User Design
Libero promotes the SERDES I/Os to the top level and exposes the AXI3/AHB (based on user settings)
and APB interface to the FPGA fabric. In addition, the SERDES block exposes the clocks, resets, PLL
locks, and power management signals for PCIe implementation.The appropriate setup is done using the
SERDES block configurator in the Libero software tools.
The user logic block implements an AXI3 slave interface to transfer data to the PCIe link and transaction
requests come through the AXI3 master interface to receive the data from the PCIe link. A Fabric clock
conditioning circuit (SPLL) generates the clock for the AXI3 interface on the port CLK_BASE.
PCIe System Architecture
PCIe is a high-speed, packet based, point-to-point, low pin count, serial interconnect bus. RTG4 has a
fully integrated PCIe End Point (EP) implementation. This section describes the architecture of the PCIe
system that implements the main PCIe IP function.
Physical Coding Sublayer Block
The PCS block implements 8b/10b encoder/decoder, RX detection, and an elastic buffer for the PCIe
protocol. It has transmitter and receiver blocks, as shown in Figure 3-6 on page 49.
46
R e visio n 3
RTG4 FPGA High-Speed Serial Interfaces
Transmitter Block
The Transmitter block consists of an 8b/10b encoder and a phase matching first-in-first-out (FIFO), as
shown in Figure 3-4. The transmitter block passes the input data in the PCLK domain (PIPE clock
domain) to the PMA block in the TX clock domain.
PIPE
Interface
CLK MUX
TXCLK
TXClk
RefClk
CLK
Divider
PIPE_PCLKOUT
To
PCIe
System
Single
Lane PMA
Hard
Macro
TXDP/N Pins
TX Data
MUX
Phase
Matching
FIFO
TX Clock Domain
PIPE_PCLKIN (PCLK)
8b/10b
Txdata0
PCLK Clock Domain
Figure 3-4 • Transmit Clock and Transmit Datapath (x1 PCIe Link)
The reference clock (RefClk) is the per-lane PCIe reference clock, which is generally the PCIe 100 MHz
reference clock. During multiple lane implementations, the clock is sent to each PMA single lane block
and skew between lanes is finely controlled. Effectively, each PMA block generates a transmit clock TX
clock, from which is generated the pipe clock (generated by one lane) used by the PCIe controller and
also used by the PCS logic in all lanes.
•
CLK MUX Block: is a glitchless clock multiplexer for sourcing the RefClk or TXClk to the TX
Clock Domain of the PCS sublayer. This mux is used for operation at power-up and during speed
changes.
•
CLK Divider Module: is used to generate the PIPE clock (PCLK) for the PCIe controller. The
PIPE_PCLKOUT signal is the output signal of the PCS and is generated on a per-lane basis.
•
Phase Matching FIFO: is used to recapture the transmitted data generated on the PCLK clock
domain back to the aTXClk domain, considering the two clocks are fully independent
(asynchronous). The TX data MUX performs multiplexing between data coming from the PCIe
PCS and the external PCS.
•
8b/10b Encoder: is used to implement an 8-bit to 10-bit encoder that encodes 8-bit data or
control characters in to 10-bit symbols.
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Receiver Block
The Receiver block consists of receive capture logic, word alignment logic, elastic buffer, and an 8b/10b
decoder, as shown in Figure 3-5.
aRxClkp
CLK
Down
Single
Lane PMA
Hard
Macro
RXDP
To
PCIe
System
RXCLK
CLK
Divider
Elastic
Buffer
aRXDo[19:0]
RXDN
Capture
Register
Word
Aligner
CDR Clock Domain
8b/10b
PCLK Clock Domain
Figure 3-5 • Receive Clock and Receive Datapath (x1 PCIe Link)
•
CLK Down block shuts down the receive clock when it is not stable and glitch-free.
•
CLK Divider function on the RX path is very similar to the one on the transmit side.
•
Capture Register is clocked directly by RXCLK (output of clock divider) rising edge which is a
"divide by" and delayed version of the RX clock from the PMA block.
•
Elastic Buffers (also known as elasticity buffers, synchronization buffers, and elastic stores) are
used to ensure data integrity when bridging two different clock domains using the PCIe SKP
symbol for rate monitoring.
•
Each receiver lane incorporates a decoder, which is fed from the elastic buffer.
•
8b/10b decoder uses two lookup tables (LUT) (the D and K tables) to decode the 10-bit symbol
stream into 8-bit Data (D) or Control (K) characters plus the D/K# signal.
PCIe System
The PCIe system sub-block inside the SERDES block implements the PCIe physical layer, data link
layer, and transaction layer of the PCIe specification. It interfaces with the SERDES block on one side
and the FPGA fabric on the other side. Figure 3-6 on page 49 shows the RTG4 SERDES block in PCIE
mode, and also shows various sub-blocks for the PCIe system block. The main sub-blocks for PCIe
system include:
48
•
PCIe IP Block with AXI3 Interface
•
AXI to AXI3/AHBL Bridge
•
Glue Logic Blocks
R e visio n 3
RTG4 FPGA High-Speed Serial Interfaces
SERDES Block
Fabric
PCIe System
CORE_RESET_N
PHY
Ref. CLK
MUX
RESET
CONTROLLER
PHY_RESET_N
PCIe Bridge
Registers
AXI3 - Master
Interface
PCIe IP with
AXI Interface
AXI3 - Slave
Interface
SERDES
(PMA + PCS)
x4 PIPE Interface
16-bit
Pad Signals
phy_clk
AXI3/AHBL Bridge
AHBL/AXI3 Bridge
AXI3 - Slave
AHBL - Slave
Interface
AXI3 - Master
AHBL - Master
Interface
L2/P2 Control Logic
Lane-to-Lane
Calibration Logic
SERDES Block
System Registers
APB Interface
APB
Decoder
APB Interface
Figure 3-6 • Detailed PCIe System Block Diagram
PCIe IP Block with AXI3 Interface
The PCIe IP block is a fixed integrated block in the RTG4 FPGA, which implements a x1, x2, or x4 PCIe
interface. On the application side, it has one master interface and one slave interface. The master
interface can be a 64-bit AXI3 master or a 32-bit AHBL master. The slave interface can be a 64-bit AXI3
slave or a 32-bit AHBL slave interface. The PCIe link initiates transactions to the RTG4 fabric through the
AXI3 master or AHBL master. RTG4 fabric initiates transactions towards the PCIe link through the AXI3
slave or the AHBL slave interface. There is an APB interface that has access to the SERDES block
system registers.
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PCI Express
Figure 3-7 shows the architecture of the PCIe IP block.
PCIe to AXI Window0
PCIe to AXI Window1
AXI Master
AXI
PCIe to AXI Window3
PCIe to AXI Window3
Controls
PCIe Base
IP core
SERDES
x4 Link
IRQ
AXI to PCIe Window0
AXI to PCIe Window1
AXI to PCIe Window2
AXI Slave
AXI
AXI to PCIe Window3
PCIe Core Bridge
Registers
APB Slave
APB
Figure 3-7 • PCIe IP Block Diagram
The main components for the PCIe IP sub-block include:
•
PCIe Base IP Core
•
PCIe to AXI Window
•
AXI Master Block
•
AXI to PCIe Window
•
AXI Slave Block
•
PCIe Core Bridge Register
•
APB Slave Interface
PCIe Base IP Core
The PCIe base IP core implements an x4 PCIe EP link, compliant to PCIe/Gen1 Rev. 2.0. The following
sections describe the features of the RTG4 PCIe IP.
General
•
x1, x2, x4 PCIe core
•
Supports link rate of 2.5 Gbps per lane
•
Endpoint Topology
•
PCIe Base Specification Revision 2.0 and Revision 1.1 compliant
•
Single-function/Single virtual channel (VC)
•
AXI3 64-bit or AHB-Lite 32-bit Master and Slave Interfaces
•
Advanced error reporting (AER) support
•
End-to-end cyclic redundancy check (ECRC) generation, check, and forward support
Data Transfer
50
•
Supports all base memory, configuration, and message transactions
•
Implements type 0 configuration space for EP (Refer to "PCIe Configuration Space" on page 96)
R e visio n 3
RTG4 FPGA High-Speed Serial Interfaces
Configuration
•
Supports three 64-bit BARs or six 32-bit BARs
Power Management and Interrupts
•
Native active state power management L0s, L1, and L2 state support
•
Power management event (PME message)
The PCIe base IP core implements the transaction layer and data link layer described by the PCIe base
specifications.
•
Transaction layer: The transaction layer (TL) contains the configuration space, which manages
communication with the user application layer such as the receive and transmit channels, the
receive buffer, and flow control (FC) credits.
•
Data link layer: The data link layer (DLL) is responsible for link management, including transaction
layer packet (TLP) acknowledgment, a retry mechanism in case of a non-acknowledged packet,
flow control across the link (transmission and reception), power management, CRC generation
and CRC checking, error reporting, and logging.
Toward SERDES
RX
Clock Domain Crossing
TX
Toward Application Layer
The Data Link Layer
ensures packet
integrity, and adds
a sequence number
and Link Cyclic
Redundancy Check
(LCRC) to the
packet.
The Transaction Layer
generates a TLP
from information
sent by the
Application Layer.
This TLP includes
a header and can
also include a
data payload.
The Data Link Layer
verifies the packet’s
sequence number
and checks for errors.
The Transaction Layer
disassembles the
transaction and
transfers data to
the Application Layer
in a form that it
recognizes.
Data Link Layer
Transaction Layer
Figure 3-8 • PCIe Transaction Layer and Data Link Layer
The PCIe IP core also utilizes a clock domain crossing (CDC) synchronizer between the data link layer
(DLL) and the physical layer that enables the data link and transaction layers to operate at a frequency
independent from that of the physical layer.
PCIe to AXI Window
The PCIe base IP receives both 32-bit address and 64-bit address PCIe requests, but only 32-bit
address bits are provided to the AXI3 master. The PCIe to AXI3 address windows manage read and write
requests from the PCIe link and are used to translate a PCIe 32-bit or 64-bit base address to a 32-bit
AXI3 base address transaction.
AXI Master Block
The AXI3 master only supports memory read and write transactions.
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AXI Master Write Transaction Handling
•
The write transaction is handled in big-endian order, as required by the "PCI Express" section on
page 41.
•
PCIe transactions can be any size up to the configurable maximum payload size (256 bytes)
•
AXI3 transactions are limited to 128 bytes, a received TLP is divided in to several AXI3
transactions.
•
AXI3 master receives a write transaction, it processes the transaction as 128-byte segments
(aligned on a 128-byte address boundary) until the segments in the transaction have been
processed.
•
TLP is de-constructed and sent to the AXI3/AHB interface, and the data is presented as little
endian.
AXI Master Read Transaction Handling
•
Read transactions are handled the same way as write transactions, except that before
transferring the transaction to the AXI3 master read channel, the PCIe IP checks the transmit
buffer for available space.
•
PCIe IP does not transfer the read transaction if there is not sufficient space in the transmit replay
buffer to store PCIe completions.
•
The number of outstanding AXI3 master read transactions is therefore limited by the size of the
Tx buffer.
•
The AXI3 master read channel can receive transactions in any order, and data can be completely
interleaved. However, the PCIe IP generates completions in the order they are initiated on the
link.
AXI to PCIe Window
The AXI3 to PCIe address windows are used to translate a 32-bit AXI3 base address for a transaction to
a PCIe 32-bit or 64-bit base address to generate a PCIe TLP.
AXI Slave Block
The AXI3 slave interface forwards AXI3 read and write requests from the FPGA fabric to the PCIe link.
AXI Slave Write Transaction Handling
•
Minimum 128 Bytes must be available for write transaction.
•
Data interleaving is not supported.
•
Wait states are used if buffer is full or has less then 128 Bytes of space available.
•
Write responses are generated as soon as the last data phase is over.
•
Maximum of 128 Bytes data packet can be created.
•
Only four outstanding write transactions are supported.
•
Incrementing-address burst is supported.
AXI Slave Read Transaction Handling
52
•
Minimum 128 Bytes must be available for read transaction.
•
PCIe IP generates a PCIe tag, arbitrates between write requests and completions, then checks
for available FC credits.
•
Response is generated if a timeout occurs or if a completion with error status is received.
R e visio n 3
RTG4 FPGA High-Speed Serial Interfaces
Outstanding Requests
The AXI3 interface supports the following number of outstanding requests as listed in Table 3-3.
Table 3-3 • AXI3 and Outstanding Transactions
AXI3 Transaction
Outstanding Transactions
Master Write
Limited by Tx Credits
Master Read
4
Slave Write
Limited by Rx Credits
Slave Read
4
AXI3 Transaction and TLP Ordering Rules
This section describes the TLP ordering rules for sending and receiving TLPs.
AXI3 Slave Interface
The slave path does not reorder transactions, but does arbitrate between transactions when they occur
simultaneously. The order of priority for arbitrations is master read completions, slave write requests,
then slave read requests.
AXI3 Master Interface
The master path does not reorder transactions, but does arbitrate between transactions at the AXI3
master interface. If a transaction is currently waiting for a response phase, the transaction is allowed to
complete before the read transaction that is forwarded to the AXI3 master interface.
PCIe Core Bridge Register
The PCIe core bridge registers occupy 4 KB of the configuration memory map space. These registers set
the PCIe configuration and status. These registers are initialized from flash while configuring the highspeed serial interface generator in the Libero SoC. These registers can also be accessed through the 32bit APB interface. The physical offset location of the PCIe core registers is 0x0000-0x0FFF from the
SERDES block system memory map.
APB Slave Interface
The APB slave interface provide APB interface to SERDES block System Registers. Refer to the "Bridge
Register Space" section on page 70 for details.
AXI to AXI3/AHBL Bridge
The PCIe user interface can support either an AXI3 master/ a slave interface or an AHBL master/ a slave
interface. Table 3-4 and Table 3-5 list the fabric interface pins. The AXI3 interface uses a 64-bit data bus
while the AHBL uses a 32-bit data bus. In the PCIe core, the native interface to the controller is AXI3. If
the user selects the AHBL interface, a bridge is available between the PCIe controller and the user
interface. The bridge is completely transparent to the user and the following sections explain some of the
special conditions:
AHBL Master Interface
The AHBL master interface is used for processing TLPs coming into the PCIe controller towards the
FPGA fabric. Memory Read TLPs received by the PCIe controller are constructed as AHBL read
transactions. Memory Write TLPs received are constructed as AHBL write transactions. The AHBL
master supports both SINGLE and burst type transactions. For burst transactions, the AHBL uses either
the INCR or WRAP burst type. Following are the three special conditions for SINGLE transactions:
•
If an 8-bit, 16-bit, 32-bit, or 64-bit read transaction is received on the PCIe link, the AHBL master
initiates two 32-bit read transactions using an increasing 32-bit address. It is done as the internal
AXI3 bus is 64-bits and a read on this interface is always 64-bit wide requiring the AHBL to issue
two AHBL transactions to satisfy the AXI3 transaction.
•
If a 64-bit PCIe read or write transaction is received on the PCIe link, the transaction is broken up
in to two AHBL master transactions.
•
If a 64-bit or 32-bit write transfer is received on the PCIe link with some of the byte lanes are not
enabled, the AHBL master breaks the transaction up in to byte and/or halfword transactions with
the proper address offsets to only write data for those bytes that are enabled.
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PCI Express
AHBL Slave Interface
The AHBL slave interface is used for sending transactions via TLPs over the PCIe link. The AHBL write
transactions create Memory Write TLPs. The AHBL read transactions create Memory Read TLPs. A
Completion TLP from the PCIe link has the read data for an AHBL read transaction. The AHBL interface
is limited to one outstanding transaction. It requires the AHBL transaction to stall until the Completion
TLP is received to terminate the transaction with the read data.
The AHBL slave interface supports all BURST types. The notable special case for the burst type of INCR
(001) is that the burst is broken up in to single DW PCIe TLPs on the PCIe link.
The PCIe Core supports a 64-bit AXI3 native bus. If the user interface requires a 32-bit AHBL interface, a
bridge is provided to translate it from AHBL to AXI3 transactions.
Figure 3-9 shows the block diagram of the AXI3-AHB top bridge.
AXI-AHB
AXI-AXI
AXI3 - Master
AHBL - Master
Interface
PCIe
AXI3
Master
Interface
AXI3 - Slave
Interface
AXI-AHB-TOP
AXI3 - Slave
AHBL - Slave
Interface Fabric
Figure 3-9 • AXI3-to-AXI3/AHBL Bridge Block Diagram
Figure 3-10 shows the block diagram of the AHBL/AXI3 to AXI3 bridge.
AXI-AHB
AXI-AXI
AXI3 - Slave
AHBL - Slave
Interface
PCIe
AXI3 Slave
Interface
AXI3 - Master
Interface
AXI-AHB-TOP
AXI3 - Master
AHBL - Master
Interface FABRIC
Figure 3-10 • AHBL/AXI3 to AXI3 Bridge Block Diagram
Glue Logic Blocks
The PCIe system block has several small logic blocks for PCIe subsystem functionality.
•
PCIe/PHY reset controller: This block controls the assertion and deassertion of reset to the PCIe
core, SERDES block, and other glue-logic.
•
L2/P2 control logic: This block controls logic to implement the L2/P2 state.
Fabric Interface for PCIe System
The RTG4 PCIe system block interfaces with the FPGA fabric on one side and the SERDES block on the
other side. Following are the PCIe system block interface signals to the FPGA fabric:
54
•
PCIe System AXI3/AHBL Master Interface
•
PCIe System AXI3/AHBL Slave Interface
•
PCIe System APB Slave Interface
•
PCIe System Clock Signals
•
PCIe System Reset Signals
•
PCIe Interrupt and Power Management Interface
R e visio n 3
RTG4 FPGA High-Speed Serial Interfaces
Table 3-4 • PCIe System AXI3/AHBL Master Interface
Port
AHB_M_HADDR[31:0]
Type
Output
32-bit Transaction Address
AHB_M_HTRANS[1:0]
Output
Transfer type indicator
AHB_M_HWRITE
Output
Indicates transfer direction
AHB_M_HSIZE[1:0]
Output
Size of the transaction
AHB_M_HBURST[2:0]
Output
Description
•
00 - Byte (8-bit)
•
01 - Halfword (16-bit)
•
10 - Word (32-bit)
• 11 - Not supported (Doubleword)
Burst type indicator
•
000 - SINGLE
•
001 - INCR
•
010 - WRAP4
•
011 - INCR4
•
100 - Not Supported (WRAP8)1
•
101 - Not Supported (INCR8)1
•
110 - Not Supported (WRAP16)2
• 111 - Not Supported (INCR16)2
32-bit Write Data
AHB_M_HWDATA[31:0]
Output
AHB_M_HRDATA[31:0]
Input
32-bit Read Data
AHB_M_HREADY
Input
Transaction finished indicator
AHB_M_HRESP
Input
Transfer response. In response to a read request, an ERROR response
causes the PCIe controller to issue an Unsupported Request back to the
initiator.
Note:
• The Libero component for the AHBL interface only supports HBURST[1:0].
• The PCIe AHBL interface does not support the WRAP16 and INCR16 burst types.
Table 3-5 • PCIe System AXI3/AHBL Slave Interface
Port
AHB_S_HADDR[31:0]
Type
Input
32-bit Transaction Address
Description
AHB_S_HTRANS[1:0]
Input
Transfer type indicator
AHB_S_HWRITE
Input
Indicates transfer direction
AHB_S_HSIZE[1:0]
Input
Size of the transaction
•
00 - Byte (8-bit)
•
01 - Halfword (16-bit)
•
10 - Word (32-bit)
•
11 - Not supported (Doubleword)
Revision 3
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PCI Express
Table 3-5 • PCIe System AXI3/AHBL Slave Interface (continued)
Port
AHB_S_HBURST[2:0]
Type
Input
Description
Burst type indicator
•
000 - SINGLE
•
001 - INCR
•
010 - WRAP4
•
011 - INCR4
•
100 - Not Supported (WRAP8)1
•
101 - Not Supported (INCR8)1
•
110 - Not Supported (WRAP16)1
AHB_S_HWDATA[31:0]
Input
• 111 - Not Supported (INCR16)1
32-bit Write Data
AHB_S_HSEL
Input
Slave select signal
AHB_S_HREADY
Input
Transaction finished indicator.
AHB_S_HRDATA[31:0]
Input
32-bit Read Data
AHB_S_HREADYOUT
Output Transaction finished indicator from the slave
AHB_S_HRESP
Output Transfer response. The interface responds with an ERROR under the following
conditions:
•
If a completion TLP has the EP (poisoned) bit set
•
If a completion TLP has an error
•
If a completion timeout event occurs
•
If an invalid AHBL slave transaction is encountered
Note:
• The Libero component for the AHBL interface only supports HBURST[1:0].
Table 3-6 • PCIe System APB Slave Interface
Port
Type
Description
APB_S_PSEL
Input
APB slave select; select signal for register for reads or writes.
APB_S_PENABLE
Input
APB strobe. This signal indicates the second cycle of an APB transfer.
APB_S_PWRITE
Input
APB write or read. If High, a write occurs when an APB transfer takes place. If
low, a read takes place.
APB_S_PADDR[13:0]
Input
APB address bus.
APB_S_PWDATA[31:0]
Input
APB write data.
APB_S_PREADY
Output APB ready. Used to insert wait states.
APB_S_PRDATA[31:0]
Output APB read data.
APB_S_PSLVERR
Output APB Error.
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R e visio n 3
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Table 3-7 • PCIe System Clock Signals
Port
Type
Description
CLK_BASE
Input
Fabric source clock. This clock input is used for the Master and Slave interfaces.
It is also used as the reference clock to the SPLL which is used to achieve
interface timing across the fabric to SERDES block.
Note: The frequency of this clock must match the GUI option for the CLK. BASE
rate to guarantee timing is met across the fabric interface.
APB_S_CLK
Input
PCLK for APB slave interface in SERDES Block
SPLL_LOCK
Output PLL Lock signal. High indicates that the frequency and phase lock are achieved.
PLL_LOCK_INT
Output The SPLL Lock status register (Active High indicates locked).
PLL_LOCKLOST_INT
Output The SPLL Lock lost status register (Active high indicates that the lock is lost).
Table 3-8 • PCIe System Reset Signals
Ports
Type
Description
CORE_RESET_N
Input
PCIe core active low reset. Top-level fundamental asynchronous RESET to the
PCIe system. It affects only those SERDES lanes which are in PCIe mode.
Lanes associated with the PCIe link must have one reset for all lanes.
PHY_RESET_N
Input
Active low – SERDES – reset. Top-level fundamental asynchronous RESET to
the SERDES block.
APB_S_PRESET_N
Input
APB slave interface – PRESETN: Async set. APB asynchronous reset to all APB
registers.
Note: More information for these resets is provided in Figure 3-17 on page 68.
PCIE_WAKE_N, PCIE_WAKE_REQ, and PCIE_PERST_N ports are added optionally with L2/P2
selection. PCIE_WAKE_N is an output and PCIE_WAKE_REQ, and PCIE_PERST_N ports are inputs to
the PCIE core.
Table 3-9 • PCIe Interrupt and Power Management Interface
Port
Type
Description
PCIE_INTERRUPT[3:0]
Input
PCIe system interrupt inputs. When using INTx legacy interrupts
PCIE_INTERRUPT[0] is used to assert/de-assert INTA. When using MSI
interrupts up to 4 MSI interrupts can be sent. Each bit sends an MSI vector with
bit 0 starting at the MSI base and each bit increments the vector. Asynchronous.
Synchronized internally to each lane’s PIPE clock.
PCIE_SYSTEM_INT
PCIE_WAKE_REQ
Output PCIe system interrupt output (not supported)
Input
L2/P2 implementation: (L2 requests from fabric)*
Asynchronous. Input to power-management state machine.
PCIE_WAKE_N
PCIE_PERST_N
Output L2/P2 implementation: (L2 exit request to RP)*
Input
L2/P2 implementation: (L2 exit request from RP)*
Asynchronous. Synchronized to the internal 50 MHz RC Oscillator.
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PCI Express
Table 3-9 • PCIe Interrupt and Power Management Interface
PCIE_LTSSM[5:0]
Output Ports indicate the status of ltssm state management. Equivalent to LTSSM
Register (044h) [28:24]. These bits set to LTSSM state encoding (RO)- output
bits [4:0] ltssm state. Bit[5] Pulses high to indicate that a hot-reset, data link up or
L2 exit condition has occurred. Synchronized to the PIPE clock.
PCIE_L2P2_ACTIVE
Output Active high output indicating the LTSSM is in low-power state.
PCIE_RESET_PHASE
Output Active high output indicating the LTSSM is in reset state.
Note: * This in only available when L2/P2 option is selected in SERDES block Configurator GUI.
Functional Description
This section covers the functional aspects of the reset and clock circuitry inside the SERDES block for
PCIe. It includes the following sub-sections:
•
PCIe Clocking Architecture
•
PCIe Reset Network
•
PCI Express Power-Up
PCIe Clocking Architecture
The RTG4 SERDES block, when configured in PCIe mode, uses multiple clocks inside the SERDES
block. This sub-section describes the PCIe clocking architecture inside SERDES block in PCIe mode.
Figure 3-11 shows the PCIe clocking architecture in the RTG4 device. The two main clock inputs are a
differential SERDES reference clock (100 MHz) for SERDES physical media attachment (PMA), and a
CLK_BASE input for SERDES block from the FPGA fabric. In addition, there is a APB clock input for
SERDES block from the FPGA fabric.
SERDES reference clock: The differential 100 MHz reference clock is used by SERDES (TX PLL and
CDR PLL) to generate 125 MHz clock and passed to PCIe System IP block. The setting for TX PLL and
CDR PLL are calculated automatically by the Libero software. This 125 MHz clock output from SERDES
is used by PCIe system. There are several options for providing this SERDES reference clock. Refer to
the "SERDES Reference Clock Inputs" section in the "Serializer/De-serializer" chapter on page 21 for
details.
The PCIe standard specifies a 100 MHz clock (Refclk) with greater than ±300 ppm frequency stability at
both the transmitting and receiving devices. RTG4 does support two distinct clocking topologies:
Common Refclk and Separate Refclk.
Common Refclk is the most widely supported clocking method in open systems where the host (switch or
root) provides a clock to the end point. An advantage of this clocking architecture is that it supports
spread spectrum clocking (SSC) which can be very useful in reducing electromagnetic interference
(EMI). RTG4 does support SSC clocking in common clock systems.
Separate Refclk uses two independent clock sources. One clock for the host (switch or root) and another
clock source for the endpoint. The clock sources still must be ±300 ppm frequency accuracy and cannot
use any SSC.
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R e visio n 3
RTG4 FPGA High-Speed Serial Interfaces
TXDP
TXDN
Gen1 2.5 GHz
RXDP
RXDN
Gen1 2.5 GHz
Fabric
SERDES Block
TX
PLL
CDR
PLL
SERDES Reference
Clock (100 MHz)
500 MHz
RxCLK-x4clks
500 MHz
TxClk-x4clks
PCIe PCS
Div 2/4
APB_S_CLK
125 MHz
TxClk-x4clks
CLK_BASE
PCIe
System
4 to 1
MUX
125 MHz TxClk
Deskew
PLL_SERDES_BLOCK_REF
SPLL
PCIE_AXI_AHB_CLK
Deskew
PLL_SERDES_BLOCK_FB
PLL_ACLK
Figure 3-11 • Various Clocks in PCIe Mode
The clocking architecture also uses SPLL to synchronize data between CLK_BASE and the clock
generated from SERDES (125 MHz clocks). The SPLL allows the reduction of the skew between the
fabric and the RTG4 SERDES block module. Table 3-7 on page 57 summarizes the SERDES block clock
signals in PCIe mode.
Revision 3
59
PCI Express
SERDES Reference Clocks Selection
RTG4 accepts the PCIE reference clock. It is fully compliant with the PCI Express add-in card
specifications and can directly receive the 100 MHz reference clock from the PCI Express Connector.
The differential PCIE clock is connected to the REFCLK_P and REFCLK_N pins and are configured
correctly by the Libero software. Refer to the "Serializer/De-serializer" chapter on page 21 for more
information on REFCLK block of RTG4.
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Figure 3-12 • SERDES Reference Clock for PCIe Mode
The reference clock needs to be compliant with the PCIe protocol. Refer to the RTG4 FPGA Datasheet
for the specification. The Libero software only permits using REFCLK_P or REFCLK_N for PCIe mode.
Table 3-10 • Reference Clock Signals for SERDES in PCIe Mode
Clock Signal
Description
REFCLKP
Reference clock input for SERDES_(PCIE)_#_REFCLK_P
REFCLKN
Reference clock input for SERDES_(PCIE)_#_REFCLK_N
PCIe Reset Network
SERDES block has different reset inputs when configured in the PCIe mode. Table 3-8 on page 57
shows the reset signals and recommended connection. The reset connections are required for a proper
PCIe SERDES initialization solution. To build the initialization circuitry, Microsemi provides the pcie_init
component ready to import as a Block in the Libero SoC project. The pcie_init component has a one for
one connection for the fabric signals, as shown in Figure 3-13 on page 61.
60
R e visio n 3
RTG4 FPGA High-Speed Serial Interfaces
Figure 3-13 shows a simplified view of the reset signal in SERDES block in PCIe mode.
Fabric
CORE_RESET_N
SERDES Block
PHY CLK
Sync
PCIe/PHY
Reset
Controller
SERDES
PHY_RESET_N
Sync
PCIe IP Block
APB_S_CLK
APB_S_PRESET_N
Sync
Figure 3-13 • Reset Signals in PCIe Mode
PCI Express Power-Up
The PCI Express (PCIe) specification provides timing requirements for power-up. As with SRAM-based
FPGA endpoint devices, power-up is a concern when working within these tight specifications. The PCIe
specification specifies the release of the fundamental reset (PERST#) in the connector specification. The
PERSTn release time (TPVPERL) of 100ms is used for the PCIe Card Electromechanical Specification
for add-in cards. From the point of power stable to at least 100 ms, the PERST# must remain asserted.
Different PCIe systems hold PERSTn longer than 100 ms, but the minimum time is 100 ms.
The advantage of flash-based RTG4 device is that its wake up time is very fast in contrast to SRAM
FPGA endpoints due to their configuration requirement. The semi-autonomous nature to the PCIe Core
in the RTG4 device quickly moves from power-up to link detectable allowing the device to be detected by
the root. When the device is detected by the root, it proceeds to the Polling state of the LTSSM. The link
now cycles through the remainder of the LTSSM.
In use cases where the root and endpoint power-up separately, the PERSTn signal must be used to
handshake the link startups.
Revision 3
61
PCI Express
Power
Stable
Power Up
EP
Device
PERSTn
Wake up
Link
Detect
See Note*
Link Training
Link State
L0 (Active)
Inactive
Figure 3-14 • PCI Express Power-Up States
1. EP Device Wake Up: The internal flash loads the configuration information to the PCIe logic data
to the device. If PERSTn is required, a fabric GPIO must be connected to the PERSTn of the
Root. This GPIO must be connected in the FPGA design to the CORE_RESETn pin of the PCIe
core. The embedded PCIe core is held in reset by PERSTn, and is released afterwards to start
PCIe link detection and training.
2. Link Detection: Out-of-band pulse looks for far-end connection.
3. The PCIe link completes the training phase and reaches the L0 state.
4. After the embedded PCIe endpoint core reaches the L0 state, the host operating system (OS)
accesses the PCIe core’s configuration space registers (CSR) to perform configuration write
access cycles that are part of the system enumeration process.
Note: PERSTn is controlled by the root. If not connected to the EP, the EP enters Link Detect as soon as
the device wake up is complete.
Designing with PCIe
This section provides instruction for using the RTG4 PCIe EP implementation user design. It includes the
following sub-sections:
•
Base Address Register Settings
•
Address Translation on AXI3 Master Interface
•
AXI3 Slave Interface Address Translation
•
PCIe System Credit Settings
•
Setting up Lane Reversal
•
PCIe Power Management
Base Address Register Settings
The PCIe implementation supports up to six 32-bit BARs or three 64-bit BARs. The BARs can be one of
two sizes:
62
•
32-bit BAR: The theoretical address space can be as small as 16 bytes or as large as 2
gigabytes.
•
64-bit BAR: The theoretical address space can be as small as 128 bytes or as large as 8
gigabytes. Used for memory only.
R e visio n 3
RTG4 FPGA High-Speed Serial Interfaces
Each BAR register is 32 bits, but BARs can be combined to make a 64-bit BAR. For example, BAR0
(address offset 010h) and BAR1 (address offset 014h) define the type and size of BAR01 of the PCIe
native endpoint. BAR01 can be memory-mapped prefetchable (64-bit BAR) or non-prefetchable (32-bit
BAR).
The SERDES block Configurator in Libero provides a GUI to configure the BAR settings for the EP
application. Refer to Figure 3-15 on page 64 for details. The BAR registers share the options below:
•
Width: Width can be 32-bit or 64-bit. If an even register is selected to be 64-bit wide, then the
subsequent (odd) register serves as the upper half of 64 bits. Otherwise, the width of odd
registers is restricted to 32-bit.
•
Size: Ranges from 4 Kbytes to 1 Gbyte, with 4 Kbytes increments.
•
Prefetchable: Prefetchable option for memory BAR.
–
A PCI Express Endpoint requesting memory resources through a BAR must set the BAR’s
Prefetchable bit unless the range contains locations with read side-effects or locations in
which the device does not tolerate write merging. It is recommended that memory-mapped
resources be designed as prefetchable whenever possible. For a PCI Express Endpoint, 64bit addressing must be supported for all BARs that have the prefetchable bit set. 32-bit
addressing is permitted for all BARs that do not have the prefetchable bit set.
Address Translation on AXI3 Master Interface
The address space for PCIe is different from the AXI3 address space. To access one address space from
another address space requires an address translation process.
The PCIe IP can receive both 32-bit address and 64-bit address PCIe requests, but only 32-bit address
bits are provided to the AXI3 master. In order to manage address translation, the PCIe IP can implement
up to 4 AXI3 master address windows, which can be mapped to 3 BARs in the main PCIe IP core.
The address mapping registers (AXI_MASTER_WINDOWx[x], where x can be 0, 1, 2, or 3) are shown in
Table 3-11 and are used to set the address mapping.
Table 3-11 • AXI_MASTER_WINDOW Registers
Bit
Number
[31:12]
Name
AXI_MASTER_WINDOWx[0]
[11:0]
[31:12]
Description
Base address AXI3 master window x
Reserved
AXI_MASTER_WINDOWx[1]
Size of AXI3 master window x
[11:1]
Reserved
0
Enable bit of AXI3 master window x
[31:12]
AXI_MASTER_WINDOWx[2]
LSB of base address PCIe window x
[11:6]
Reserved
[5:0]
These bits set the BAR. To select a BAR, set the following
values:
0x01: BAR0 (32-bit BAR) or BAR0/1 (64-bit BAR)
0x02: BAR1 (32-bit BAR) only
0x04: BAR2 (32-bit BAR) or BAR2/3 (64-bit BAR)
0x08: BAR3 (32-bit BAR) only
0x10: BAR4 (32-bit BAR) or BAR4/5 (64-bit BAR)
0x20: BAR5 (32-bit BAR) only
[31:0]
AXI_MASTER_WINDOWx[3]
MSB of base address PCIe window x
Note: x = 0, 1, 2, and 3
Revision 3
63
PCI Express
Each AXI3 master address window implemented can be mapped to a BAR, and several address
windows can be mapped to the same BAR. When transferring PCIe receive requests to the AXI3 Master,
the PCIe IP core automatically removes the decoded BAR base address, then performs a windows
match using the PCIe offset address. If a match is found, the bridge then maps the corresponding AXI3
base address.
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Figure 3-15 • PCIe to AXI3 Master Address Translation
For example, in Figure 3-15 on page 64, four BARS are enabled in the bridge; two 64-bit BARS (BAR01
and BAR23), and two 32-bit BARS (BAR4 and BAR5). All AXI3 master windows are utilized: 64-bit
BAR01 is mapped to AXI3 master window 0; 64-bit BAR23 is mapped to AXI3 master window 1; and
AXI3 master window 2 is mapped to the upper 64 bytes of BAR23. 32-bit BAR4 is mapped to AXI3
master window 3. BAR5 is not mapped to an AXI3 window; its offset is passed directly to the AXI3 master
and translation is not performed.
To configure AXI_MASTER_WINDOWs, four APB write operations are performed to
AXI_MASTER_WINDOW0[0],
AXI_MASTER_WINDOW0[1],
AXI_MASTER_WINDOW0[2]
and
AXI_MASTER_WINDOW0[3] registers:
•
APB write to AXI_MASTER_WINDOW0[0]: APB PADDR = 100h, APB PWDATA = FFF0 0000
•
APB write to AXI_MASTER_WINDOW0[1]: APB PADDR = 104h, APB PWDATA = FFF0 0001
•
APB write to AXI_MASTER_WINDOW0[2}: APB PADDR = 108h, APB PWDATA = 0000 0001
•
APB write to AXI_MASTER_WINDOW0[3]: APB PADDR = 10Ch, APB PWDATA = 0000 0000
The example is shown using relative SERDES block addressing for PADDR.
If window size is not enabled or if the PCIe offset address is located in a BAR but not in any of the
windows, address translation is not performed. In this case, the PCIe base address is removed to create
the AXI3 address and, for BARs larger than 4 Kbytes, MSBs are ignored.
The address translation needs to be pre-defined in the user design. This is completed using the
SERDES block configurator GUI.
The PCIe AXI3 master windows are used to translate the PCIe base address domain to the local address
domain.
64
R e visio n 3
RTG4 FPGA High-Speed Serial Interfaces
AXI3 Slave Interface Address Translation
The bridge can configure up to four AXI3 slave address windows to handle address translation on
read/write requests initiated from the FPGA fabric. The AXI3 slave address windows are used to
translate a 32-bit AXI3 base address for a transaction to a PCIe 32-bit or 64-bit base address to generate
a PCIe TLP. The slave address windows can also be used to generate the following PCIe parameters:
•
TC Selection: Indicates the PCIe traffic class in the PCIe packet header.
•
RO Bit Selection: Generates the PCIe TLP using a selectable relaxed ordering bit.
•
No Snoop Bit Selection: Generates the PCIe TLP using a selectable no snoop bit. See Section
2.2.6.5 of the PCIE 2.0 Base specification for option details.
The address mapping registers (AXI_SLAVE_WINDOWx[x], x can be 0, 1, 2, or 3) is used to set the 
address mapping, refer to Table 3-12 on page 65.
Table 3-12 • AXI_SLAVE_WINDOW Registers
Bit
Number
[31:12]
Name
AXI_SLAVE_WINDOWx[0]
[11:0]
[31:12]
Description
Base address AXI3 slave window x
Reserved
AXI_SLAVE_WINDOWx[1]
Size of AXI3 slave window x
[11:1]
Reserved
0
Enable bit of AXI3 slave window x
[31:12]
AXI_SLAVE_WINDOWx[2]
LSB of base address PCIe window 0
[11:5]
Reserved
[4:2]
AXI3 slave window 0 traffic class (TC)
1
AXI3 Slave window 0 relaxed ordering (RO)
0
AXI3 Slave window 0 no snoop (NS)
[31:0]
AXI_SLAVE_WINDOWx[3]
Note: x = 0, 1, 2, and 3
MSB of base address PCIe window x
Revision 3
65
PCI Express
Figure 3-16 shows address translation when AXI3 slave address window 0 and window 2 target two
different regions of the host memory and the AXI3 slave address window 1 targets a PCIe memorymapped device (enabling peer-to-peer transactions). Window 3 is not used in this example.
PCIe
full address
AXI
full address
Host processor
address space
0x00000000
Local device
address space
0x00000000
Host
memory
Window0
0x40000000
Window1
0x80000000
Window2
Window3
PCIe
memorymapped
PCIe-to-AXI Bridge
0xC0000000
0xFF640000
0xFFFFFFFF
0xFFFFFFFF
Figure 3-16 • AXI3 Slave to PCIe Address Translation
If AXI3 slave windows are not enabled, address translation is not performed and AXI3 slave requests are
transferred to the PCIe IP core with defaults of TC = 0, RO = 0, and NS = 0.
PCIe System Credit Settings
PCIe system has 2 Kbytes of receive buffer (RAM) and 1 Kbyte of transmit and replay buffer (RAM). The
following sections describe the different features that impact credit processing. All of the credit settings
are set automatically by the Libero software based on the buffer sizes fixed in the SERDES block.
Maximum Payload Size
The size of TLP is restricted by the capabilities of both link partners. After the link is trained, the root
complex sets the MAX_PAYLOAD_SIZE (maximum payload size register) value in the device control
register. The possible settings are128 and 256 bytes.
Replay Buffer
The replay buffer, located in the data link layer, stores a copy of a transmitted TLP until the transmitted
packet is acknowledged by the receiving side of the link. Each stored TLP includes the header, an
optional data payload (of which the maximum size is determined by the maximum payload size
parameter), an optional ECRC, the sequence number, and the link CRC (LCRC) field.
Transmit Buffer
The transmit buffer (Tx buffer) stores the read data payload from the AXI3 master as well as the write
data payload from the AXI3 slave.
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Receive Buffer
The receive buffer is located in the transaction layer and accepts incoming TLPs from the link and then
sends them to the application layer for processing. The receive buffer stores TLPs based on the type of
transaction, not the transaction count (TC) of a transaction. Types of transactions include posted
transactions, non-posted transactions, and completion transactions. A transaction always has a header
but does not necessarily have data. The receive buffer accounts for this distinction, maintaining separate
resources for the header and data of each type of transaction. To summarize, distinct buffer resources
are maintained for each of the following elements:
•
Posted transactions, header (PH)
•
Posted transactions, data (PD)
•
Non-posted transactions, header (NPH)
•
Non-posted transactions, data (NPD)
•
Completion transactions, header (CPLH)
•
Completion transactions, data (CPLD)
TLPs are stored in the received buffer in 64-bit addressing format, with each AXI3 slave read outstanding
request consuming 16 credits (128 bytes), plus headers and data credits consuming 1 credit each 
(16 bytes).
User Data Throughput
PCIe uses credits to handle throughput balancing between both ends of the link. At the initial link-up,
both sides of the link share their transmit and receive buffer sizes in terms of credits. As TLPs are sent
across the link, credits are used. As user data is pulled out of the TLPs stored in the receive buffers
credits are released. Information on the current state of the credits is continuously sent across the link
using data link layer packets. All of this happens transparent to the user inside the PCIe core.
The [RTG4] PCIe core uses an AHB or AXI3 fabric interface for user data. AHB and AXI3 slave
interfaces only allow a transaction when 128 byte TLP worth of credits is available to be sent. Using this
method, the PCIe core can back pressure the fabric interface when credits are not available to send a
TLP.
The flow control works by releasing credits to the sender as data is pulled across to the fabric. If the user
is not pulling the data out fast enough, then the sender runs out of credits. In the worst case situation
where the sender is 100% writing data to the PCIe core only 1325 MBps is able to go through. The credit
system holds the sender back from sending more data. Similar for where the sender is 100% pulling data
via a read, only 1325 MBps comes back. In this case, PCIe core is never throttled back due to a lack of
credits.
Reverse the situation with the PCIe core as the sender. For 100% write data, the fabric interface is held
up at 1325 Mbps. For 100% read requests the receiver sends them back faster than 1325 Mbps, but the
fabric interface only pulls them out at 1325 Mbps. The receiver is Blocked by a lack of completion credits
until credits are released.
The transaction size in this situation is more efficient when small (128 byte TLPs). Smaller packet sizes
allow PCIe core to release credits faster compared to large packets. As a packet is pulled across the
fabric interface the credit is released for the sender to send another. If this happens quickly the next
packet can be sent. For large packets it takes longer to release the credit and therefore the next packet is
not sent as quickly.
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Setting up Lane Reversal
Polarity swapping or inversion capability within a PCIE receive or transmit lane is not available in RTG4.
PCIe system supports lane reversal capabilities and therefore provides flexibility in the design of the
board. It is possible to choose to lay out the board with reversed lane numbers and the PCIe EP
continues to link train successfully and operate normally. The SERDES block Configurator in Libero
allows configuration of the SERDES block in reverse lane PCIe mode, as shown in Figure 3-17.
Device A
(Upstream Device)
0 1 2 3
0 1 2 3
Device A
(Upstream Device)
0 1 2 3
0 1 2 3
3 2 1 0
3 2 1 0
3 2 1 0
Device B
(Downstream Device)
0 1 2 3
0 1 2 3
3 2 1 0
Device B
(Downstream Device)
After Lane
Reversal
Before Lane
Reversal
Figure 3-17 • Reversed Signals in PCIe Mode
PCIe Power Management
This section describes the power management scheme in the FPGA PCIe implementation. This has the
following sub-sections:
•
Power Domain Implementation
•
Legacy Power Management
•
PCIe Power Management
Power Domain Implementation
In the RTG4 devices, the FPGA and PCIe link (including PMA, PCS, and PCIe controller) are combined
in a single chip, so they have separate power supplies. Figure 3-18 shows the RTG4 power rails. Refer
to the AC439: Board Design Guidelines for RTG4 FPGA Application Note (to be released) for detailed
power supply connections.
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VDD = 1.2 V
SERDES_PCIE_#_L[0:1][2:3]_VDDAIO = 1.2 V
VDDPLL = 3.3 V
SERDES I/O
Pads
SERDES_PCIE_#_L[0:1][2:3]_VDDAPLL = 2.5 V
PMA
Block
PMA
Control
Logic
PCIe PCS
(Lane0)
PMA
Block
PMA
Control
Logic
PCIe PCS
(Lane1)
TX/CDR
PLL
PCIe System
Fabric
SPLL
Common
Logic
PMA
Block
PMA
Control
Logic
PCIe PCS
(Lane2)
PMA
Block
PMA
Control
Logic
PCIe PCS
(Lane3)
Figure 3-18 • RTG4 Power Supply to the PCIe Link Implementation
Legacy Power Management
The PCIe bridge register space defines the capabilities of the PCIe bridge in term of legacy power
management (PME support, auxiliary current requirement and so on.). The power management control
and status register also contain the current power management state. The PM data and PM scale value
array can define the power consumed in each power state. Refer to the "Bridge Register Space" section
on page 70 for more information.
PCIe Power Management
PCIe active state power management (ASPM) defines link power management states that a PCIe
physical link is permitted to enter in response to software-driven D-state transitions or active state link
power management activities.
The PCIe protocol defines the following low power link states.
Table 3-13 • PCIe Low Power States
Low Power State
Description
L0s
Autonomous electrical idle: This state reduces power during short intervals of idle. Devices must
transition to L0s independently on each direction of the link.
L1
Directed electrical idle: The L1 state reduces power when the downstream port directs the
upstream ports. This state saves power in two ways:
•
Shutting down the transceiver circuitry and associated PLL
•
Significantly decreasing the number of internal core transitions
L2
In this state, a WAKE# signal is required to reinitialize the Link. However, the Auxiliary power is
still available.
L2/L3 ready
This state prepares the PCIe link for the removal of main power and the reference clock.
PCIe EP implementation supports L0, L1, and a special version of L2.
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PCIe Interrupts for Endpoints
The RTG4 PCIe EP implementation supports 32 MSI interrupt and INTx interrupts. It cannot support both
at the same time. The user can select which interrupt model to use in the High Speed Serial Interfaces
Configurator. The Libero software initializes the interrupts. For MSI, the user has a selection of up to 32
MSI vectors. When using MSI, the first 4 interrupts can be sent using the PCIE_INTERRUPTS[3:0] port
of the SERDES block [0] for MSI0, [1] for MSI1. To send more than 4 interrupts the user must use the
AXI3 Slave interface and send a memory write transaction to the specific address set by the root
complex during interrupt negotiation.
ECRC Handling
ECRC ensures end-to-end data integrity. The PCIe implementation transmits a TLP with ECRC from the
transmit port of the application layer. When using ECRC forwarding mode, the ECRC check and
generate are done in the application layer. The PCIE_AER_ECRC_CAPABILITY register in bridge
configuration registers sets the ECRC settings.
Bridge Register Space
The PCIe core bridge register space is used to configure the PCIe core settings at power-up. Initialization
IP module facilitates configuration of the SERDES block in an RTG4 device. These registers are 32 bits
wide and part of the SERDES block system register. Refer to the "SERDES Block System Register"
section in the "SERDES Block Register Access Map" chapter on page 140.
The PCIe system block registers consist of:
•
Read-only registers that report control and status registers to the AXI3 side through the APB bus
•
Bridge settings that must be configured at power-up, such as local interrupt mapping to MSI and
test mode
•
Control/status registers that can be used by the AXI3 bus to control bridge behavior during an
operation
Most bridge registers are hardwired to a fixed value.
These registers are described in the next section according to their function:
•
Information Registers: provide device, system, and bridge identification information.
•
Bridge Configuration Registers: enable configuration of bridge functionality.
•
Power Management Registers: enable configuration of the power management capabilities of the
bridge.
•
Address Mapping Registers: provide address mapping for AXI3 master and slave windows.
These windows are used for address translation.
•
EP Interrupt Registers: used in EP mode to manage interrupts.
•
PCIe Control and Status Registers: read-only registers enable the local processor to check useful
information related to the PCIe interface status. This enables the local processor to detect when
the bridge’s PCIe interface is initialized and to monitor PCI link events.
Register Initialization
The registers contained in the SERDES block are initialized automatically when the device powers-up
using data stored in non-volatile storage in the device. There are two types of initialization that are used
to set the value in the registers (flash bits and APB accessed registers).
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Flash Bits (Flash)
There are several flash bits that are associated with each SERDES block. These flash bits contain the
settings for registers that need to be initialized quickly when the device powers up such as PLL and clock
configurations, PCIe configuration space, and resets. The flash bits are set by the Libero configuration
GUI based on the user selections, programmed into the device, and are statically set at device power-up.
APB
The SERDES block supports an APB slave interface connected to the fabric interface. When the Libero
software assembles the SERDES block supporting modules the APB needs to be connected to the
module's APB master port. After the device powers up the supporting modules initializes the necessary
registers in the SERDES block that use the APB interface.
It is possible that the APB initialization overwrites registers that have been initialized by the flash bits
since the APB is written after the flash bit value has been loaded.
Fixed
These registers are read-only registers and their values are fixed based on the implementation of the
device.
Information Registers
The registers listed in Table 3-14 provide device, system, and bridge identification information.
Table 3-14 • Information Registers
Register Name
Address Register
Type
Initialization
Offset
Description
PCIE_VID_DEVID
000h
R/O
Flash
Identifies the manufacturer of the
device or application. Refer to the PCIe
specification for details.
PCIE_CLASS_CODE_REG
008h
R/O
Flash
Identifies the generic function of the
device and, in some cases, a specific
register-level programming interface.
PCIE_CAPTURED_BUS_DEVICE_NB
03Ch
R/O
N/A
Reports the bus and device number of
the EP device for each configuration
write TLP received.
PCIE_SUBSYSTEM_ID
02Ch
R/O
Flash
Identifies the manufacturer of the
device or application. Refer to the PCIe
specification for details.
PCIE_INFO
16Ch
R/O
N/A
Revision 3
Reports the bridge version.
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PCI Express
Bridge Configuration Registers
The registers listed in Table 3-15 enable to configure bridge functionality.
Table 3-15 • Bridge Configuration Registers
Byte
Offset
State
Initialization
RESERVED
204h
R/O
Flash
Sets the PCIe configuration.
PCIE_BAR0
010h
R/W
Flash
Defines the type and size of BAR0 of the PCIe
native endpoint. This register combines with
BAR1 for defining the type and size of BAR01 of
the PCIe native endpoint.
PCIE_BAR1
014h
R/O
Flash
Defines the type and size of BAR1 of the PCIe
native endpoint. This register combines with
BAR0 for defining the type and size of BAR01 of
the PCIe native endpoint.
PCIE_BAR2
018h
R/O
Flash
Defines the type and size of BAR2 of the PCIe
native endpoint. This register combines with
BAR3 for defining the type and size of BAR23 of
the PCIe native endpoint.
PCIE_BAR3
01Ch
R/O
Flash
Defines the type and size of BAR3 of the PCIe
native endpoint. This register combines with
BAR2 for defining the type and size of BAR23 of
the PCIe native endpoint.
PCIE_BAR4
020h
R/O
Flash
Defines the type and size of BAR4 of the PCIe
native endpoint. This register combines with
BAR5 for defining the type and size of BAR45 of
the PCIe native endpoint.
PCIE_BAR5
024h
R/O
Flash
Defines the type and size of BAR5 of the PCIe
native endpoint. This register combines with
BAR4 for defining the type and size of BAR45 of
the PCIe native endpoint.
PCIE_AER_ECRC_CAPABILITY
050h
R/W
APB
Defines whether the bridge supports AER and
ECRC
generation/check
and
whether
AER/ECRC is implemented. ECRC generation
and check bits can only be set if AER is
implemented.
MAX_PAYLOAD_SIZE
058h
R/O
Fixed
Negotiated maximum payload size.
PCIE_CREDIT_ALLOCATION_0
0B0h
R/O
Fixed
Provides the initial credit values for posted
transactions.
PCIE_CREDIT_ALLOCATION_1
0B4h
R/O
Fixed
Provides the initial credit values for non-posted
transactions.
PCIE_ERROR_COUNTER_0
0A0h
R/W
N/A
Has four 8-bit counters for the four error sources.
To clear the register content, the bridge must
perform a write transaction (any value) to this
register.
PCIE_ERROR_COUNTER_1
0A4h
R/W
N/A
Has four 8-bit counters for the four error sources.
To clear the register content, the bridge must
perform a write transaction (any value) to this
register.
Register Name
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RTG4 FPGA High-Speed Serial Interfaces
Table 3-15 • Bridge Configuration Registers (continued)
Register Name
Byte
Offset
State
Initialization
Description
PCIE_ERROR_COUNTER_2
0A8h
R/W
N/A
Has four 8-bit counters for the four error sources.
To clear the register content, the bridge must
perform a write transaction (any value) to this
register.
PCIE_ERROR_COUNTER_3
0ACh
R/W
N/A
Has four 8-bit counters for the four error sources.
To clear the register content, the bridge must
perform a write transaction (any value) to this
register.
Power Management Registers
The registers listed in Table 3-16 enable to configure the power management capabilities of the bridge.
Table 3-16 • Bridge Power Management Registers
Byte
Offset
State
Description
PCIE_LTSSM
044h
R/O
Can be used to monitor the core state or to select a specific
test mode on bits [31:16] and to control L2 entry on bits [15:0].
PCIE_POWER_MGT_CAPABILITY
048h
R/W
Enables the local processor to configure power management
capability.
PCIE_PM_DATA_SCALE_0
070h
R/W
PCIE_PM_DATA_SCALE_1
074h
R/W
PCIE_PM_DATA_SCALE_2
078h
R/W
There are four PM data and scale registers that define the PM
data value of the device for each possible power state defined
by the PCI power management specification, used in
conjunction with the PM scale field.
PCIE_PM_DATA_SCALE_3
07Ch
R/W
PCIE_ASPM_L0S_CAPABILITY
060h
R/W
Defines the EP L0s acceptable latency and the number of fast
training sequences (FTS) required by the SERDES to
resynchronize its receiver on incoming data, depending on
clock mode configuration (separated clock or common clock).
The number of FTS required in separated clock mode must be
higher than that required in common clock mode. The bridge
automatically computes the ASPM L0s exit latency based on
these two register values, and on the maximum payload size
of the control register. The selected NFTS field is that
transmitted by the link training and status state machine
(LTSSM) to the opposite component in order to define the
number of FTS that the opposite component must send to be
sure that the device receiver has re-locked onto incoming data.
Reserved
260h
R/W
–
PCIE_ASPM_L1_CAPABILITY
064h
R/W
Defines the EP L1 acceptable latency and the number of FTS
required. The EP L1 acceptable latency is used to enable or
disable ASPM L1 entry by comparing its value to the maximum
ASPM L1 exit latency of all components in the hierarchy (plus
1 microsecond per switch). If the ASPM L1 acceptable latency
is lower than the maximum ASPM L1 exit latency, ASPM L1
entry is not enabled.
PCIE_TIMEOUT_COMPLETION
068h
R/W
Defines four timeout ranges for the completion timeout
mechanism.
Register Name
Revision 3
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PCI Express
Address Mapping Registers
The registers listed in Table 3-17 provide the address mapping for AXI3 master and slave windows.
These windows are used for address translation.
Table 3-17 • Address Mapping Registers
Address Offset
Register Type
Description
PCIE_AXI_SLAVE_WINDOW0_0
0C0h
R/W
PCIE_AXI_SLAVE_WINDOW0_1
0C4h
There are four register sets that define the
address mapping for AXI3 slave window 0.
PCIE_AXI_SLAVE_WINDOW0_2
0C8h
PCIE_AXI_SLAVE_WINDOW0_3
0CCh
PCIE_AXI_SLAVE_WINDOW1_0
0D0h
R/W
PCIE_AXI_SLAVE_WINDOW1_1
0D4h
There are four register sets that define the
address mapping for AXI3 slave window 1.
PCIE_AXI_SLAVE_WINDOW1_2
0D8h
PCIE_AXI_SLAVE_WINDOW1_3
0DCh
PCIE_AXI_SLAVE_WINDOW2_0
0E0h
R/W
PCIE_AXI_SLAVE_WINDOW2_1
0E4h
There are four register sets that define the
address mapping for AXI3 slave window 2.
PCIE_AXI_SLAVE_WINDOW2_2
0E8h
PCIE_AXI_SLAVE_WINDOW2_3
0ECh
PCIE_AXI_SLAVE_WINDOW3_0
0F0h
R/W
PCIE_AXI_SLAVE_WINDOW3_1
0F4h
There are four register sets that define the
address mapping for AXI3 slave window 3.
PCIE_AXI_SLAVE_WINDOW3_2
0F8h
PCIE_AXI_SLAVE_WINDOW3_3
0FCh
PCIE_AXI_MASTER_WINDOW0_0
100h
R/W
PCIE_AXI_MASTER_WINDOW0_1
104h
There are four register sets that define the
address mapping for AXI3 master window
0.
PCIE_AXI_MASTER_WINDOW0_2
108h
PCIE_AXI_MASTER_WINDOW0_3
10Ch
PCIE_AXI_MASTER_WINDOW1_0
110h
R/W
PCIE_AXI_MASTER_WINDOW1_1
114h
There are four register sets that define the
address mapping for AXI3 master window
1.
PCIE_AXI_MASTER_WINDOW1_2
118h
PCIE_AXI_MASTER_WINDOW1_3
11Ch
PCIE_AXI_MASTER_WINDOW2_0
120h
R/W
PCIE_AXI_MASTER_WINDOW2_1
124h
There are four register sets that define the
address mapping for AXI3 master window
2.
PCIE_AXI_MASTER_WINDOW2_2
128h
PCIE_AXI_MASTER_WINDOW2_3
12Ch
PCIE_AXI_MASTER_WINDOW3_0
130h
R/W
PCIE_AXI_MASTER_WINDOW3_1
134h
There are four register sets that define the
address mapping for AXI3 master window
3.
PCIE_AXI_MASTER_WINDOW3_2
138h
PCIE_AXI_MASTER_WINDOW3_3
13Ch
Register Name
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EP Interrupt Registers
The PCIe IP core can generate interrupts through the input signal. This signal may be required by a
device in order to interrupt the host processor, call its device drivers, or report application layer-specific
events or errors. The parameter of the bridge defines the number of interrupt bits for this signal.
Table 3-18 • EP Interrupt Registers
Register Name
Address Register
Type
Offset
Description
PCIE_MSI_0
080h
R/W
Defines single MSI function, with up to 32 possible MSI messages.
PCIE_MSI_CTRL_S
TATUS
040h
R/W
This register sets MSI control and status. All bits are R/O except the
number of MSI requested and the multiple message enable fields, which
are R/W. Up to 32 MSI messages can be requested by the device,
although the PCI software can allocate less than the number of MSI
requested. This information can be read by the local processor through
the multiple message enable field of the register.
PCIe Control and Status Registers
The following registers are read-only registers that enable the local processor to check useful information
related to the PCIe interface status, such as when the PCIe interface is initialized and monitoring of PCI
link events, as shown in Table 3-19. A complete description of these registers can be found in the PCIe
specifications.
Table 3-19 • PCIe Control and Status Registers
Register Name
Address
Offset
Register
Type
CFG_PRMSCR
004h
R/O
The command and status register of PCI configuration space.
PCIE_DEVSCR
030h
R/O
Reports the current value of the PCIe device control and status register.
It can be monitored by the local processor when relaxed ordering and
no snoop bits are enabled in the system.
PCIE_LINKSCR
034h
R/O
Reports the current value of the PCIe link control and status register. It
can be monitored by the local processor when relaxed ordering and no
snoop bits are enabled in the system.
CFG_PRMSCR
04Ch
R/O
Reports the current values of the XpressRich2 core’s power
management control status register.
PCIE_SLOTCAP
154h
-
Reserved
PCIE_SLOTCSR
158h
-
Reserved
PCIE_ROOTCSR
15Ch
-
Reserved
Description
Revision 3
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PCI Express
PCIe Bridge Registers
The following sub-section describes all PCIe bridge registers in detail.
PCIE_VID_DEVID Register (000h)
Table 3-20 • PCIE_VID_DEVID
Bit
Number
Name
Reset Value
Description
[31:16]
Device ID
0x11AA
Identifies the manufacturer of the device or application. The values
are assigned by PCI-SIG. The default value, 11AA, is the Device ID
for Microsemi.
[15:0]
Vendor ID
0x1556
The field Identifies the manufacturer of the device or application. The
values are assigned by PCI-SIG. The default value, 1556, is the
Vendor ID for Microsemi.
PCIE_CFG_PRMSCR Register (004h)
Table 3-21 • CFG_PRMSCR
Bit
Number
[31:0]
Name
Configuration
Primary Control
Status Register
Reset Value
Description
0x00100000 The command and status register of PCI configuration space.
PCIE_CLASS_CODE Register (008h)
Table 3-22 • PCIE_CLASS_CODE_REG
Bit
Number
Name
Reset Value
Description
[31:16]
PCIE_CLASS_CODE
0x0000
Identifies the manufacturer of the device or application. The values
are assigned by PCI-SIG.
[15:0]
RESERVED0
0x0000
Identifies the manufacturer of the device or application. The values
are assigned by PCI-SIG.
PCIE_BAR0 Register (010h)
Table 3-23 • PCIE_BAR0
Bit
Number
Name
Reset Value
[31:4]
BAR0_31_4
3
BAR0_3
0x1
Identifies the ability of the memory space to be prefetched.
[2:1]
BAR0_2_1
0x10
Set to '00' to indicate anywhere in 32-bit address space.
0
BAR0_0
0x0
Memory space indicator
76
0x000000
Description
Defines the type and size of BAR0 of the PCIe native endpoint.
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PCIE_BAR1 Register (014h)
Table 3-24 • PCIE_BAR1
Bit
Number
Name
Reset Value
0x000000
Description
[31:4]
BAR1_31_4
Defines the type and size of BAR1 of the PCIe native endpoint.
3
BAR1_3
0x0
Identifies the ability of the memory space to be prefetched.
[2:1]
BAR1_2_1
0x00
Set to '00' to indicate anywhere in 32-bit address space.
0
BAR1_0
0x0
Memory space indicator.
PCIE_BAR2 Register (018h)
Table 3-25 • PCIE_BAR2
Bit
Number
Name
Reset Value
Description
0x000000
The register defines the type and size of BAR2 of the PCIe native EP
[31:4]
BAR2_31_4
3
BAR2_3
0x1
Identifies the ability of the memory space to be prefetched.
[2:1]
BAR2_2_1
0x10
Set to '00' to indicate anywhere in 32-bit address space.
0
BAR2_0
0x0
Memory space indicator.
PCIE_BAR3 Register (01Ch)
Table 3-26 • PCIE_BAR3
Bit
Number
[31:4]
Name
BAR3_31_4
3
BAR3_3
0x0
Identifies the ability of the memory space to be prefetched.
[2:1]
BAR3_2_1
0x00
Set to '00' to indicate anywhere in 32-bit address space.
0
BAR3_0
0x0
Memory space indicator.
Reset Value
Description
0x000000 The register defines the type and size of BAR3 of the PCIe native EP.
PCIE_BAR4 Register (020h)
Table 3-27 • PCIE_BAR4
Bit
Number
Name
Reset Value
Description
0x000000
The register defines the type and size of BAR4 of the PCIe native EP.
[31:4]
BAR4_31_4
3
BAR4_3
0x1
Identifies the ability of the memory space to be prefetched.
[2:1]
BAR4_2_1
0x10
Set to '00' to indicate anywhere in 32-bit address space.
0
BAR4_0
0x0
Memory space indicator.
Revision 3
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PCI Express
PCIE_BAR5 Register (024h)
Table 3-28 • PCIE_BAR5
Bit
Number
Name
Reset Value
Description
0x000000
The register defines the type and size of BAR1 of the PCIe native EP.
[31:4]
BAR5_31_4
3
BAR5_3
0x0
Identifies the ability of the memory space to be prefetched.
[2:1]
BAR5_2_1
0x00
Set to '00' to indicate anywhere in 32-bit address space.
0
BAR5_0
0x0
Memory space indicator.
PCIE_SUBSYSTEM_ID Register (02Ch)
Table 3-29 • PCIE_SUBSYSTEM_ID
Bit
Number
Name
Reset Value
Description
[31:16]
SUBSYSTEM_ID
0x11AA
This field further qualifies the manufacturer of the device or
application. This value is typically the same as the Device
ID.
[15:0]
SUBSYSTEM_VENDOR_ID
0x1556
This field further qualifies the manufacturer of the device or
application.
PCIE_DEVSCR Register (030h)
Table 3-30 • PCIE_DEVSCR
Bit
Number
[31:0]
Name
PCIE_DEVSCR
Reset Value
Description
0x00000000 Device control and status: This register reports the current
value of the PCIe device control and status register. It can
be monitored by the local processor when relaxed ordering
and no snoop bits are enabled in the system.
Note: This register is READ only.
PCIE_LINKSCR Register (034h)
Table 3-31 • PCIE_LINKSCR
Bit
Number
[31:0]
78
Name
PCIE_LINKSCR
Reset Value
Description
0x00000050 This register reports the current value of the PCIe link
control and status register. It can be monitored by the local
processor when relaxed ordering and no snoop bits are
enabled in the system.
R e visio n 3
RTG4 FPGA High-Speed Serial Interfaces
PCIE_TC_VC_MAPPING Register (038h)
Table 3-32 • PCIE_TC_VC_MAPPING
Bit
Number
Name
Reset Value
Description
[31:24]
TC_VC_MAPPING_31_24
0x0
Reserved
[23:21]
TC_VC_MAPPING_23_21
0x0
Mapping for TC7
[20:18]
TC_VC_MAPPING_20_18
0x0
Mapping for TC6
[17:15]
TC_VC_MAPPING_17_15
0x0
Mapping for TC5
[14:12]
TC_VC_MAPPING_14_12
0x0
Mapping for TC4
[11:9]
TC_VC_MAPPING_11_9
0x0
Mapping for TC3
[8:6]
TC_VC_MAPPING_8_6
0x0
Mapping for TC2
[5:3]
TC_VC_MAPPING_5_3
0x0
Mapping for TC1
[2:0]
TC_VC_MAPPING_2_0
0x0
Mapping for TC0 (always 0)
Note: This register reports the TC-to-VC mapping configured for each PCI Express Traffic Channel.
PCIE_CAPTURED_BUS_DEVICE_NB Register (03Ch)
Table 3-33 • PCIE_CAPTURED_BUS_DEVICE_NB
Bit
Number
[31:0]
Name
PCIE_CAPTURED_BUS_DEVICE_NB
Reset
Value
0x0
Description
This register reports the bus and device number of
the EP device for each configuration write TLP
received.
PCIE_MSI_CTRL_STATUS Register (040h)
Table 3-34 • PCIE_MSI_CTRL_STATUS
Bit
Number
Name
Reset
Value
Description
[31:24]
MSI_CTRL_STATUS_31_24
0x0
These RO bits are hardwired to 00000000.
23
MSI_CTRL_STATUS_23
0x0
This RO bit is hardwired to 1.
[22:20]
MSI_CTRL_STATUS_22_20
0x0
Multiple message enable. Fabric logic/MSS checks
this RO APB register to see how many MSI interrupt
resources are allocated from the host side.
[19:17]
MSI_CTRL_STATUS_19_17
0x0
Number of MSI requested. Fabric logic/MSS writes
this RW APB register to request the number of MSI
interrupt resources needed from the host.
16
MSI_CTRL_STATUS_16
0x0
MSI is enabled. Fabric logic/MSS checks this RO
APB register to see if host has enabled MSI on the
PCIe bus.
[15:0]
MSI_CTRL_STATUS_15:0
0x0
This bits are hardwired to 0x7805.
Revision 3
79
PCI Express
PCIE_LTSSM Register (044h)
Table 3-35 • PCIE_LTSSM
Bit
Number
Name
Reset
Value
Description
[31:29]
LTSSM_31_29
0x0
Reserved
[28:24]
LTSSM_28_24
0x0
These bits set LTSSM state encoding (RO):
00000: Detect.quiet
00001: Detect.active
00010: Polling.active
00011: Polling.compliance
00100: Polling.configuration
00101: Reserved (ex polling.speed)
00110: Configuration.linkwidth.start
00111: Configuration.linkwidth.accept
01000: Configuration.lanenum.accept
01001: Configuration.lanenum.wait
01010: Configuration.complete
01011: Configuration.idle
01100: Recovery.RcvrLock
01101: Recovery.RcvrCfg
01110: Recovery.idle
01111: L0
10000: Disabled
10001: Loopback.entry
10010: Loopback.active
10011: Loopback.exit
10100: Hot reset
10101: L0s (transmit)
10110: L1.entry
10111: L1.Idle
11000: L2.idle
11001: L2.TransmitWake
11010: Recovery.speed
11011 - 11111: Reserved
[23:20]
LTSSM_23_20
0x0
Reserved
19
LTSSM_19
0x0
Forces compliance pattern (R/W).
18
LTSSM_18
0x0
Fully disables power management (R/W).
17
LTSSM_17
0x0
Sets master loopback (R/W).
16
LTSSM_16
0x0
Disables scrambling (R/W).
[15:2]
LTSSM_15_2
0x0
Reserved
1
LTSSM_1
0x0
Indicates if PME_TURN_OFF was received (RO).
0
LTSSM_0
0x0
Acknowledges PME_TURN_OFF (R/W).
80
R e visio n 3
RTG4 FPGA High-Speed Serial Interfaces
PCIE_POWER_MGT_CAPABILITY Register (048h)
Table 3-36 • PCIE_POWER_MGT_CAPABILITY
Bit
Number
Name
Reset
Value
[31:27]
POWER_MGT_CAPABILITY_31_27
0x0
These bits set PME support.
26
POWER_MGT_CAPABILITY_26
0x0
Sets D2 support. If this field is cleared,
PME_SUPPORT bit 29 must also be cleared.
25
POWER_MGT_CAPABILITY_25
0x0
Sets D1 support. If this field is cleared,
PME_SUPPORT bit 28 must also be cleared.
[24:22]
POWER_MGT_CAPABILITY_24_22
0x0
These bits set maximum current required.
21
POWER_MGT_CAPABILITY_21
0x0
Sets device specification initialization.
[20:19]
POWER_MGT_CAPABILITY_20_19
0x0
Reserved
18
POWER_MGT_CAPABILITY_18
0x0
Sets PCI power management interface specification
version; hardwired to 011b (PCIe Spec. v1.1)
[17:0]
POWER_MGT_CAPABILITY_17_0
0x0
Reserved
Description
PCIE_CFG_PMSCR Register (04Ch)
Table 3-37 • PCIE_CFG_PMSCR
Bit
Number
31:0
Name
CFG_PMSCR
Reset
Value
0x0
Description
Reports the current values of the PCIe IP core’s power
management control status register.
PCIE_AER_ECRC_CAPABILITY Register (050h)
Table 3-38 • PCIE_AER_ECRC_CAPABILITY
Bit
Number
Name
Reset
Value
Description
[31:3]
AER_ECRC_CAPABILITY_31_3
0x0
Reserved
2
AER_ECRC_CAPABILITY_2
0x0
Defines whether advanced error reporting (AER) is
implemented or not.
1
AER_ECRC_CAPABILITY_1
0x0
Defines ECRC generation.
0
AER_ECRC_CAPABILITY_0
0x0
Defines ECRC check.
PCIE_VC1_CAPABILITY Register (054h)
Table 3-39 • PCIE_VC1_CAPABILITY
Bit
Number
[31:0]
Name
Reserved
Reset
Value
0x0
Description
Reserved
Revision 3
81
PCI Express
PCIE_MAX_PAYLOAD_SIZE Register (058h)
Table 3-40 • MAX_PAYLOAD_SIZE
Bit
Number
Name
Reset
Value
Description
[31:3]
Reserved
0x0
Reserved
2:0
MAX_PAYLOAD_SIZE_2_0
0x0
Negotiated max payload size. The EP sets its own max
payload size to 2 KB:
000: 128 bytes
001: 256 bytes
010: 512 bytes
011: 1 Kbytes
100: 2 Kbytes
PCIE_ASPM_L0S_CAPABILITY Register (060h)
Table 3-41 • PCIE_ASPM_L0S_CAPABILITY
Bit
Number
Name
Reset
Value
Description
31
ASPM_L0S_CAPABILITY _31
0x0
NFTS_COMCLK in common clock mode
[23:16]
ASPM_L0S_CAPABILITY _23_16
0x0
NFTS_SPCLK in separated clock mode
[15:10]
ASPM_L0S_CAPABILITY _15_10
0x0
Reserved
[9:7]
ASPM_L0S_CAPABILITY _9_7
0x0
L0s exit latency for separate clock
[6:4]
ASPM_L0S_CAPABILITY _6_4
0x0
L0s exit latency for common clock
[3:1]
ASPM_L0S_CAPABILITY _3_1
0x0
EP L0s acceptable latency
0
ASPM_L0S_CAPABILITY _0
0x0
Reserved
PCIE_ASPM_L1_CAPABILITY Register (064h)
Table 3-42 • PCIE_ASPM_L1_CAPABILITY
Bit
Number
Name
Reset
Value
Description
[31:24]
ASPM_L1_CAPABILITY_31_24
0x0
NFTS_COMCLK in common clock mode at 5.0 Gbps
[23:16]
ASPM_L1_CAPABILITY_23_16
0x0
NFTS_SPCLK in independent clock mode at 5.0 Gbps
[15:4]
ASPM_L1_CAPABILITY_15_4
0x0
Reserved
[3:0]
ASPM_L1_CAPABILITY_3_0
0x0
Number of electrical idle exit (EIE) symbols sent before
transmitting the first FTS
82
R e visio n 3
RTG4 FPGA High-Speed Serial Interfaces
PCIE_TIMEOUT_COMPLETION Register (068Ch)
Table 3-43 • PCIE_TIMEOUT_COMPLETION
Bit
Number
Name
Reset
Value
Description
[31:4]
TIMEOUT_COMPLETION_31_4
0x0
Reserved
[3:0]
TIMEOUT_COMPLETION_3_0
0x0
Completion Timeout Ranges Supported – This field
indicates device Function support for the optional
Completion Timeout programmability mechanism. This
mechanism allows system software to modify the
Completion Timeout value.
Four time value ranges are defined:
Range A: 50 μs to 10 ms
Range B: 10 ms to 250 ms
Range C: 250 ms to 4 s
Range D: 4 s to 64 s
Bits are set according to the table below to show timeout
value ranges supported.
0000b Completion Timeout programming not supported.
–0000b is default setting. An error is not produced if a
completion does not come back.
0001b Range A
0010b Range B
0011b Ranges A and B
0110b Ranges B and C
0111b Ranges A, B, and C
1110b Ranges B, C and D
1111b Ranges A, B, C, and D
All other values are reserved.
Revision 3
83
PCI Express
PCIE_PM_DATA_SCALE_0 Register (070h)
Table 3-44 • PCIE_PM_DATA_SCALE_0
Bit
Number
Name
Reset
Value
Description
[31:24]
PM_DATA_SCALE_0_31_24
0x0
Set the register that defines Data3 of the PM data value of the
device for each possible power state defined by the PCI power
management specification, used in conjunction with the PM
scale field.
[23:16]
PM_DATA_SCALE_0_23_16
0x0
Set the register that defines Data2 of the PM data value of the
device for each possible power state defined by the PCI power
management specification, used in conjunction with the PM
scale field.
[15:8]
PM_DATA_SCALE_0_15_8
0x0
Set the register that defines Data1 of the PM data value of the
device for each possible power state defined by the PCI power
management specification, used in conjunction with the PM
scale field.
[7:0]
PM_DATA_SCALE_0_7_0
0x0
Set the register that defines Data0 of the PM data value of the
device for each possible power state defined by the PCI power
management specification, used in conjunction with the PM
scale field.
PCIE_PM_DATA_SCALE_1 Register (074h)
Table 3-45 • PCIE_PM_DATA_SCALE_1
Bit
Number
Name
Reset
Value
Description
[31:24]
PM_DATA_SCALE_1_31_24
0x0
Set the register that defines Data7 of the PM data value of the
device for each possible power state defined by the PCI power
management specification, used in conjunction with the PM
scale field.
[23:16]
PM_DATA_SCALE_1_23_16
0x0
Set the register that defines Data6 of the PM data value of the
device for each possible power state defined by the PCI power
management specification, used in conjunction with the PM
scale field.
[5:8]
PM_DATA_SCALE_1_15_8
0x0
Set the register that defines Data5 of the PM data value of the
device for each possible power state defined by the PCI power
management specification, used in conjunction with the PM
scale field.
[7:0]
PM_DATA_SCALE_1_7_0
0x0
Set the register that defines Data4 of the PM data value of the
device for each possible power state defined by the PCI power
management specification, used in conjunction with the PM
scale field.
84
R e visio n 3
RTG4 FPGA High-Speed Serial Interfaces
PCIE_PM_DATA_SCALE_2 Register (078h)
Table 3-46 • PCIE_PM_DATA_SCALE_2
Bit
Number
Name
Reset
Value
Description
[31:26]
PM_DATA_SCALE_2_31_26
0x0
Reserved
[25:24]
PM_DATA_SCALE_2_25_24
0x0
Set the register that defines data scale 3 of the PM data
value of the device for each possible power state defined
by the PCI power management specification, used in
conjunction with the PM scale field.
[23:18]
PM_DATA_SCALE_2_23_18
0x0
Reserved
[17:16]
PM_DATA_SCALE_2_17_16
0x0
Set the register that defines data scale 2 of the PM data
value of the device for each possible power state defined
by the PCI power management specification, used in
conjunction with the PM scale field.
[15:10]
PM_DATA_SCALE_2_15_10
0x0
Reserved
[9:8]
PM_DATA_SCALE_2_9_8
0x0
Set the register that defines data scale 1 of the PM data
value of the device for each possible power state defined
by the PCI power management specification, used in
conjunction with the PM scale field.
[7:2]
PM_DATA_SCALE_2_7_2
0x0
Reserved
[1:0]
PM_DATA_SCALE_2_1_0
0x0
Set the register that defines data scale 0 of the PM data
value of the device for each possible power state defined
by the PCI power management specification, used in
conjunction with the PM scale field.
Revision 3
85
PCI Express
PCIE_PM_DATA_SCALE_3 Register (07Ch)
Table 3-47 • PCIE_PM_DATA_SCALE_3
Bit
Number
Name
Reset
Value
Description
[31:26]
PM_DATA_SCALE_3_31_26
0x0
Reserved
[25:24]
PM_DATA_SCALE_3_25_24
0x0
Set the register that defines data scale 7 of the PM data
value of the device for each possible power state defined
by the PCI power management specification, used in
conjunction with the PM scale field.
[23:18]
PM_DATA_SCALE_3_23_18
[17:16]
PM_DATA_SCALE_3_17_16
0x0
Set the register that defines data scale 6 of the PM data
value of the device for each possible power state defined
by the PCI power management specification, used in
conjunction with the PM scale field.
[15:10]
PM_DATA_SCALE_3_15_10
0x0
Reserved
[9:8]
PM_DATA_SCALE_3_9_8
0x0
Set the register that defines data scale 5 of the PM data
value of the device for each possible power state defined
by the PCI power management specification, used in
conjunction with the PM scale field.
[7:2]
PM_DATA_SCALE_3_7_2
0x0
Reserved
[1:0]
PM_DATA_SCALE_3_1_0
0x0
Set the register that defines data scale 4 of the PM data
value of the device for each possible power state defined
by the PCI power management specification, used in
conjunction with the PM scale field.
Reserved
PCIE_MSI_0 Register (080h)
Table 3-48 • PCIE_MSI_0
Bit
Number
Name
Reset
Value
Description
[31:27]
MSI0_31_27
0x0
These bits set MSI_Offset[4] of MSI_MAP0.
[26:24]
MSI0_26_24
0x0
These bits set MSI_TC[4] of MSI_MAP0.
[23:19]
MSI0_23_19
0x0
These bits set MSI_Offset[3] of MSI_MAP0.
[18:16]
MSI0_18_16
0x0
These bits set MSI_TC[3] of MSI_MAP0.
[15:11]
MSI0_15_11
0x0
These bits set MSI_Offset[2] of MSI_MAP0.
[10:8]
MSI0_10_8
0x0
These bits set MSI_TC[2] of MSI_MAP0.
[7:3]
MSI0_7_3
0x0
These bits set MSI_Offset[1] of MSI_MAP0.
[2:0]
MSI0_2_0
0x0
These bits set MSI_TC[1] of MSI_MAP0.
86
R e visio n 3
RTG4 FPGA High-Speed Serial Interfaces
PCIE_ERROR_COUNTER_0 Register (0A0h)
Table 3-49 • PCIE_ERROR_COUNTER_0
Bit
Number
Name
Reset
Value
Description
[31:24]
ERROR_COUNTER0_31_24
0x0
8-bit counter that reports the following error source: 
A3: DLLP error
[23:16]
ERROR_COUNTER0_23_16
0x0
8-bit counter that reports the following error source: 
A2: TLP error
[15:8]
ERROR_COUNTER0_15_8
0x0
8-bit counter that reports the following error source: 
A1: Training error (not supported)
[7:0]
ERROR_COUNTER0_7_0
0x0
8-bit counter that reports the following error source: 
A0: Receiver port error
PCIE_ERROR_COUNTER_1 Register (0A4h)
Table 3-50 • PCIE_ERROR_COUNTER_1
Bit
Number
Name
Reset
Value
Description
[31:24]
ERROR_COUNTER1_31_24
0x0
8-bit counter that reports the following error source: 
A7: Poisoned TLP received error
[23:16]
ERROR_COUNTER1_23_16
0x0
8-bit counter that reports the following error source: 
A6: Data link layer protocol error
[15:8]
ERROR_COUNTER1_15_8
0x0
8-bit counter that reports the following error source: 
A5: Replay number rollover error
[7:0]
ERROR_COUNTER1_7_0
0x0
8-bit counter that reports the following error source: 
A4: Replay time error
PCIE_ERROR_COUNTER_2 Register (0A8h)
Table 3-51 • PCIE_ERROR_COUNTER_2
Bit
Number
Name
Reset
Value
Description
[31:24]
ERROR_COUNTER2_31_24
0x0
8-bit counter that reports the following error source: 
AB: Completer abort error
[23:16]
ERROR_COUNTER2_23_16
0x0
8-bit counter that reports the following error source: 
AA: Completion timeout error
[15:8]
ERROR_COUNTER2_15_8
0x0
8-bit counter that reports the following error source: 
A9: Unsupported request error
[7:0]
ERROR_COUNTER2_7_0
0x0
8-bit counter that reports the following error source: 
A8: ECRC error
Revision 3
87
PCI Express
PCIE_ERROR_COUNTER_3 Register (0ACh)
Table 3-52 • PCIE_ERROR_COUNTER_3
Bit
Number
Name
Reset
Value
Description
[31:14]
ERROR_COUNTER3_31_24
0x0
8-bit counter that reports the following error source:
AF: Malformed TLP error
[23:16]
ERROR_COUNTER3_23_16
0x0
8-bit counter that reports the following error source: 
AE: Flow control protocol error
[15:8]
ERROR_COUNTER3_15_8
0x0
8-bit counter that reports the following error source:
AD: Receiver overflow error
[7:0]
ERROR_COUNTER3_7_0
0x0
8-bit counter that reports the following error source:
AC: Unexpected completion error
PCIE_CREDIT_ALLOCATION_0 Register(0B0h)
Table 3-53 • PCIE_CREDIT_ALLOCATION_0
Bit
Number
Name
Reset
Value
Description
[31:28]
CREDIT_ALLOCATION0_31_28
0x0
Reserved
[27:16]
CREDIT_ALLOCATION0_27_16
0x0
VC0 posted header/data credit pd_cred0
[15:8]
CREDIT_ALLOCATION0_15_8
0x0
Reserved
[7:0]
CREDIT_ALLOCATION0_7_0
0x0
VC0 posted header/data credit ph_cred0
PCIE_CREDIT_ALLOCATION_1 Register (0B4h)
Table 3-54 • PCIE_CREDIT_ALLOCATION_1
Bit
Number
Name
Reset
Value
Description
[31:28]
CREDIT_ALLOCATION1_31_28
0x0
Reserved
[27:16]
CREDIT_ALLOCATION1_27_16
0x0
VC0 non-posted header/data credit npd_cred0
[15:8]
CREDIT_ALLOCATION1_15_8
0x0
Reserved
[7:0]
CREDIT_ALLOCATION1_7_0
0x0
VC0 non-posted header/data credit nph_cred0
PCIE_AXI_SLAVE_WINDOW0_0 Register (0C0h)
Table 3-55 • PCIE_AXI_SLAVE_WINDOW0_0
Bit
Number
Name
Reset
Value
Description
[31:12]
PCIE_AXI_SLAVE_WINDOW00_31_12
0x0
Base address AXI3 slave window 0
[11:0]
Reserved
0x0
Reserved
88
R e visio n 3
RTG4 FPGA High-Speed Serial Interfaces
PCIE_AXI_SLAVE_WINDOW0_1 Register (0C4h)
Table 3-56 • PCIE_AXI_SLAVE_WINDOW0_1
Bit
Number
Reset
Value
Name
Description
[31:12]
PCIE_AXI_SLAVE_WINDOW0_1_31_12
0x0
Size of AXI3 Slave window 0
[11:1]
Reserved
0x0
Reserved
0
PCIE_AXI_SLAVE_WINDOW0_1_0
0x0
Enable bit of AXI3 slave window 0
PCIE_AXI_SLAVE_WINDOW0_2 Register (0C8h)
Table 3-57 • PCIE_AXI_SLAVE_WINDOW0_2
Bit
Number
Name
Reset
Value
Description
[31:12]
PCIE_AXI_SLAVE_WINDOW0_2_31_12
0x0
LSB of base address PCIe window 0
[11:5]
Reserved
0x0
Reserved
[4:2]
PCIE_AXI_SLAVE_WINDOW0_2_4_2
0x0
AXI3 slave window 0 traffic class (TC)
1
PCiE_AXI_SLAVE_WINDOW0_2_1
0x0
AXI3 Slave window 0 relaxed ordering (RO)
0
PCIE_AXI_SLAVE_WINDOW0_2_0
0x0
AXI3 Slave window 0 no snoop (NS)
PCIE_AXI_SLAVE_WINDOW0_3 Register (0CCh)
Table 3-58 • PCIE_AXI_SLAVE_WINDOW0_3
Bit
Number
[31:0]
Name
PCIE_AXI_SLAVE_WINDOW0_3_31_0
Reset
Value
0x0
Description
MSB of base address PCIe window 0
PCIE_AXI_SLAVE_WINDOW1_0 Register (0D0h)
Table 3-59 • PCIE_AXI_SLAVE_WINDOW1_0
Bit
Number
Name
Reset
Value
Description
[31:12]
PCIE_AXI_SLAVE_WINDOW1_0_31_12
0x0
Base address AXI3 slave window 1
[11:0]
Reserved
0x0
Reserved
PCIE_AXI_SLAVE_WINDOW1_1 Register (0D4h)
Table 3-60 • PCIE_AXI_SLAVE_WINDOW1_1
Bit
Number
Name
Reset
Value
Description
[31:12]
PCIE_AXI_SLAVE_WINDOW1_1_31_12
0x0
Size of AXI3 slave window 1
[11:1]
Reserved
0x0
Reserved
0
PCIE_AXI_SLAVE_WINDOW1_1_0
0x0
Enable bit of AXI3 slave window 1
Revision 3
89
PCI Express
PCIE_AXI_SLAVE_WINDOW1_2 Register (0D8h)
Table 3-61 • PCIE_AXI_SLAVE_WINDOW1_2
Bit
Number
Reset
Value
Name
Description
[31:12]
PCIE_AXI_SLAVE_WINDOW1_2_31_12
0x0
LSB of base address PCIe window 1
[11:5]
Reserved
0x0
Reserved
[4:2]
PCIE_AXI_SLAVE_WINDOW1_2_4_2
0x0
AXI3 slave window 0 traffic class (TC)
1
PCIE_AXI_SLAVE_WINDOW1_2_1
0x0
AXI3 slave window 0 relaxed ordering (RO)
0
PCIE_AXI_SLAVE_WINDOW1_2_0
0x0
AXI3 slave window 0 no snoop (NS)
PCIE_AXI_SLAVE_WINDOW1_3 Register (0DCh)
Table 3-62 • PCIE_AXI_SLAVE_WINDOW1_3
Bit
Number
[31:0]
Name
PCIE_AXI_SLAVE_WINDOW1_3_31_0
Reset
Value
0x0
Description
MSB of base address PCIe window 1
PCIE_AXI_SLAVE_WINDOW2_0 Register (0E0h)
Table 3-63 • PCIE_AXI_SLAVE_WINDOW2_0
Bit
Number
Name
Reset
Value
Description
[31:12]
PCIE_AXI_SLAVE_WINDOW2_0_31_12
0x0
Base address AXI3 slave window 2
[11:0]
Reserved
0x0
Reserved
PCIE_AXI_SLAVE_WINDOW2_1 Register (0E4h)
Table 3-64 • PCIE_AXI_SLAVE_WINDOW2_1
Bit
Number
Name
Reset
Value
Description
[31:12]
PCIE_AXI_SLAVE_WINDOW2_1_31_12
0x0
Size of AXI3 slave window 2
[11:1]
Reserved
0x0
Reserved
0
PCIE_AXI_SLAVE_WINDOW2_1_0
0x0
Enable bit of AXI3 slave window 2
PCIE_AXI_SLAVE_WINDOW2_2 Register (0E8h)
Table 3-65 • PCIE_AXI_SLAVE_WINDOW2_2
Bit
Number
Name
Reset
Value
Description
[31:12]
PCIE_AXI_SLAVE_WINDOW2_2_31_12
0x0
LSB of base address PCIe window 2
[11:5]
Reserved
0x0
Reserved
[4:2]
PCIE_AXI_SLAVE_WINDOW2_2_4_2
0x0
AXI3 slave window 0 traffic class (TC)
1
PCIE_AXI_SLAVE_WINDOW2_2_1
0x0
AXI3 slave window 0 relaxed ordering (RO)
0
PCIE_AXI_SLAVE_WINDOW2_2_0
0x0
AXI3 slave window 0 no snoop (NS)
90
R e visio n 3
RTG4 FPGA High-Speed Serial Interfaces
PCIE_AXI_SLAVE_WINDOW2_3 Register (0ECh)
Table 3-66 • PCIE_AXI_SLAVE_WINDOW2_3
Bit
Number
[31:0]
Reset
Value
Name
PCIE_AXI_SLAVE_WINDOW2_3_31_0
0x0
Description
MSB of base address PCIe window 3
PCIE_AXI_SLAVE_WINDOW3_0 Register (0F0h)
Table 3-67 • PCIE_AXI_SLAVE_WINDOW3_0
Bit
Number
Reset
Value
Name
Description
[31:12]
PCIE_AXI_SLAVE_WINDOW3_0_31_12
0x0
Base address AXI3 slave window 3
[11:0]
Reserved
0x0
Reserved
PCIE_AXI_SLAVE_WINDOW3_1 Register (0F4h)
Table 3-68 • PCIE_AXI_SLAVE_WINDOW3_1
Bit
Number
Reset
Value
Name
Description
[31:12]
PCIE_AXI_SLAVE_WINDOW3_1_31_12
0x0
Size of AXI3 slave window 3
[11:1]
Reserved
0x0
Reserved
0
PCIE_AXI_SLAVE_WINDOW3_1_0
0x0
Enable bit of AXI3 slave window 3
PCIE_AXI_SLAVE_WINDOW3_2 Register (0F8h)
Table 3-69 • PCIE_AXI_SLAVE_WINDOW3_2
Bit
Number
Reset
Value
Name
Description
[31:12]
PCIE_AXI_SLAVE_WINDOW3_2_31_12
0x0
LSB of base address PCIe window 3
[11:5]
Reserved
0x0
Reserved
[4:2]
PCIE_AXI_SLAVE_WINDOW3_2_4_2
0x0
AXI3 slave window 0 traffic class (TC)
1
PCIE_AXI_SLAVE_WINDOW3_2_1
0x0
AXI3 Slave window 0 relaxed ordering (RO)
0
PCIE_AXI_SLAVE_WINDOW3_2_0
0x0
AXI3 Slave window 0 no snoop (NS)
PCIE_AXI_SLAVE_WINDOW3_3 Register (0FCh)
Table 3-70 • PCIE_AXI_SLAVE_WINDOW3_3
Bit
Number
[31:0]
Reset
Value
Name
PCIE_AXI_SLAVE_WINDOW3_3_31_0
0x0
Description
MSB of base address PCIe window 0
PCIE_AXI_MASTER_WINDOW0_0 Register (100h)
Table 3-71 • PCIE_AXI_MASTER_WINDOW0_0
Bit
Number
Name
Reset
Value
[31:12]
PCIE_AXI_MASTER_WINDOW0_0_31_12
0x0
Base address AXI3 master window 0
[11:0]
Reserved
0x0
Reserved
Revision 3
Description
91
PCI Express
PCIE_AXI_MASTER_WINDOW0_1 Register (104h)
Table 3-72 • PCIE_AXI_MASTER_WINDOW0_1
Bit
Number
Name
Reset
Value
[31:12]
PCIE_AXI_MASTER_WINDOW0_1_31_12
0x0
Size of AXI3 master window 0
[11:1]
Reserved
0x0
Reserved
0
PCIE_AXI_MASTER_WINDOW0_1_0
Description
Enable bit of AXI3 master window 0
PCIE_AXI_MASTER_WINDOW0_2 Register (108h)
Table 3-73 • PCIE_AXI_MASTER_WINDOW0_2
Bit
Number
Reset
Value
Name
Description
[31:12]
PCIE_AXI_MASTER_WINDOW0_2_31_12
0x0
LSB of base address PCIe window 0
[11:6]
Reserved
0x0
Reserved
[5:0]
PCIE_AXI_MASTER_WINDOW0_2_5_0
0x0
These bits set the BAR. To select a BAR, set the
following values:
0x01: BAR0 (32-bit BAR) or BAR0/1 (64-bit BAR)
0x02: BAR1 (32-bit BAR) only
0x04: BAR2 (32-bit BAR) or BAR2/3 (64-bit BAR)
0x08: BAR3 (32-bit BAR) only
0x10: BAR4 (32-bit BAR) or BAR4/5 (64-bit BAR)
0x20: BAR5 (32-bit BAR) only
PCIE_AXI_MASTER_WINDOW0_3 Register (10Ch)
Table 3-74 • PCIE_AXI_MASTER_WINDOW0_3
Bit
Number
[31:0]
Reset
Value
Name
PCIE_AXI_MASTER_WINDOW0_3_31_0
0x0
Description
MSB of base address PCIe window 0
PCIE_AXI_MASTER_WINDOW1_0 Register (110h)
Table 3-75 • PCIE_AXI_MASTER_WINDOW1_0
Bit
Number
Name
Reset
Value
[31:12]
PCIE_AXI_MASTER_WINDOW1_0_31_12
0x0
Base address AXI3 master window 1
[11:0]
Reserved
0x0
Reserved
Description
PCIE_AXI_MASTER_WINDOW1_1 Register (114h)
Table 3-76 • PCIE_AXI_MASTER_WINDOW1_1
Bit
Number
Name
Reset
Value
[31:12]
PCIE_AXI_MASTER_WINDOW1_1_31_12
0x0
Size of AXI3 master window 1
[11:1]
Reserved
0x0
Reserved
0
PCIE_AXI_MASTER_WINDOW1_1_0
0x0
Enable bit of AXI3 master window 1
92
R e visio n 3
Description
RTG4 FPGA High-Speed Serial Interfaces
PCIE_AXI_MASTER_WINDOW1_2 Register (118h)
Table 3-77 • PCIE_AXI_MASTER_WINDOW1_2
Bit
Number
Reset
Value
Name
Description
[31:12]
PCIE_AXI_MASTER_WINDOW1_2_31_12
0x0
LSB of base address PCIe window 1
[11:6]
Reserved
0x0
Reserved
[5:0]
PCIE_AXI_MASTER_WINDOW1_2_5_0
0x0
These bits set the BAR. To select a BAR, set
the following values:
0x01: BAR0 (32-bit BAR) or BAR0/1 (64-bit
BAR)
0x02: BAR1 (32-bit BAR) only
0x04: BAR2 (32-bit BAR) or BAR2/3 (64-bit
BAR)
0x08: BAR3 (32-bit BAR) only
0x10: BAR4 (32-bit BAR) or BAR4/5 (64-bit
BAR)
0x20: BAR5 (32-bit BAR) only
PCIE_AXI_MASTER_WINDOW1_3 Register (11Ch)
Table 3-78 • PCIE_AXI_MASTER_WINDOW1_3
Bit
Number
[31:0]
Reset
Value
Name
PCIE_AXI_MASTER_WINDOW1_3_31_0
0x0
Description
MSB of base address PCIe window 1
PCIE_AXI_MASTER_WINDOW2_0 Register (120h)
Table 3-79 • PCIE_AXI_MASTER_WINDOW2_0
Bit
Number
Reset
Value
Name
Description
[31:12]
PCIE_AXI_MASTER_WINDOW2_0_31_12
0x0
Base address AXI3 master window 2
[11:0]
Reserved
0x0
Reserved
PCIE_AXI_MASTER_WINDOW2_1 Register (124h)
Table 3-80 • PCIE_AXI_MASTER_WINDOW2_1
Bit
Number
Reset
Value
Name
Description
[31:12]
PCIE_AXI_MASTER_WINDOW2_1_31_12
0x0
Size of AXI3 master window 2
[11:1]
Reserved
0x0
Reserved
0
PCIE_AXI_MASTER_WINDOW2_1_0
0x0
Enable bit of AXI3 master window 2
Revision 3
93
PCI Express
PCIE_AXI_MASTER_WINDOW2_2 Register (128h)
Table 3-81 • PCIE_AXI_MASTER_WINDOW2_2
Bit
Number
Reset
Value
Name
Description
[31:12]
PCIE_AXI_MASTER_WINDOW2_2_31_12
0x0
LSB of base address PCIe window 2
[11:6]
Reserved
0x0
Reserved
[5:0]
PCIE_AXI_MASTER_WINDOW2_2_5_0
0x0
These bits set the BAR. To select a BAR, set the
following values:
0x01: BAR0 (32-bit BAR) or BAR0/1 (64-bit BAR)
0x02: BAR1 (32-bit BAR) only
0x04: BAR2 (32-bit BAR) or BAR2/3 (64-bit BAR)
0x08: BAR3 (32-bit BAR) only
0x10: BAR4 (32-bit BAR) or BAR4/5 (64-bit BAR)
0x20: BAR5 (32-bit BAR) only
PCIE_AXI_MASTER_WINDOW2_3 Register (12Ch)
Table 3-82 • PCIE_AXI_MASTER_WINDOW2_3
Bit
Number
[31:0]
Reset
Value
Name
PCIE_AXI_MASTER_WINDOW2_3_31_0
0x0
Description
MSB of base address PCIe window 3
AXI_MASTER_WINDOW3_0 Register (130h)
Table 3-83 • PCIE_AXI_MASTER_WINDOW3_0
Bit
Number
[31:0]
Reset
Value
Name
PCIE_AXI_MASTER_WINDOW3_0_31_0
0x0
Description
Base address AXI3 master window 3
PCIE_AXI_MASTER_WINDOW3_1 Register (134h)
Table 3-84 • PCIE_AXI_MASTER_WINDOW3_1
Bit
Number
Name
Reset
Value
[31:12]
PCIE_AXI_MASTER_WINDOW3_1_31_12
0x0
Size of AXI3 master window 3
[11:1]
Reserved
0x0
Reserved
0
PCIE_AXI_MASTER_WINDOW3_1_0
0x0
Enable bit of AXI3 master window 3
94
R e visio n 3
Description
RTG4 FPGA High-Speed Serial Interfaces
PCIE_AXI_MASTER_WINDOW3_2 Register (138h)
Table 3-85 • PCIE_AXI_MASTER_WINDOW3_2
Bit
Number
Reset
Value
Name
Description
[31:12]
PCIE_AXI_MASTER_WINDOW3_2_31_12
0x0
LSB of base address PCIe window 3
[11:5]
Reserved
0x0
Reserved
[5:0]
PCIE_AXI_MASTER_WINDOW3_2_5_0
0x0
These bits set the BAR. To select a BAR, set the
following values:
0x01: BAR0 (32-bit BAR) or BAR0/1 (64-bit BAR)
0x02: BAR1 (32-bit BAR) only
0x04: BAR2 (32-bit BAR) or BAR2/3 (64-bit BAR)
0x08: BAR3 (32-bit BAR) only
0x10: BAR4 (32-bit BAR) or BAR4/5 (64-bit BAR)
0x20: BAR5 (32-bit BAR) only
PCIE_AXI_MASTER_WINDOW3_3 Register (13Ch)
Table 3-86 • PCIE_AXI_MASTER_WINDOW3_3
Bit
Number
Name
Reset
Value
[31:12]
PCIE_AXI_MASTER_WINDOW3_3_31_12
0x0
MSB of base address PCIe window 0
[11:0]
Reserved
0x0
Reserved
Description
PCIE_INFO Register (016Ch)
Table 3-87 • PCIE_INFO
Bit
Number
Reset
Value
Name
Description
[31:12]
INFO_31_12
0x0
Bridge version
[11:0]
INFO_11_0
0x0
Reserved
RESERVED Register (204h)
Table 3-88 • RESERVED
Bit
Number
[31:0]
Name
Reserved
Reset
Value
0x0
Description
Reserved
PCIE_DEV2SCR Register (230h)
Table 3-89 • PCIE_DEV2SCR
Bit
Number
[31:0]
Name
Reset
Value
PCIE_DEV2SCR_31_0
0x0
Description
Reports the current value of the PCIe device control and status register.
It can be monitored by the local processor when relaxed ordering and
no snoop bits are enabled in the system.
Revision 3
95
PCI Express
PCIE_LINK2SCR Register (234h)
Table 3-90 • PCIE_LINK2SCR
Bit
Number
[31:0]
Name
Reset
Value
PCIE_INK2SCR_31_0
0x0
Description
Reports the current value of the PCIe Link Control and Status register. It
can be monitored by the local processor when Relaxed Ordering and
No Snoop bits are enabled in the system.
RESERVED Register (260h)
Table 3-91 • RESERVED
Bit
Number
[31:0]
Name
Reserved
Reset
Value
0x0
Description
Reserved
PCIe Configuration Space
The PCIe base IP core transaction layer (TL) contains the 4 Kbyte configuration space. The configuration
space implements all configuration registers and associated functions. It manages BAR and window
decoding, interrupt/MSI message generation, power management negotiation, and error handling. For
upstream ports, the configuration space is accessed through the PCIe link using Type 0 requests. Type 1
requests are forwarded to the application layer. For downstream ports, the configuration space is
accessed through the application interface using Type 0 requests. Type 1 requests are forwarded to the
PCIe link. The first 256 bytes of the configuration space are the function’s configuration space, and the
remaining configuration space is PCIe extended configuration space (see Figure 3-19).
FFFh
Extended
Configuration
Space
for PCI Express
parameters and
capabilities (not
available on legacy
operating systems)
PCI Express
Extended
Configuration
Space
(not visible on
legacy operating
systems)
PCI Express
Capability Structure
Capabioity needed
by BIOS or by
driver software on
non PCI Express
aware operating
systems
0FFh
PCI Configuration
Space (available on
legacy operating
systems through
legacy PCI
mechanisms)
03Fh
PCI 3.0 Compatible
Configuration Space
Header
000h
Figure 3-19 • PCIe Configuration Space
96
R e visio n 3
RTG4 FPGA High-Speed Serial Interfaces
Common Configuration Space Header
Table 3-92 shows the common configuration space header. The PCIe common configuration space
includes the following registers:
•
Type 0 configuration settings
•
MSI capability structure
•
Power management capability structure
•
PCIe capability structure
For comprehensive information about these registers, refer to PCIe Base Specification Revision 1.0a, 1.1
or 2.0 specifications.
Table 3-92 • Configuration Inputs for AHBL/AXI3 to AXI3 Bridge
31:24
23:16
15:8
7:0
TYPE 0 configuration registers
Byte Offset
000h...03Ch
Reserved
040h
Core Version Register
044h
Reserved
048h...04Ch
MSI capability structure
050...05Ch
Reserved
060h...064h
Power management capability structure
078...07Ch
PCIe capability structure
080h...0BCh
Reserved
0C8h...0FCh
PCIe Extended Capability Structure
Table 3-93 shows the PCIe extended capability structure. RTG4 PCIe common configuration space
includes the following registers:
•
PCIe advanced error reporting (AER) extended capability structure
Table 3-93 • PCIe Extended Capability Structure (Function 0)
31:24
23:16
15:8
7:0
AER
Byte Offset
800h.834h
Revision 3
97
PCI Express
Type 0 Configuration Settings
Table 3-94 shows the type 0 configuration settings.
Table 3-94 • Type 0 Configuration Register
31:24
23:16
15:8
7:0
Device ID
Vendor ID
000h
Status
Command
004h
Class Code
BIST
Byte Offset
Header Type
Latency Timer
Revision ID
008h
Cache Line Size
00Ch
Base address 0
010h
Base address 1
014h
Base address 2
018h
Base address 3
01Ch
Base address 4
020h
Base address 5
024h
Reserved
028h
Subsystem ID
Subsystem Vendor ID
02Ch
RESERVED
030h
Capabilities PTR
Reserved
034h
038h
Int. pin
Int. line
03Ch
IP Core Status Register
Table 3-95 illustrates the content of the IP Core Status Register.
Table 3-95 • IP Core Status Register
31:28
Reserved
27:16
15:4
3:0
Core version
Signature
Reserved
MSI Capability Structure
Table 3-96 illustrates the content of the MSI capability structure.
Table 3-96 • MSI Capability Structure Register
31:24
23:16
Message control
Reserved
98
15:8
7:0
Byte Offset
Next pointer
Cap ID
050h
Message address
054h
Message upper address
058h
Reserved
Message data
R e visio n 3
05Ch
RTG4 FPGA High-Speed Serial Interfaces
Power Management Capability Structure
Table 3-97 illustrates the content of the power management capability structure.
Table 3-97 • Power Management Capability Structure
31:24
23:16
Capabilities register
Data
PM control/status
15:8
7:0
Byte Offset
Next cap PTR
Cap ID
078h
Power management status and control
07Ch
bridge extensions
PCIe Capability Structure
Table 3-98 illustrates the content of the PCIe capability structure.
Table 3-98 • PCIe Capability Structure Register
31:24
23:16
Capabilities register
15:8
7:0
Byte Offset
Next cap PTR
cap ID
080h
Device capabilities
Device status
084h
Device control
Link capabilities
Link status
088h
08Ch
Link control
Slot capabilities
090h
094h
Slot status
Slot control
098h
Reserved
Root control
09Ch
Root status
0A0h
Device capabilities 2
0A4h
Device status 2
Device control 2
Link capabilities 2
Link status 2
0ACh
Link control 2
Revision 3
0A8h
0B0h
99
PCI Express
PCIe AER Extended Capability Structure
Table 3-99 shows the advanced error reporting (AER) extended capability structure for Function 0. For
Functions 1 - 7, the byte offset is from 100h to 134h.
Table 3-99 • PCIe AER Extended Capability Structure
31:24
23:16
15:8
7:0
Byte Offset
PCIe enhanced capability header
800h
Uncorrectable error status register
804h
Uncorrectable error mask register
808h
Uncorrectable error severity register
80Ch
Correctable error status register
810h
Correctable error mask register
814h
Advanced error capabilities and control register
818h
Header log register
81Ch
Root error command
82Ch
Root error status
830h
Error source identification register
Correctable error source ID register
834h
TLP Contents
The following tables describe the contents of all TLPs. Please note that bit assignments are mapped with
the MSB in the top-left and the LSB in the bottom-right of the tables.
C.1 Content of a TLP without a Data Payload
Table 3-100 • Memory Read Request 32-bit Addressing Descriptor Format
+0
+1
+2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
Byte 0
0 0 0 0 0 0 0 0 0 TC
Byte 4
Requester ID
Byte 8
Address [31:2]
Byte 12
Reserved
+3
6
5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 0 0 0 TD EP Attr
0 0 Length
Tag
Last BE
First BE
0 0
Table 3-101 • Memory Read Request-Locked 32-bit Addressing Descriptor Format
+0
+1
+2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
Byte 0
0 0 0 0 0 0 0 1 0 TC
Byte 4
Requester ID
Byte 8
Address [31:2]
Byte 12
Reserved
+3
6
5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 0 0 0 TD EP Attr
Tag
0 0 Length
Last BE
0 0
Table 3-102 • Memory Read Request 64-bit Addressing Descriptor Format
+0
100
First BE
+1
+2
R e vi s i o n 3
+3
RTG4 FPGA High-Speed Serial Interfaces
Table 3-102 • Memory Read Request 64-bit Addressing Descriptor Format
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
Byte 0
0 0 1 0 0 0 0 0 0 TC
Byte 4
Requester ID
Byte 8
Address [63:32]
Byte 12
Address [31:2]
6
5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 0 0 0 TD EP Attr
0 0 Length
Tag
Last BE
First BE
0 0
Table 3-103 • Memory Read Request-Locked 64-bit Addressing Descriptor Format
+0
+1
+2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
Byte 0
0 0 1 0 0 0 0 1 0 TC
Byte 4
Requester ID
Byte 8
Address[63:32]
Byte 12
Address [31:2]
+3
6
5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 0 0 0 TD EP Attr
0 0 Length
Tag
Last BE
First BE
0 0
Table 3-104 • Type 0 Configuration Read Request Descriptor Format
+0
+1
+2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
+3
6
5 4 3 2 1 0 7 6 5 4 3 2 1 0
Byte 0
0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 TD EP 0 0
Byte 4
Requester ID
Byte 8
Bus Number
Byte 12
R
0 0 0 0 0 0 0 0 0 0 0 1
Tag
Device Nb.
Func
0
0 0 0 0 First BE
0
0 0 Ext. Reg.
Register Nb.
0 0
Table 3-105 • Type 0 Configuration Read Request Descriptor Format
+0
+1
+2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
+3
6
5 4 3 2 1 0 7 6 5 4 3 2 1 0
Byte 0
0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 TD EP 0 0
Byte 4
Requester ID
Byte 8
Bus Number
Byte 12
R
0 0 0 0 0 0 0 0 0 0 0 1
Tag
Device Nb.
Func
0
0000
0
0 0 Ext. Reg.
First BE
Register Nb.
0 0
Table 3-106 • Message (without data) Descriptor Format
+0
+1
+2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
Byte 0
0 0 1 1 0 r r r 0 TC
2 1 0
Byte 4
Requester ID
Byte 8
Vendor defined or all zeros
Byte 12
Vendor defined or all zeros
+3
6
5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 0 0 0 TD EP 0 0
Tag
Revision 3
0 0 0 0 0 0 0 0 0 0 0 0
Message Code
101
PCI Express
Table 3-107 • Completion (without data) Descriptor Format
+0
+1
+2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
+3
6
Byte 0
0 0 0 0 1 0 1 0 0 TC
Byte 4
Completer ID
Status
Byte 8
Requester ID
Tag
Byte 12
R
5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 0 0 0 TD EP Attr
0 0 Length
B Byte Count
0 Lower Address
Table 3-108 • Completion Locked (without data) Descriptor Format
+0
+1
+2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
+3
6
Byte 0
0 0 0 0 1 0 1 1 0 TC
Byte 4
Completer ID
Status
Byte 8
Requester ID
Tag
5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 0 0 0 TD EP Attr
0 0 Length
B Byte Count
0 Lower Address
Byte 12
C.2 Content of a TLP with a Data Payload
Table 3-109 • Memory Write Request 32-bit Addressing Descriptor Format
+0
+1
+2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
Byte 0
0 1 0 0 0 0 0 0 0 TC
Byte 4
Requester ID
Byte 8
Address [31:2]
Byte 12
R
+3
6
5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 0 0 0 TD EP Attr
0 0 Length
Tag
Last BE
First BE
0 0
Table 3-110 • Memory Write Request 64-bit Addressing Descriptor Format
+0
+1
+2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
Byte 0
0 1 1 0 0 0 0 0 0 TC
Byte 4
Requester ID
Byte 8
Address [63:32]
Byte 12
Address [31:2]
+3
6
5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 0 0 0 TD EP Attr
0 0 Length
Tag
Last BE
First BE
0 0
Table 3-111 • Type 0 Configuration Write Request Descriptor Format
+0
+1
+2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
+3
6
5 4 3 2 1 0 7 6 5 4 3 2 1 0
Byte 0
0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 TD EP 0 0
Byte 4
Requester ID
Byte 8
Bus Number
Byte 12
R
102
0 0 0 0 0 0 0 0 0 0 0 1
Tag
Device Nb.
Func
0
R e vi s i o n 3
0 0 0 0 First BE
0
0 0 Ext. Reg.
Register Nb.
0 0
RTG4 FPGA High-Speed Serial Interfaces
Table 3-112 • Type 0 Configuration Write Request Descriptor Format
+0
+1
+2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
+3
6
5 4 3 2 1 0 7 6 5 4 3 2 1 0
Byte 0
0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 TD EP 0 0
Byte 4
Requester ID
Byte 8
Bus Number
Byte 12
R
0 0 0 0 0 0 0 0 0 0 0 1
Tag
Device Nb.
Func
0
0 0 0 0 First BE
0
0 0 Ext. Reg.
Register Nb.
0 0
Table 3-113 • Type 1 Configuration Write Request Descriptor Format
+0
+1
+2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
+3
6
5 4 3 2 1 0 7 6 5 4 3 2 1 0
Byte 0
0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 TD EP 0 0
Byte 4
Requester ID
Byte 8
Bus Number
Byte 12
R
0 0 0 0 0 0 0 0 0 0 0 1
Tag
Device Nb.
Func
0
0 0 0 0 First BE
0
0 0 Ext. Reg.
Register Nb.
0 0
Table 3-114 • Completion (with data) Descriptor Format
+0
+1
+2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
+3
6
Byte 0
0 1 0 0 1 0 1 0 0 TC
Byte 4
Completer ID
Status
Byte 8
Requester ID
Tag
Byte 12
R
5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 0 0 0 TD EP Attr
0 0 Length
B Byte Count
0 Lower Address
Table 3-115 • Completion Locked (with data) Descriptor Format
+0
+1
+2
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
+3
6
5 4 3 2 1 0 7 6 5 4 3 2 1 0
Byte 0
0 1 0 0 1 0 1 1 0 TC
0 0 0 0 TD EP Attr
0 0 Length
Byte 4
Completer ID
Status
Byte 8
Requester ID
Tag
0 Lower Address
+2
+3
B Byte Count
Byte 12
Table 3-116 • Message (with data) Descriptor Format
+0
+1
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
Byte 0
0 1 1 1 0 r r r
2 1 0
TC
Byte 4
Requester ID
Byte 8
Vendor defined or all zeros for Slot Power Limit
Byte 12
Vendor defined or all zeros for Slots Power Limit
6
5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 0 0 0 TD EP 0 0
Tag
Revision 3
0 0 Length
Message Code
103
PCI Express
SERDES Block PCIe Debug Interface
SERDES block has a debug mode mostly for debugging PCIe link. A number of internal status/error
signals are available to the fabric to be used for end-to-end system debug functions. To keep the number
of signals interfacing between the fabric and SERDES block to a minimum, these debug signals are
multiplexed on PRDATA signals of the APB bus. Debug mode is enabled only when
SYSTEM_DEBUG_MODE_KEY (8'b1010_0101) is written (offset - address: A8). Once correctly written,
the APB READ-BUS is multiplexed with PCIe debug data. PCIe DEBUG data is available only when
APB-READ is not taking place. This feature can be activated only from the Edit Registers GUI of the
SERDES Configurator.
Table 3-117 shows the condition where debug information is available.
Table 3-117 • Debug Information Available Conditions
Debug Mode
APB-Bus Operation
APB_PRDATA Bus Behavior
Enabled
Write
Debug information
Enabled
Read
APB read data
Enabled
Idle
Debug information
Disabled
Don’t care
APB read data
Table 3-118 shows the debug signals that are mapped to APB PRDATA bus.
Table 3-118 • Debug Signals Mapping to APB Bus
APB_PRDAT Signals
APB_S_PRDATA[31]
Debug Signal
PHY_LOCK_STATUS
Description
SERDES PHY related status signals. Combined status of 
PHY - Tx/CDR- PLL lock status. Only PHY-lanes which are used
are considered for this PHY_LOCK_STATUS signal generation.
When any used PLL's PHY lanes are locked, then
PHY_LOCK_STATUS is either 1'b1 or it is 1'b0.
Note: Individual PHY lane's PLL information is available in
"SERDES_TEST_OUT" register in the SERDES block
system block.
APB_S_PRDATA[30:26]
LTSSM_R [4:0]
LTSSM state: LTSSM state encoding. Refer to LTSSM_28_24
register for more information.
APB_S_PRDATA[25:24]
ERR_PHY [1:0]
PHY error: Physical layer error
bit0: Receiver port error
bit1: Training error
APB_S_PRDATA[23:19]
ERR_DLL [4:0]
DLL error: Data link layer error
bit0: TLP error
bit1: DLLP error
bit2: Replay timer error
bit3: Replay counter rollover
bit4: DLL protocol error
104
R e vi s i o n 3
RTG4 FPGA High-Speed Serial Interfaces
Table 3-118 • Debug Signals Mapping to APB Bus (continued)
APB_PRDAT Signals
APB_S_PRDATA[18:10]
Debug Signal
ERR_TRN [8:0]
Description
TRN error: Transaction layer error
bit0: Poisoned TLP received
bit1: ECRC check failed
bit2: Unsupported request
bit3: Completion timeout
bit4: Completer abort
bit5: Unexpected completion
bit6: Receiver overflow
bit7: Flow control protocol error
bit8: Malformed TLP
APB_S_PRDATA[9]
ERR_DL
Error ACK/NACK DLLP parameter: This signal reports that the
received ACK/NACK DLLP has a sequence number higher than
the sequence number of the last transmitted TLP.
APB_S_PRDATA[8]
TIMEOUT
LTSSM timeout: This signal serves as a flag, which indicates that
the LTSSM timeout condition is reached for the current LTSSM
state.
1’b1: Timeout condition reached
1’b0: No time condition reached
APB_S_PRDATA[7]
CRCERR
Received TLP with LCRC error: This signal reports that a TLP is
received, which contains an LCRC error.
APB_S_PRDATA[6]
CRCINV
Received nullified TLP: This signal indicates that a nullified TLP
is received.
APB_S_PRDATA[5]
RX_ERR_DLLP
Received DLLP with LCRC error: This signal reports that a DLLP
has been received that contains an LCRC error.
APB_S_PRDATA[4]
ERR_DLLPROT
DLL protocol error at data link layer: This signal reports a DLL
protocol error.
APB_S_PRDATA[3]
RX_ERR_FRAME
DLL framing error detected: This signal indicates that received
data cannot be considered as a DLLP or TLP, in which case, a
receive port error is generated and link retraining is initiated.
APB_S_PRDATA[2]
L2-EXIT
l2_exit information signal
APB_S_PRDATA[1]
DLUP_EXIT
dlup_exit information signal
APB_S_PRDATA[0]
HOTRST_EXIT
hotrst_exit information signal
Revision 3
105
PCI Express
Glossary
AXI3
Advanced extensible interface
EPs
Endpoints
PCI Express
Peripheral component interconnect express
PCIe
PCI Express
SERDES Block
Serializer/de-serializer interface block
106
R e vi s i o n 3
4 – XAUI
Introduction
This chapter describes implementing XAUI in the RTG4 FPGA devices using the XAUI extender block
inside the high-speed serial Interface (SERDES Block) block. XAUI is a standard for extending the 10 Gb
media independent interface (XGMII) between the media access control (MAC) and PHY layer of 10 Gb
Ethernet (10 GbE). The RTG4 high-speed serial block implements the integrated XAUI, which can be
connected to a 10 Gb Ethernet FPGA IP core in the FPGA fabric for a complete solution.
Overview of XAUI Implementation in RTG4
The RTG4 SERDES block (PCIESS and NPSS blocks) integrates the functionality of supporting multiple
high-speed serial protocols. Figure 4-1 shows the peripheral component interconnect express (PCIe)
2.0, XAUI, and SGMII. All SERDES blocks can be configured in various modes, including XAUI. XAUI is
a standard for extending the 10 Gb media independent interface (XGMII) between the media access
control (MAC) and PHY layer of 10 Gb Ethernet (10 GbE).
SERDES
I/O
PMA LANE0
Up to 24 Lanes Multi Protocol 3.125G SERDES
PMA
PMA
PCI Express
x1,x2,x4
2 Per Device
PMA
LANE[0:1] Calibration
Standard Cell /
SEL Immune
Flash Based /
SEL Immune
PMA
SERDES
I/O
Native SERDES
EPCS
XAUI
XGXS
PCIe PCS
LANE0
PMA Control
Logic
PMA LANE1
EPCS
LANE
0:1
PCIe PCS
LANE1
PMA Control
Logic
AXI/AHB, XGMII, Direct 20 Bit Bus
System
Controller
POR
Generator
Math Blocks
(18x18)
JTAG
RT PLLs
462
Math Blocks
(18x18)
Micro SRAM
(64x18)
210
Micro SRAM
(64x18)
Large SRAM
(1024x18)
uPROM
SERDES
I/O
PMA LANE2
SERDES
I/O
PMA LANE3
209
Large SRAM
(1024x18)
PIPE
Controller
APB Bus
Up to 16 SpaceWire Clock
& Data Recovery Circuits
FPGA Fabric
Up to 150K Logic Elements
PMA Control
Logic
XAUI
Extender
PCIe PCS
LANE2
LANE[2:3] Calibration
AXI/AHB
667 Mb/s DDR
Controller/PHY
AXI/AHB
667 Mb/s DDR
Controller/PHY
PMA Control
Logic
EPCS
LANE
2:3
PCIe PCS
LANE3
RC OSC
Multi-Standard GPIO
(1.2 – 3.3 V, LVTTL, LVCMOS, LVDS, HSTL/SSTL, PCI)
FPGA Fabric Interface
APB Slave
Register Space
Interface
XGMII/MDIO
User Gigabit
Ethernet IP
Figure 4-1 • RTG4 SERDES Block Diagram
The XAUI implementation in the RTG4 devices offers the following features:
•
Full compliance with IEEE 802.3
•
IEEE 802.3ae- clause 45 MDIO interface
•
IEEE 802.3ae- clause 48 state machines
•
Pseudo-random idle insertion (PRBS Polynomial X^7 + X^3 + 1)
•
FPGA interface Clock frequency of 156.25 MHz
•
Double-width 64-bit single data rate (SDR) interface
•
Comma alignment function
•
Low power mode
•
PHY-XS and DTE-XS loopback
•
IEEE 802.3ae- annex 48A jitter test pattern support
•
IEEE 802.3 clause 36 8B/10B encoding compliance
•
Tolerance of lane skew up to 16 ns (50 UI)
•
IEEE 802.3 PICs compliance matrix
Revision 3
107
XAUI
Device Support
Table 4-1 shows the total number of SERDES Blocks in each RTG4 device that can be configured to
support XAUI.
Table 4-1 • SERDES Blocks in RTG4 FPGAs Supporting XAUI (PCIESS and NPSS)
SERDES block available for XAUI
RT4G075
RT4G150
Up to 4
Up to 6
Notes:
1. The specified number of SERDES blocks varies depending on the device package.
2. XAUI uses the entire SERDES block (4-Lanes).
XAUI Overview
XGMII provides a 10 Gbps pipeline; the separate transmission of clock and data coupled with the timing
requirement to latch data on both the rising and falling edges of the clock results in a significant challenge
in routing the bus more than the recommended short distance of 7 cm. Also, the XGMII bus puts several
limitations on the number of ports that can be implemented on a system line card. To overcome these
issues, IEEE 802.3ae 10 GbE Task Force developed the XAUI interface. XAUI is a 
full-duplex interface that uses four self-clocked serial differential links in each direction to achieve 10
Gbps data throughput. Each serial link operates at 3.125 Gbps to accommodate both data and the
overhead associated with 8B/10B coding. The self-clocked nature of XAUI eliminates skew concerns
between clock and data, and extends the functional reach of the XGMII by approximately another 50 cm.
Its compact nature and robust performance make it ideal for chip-to-chip, board-to-board, and 
chip-to-optics module applications. The XAUI standard is fully specified in clauses 47 and 48 of the 10
GbE specification IEEE Std. 802.3-2008.
The RTG4 XAUI block has the following features:
•
Simple signal mapping to the XGMII
•
Independent transmit and receive data paths
•
Four lanes conveying the XGMII 64-bit data and control
•
Differential signaling with low voltage swing (1600 mV(p-p))
•
Self-timed interface allowing jitter control to the physical coding sublayer (PCS)
•
Shared technology with other 10 Gbps interfaces
•
Shared functionality with other 10 Gbps Ethernet block
•
Utilization of 8b/10b encoding
The conversion between the XGMII and XAUI interfaces occurs at the XGXS (XAUI extender sublayer).
RTG4 XAUI
The RTG4 FPGA has an integrated XAUI implementation. The RTG4 high-speed interface (SERDES
Block) has a XAUI IP block (XAUI Extender) and SERDES block. Figure 4-1 on page 107 shows an
application example; the XAUI IP is extending the 10 Gb soft IP in the fabric. The XAUI IP block in
SERDES block provides the XGXS functionality and the SERDES block provides the physical layer. The
XAUI IP block connects a 10 Gb Ethernet MAC to SERDES physical medium attachment (PMA) logic. In
addition, the XAUI IP block has a management data input/output (MDIO) interface allowing an MDIO
manageable device to program the MDIO registers. The SERDES block is configured to PMA only mode
and requires a reference clock of 156.25 MHz to operate at a line rate of 3.125 Gbps.
108
R e vi s i o n 3
RTG4 FPGA High-Speed Serial Interfaces
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Figure 4-2 • XAUI Implementation in RTG4
The high-speed serial interface (SERDES Block) can be configured to support multiple serial protocols.
However, when using the XAUI protocol, only one protocol can be implemented as XAUI uses all four
SERDES lanes of the Quad. Table 4-2 shows the lane speed of four physical SERDES lanes when using
XAUI.
Table 4-2 • XAUI Implementation in RTG4
Lane0
XAUI Protocol
Single Protocol PHY
Lane1
Lane2
Lane3
Protocol
Speed
Protocol
Speed
Protocol
Speed
Protocol
Speed
XAUI
3.125 G
XAUI
3.125 G
XAUI
3.125 G
XAUI
3.125 G
The SERDES block in XAUI mode has SERDES I/O pads on one side and an XGMII interface and MDIO
interface on the FPGA fabric side. Table 4-2 shows the RTG4 SERDES Lane assignments in XAUI
mode.
The RTG4 XAUI interface uses the I/O signal interfaces listed in Table 2-4 on page 38. Refer to the
"XAUI IP Fabric Interface" section on page 111 for detailed information on XGMII and MDIO interfaces on
the fabric side.
Refer to RTG4 Pin Description for other SERDES required pins.
Revision 3
109
XAUI
Getting Started
This section provides an overview of how to configure a SERDES block in XAUI mode, and instructions
for using XAUI IP in an RTG4 device.
The following sections describe how to instantiate XAUI in a design by completing the following steps:
•
Using High-Speed Serial Configurator for XAUI Mode
•
Simulating the SERDES Block with XAUI Mode
•
Using the XAUI IP Architecture
Using High-Speed Serial Configurator for XAUI Mode
The High-Speed Serial Interface Configurator in Libero SoC can be used to configure the SERDES
block in XAUI mode.
Protocol Selection
These settings are used for protocol selection:
•
Protocol 1 Type: This is the protocol setting. Select XAUI from the drop-down menu.
•
Protocol 1 PHY Reference Clock: This is the PHY reference clock selection. Refer to the
"SERDES Reference Clocks Selection" section on page 116 for details on PHY reference clock
selection.
Simulating the SERDES Block with XAUI Mode
When configured in XAUI mode, the SERDES block only allows the user to run simulation using the
APB3 interface. The user can read and write to the SERDES block and SERDES registers using the
simulation library. Refer to the SERDES Block BFM Simulation Guide for details for using RTL mode for
simulation. BFM mode for simulation is not supported for XAUI.
Using the XAUI IP Architecture
The following sections describe the XAUI IP architecture:
•
XAUI IP Block Overview
•
XAUI IP Fabric Interface
XAUI IP Block Overview
Figure 4-3 shows the XAUI IP block. This module is connected to the SERDES PMA block through the
two EPCS interface blocks, and the FPGA fabric via XGMII and MDIO interfaces. It has three major
blocks:
110
•
Transmit Block: This block is responsible for encoding the XGMII data (using 8B/10B). The output
to the transmit block is an 80-bit interface (20 bits per lane). The PMA in the SERDES receives
this 80-bit data and transmits it to the XAUI bus.
•
Receive Block: This block receives 8B/10B encoded data and four recovered clocks from an
external XAUI SERDES PMA. The receive block performs comma alignment on the data, phasealigns the four lanes of data, and performs the 8B/10B decode function.
•
Management Block: The management block is the MDIO interface to the design registers.
•
The transmit and receive FPGA interface frequencies are set at 156.25 MHz.
R e vi s i o n 3
RTG4 FPGA High-Speed Serial Interfaces
SERDES Block
XAUI Extender
IP Block
Transmit Block
XGMII Interface
Lane12
Interface
SERDES
I/O PADS
SERDES
(PMA only)
Management Block
MDIO Interface
Lane23
Interface
Receive Block
Figure 4-3 • XAUI IP Block Diagram
XAUI IP Fabric Interface
The RTG4 SERDES block in XAUI mode interfaces with the fabric and differential I/O pads.
Table 4-3 • MDIO Interface Signals
Port
Type
Description
XAUI_MMD_MDC
Input
MDIO I/F clock. 40 MHz or less.
XAUI_MMD_MDI
Input
MDIO data input from bidirectional pad.
XAUI_MMD_MDI_ EXT
Input
Serial data output of another block that is responding to a host read transaction.
XAUI_MMD_MDO
Output MDIO data output to bidirectional pad.
XAUI_MMD_ MDOE
Output MDIO data output enable. This is used to control bidirectional pad. It is active
High.
XAUI_MMD_ MDOE_IN
Input
MDIO data output enable input. This is used to force MMD_MDI High in an idle
state. It is active High.
XAUI_MMD_PRTAD[4:0]
Input
A static signal that defines the port address of the XAUI extender block
instantiated. Access to the MDIO registers is granted only if the port address
specified in the MDI stream matches this input.
Revision 3
111
XAUI
Table 4-3 • MDIO Interface Signals (continued)
XAUI_MMD_ DEVID[4:0]
Input
A static signal that defines the device ID of the XAUI extender block instantiated.
Access to the MDIO registers is granted only if the device ID (DEVID) specified
in the MMD_MDI stream matches this input. For the PHY-XS, this value must be
04h. For the DTE-XS, this value must be 05h.
XAUI_VNDRRESLO[31:0] Output A general purpose register for vendor use, reset Low. The output of two 16-bit
registers (address 0x8000 and 0x8001) that are set Low on reset for general
purpose use.
XAUI_VNDRRESHI[31:0]
Output General purpose register for vendor use, reset High. The output of two 16-bit
registers (address 0x8002 and 0x8003) that are set High on reset for general
use.
Table 4-4 • XGMII Transmit Interface Signals
Port
Type
XAUI_TXD[63:0]
Input
Description
Transmit data input from the XGMII. The signal has the following lane definitions:
Lane0, row0: txd[7:0]
Lane1, row0: txd[15:8]
Lane2, row0: txd[23:16]
Lane3, row0: txd[31:24]
Lane0, row1: txd[39:32]
Lane1, row1: txd[47:40]
Lane2, row1: txd[55:48]
Lane3, row1: txd[63:56]
The row0 lanes are leading the row1 lanes in time. Refer to IEEE 802.3ae, clause
46, for a complete definition.
XAUI_TXC[7:0]
Input
Transmit data lane control signals. The signal has the following lane definitions:
Lane0, row0: txc[0]
Lane1, row0: txc[1]
Lane2, row0: txc[2]
Lane3, row0: txc[3]
Lane0, row1: txc[4]
Lane1, row1: txc[5]
Lane2, row1: txc[6]
Lane3, row1: txc[7]
The row0 lanes are leading the row1 lanes in time. Refer to IEEE 802.3ae, clause
46, for a complete definition.
112
R e vi s i o n 3
RTG4 FPGA High-Speed Serial Interfaces
Table 4-5 • XGMII Receive Interface Signals
Port
Type
Description
XAUI_RX_CLK
Output
Receive clock synchronous with Rxd, clock synchronous with the output XGMII
data Rxd. Equal to the input recovered clock RX_CLKI0. This clock operates
nominally at 156.25 MHz. Refer to IEEE 802.3ae, clause 46, for a complete
definition.
XAUI_RXD[63:0]
Output
Receive data output to the XGMII. The signal has the following lane definitions:
Lane0, row0: rxd[7:0]
Lane1, row0: rxd[15:8]
Lane2, row0: rxd[23:16]
Lane3, row0: rxd[31:24]
Lane0, row1: rxd[39:32]
Lane1, row1: rxd[47:40]
Lane2, row1: rxd[55:48]
Lane3, row1: rxd[63:56]
The row0 lanes are leading the row1 lanes in time. Refer to IEEE 802.3ae, clause
46, for a complete definition.
XAUI_RXC[7:0]
Output
Receive lane data control signals. The signal has the following lane definitions:
Lane0, row0: rxc[0]
Lane1, row0: rxc[1]
Lane2, row0: rxc[2]
Lane3, row0: rxc[3]
Lane0, row1: rxc[4]
Lane1, row1: rxc[5]
Lane2, row1: rxc[6]
Lane3, row1: rxc[7]
The row0 lanes are leading the row1 lanes in time. Refer to IEEE 802.3ae, clause
46, for a complete definition.
Table 4-6 • XAUI IP Block Miscellaneous Control Signal
Port
XAUI_ LOOPBACK_OUT
XAUI_ LOOPBACK_IN
XAUI_ LOWPOWER
Type
Description
Output
Loopback mode enable out. This signal is asserted when the XAUI extender
block is placed in loopback. Typically, this signal is shunted back into the
input XAUI_ LOOPBACK_IN port. In this case, loopback is implemented in
the XAUI extender block.
Input
Loopback mode enable in. When asserted, the XAUI PMA output data
signals are shunted back into the input signals. For loopback to function
appropriately, the XGMII transmit clock TX_CLK must be shunted back into
the PMA recovered clock inputs.
Output
SERDES low power status. When set to 1, the SERDES block is placed in a
low power state.
Revision 3
113
XAUI
Reset and Clocks for XAUI
This section covers the functional aspects of the reset and clock circuitry inside the high-speed serial
interface block for XAUI mode. It has the following sections:
•
XAUI Mode Clocking
•
XAUI Mode Reset Network
XAUI Mode Clocking
When the SERDES block is configured in XAUI mode, it has multiple clock inputs and outputs. This
section describes the XAUI clocking scheme.
SERDES Block Clock Network in XAUI
In XAUI mode, data is exchanged from FPGA IP in the fabric and XAUI IP. Figure 4-4 on page 115 shows
the clocking of the XAUI IP block. The 156.25 MHz reference clock is used by the SERDES PMA (Tx PLL
and CDR PLL). The PLLs generate 156.25 MHz clocks and send 4 Rx and 4 Tx clocks through the EPCS
interface. The Lane0 Tx clock is fed in to the reference clock of SPLL and XAUI extender block. This
SPLL is used to reduce the skew between the fabric and RTG4 SERDES block module. Libero SOC
automatically connects the XAUI_CLK_OUT signal with the XAUI_FDB_CLK signal in the FPGA fabric
through the global network, as shown in Figure 4-4 on page 115. The 4 Rx clocks are fed in to the XAUI
extender block, where lane de-skewing is done and only one Rx clock is given out to the FPGA fabric.
The XAUI_CLK_OUT and XAUI_RX_CLK signals are used by XGMII FPGA IP. The APB clock
(APB_S_CLK) is an asynchronous clock used for SERDES block register access.
In XAUI only mode, the Tx clock is generated from the PMA. The lane0 Tx clock is used for this purpose.
The Rx clock for all four lanes is passed to the XGXS receiver block with gating logic in between to low
power operation.
114
R e vi s i o n 3
RTG4 FPGA High-Speed Serial Interfaces
TXDP
TXDN
3.125 GHz
RXDP
RXDN
3.125 GHz
SERDES Block
Fabric
SERDES
Reference Clock (156.25 MHz)
CDR
PLL
TX
PLL
APB_S_CLK
MDD_MDC
156.25 MHz
TxClk-x4 Clks
156.25 MHz
RxClk-x4 Clks
XAUI_RX_CLK
XAUI
IP
4 to 1
Mux
156.25 MHz
TxClk
EPCS_TXCLK[0]
XGMII
FPGA
IP
PLL_SERDES_BLOCK_REF
deskew
SPLL
PLL_SERDES_BLOCK_FB
deskew
GB
PLL_ACLK
XAUI_CLK_OUT
Figure 4-4 • Clocking in XAUI Mode
Table 4-7 lists the various clocks in the XAUI mode.
Table 4-7 • Clock Signals in XAUI Mode
Clock Signal
Description
XAUI_OUT_CLK
Transmit clock to be used for the transmit data. Divided down 156.52 MHz clock from the
transmit PLL.
MMD_MDC
MDIO clock
XAUI_RX_CLK
Receive clock synchronous with Rxd, clock synchronous with the output XGMII data Rxd.
Equal to the input recovered clock RX_CLKI0. Refer to IEEE 802.3ae, clause 46, for a
complete definition.
APB_S_CLK
PCLK for APB interface
Revision 3
115
XAUI
SERDES Reference Clocks Selection
The PMA in the SERDES block needs a reference clock on each of its lanes for Tx and Rx clock
generation through PLLs. Figure 4-5 shows reference clock selection in the high-speed serial interface
generator available in Libero SoC. In XAUI mode, the protocol expects a differential clock to be input to
the REFCLK_P and REFCLK_N pads. Therefore, the software correctly sets the input mux for the refclk
inputs to the SERDES block. The FAB_REF_CLK option is not available in XAUI mode. The reference
clock pads are differential input. In XAUI mode, the user must choose one reference clock for all 4 lanes.
Refer to the "Serializer/De-serializer" chapter on page 21 for more information on the REFCLK block.
5()&/.B3
5()&/.B1
)$%B5()B&/.
D5HI&ON>@
D5HI&ON>@
/$1(B5()&/.B
6(/>@
7KH)$%B5()B&/.RSWLRQLVQRWDYDLODEOH
LQWKH;$8,PRGH
D5HI&ON>@
D5HI&ON>@
/$1(B5()&/.B6(/>@
Figure 4-5 • SERDES Reference Clock for XAUI Mode
Table 4-8 • Reference Clock Signals for SERDES
Clock Signal
REFCLK_P, REFCLK_N
Description
Reference clock output of REFCLK_P and REFCLK_N (Differential)
XAUI Mode Reset Network
The RTG4 SERDES block configured in XAUI mode has multiple reset inputs. Figure 4-6 on page 117
shows the reset signals and how they are connected internally. The CORE_RESET_N input is an
asynchronous reset input XAUI extender block, the XAUI_MDC_RESET input asynchronously resets all
of the MDIO registers, the XAUI_TX_RESET input resets the TX block register, and the
XAUI_RX_RESET input resets the RX block register. The XAUI IP generates several reset signals that are
used by the FPGA IP. In addition, there are several input reset signal SERDES and SERDES block
registers.
116
R e vi s i o n 3
RTG4 FPGA High-Speed Serial Interfaces
Fabric
SERDES Block
PHY_RESET_N
APB_S_PRESET_N
Power-up
CORE_RESET_N
epcs_rstn[3:0]
XAUI_MDC_RESET
MDC_RESET
XAUI_TX_RESET
Reset
Glue Logic
SERDES
TX_RESET
MSTR_RESET
XAUI
Extender
XAUI_RX_RESET
RX_RESET[3:0]
epcs_ready[3:0]
RX_RESETOUT[3:0]
XAUI_RX_RESET_OUT
XAUI_TX_RESET_OUT
XAUI_MDC_RESET_OUT
Figure 4-6 • XAUI Reset Scheme
Table 4-9 describes the reset signals and recommended connections.
Table 4-9 • XAUI Mode Reset Signals
Port
Type
Description
CORE_RESET_N
Input
External asynchronous reset input. Must be asserted for at least two clock
cycles of the host clock MMD_MDC for a full reset of the XAUI extender to
occur. It is active Low.
PHY_RESET_N
Input
Active Low SERDES reset. It is synchronized with the SERDES reference
clock.
Output
MDC synchronous reset. This reset is asynchronously asserted by
MSTR_RESET and synchronously deasserted with the XAUI_MMD_MDC
clock. Typically, this output is connected to the XAUI_MDC_RESET input. It
is active High.
Input
Asynchronously resets all the MDIO registers to their default values. This
pin is connected directly to set/reset ports of all flops in the MMD_MDC
clock
domain.
Typically, this input
is
connected
to
the
XAUI_MDC_RESET_OUT signal.
Output
Software generated reset XS control 1 register [bit 15] synchronized with
TX_CLK. This signal is held High whenever the low power mode is enabled.
This signal is asynchronously asserted by the software generated reset and
synchronously deasserted with EPCS_TXCLK[0]. It is active high. Typically,
this output is connected to the XAUI_TX_RESET input.
XAUI_MDC_RESET_ OUT
XAUI_MDC_RESET
XAUI_TX_RESET_OUT
Revision 3
117
XAUI
Table 4-9 • XAUI Mode Reset Signals (continued)
XAUI_TX_RESET
Input
Resets the XAUI Transmit block. This pin is connected directly to the
set/reset ports of all flip-flops in the EPCS_TXCLK[0] clock domain. It is
active high. Typically, this is connected to the XAUI_TX_RESET_OUT
signal.
XAUI_RX_RESET_
OUT[3:0]
Output
Software generated resets XS control 1 register [bit 15] synchronized with
the XAUI_RX_CLK[3:0] clocks. These signals are held high whenever the
low power mode is enabled. These signals are asynchronously asserted by
the software-generated reset and synchronously deasserted with the
XAUI_RX_CLK[3:0]. It is active high.
XAUI_RX_RESET
Input
Resets the XAUI extender block. These pins are connected to set/reset
ports of all flip-flops in the corresponding XAUI_RX_CLK[3:0] clock domain.
APB_S_PRESET_N
Input
APB asynchronous reset to all SERDES block APB registers.
Design Considerations
This section provides instruction for implementing XAUI in the RTG4 devices. It includes the following
sections:
•
Using MDIO Interface
•
XAUI IP Block Timing Diagram
•
XAUI Mode Loopback Test Operation
•
Using MMD Status Registers
Using MDIO Interface
The MDIO interface allows users to access the MDIO registers. Figure 4-7 on page 119 shows a system
block diagram for connecting XAUI IP and an MDIO manageable device (MMD) to a station management
entity (STA). In this case, the STA is A-XGMAC. If the MDIO is not required for the user application, the
MDIO ports can be tied off inactive.
118
R e vi s i o n 3
RTG4 FPGA High-Speed Serial Interfaces
To External Device
Fabric
SERDES Block
XAUI_MMD_MDI_EXT
10 Gig
MAC
(STA)
XAUI_MMD_MDO
XAUI_MMD_MDI
XAUI Extender
XAUI_MMD_MDOE_IN
XAUI_MMD_MDI
XAUI_MMD_MDOE_IN
XAUI_MMD_MDO
XAUI_MMD_MDOE
Figure 4-7 • MDIO System Block Diagram
Revision 3
119
XAUI
XAUI IP Block Timing Diagram
The following sections show the timing relations between clock and data for the three interfaces of the
XAUI extender.
•
Transmit Interface
•
Receive Interface
•
MMD Read Timing
•
MMD Write Timing
Refer to the RTG4 FPGA Datasheet for the detailed timing numbers.
Transmit Interface
Figure 4-8 shows the XGMII transmit timing diagram. The transmit data and control signals are source
centered on the transmit clock per requirements of IEEE 802.3ae, clause 46. All four lanes of data are
synchronous with a common clock.
XAUI_TX_CLK
XAUI_TXD[31:0]
S
D
XAUI_TXC[3:0]
0x1
0x0
D
D
XAUI_TXD[64:32]
XAUI_TXC[7:4]
D
D
D
D
I
0xF
D
0x0
D
D
T
I
0xC
0xF
Figure 4-8 • Transmit XGMII Interface Timing Diagram
Receive Interface
Figure 4-9 shows the XGMII receive timing diagram. The receive data and control signals are edgealigned with the receive clock XAUI_RX_CLK. To be fully compliant with IEEE 802.3ae, the data and
control signals are normally source centered on XAUI_RX_CLK. However, in the RTG4 FPGA, the XAUI
extender is interfaced with a FPGA 10G MAC in the fabric within the same device, eliminating the need
to source center the data. All four lanes of data are synchronous with the common clock XAUI_RX_CLK.
The user must check timing and ensure that the data is captured by the FPGA 10G MAC in the fabric.
120
R e vi s i o n 3
RTG4 FPGA High-Speed Serial Interfaces
XAUI_RX_CLK
XAUI_RXD[31:0]
S
D
XAUI_RXC[3:0]
0x1
0x0
D
D
XAUI_RXD[64:32]
XAUI_RXC[7:4]
D
D
D
D
I
I
0xF
D
D
D
0x0
T
0xC
I
I
0xF
Figure 4-9 • XGMII Interface Receive Timing Diagram
MMD Read Timing
Figure 4-10 shows the timing diagram for an MDIO register read. The XAUI_MMD_MDO signal is
controlled by XAUI_MMD_MDOE.
<read/read inc>
<Z>
<0>
XAUI_MMD_MDC
XAUI_MMD_MDO
XAUI_MMD_MDOE
Figure 4-10 • MDIO Interface Read Timing Diagram
MMD Write Timing
Figure 4-11 shows the timing diagram for MDIO registers. XAUI_MMD_MDOE must not be asserted
during a write operation. Refer to the IEEE 802.3ae specification, clause 45, for a complete definition.
<idle>
<0>
<0>
XAUI_MMD_MDC
XAUI_MMD_MDI
XAUI_MMD_MDOE
Figure 4-11 • MDIO Interface Read Timing Diagram
Revision 3
121
XAUI
XAUI Mode Loopback Test Operation
The XAUI extender block can be placed in loopback mode for testing purposes. It can also be placed in
multiple loopback operations.
XAUI—Near End Loopback Test
Bit 14 of Reg00 can be used to enable the loopback. When loopback mode is enabled, the transmit
output is shunted back into the receive input. For loopback mode to work appropriately, the transmit clock
is also shunted back into the receive clock inputs. The loopback test data must be fed from the XGMII
interface available to fabric.
XAUI—Far End Loopback Test
In the XAUI far end loopback test, the transmit interface of the XAUI extender block is connected to the
SERDES block interface. In this case, the SERDES block is put in loopback mode, where serial data
from transmit side is fed to the serial receive interface. XAUI far-end loopback verifies the transmit and
receives the paths of the XAUI extender block, and then tests the validity of the PMA data path. The
XAUI_ LOOPBACK_IN signal is used for this mode.
Using MMD Status Registers
The two MMD status registers: XS status 1 (Reg01) and XS status 2 (Reg07). When the reset signal on
the XAUI block is de-asserted, the initial state of these status registers indicates a fault condition. The
initial fault condition must be ignored, and a read operation is required to be performed on these registers
to clear the initial false fault-status. After this, when a real fault condition happens (for example, when a
link is down), the fault register properly indicates any fault, as expected.
MDIO Register Map
Table 4-10 lists the MDIO registers.
Table 4-10 • MDIO Registers
Register Name
Register Address
Read /
Writable
Device
Address
Description
Reg00
0x0000
R/W
04h/05h
XS control 1 register
Reg01
0x0001
R/O
04h/05h
XS status 1 register
Reg02
0x 0002
R/O
04h/05h
XS device identifier register Low
Reg03
0x0003
R/O
04h/05h
XS device identifier register High
Reg04
0x0004
R/O
04h/05h
XS speed ability register
Reg05
0x0005
R/O
04h/05h
XS devices in package register Low
Reg06
0x0006
R/O
04h/05h
XS devices in package register High
–
0x0007
N/A
04h/05h
Reserved
Reg07
0x0008
R/O
04h/05h
XS status 2
–
0x0009 to 0x000d
N/A
04h/05h
Reserved
Reg08
0x000e
R/O
04h/05h
XS package identifier register Low
Reg09
0x000f
R/O
04h/05h
XS package identifier register High
–
0x0010 to 0x0017
N/A
04h/05h
Reserved
Reg10
0x0018
R/O
04h/05h
10G XGXS lane status register
122
R e vi s i o n 3
RTG4 FPGA High-Speed Serial Interfaces
Table 4-10 • MDIO Registers (continued)
Reg11
0x0019
R/W
04h/05h
10G XGXS test control register
–
0x001a to 0x7fff
N/A
04h/05h
Reserved
Reg12
0x8000
R/W
04h/05h
Vendor-specific reset Lo 1
Reg13
0x8001
R/W
04h/05h
Vendor-specific reset Lo 2
Reg14
0x8002
R/W
04h/05h
Vendor-specific reset Hi 1
Reg15
0x8002
R/W
04h/05h
Vendor-specific reset Hi 1
–
0x8004 to 0xffff
N/A
04h/05h
Reserved
Table 4-11 lists the XS Control 1 Register.
Table 4-11 • Reg00
Bit
Number
15
Name
Reset
Reset
Value
0x0
Description
The XAUI extender block is reset when this bit is set to 1. It returns to 0 when
the reset is complete (self-clearing).
1: Block reset
0: Normal operation
14
Loopback
0x0
The XAUI extender block loops the transmit signal back into the receiver.
0: Disable loopback
1: Enable loopback
13
Speed selection
0x1
This bit is for speed selection and is set to 1'b1 for compatibility with clause 22.
0: Unspecified
1: 10 Gbps and above
Any write to this bit is ignored.
12
Reserved
0x0
Reserved
11
Low power mode
0x0
When set to 1, the SERDES block is placed in a Low power mode. Set to 0 to
return to normal operation.
0: Normal operation
1: Low power mode
[10:7]
Reserved
0x0
Reserved
6
Speed selection
0x1
This bit is set to 1'b1 for compatibility with clause 22.
0: Unspecified
1: 10 Gbps and above
[5:2]
Speed selection
0x0
The speed of the PMA/PMD may be selected using bits 5 through 2.
1 x x x: Reserved
x 1 x x: Reserved
x x 1 x: Reserved
0 0 0 1: Reserved
0 0 0 0: 10 Gbps
Any write to this bit is ignored.
[1:0]
Reserved
0x0
Reserved
Revision 3
123
XAUI
Table 4-12 lists the XS Status 1 register.
Table 4-12 • Reg01
Bit
Number
2
Name
PHY/DTE
transmit/receive link
status
Reset
Value
0x0
Description
When read as a one, the receive link is up.
0: Link down
1: Link up
The receive link status bit is implemented with latching low behavior.
1
Low power ability
0x1
When read as a one, it indicates that the Low power feature in
supported.
0: Low power not supported
1: Low power is supported
0
Reserved
0x0
Reserved
Table 4-13 lists the XS Device Identifier Low register.
Table 4-13 • Reg02
Bit
Number
[15:0]
Name
Organizationally unique
identifier (OUI)
Reset
Value
0x0
Description
Reg02 and Reg03 provide a 32-bit value, which may constitute a
unique identifier for a particular type of SERDES. The identifier is
composed of the 3rd through 24th bits of the OUI assigned to the
device manufacturer by the IEEE, a 6-bit model number, and a 4-bit
revision number.
Reg02 sets bits [3:18] of the OUI. Bit 3 of the OUI is located in bit 15 of
the unique identifier of the register, and bit 18 of the OUI is located in bit
0 of the register.
Table 4-14 lists the XS Device Identifier High register.
Table 4-14 • Reg03
Bit
Number
Name
Reset
Value
Description
[15:10]
OUI
0x0
Bits [19:24] of the OUI. Bit 19 of the OUI is located in bit 15 of the
register, and bit 24 of the OUI is located in bit 10 of the register.
[9:4]
Manufacturer model
number
0x0
Bits [5:0] of the manufacturer model number. Bit 5 of the model
number is located in bit 9 of the register, and bit 0 of the model number
is located in bit 4 of the register.
[3:0]
Revision number
0x0
Bits [3:0] of the manufacturer model number. Bit 3 of the revision
number is located in bit 3 of the register, and bit 0 of the revision
number is located in bit 0 of the register.
Table 4-15 lists the XS Speed Ability register.
Table 4-15 • Reg04
Bit
Number
Name
Reset
Value
Description
[15:10]
Reserved
0x0
Reserved
[9:4]
10g capable
0x1
0: Not capable of 10g
1: 10g capable
124
R e vi s i o n 3
RTG4 FPGA High-Speed Serial Interfaces
Table 4-16 lists the XS Devices in Package Low register.
Table 4-16 • Reg05
Bit
Number
Reset
Value
Name
[15:6]
Reserved
0x0
5
DTE XS present
0x1
Description
Reserved
0: DTE XS not present in the package
1: DTE XS present in the package
4
PHY XS present
0x0
0: PHY XS not present in the package
1: PHY XS present in the package
3
PCS present
0x0
0: PCS not present in the package
1: PCS present in the package
2
WIS present
0x0
0: WIS not present in the package
1: WIS present in the package
1
PMD/PMA present
0x0
0: PMD/PMA not present in the package
1: PMD/PMA present in the package
0
Clause 22 register
present
0x0
0: Clause 22 registers not present in the package
1: Clause 22 registers present in the package
Table 4-17 lists the XS Devices in Package High register.
Table 4-17 • Reg06
Bit
Number
15
14
[13:0]
Reset
Value
Name
Vendor-specific device2
present
0x0
Vendor-specific device1
present
0x0
Reserved
0x0
Description
0: Vendor-specific device 2 not present
1: Vendor-specific device 2 present
0: Vendor-specific device 1 not present
1: Vendor-specific device 1 present
Reserved
Table 4-18 lists the XS Status 2 register.
Table 4-18 • Reg07
Bit
Number
[15:14]
Name
Device present
Reset
Value
0x0
Description
10: Device responding at this address.
11: No device responding at this address.
01: No device responding at this address.
00: No device responding at this address.
[13:12]
Reserved
0x0
Reserved
11
Transmit fault
0x0
0: No transmit fault
1: Transmit fault
Latched High, clear on read
Revision 3
125
XAUI
Table 4-18 • Reg07 (continued)
10
Receive fault
0x0
0: No receive fault
1: Receive fault
Latched High, clear on read
[9:0]
Reserved
0x0
Reserved
Table 4-19 lists the XS Package ID Low register
Table 4-19 • Reg08
Bit
Number
[15:0]
Name
Reset
Value
OUI
0x0
Description
Reg 08 and Reg 09 provide a 32-bit value, which may constitute a unique
identifier for a particular type of package that the SERDES is instantiated
within. The identifier is composed of the 3rd through 24th bits of the OUI
assigned to the package manufacturer by the IEEE, plus a 6-bit model
number, and a 4-bit revision number. Reg08 sets bits [3:18] of the OUI. Bit 3
of the OUI is located in bit 15 unique identifier of the register, and bit 18 of the
OUI is located in bit 0 of the register.
Table 4-20 lists the XS Package ID High register.
Table 4-20 • Reg09
Bit
Number
Name
Reset
Value
Description
[15:10]
OUI
0x0
Bits [19:24] of the OUI. Bit 19 of the OUI is located in bit 15 of the register, and
bit 24 of the OUI is located in bit 10 of the register.
[9:4]
Manufacturer
model number
0x0
Bits [5:0] of the manufacturer model number. Bit 5 of the model number is
located in bit 9 of the register, and bit 0 of the model number is located in bit 4
of the register.
[3:0]
Revision number
0x0
Bits [3:0] of the manufacturer model number. Bit 3 of the revision number is
located in bit 3 of the register, and bit 0 of the revision number is located in bit
0 of the register.
Table 4-21 lists the XGXS Lane Status register.
Table 4-21 • Reg10
Bit
Number
Name
Reset
Value
[15:13]
Reserved
12
PHY/DTE XGXS lane
alignment status
0x0
Pattern testing ability
0x1
11
–
Description
Reserved
0: Lanes not aligned
1: Lanes aligned
0: (PHY/DTE)XS is unable to generate test patterns
1: (PHY/DTE)XS is able to generate test patterns
10
[9:4]
126
PHY XGXS loopback
ability
Reserved
0x1
0: PHY XGXS does not has the ability to perform a loopback
1: PHY XGXS has the ability to perform a loopback
–
Reserved
R e vi s i o n 3
RTG4 FPGA High-Speed Serial Interfaces
Table 4-21 • Reg10 (continued)
3
Lane3 synchronized
0x0
When read as a one, this register indicates that the receive Lane3 is
synchronized.
0: Lane3 is not synchronized
1: Lane3 is synchronized
2
Lane2 synchronized
0x0
When read as a one, this register indicates that the receive Lane2 is
synchronized.
0: Lane2 is not synchronized
1: Lane2 is synchronized
1
Lane1 synchronized
0x0
When read as a one, this register indicates that the receive Lane1 is
synchronized.
0: Lane1 is not synchronized
1: Lane1 is synchronized
0
Lane0 synchronized
0x0
When read as a one, this register indicates that the receive Lane1 is
synchronized.
0: Lane0 is not synchronized
1: Lane0 is synchronized
Table 4-22 lists the XGXS Test Control register.
Table 4-22 • Reg11
Bit
Number
Name
[15:3]
Reserved
2
Transmit test pattern
enabled
Reset
Value
–
0x0
Description
Reserved
When this bit is set to a one, pattern testing is enabled on the transmit
path.
0: Transmit/receive test pattern disabled
1: Transmit/receive test pattern enabled
[1:0]
Test pattern select
0x0
The test pattern is used when enabled pattern testing is selected using
these bits:
00: High frequency test pattern
01: Low frequency test pattern
10: Mixed frequency test pattern
11: Reserved
Table 4-23 lists the Vendor-Specific Reset Low 1 register.
Table 4-23 • Reg12
Bit
Number
[15:0]
Name
Reset
Value
Description
Vendor-specific reset Lo 1 0x0000 General purpose registers that are connected to the output port.
XAUI_VNDRRESLO[15:0]. Typically used for external device control.
Revision 3
127
XAUI
Table 4-24 lists the Vendor-Specific Reset Low 2 register.
Table 4-24 • Reg13
Bit
Number
[15:0]
Name
Reset
Value
Description
Vendor-specific reset Lo 2 0x0000 General purpose registers that are connected to the output port.
XAUI_VNDRRESLO[31:16]. Typically used for external device control.
Table 4-25 lists the Vendor-Specific Reset High 1 register.
Table 4-25 • Reg14
Bit
Number
[15:0]
Name
Reset
Value
Description
Vendor-specific reset Hi 1 0xFFFF General purpose registers that are connected to the output port.
XAUI_VNDRRESLI[15:0]. Typically used for external device control.
Table 4-26 lists the Vendor-Specific Reset High 2 register.
Table 4-26 • Reg15
Bit
Number
[15:0]
Name
Reset
Value
Description
Vendor-specific reset Hi 2 0xFFFF General purpose registers that are connected to the output port.
XAUI_VNDRRESLI[31:16]. Typically used for external device control.
SERDES Block System Register Configurations for XAUI
Mode
The RTG4 S E R D E S b l o c k subsystem has three regions of configuration and status registers:
•
SERDES Block System Register
•
Bridge Register Space
•
SERDES Block–I/O Signal Interface
These registers are accessed by the 32-bit APB bus. Refer to the "SERDES Block System Register" on
page 141 for details. In XAUI mode, the PCIe core registers are not used. Only the SERDES block
system registers and SERDES block register are used for XAUI mode. The XAUI block also has MDIO
registers, which are accessed via MDIO interface signals.
The SERDES block system registers occupy 1 KB of the configuration memory map. However, in XAUI
mode, only subsets of the register are used. SERDES registers can be referenced in the "SERDES Block
System Register" on page 141.These registers can be updated through the 32-bit APB interface after
power-up.
128
R e vi s i o n 3
5 – EPCS Interface
Introduction
This chapter describes using the EPCS interface in RTG4 FPGA high-speed serial interface (SERDES
Block).
The SERDES block integrates the functionality of supporting multiple high-speed serial protocols such as
PCIe 2.0, XAUI, and EPCS interfaces, as shown in Figure 5-1. The SERDES block can be configured in
various modes, including EPCS mode. In EPCS mode, Lane0 and Lane1 (L01) EPCS interface and
Lane2 and Lane3 (L23) EPCS interface are exposed to the fabric and configures serializer/de-serializer
(SERDES) in physical media attachment (PMA) only mode. The PCIe and XAUI PCS logic in SERDES is
bypassed, however, the PCS logic can be implemented in the FPGA fabric and the EPCS interface
signals of the SERDES block can be connected. This allows any user-defined high-speed serial protocol
to be implemented in the RTG4 FPGA device.
SERDES
I/O
Up to 24 Lanes Multi Protocol 3.125G SERDES
PMA
PMA
PCI Express
x1,x2,x4
2 Per Device
PMA
Standard Cell /
SEL Immune
Flash Based /
SEL Immune
PMA
PCIe PCS
LANE0
PMA Control
Logic
EPCS
LANE
0:1
LANE[0:1] Calibration
SERDES
I/O
Native SERDES
EPCS
XAUI
XGXS
PMA LANE0
PMA LANE1
PCIe PCS
LANE1
PMA Control
Logic
AXI/AHB, XGMII, Direct 20 Bit Bus
System
Controller
POR
Generator
Math Blocks
(18x18)
JTAG
RT PLLs
462
Math Blocks
(18x18)
Micro SRAM
(64x18)
210
Micro SRAM
(64x18)
Large SRAM
(1024x18)
uPROM
PIPE
Controller
APB Bus
Up to 16 SpaceWire Clock
& Data Recovery Circuits
FPGA Fabric
Up to 150K Logic Elements
SERDES
I/O
PMA LANE2
PMA Control
Logic
XAUI
Extender
PCIe PCS
LANE2
209
Large SRAM
(1024x18)
AXI/AHB
667 Mb/s DDR
Controller/PHY
LANE[2:3] Calibration
AXI/AHB
667 Mb/s DDR
Controller/PHY
PMA Control
Logic
SERDES
I/O
PMA LANE3
PCIe PCS
LANE3
EPCS
LANE
2:3
RC OSC
Multi-Standard GPIO
(1.2 – 3.3 V, LVTTL, LVCMOS, LVDS, HSTL/SSTL, PCI)
FPGA Fabric Interface
APB Slave
Register Space
Interface
EPCS_LANE[0:3]
Parallel Intf
User Protocol
IP
Figure 5-1 • RTG4 SERDES Block Diagram
Features
Following are the main features of the EPCS interface in the RTG4 devices:
•
Up to a 20-bit Rx/Tx EPCS Interface to the FPGA fabric.
•
Allows the FPGA fabric to directly access the PMA block bypassing the PCIe PCS block in
SERDES and allows implementing any serial protocol for up to four lanes using the PCS logic in
the fabric.
•
Allows the FPGA fabric to access the SERDES register through the APB interface and therefore
allows programming various PMA settings, including programming of the SERDES Tx PLL and
Rx PLLs settings.
Revision 3
129
EPCS Interface
Device Support
The RTG4 family has two devices available. Table 5-1 shows the total number of SERDES block
available in each RTG4 device that can be configured to support the EPCS interface.
Table 5-1 • Available SERDES Blocks in RTG4 Devices
SERDES block Quads available / # of SERDES Lanes
available
RT4G075
RT4G150
4/16
6/24
Note: 1. The specified number of SERDES blocks varies depending on the device package.
2. Each SERDES block supports 4- EPCS Lanes.
RTG4 EPCS Interface
All SERDES blocks can be configured in EPCS mode.This allows the FPGA fabric to directly access the
SERDES block. The PCS logic of SERDES is bypassed in this mode to allow user-defined protocol to be
supported from the FPGA fabric. Figure 5-2 shows an application example using the EPCS interface.
Refer to Figure 5-1 on page 129 for the EPCS interface signals.
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130
R e vi s i o n 3
RTG4 FPGA High-Speed Serial Interfaces
The SERDES block can be configured to operate in the following two different modes:
•
Single-protocol Mode: The EPCS interface can be configured as x4 or x2 or x1 lane.
•
Multi-protocol Mode: The SERDES block can operate using dedicated Lane2 and Lane3 in
EPCS mode, while Lane0 and Lane1 are dedicated to the PCIe protocol link implementation.
Multi-EPCS protocol allows up to all four Lanes to be used independently for customized
protocols such as SGMII or JESD204b.
Table 5-2 on page 131, Table 5-3 on page 131, and Table 5-4 on page 134 show a detailed description of
the EPCS interface usage in Single-protocol and Multi-protocol mode.
Table 5-2 • EPCS Interface Usage in Single-Protocol and Multi-Protocol Mode
Mode
Protocol
1
Description
Single-protocol
EPCS Protocol
Configured to use maximum 4 lanes. In EPCS mode, the user- defined
serial protocol implemented within the FPGA fabric is connected though the
EPCS interface.
Multi-protocol1
PCIe protocol and
EPCS protocol
Configured to use x2 and x1 lane in PCIe mode. (lane0 and lane1 are used
for the PCIe link). Any user-defined/other serial protocol connected to the
EPCS interface uses lane2 and lane3 for this purpose.
Multi-EPCS
EPCS Protocol
Configure multiple independent EPCS protocols across Lane[0:1] and
Lane[2:3].
1. PCIESS Type SERDES block only.
Table 5-3 • EPCS Interface and SERDES Lane Mapping in Single-Protocol Mode
Single
Protocol
EPCS Mode
Lane0
Lane1
Lane2
Lane3
EPCS
–
–
–
EPCS
EPCS
–
–
–
–
–
EPCS
–
–
EPCS
EPCS
EPCS
EPCS
EPCS
EPCS
Getting Started
This section describes how to configure the SERDES block in EPCS mode and instructions for using the
EPCS interface.
The following sections show how to use SERDES block in EPCS mode by completing the following
steps:
•
Using High-Speed Serial Interfaces Configurator in EPCS Mode
•
Using SERDES Block in EPCS Mode
•
Simulating the SERDES Block in EPCS Mode
•
Creating an Application in EPCS Mode
Revision 3
131
EPCS Interface
Using High-Speed Serial Interfaces Configurator in EPCS Mode
The high-speed serial interfaces configurator (SERDES block configurator) in the Libero SoC
software allows configuring the SERDES block with EPCS mode in Single-protocol mode or 
Multi-protocol mode. The Libero software provides complete register programming to support the 
pre-defined operations. For all data rates, there is a CUSTOM EPCS option within the SERDES block
configurator. This feature allows designers to opportunity to craft customized SERDES implementations.
This implementation requires a high-level of knowledge to program and setup the SERDES block.
Following are the brief descriptions of the configuration options (refer to the "SERDES Block" chapter on
page 7 for details).
Protocol Selection
The following settings are used for protocol selection:
•
Protocol 1 or Protocol 2 Type: Select protocol settings. Select EPCS or PCIe from the drop-down
based on Single-protocol or Multi-protocol mode.
•
Number of Lanes: Select number of lanes used.
•
Speed: Select the lane speed.
•
Protocol 1 or Protocol 2 PHY reference Clock: Select the inputs for the PHY reference clock
selection. Refer to the "SERDES Reference Clock Selection" section on page 137 for more
information on PHY reference clock selection.
Using SERDES Block in EPCS Mode
The SERDES block can be used in customized modes other than PCIe and XAUI. Each SERDES block
includes an EPCS interface enabling the implementation of different protocols for each PHY lane.
The Libero software provides automatic placement results using customized EPCS designs up to 3.125
Gbps. EPCS interfaces require every lane to the fabric and use careful design methods to manage the
timing across the EPCS interfaces, including:
•
Both setup and hold time analysis are required to verify timing on the interfaces.
•
Proper clock connections, pipelining, and floor-planning are required to place F*Fs at specific
locations.
Data Rate below 1Gbps
The native speed of the RTG4 SERDES is between 1 through 3.125 Gbps. Using oversampling, each
data bit is sampled in multiple clock cycles before it is transmitted. For example, to transmit a 400 Mbps
data rate over a 1.2 Gbps serial link, each bit can be sampled three times and spread over three clock
cycles for both transmitting and receiving data, called 3x oversampling. Using this technique, lower data
rates can be transmitted while the SERDES PLL continues to run within its valid operating range (1 Gbps
minimum).
Simulating the SERDES Block in EPCS Mode
The SERDES block, when configured in EPCS requires the RTL simulation model which is selectable in
the High Speed Serial Interfaces Configurator. Refer to the SERDESIF BFM Simulation Guide for details.
Creating an Application in EPCS Mode
An RTG4 EPCS protocol design can be completed using the SERDES block configurator. Libero
promotes the SERDES I/Os to top level and exposes the EPCS parallel interface for each lane into the
FPGA fabric; the SERDES block exposes the APB interface to the FPGA fabric.
Fabric logic or FPGA IP is required to be connected to the EPCS interface as shown in Figure 5-2 on
page 130.
132
R e vi s i o n 3
RTG4 FPGA High-Speed Serial Interfaces
SERDES Block Architecture in EPCS Mode
This section provides an overview of the SERDES block in EPCS mode.
It includes the following:
•
SERDES Block in EPCS Mode
•
SERDES Block Fabric Interface in EPCS Mode
SERDES Block in EPCS Mode
Figure 5-3 shows the SERDES block internal architecture during EPCS Single-protocol mode. EPCS
mode facilitates the use of four lanes of the SERDES which are exposed to the FPGA fabric with a 20-bit
EPCS interface per lane. EPCS mode gives full control over the PLL configurations in the SERDES using
the APB interface to generate the required serial link frequencies. Figure 5-3 shows the SERDES block
in EPCS mode. The EPCS interface is suitable for running any protocol, including Ethernet MAC and
PCS in the FPGA fabric. The PMA block is used for implementing any standard (SRIO, JESD204, etc.) or
user-defined serial protocol.
SERDES
SERDES
I/O
PMA
Ch0
PMA
Control
Logic
SERDES
I/O
PMA
Ch1
PMA
Control
Logic
APB Bus
SERDES
I/O
PMA
Ch2
SERDES
I/O
PMA
Ch3
To Lane01
and Lane23
EPCS Interface
PMA
Control
Logic
PMA
Control
Logic
Figure 5-3 • SERDES Datapath in EPCS Mode
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133
EPCS Interface
SERDES Block Fabric Interface in EPCS Mode
The SERDES block in EPCS mode interfaces with the fabric and differential I/O pads.
The following sections list the fabric interfaces:
•
EPCS interface signals
•
APB interface signals
Table 5-4 • SERDES Block – EPCS Interface
Port
EPCS_0_RESET_N
EPCS_1_RESET_N
EPCS_2_RESET_N
EPCS_3_RESET_N
EPCS_0_READY
EPCS_1_READY
EPCS_2_READY
EPCS_3_READY
EPCS_0_PWRDN
EPCS_1_PWRDN
EPCS_2_PWRDN
EPCS_3_PWRDN
EPCS_0_TX_OOB
EPCS_1_TX_OOB
EPCS_2_TX_OOB
EPCS_3_TX_OOB
EPCS_0_TX_VAL
EPCS_1_TX_VAL
EPCS_2_TX_VAL
EPCS_3_TX_VAL
EPCS_0_TX_DATA[19:0]
EPCS_1_TX_DATA[19:0]
EPCS_2_TX_DATA[19:0]
EPCS_3_TX_DATA[19:0]
Type
Input
Description
Active low PHY RESET. These inputs reset the associated SERDES logic for
each lane. The resets are logically ordered with the power up signal.
PHY ready: This signal is asserted when the PHY has completed the
calibration sequence for each specific lane. This signal can be used to
Output
release the reset for the external PCS and controller, start transmitting data to
the PMA, or any other purpose.
Input
PHY power-down: This signal is used to put the PMA in power-down state
where RX CDR PLL is bypassed and other low power features are applied to
the PMA. When exiting power-down, no calibration is required and the link
can be operational much faster than when using the EPCS_X_TX_OOB or
EPCS_X_RESETN signals.
Input
PHY transmit out-of-band (OOB): This signal is used to load electrical idle 3
in the TX driver of the PMA block. It can be used for serial advanced
technology attachment (SATA) as part of the sequencing for transmitting short
OOB signaling. These signals are active high. Minimum transfer burst size is
23 symbols.
Input
PHY transmit valid: This signal is used to transmit valid data. If de-asserted,
the PMA block is put in electrical idle 1. It can be used for protocols requiring
electrical idle (SATA) and must also be de-asserted when EPCS_X_READY is
not asserted. This signal must be generated one clock cycle earlier than
corresponding EPCS_TXDATA signals.
Input
PHY transmit data: This signal is used to transmit data. This signal is always
20 bits per lane, but the SERDES block only uses the number of bits selected
in the High Speed Serial Interfaces Configurator.
EPCS_0_TX_CLK
EPCS_1_TX_CLK
EPCS_2_TX_CLK
EPCS_3_TX_CLK
PHY transmit clock: This clock signal is generated by the TX PLL in the PMA
block and must be used by the external PCS logic to provide data on
Output
EPCS_X_TX_DATA.
EPCS_0_TX_RESET_N
EPCS_1_TX_RESET_N
EPCS_2_TX_RESET_N
EPCS_3_TX_RESET_N
PHY clean active low reset on the TX clock. This signal is a clean version of
the EPCS_X_RESET_N signal, which has a clean de-assertion timing with
Output
respect to EPCS_TXCLK.
EPCS_0_RX_CLK
EPCS_1_RX_CLK
EPCS_2_RX_CLK
EPCS_3_RX_CLK
PHY receive clock: This clock signal is generated by the RX PLL in the PMA
macro and must be used by the external PCS logic to provide data on
Output
EPCS_X_RX_DATA.
EPCS_0_RX_RESET_N
EPCS_1_RX_RESET_N
EPCS_2_RX_RESET_N
EPCS_3_RX_RESET_N
134
PHY clean active low reset on EPCS_X_RX_CLK.
Output This signal is a clean version of the EPCS_X_RESET_N signal, which has a
clean de-assertion timing with respect to EPCS_X_RX_CLK.
R e vi s i o n 3
RTG4 FPGA High-Speed Serial Interfaces
Table 5-4 • SERDES Block – EPCS Interface (continued)
Port
EPCS_0_RX_VAL
EPCS_1_RX_VAL
EPCS_2_RX_VAL
EPCS_3_RX_VAL
Type
Output
Description
PHY receive valid: This signal is used to signal receive valid data. It
corresponds to the two conditions completed by the PMA control logic:
•
Receiver detects incoming data (not in electrical idle)
•
CDR PLL is locked to the input bit stream in fine grain state
EPCS_0_RX_IDLE
EPCS_1_RX_IDLE
EPCS_2_RX_IDLE
EPCS_3_RX_IDLE
PHY Receive Idle: This signal is used to signal an electrical idle condition
detected by the PMA control logic. This signal is generated on
Output
EPCS_X_TX_CLK of the selected lane.
EPCS_0_RXDATA[19:0]
EPCS_1_RXDATA[19:0]
EPCS_2_RXDATA[19:0]
EPCS_3_RXDATA[19:0]
PHY receive data: This signal is always 20 bits per lane and the external PCS
can use any number of these bits for its application. The SERDES block only
Output
uses the number of bits selected in the High Speed Serial Interfaces
Configurator.
EPCS_0_TX_CLK_STABLE
EPCS_1_TX_CLK_STABLE
EPCS_2_TX_CLK_STABLE
EPCS_3_TX_CLK_STABLE
Output
EPCS_0_RX_ERR
EPCS_1_RX_ERR
EPCS_2_RX_ERR
Input
EPCS_3_RX_ERR
Active high to signal to indicate EPCS interface Lane_X clock is stable, this
indicates that the TX PLL is locked.
EPCS interface Lane_X receiver error is detected when using the external
logic. When there are many receive errors such as, invalid 8b/10b code or
disparity error, then the asynchronous signal can be used to cause the
CDRPLL to switch back to the frequency lock phase.These pins can be
hardwired to 0, and rely only on Electrical Idle detection to switch the CDR
PLL back to frequency lock state.
In EPCS modes, these ports are optionally configured to send any of the
following signals out of SERDES block on to the dedicated Global Clock
Structures:
GLOBAL_0_OUT
GLOBAL_1_OUT
•
Output •
•
EPCS_0_ARXSKIPBIT
EPCS_1_ARXSKIPBIT
EPCS_2_ARXSKIPBIT
Logic 0
•
Logic 1
Input
Input
EPCS Transmit Interface FIFO write clock for EPCS lane [0:3]. Write clock to
the transmit Fly-Wheel-FIFO used to decouple the phase of the FPGA clock
from the SERDES transmit clock. Use of the Fly-Wheel-FIFO makes the
FPGA timing closure easier on the EPCS_TX_DATA[n:0] by removing the
round trip time of the clock from the SERDES to the fabric clock resource and
back to the SERDES to capture the data.
EPCS_0_TXFWF_WCLK
EPCS_1_TXFWF_WCLK
EPCS_3_TXFWF_WCLK
SPLL_CLK
•
EPCS Receive Interface FIFO read clock for EPCS lane [0:3]. Read clock of
the receive Fly-Wheel-FIFO used to decouple the phase of the FPGA clock
from the SERDES receiver clock. Use of the Fly-Wheel-FIFO makes FPGA
timing closure easier on the EPCS_RX_DATA[n:0] by using the same clock
to launch and capture data into the fabric.
EPCS_3_RXFWF_RCLK
EPCS_2_TXFWF_WCLK
•
Input
EPCS_0_RXFWF_RCLK
EPCS_2_RXFWF_RCLK
EPCS_TXCLK[3:0]
REFCLK[P:N]
EPCS PMA slip bit for lane [0:3]. Asynchronous rising edge active signal,
which shifts the CDR high-speed clock to the next high speed bit. This can be
used to shift the EPCS_RX_DATA[n:0] to the left by 1 bit until the proper word
alignment is found.
EPCS_3_ARXSKIPBIT
EPCS_1_RXFWF_RCLK
EPCS_RXCLK[3:0]
Revision 3
135
EPCS Interface
Table 5-4 • SERDES Block – EPCS Interface (continued)
Port
Type
EPCS_FAB_REF_CLK
Input
Description
Available when Fabric is selected as the Reference Clock Source in the
Configurator.
Reset and Clocks
This section describes the functional aspects of the reset and clock circuitry inside the SERDES block in
EPCS mode.
The following topics are covered:
•
EPCS Mode Clocking
•
EPCS Mode Reset Network
EPCS Mode Clocking
When the SERDES block is configured in EPCS mode, it has multiple clock inputs and outputs. This
section describes the EPCS clocking scheme.
SERDES Block Clock Network in EPCS
Figure 5-4 on page 136 shows the SERDES block clock network in EPCS mode. In EPCS mode, data is
exchanged between the fabric and SERDES block. The SERDES PMA has two PLLs (Tx PLL and CDR
PLL) that generate the required clock frequency and send 4-Rx and 4-Tx clocks for each lane through
the EPCS interface. User design is required to use these clocks within the FPGA fabric, in custom logic
or FPGA IP, to transfer data between SERDES block and FPGA fabric. There is an additional clock
(asynchronous) dedicated to the APB interface, called APB_S_CLK, used for accessing the SERDES
block registers.The user has the option to connect several clock outputs from SERDES Blocks to two
available global clock structures within the FPGA fabric. GLOBAL_[0:1]_OUT ports are available per
SERDES block and can be programmed to expose the EPCS_RXCLK[3:0], EPCS_TXCLK[3:0],
REFCLK[0:1], or SPLL_CLK to the global fabric routing.
An EPCS transmit and receive interface FIFO is available in the data path permitting relaxation of the
clock phase relationship between the fabric logic and EPCS block. Without the use of interface FIFO,
only the local clocks provided directly from the PMA block and EPCS data must have their timing
relationships tightly controlled.
Whereas the EPCS fabric interface Tx/Rx FIFO permits the fabric clock to have lesser timing restrictions
while exposing the FIFO WRITE and READ (EPCS_#_TXFWF_WCLK and EPCS_#_RXFWF_RCLK)
clocks.
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Figure 5-4 • SERDES Block Clocking in EPCS Mode
136
R e vi s i o n 3
RTG4 FPGA High-Speed Serial Interfaces
Table 5-5 lists the various clocks in EPCS mode. Table 5-5 • Clock Signals in EPCS Mode
Clock Signal
Description
aREFCLK
Reference clock for SERDES
EPCS_X_TX_CLK
EPCS interface LaneX (X = 0, 1, 2, 3) Tx Clock
EPCS_X_RX_CLK
EPCS interface LaneX (X = 0, 1, 2, 3) Rx Clock
APB_S_CLK
PCLK for APB interface
REFCLK_P 
REFCLK_N
Differential reference clock input I/O to REFCLK_0 port (REFCLK_1 is not available
with differential clock input)
REFCLK_IO0
Single-ended reference clock input to either Lanes[0:1] or Lanes[2:3]
REFCLK_IO1
Single-ended reference clock input to either Lanes[0:1] or Lanes[2:3]
EPCS_FAB_REF_CLK
Fabric reference clock for SERDES PMA
SERDES Reference Clock Selection
The PMA in the SERDES block needs a reference clock on each of its lanes for Tx and Rx clock
generation through the PLLs. It has three options for the reference clock.Two REFCLK I/O pad options or
from the FPGA fabric. Lane0 and lane1 share the same reference clock; lane2 and lane3 share the same
reference clock, or alternatively the same clock can be shared among all four lanes. The reference clock
pads are differential input.
The reference clock selection in the SERDES block Configurator is available in Libero. I/O Port0 selects
REFCLK.
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Figure 5-5 • SERDES Reference Clock Options for EPCS Modes
EPCS Mode Reset Network
Figure 5-6 shows the reset network for the EPCS interface x4 lanes implementation. The resets for all
four lanes (EPCS_0_RESET_N, EPCS_1_RESET_N, EPCS_2_RESET_N, and EPCS_3_RESET_N)
are gated with the power valid signal from RTG4 program control and again with
SERDES_LANEx_SOFTRESET (x = 0, 1, 2, 3).
The SERDES_LANEx_SOFTRESET signals are controlled by the "SERDES Block System Register",
SERDES_Block_SOFT_RESET, (active low reset signal for each lane), which can be programmed using
the APB interface. On the output side, the SERDES block in EPCS mode generates 4 sets of reset
signals, and one for each lane. Table 5-6 on page 138 describes the reset signals and recommended
connections.
Revision 3
137
EPCS Interface
Fabric
EPCS_0_RX_RESET_N
EPCS_1_RX_RESET_N
EPCS_2_RX_RESET_N
EPCS_3_RX_RESET_N
Power-Up
SERDES Block
EPCS_0_RESET_N
SERDES_LANE0_SOFTRESET
EPCS_2_RESET_N
SERDES_LANE1_SOFTRESET
SERDES
(PMA only)
I/O PADS
EPCS_1_RESET_N
SERDES_LANE2_SOFTRESET
EPCS_3_RESET_N
SERDES_LANE3_SOFTRESET
APB_S_PRESET_N
EPCS_0_TX_RESET_N
EPCS_1_TX_RESET_N
EPCS_2_TX_RESET_N
EPCS_3_TX_RESET_N
Figure 5-6 • SERDES Block Reset Signals in EPCS Mode
Table 5-6 • SERDES Block Reset Signals in EPCS Mode
Port
Type
EPCS_X_RESET_N
Input
EPCS interface LaneX (X = 0, 1, 2, 3) clean reset, de-asserted on
EPCS_X_RX_CLK. The clean resets are the EPCS_X_Rx_RESET_N
and EPCS_X_Tx_RESET_N output signals.
Description
APB_S_PRESET_N
Input
APB asynchronous reset to all APB registers
EPCS_X_Rx_RESET_N
Output
EPCS interface LaneX (X = 0, 1, 2, 3) reset output, de-asserted on
EPCS_X_RX_CLK
EPCS_X_Tx_RESET_N
Output
EPCS interface LaneX (X = 0, 1, 2, 3) reset output, deasserted on
EPCS_X_TX_CLK
EPCS SERDES Calibration and External Resistor Configuration
An external resistor is required for the PMA block to perform an impedance calibration (transmit, receive,
and receiver equalization). The external resistor input signal must be connected to the
SERDES_PCIE_#_L[01][23]_REXT pads. The end of the calibration is signaled by the PMA block
through the EPCS_READY signal. Refer to the "SERDES Block" chapter on page 7 for detail.
138
R e vi s i o n 3
RTG4 FPGA High-Speed Serial Interfaces
Glossary
Acronyms
AXI3
Advanced extensible interface
EP
Endpoint
FPGA
Field programmable gate array
PCI Express
Peripheral component interconnect express
PCIe
PCI Express
SERDES
Serializer/de-serializer
XAUI
Extended attachment unit interface
EPCS
External Physical Coding Sublayer
Revision 3
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6 – SERDES Block Register Access Map
Configuration of SERDES Block
The SERDES block contains a large number of internal registers required to properly configure the
SERDES block module. The register settings provide initial programming at power-up and most portions
of the SERDES block can be dynamically reconfigured while in operation. A SERDES block APB
configuration interface is accessed through the FPGA fabric providing the resources to allow these
programming capabilities. The RTG4 uses a FPGA module to initialize peripherals and access the
system controller. An initialization module provides connectivity to the AHB bus matrix allowing similar
SERDES block initialization using this FPGA IP module in the fabric. It supports the SERDES block
peripheral using the Libero SoC software to correctly provision and program the user customized
features.
1 KB
0x23FF
SERDES Block System Register
(1 KB)
4 KB
4 KB
0x2000
SERDES Block Register
Lane 3 (1 KB)
0x1C00
SERDES Block Register
Lane 2 (1 KB)
0x1800
SERDES Block Register
Lane 1 (1 KB)
0x1400
SERDES Block Register
Lane 0 (1 KB)
0x1000
PCIe Core
Bridge Register
(4 KB)
0x0000
Figure 6-1 • SERDES Block Memory Map
Refer to the "PCI Express" chapter on page 41 for more information on the PCIe core register.
The SERDES block has three sets of configuration and status registers. Configuration of the SERDES
block is done through these registers. Configuration of top-level functionality of the PCIe core, XAUI
block, and SERDES block is also done through these registers. The three regions of configuration and
status registers shown in Figure 6-1 on page 140 are described in the next section.
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Figure 6-2 shows the APB implementation of three sets of configuration and status registers. The APB
decoder is an interface for the FPGA fabric to access these registers.
SERDES Block
APB 32
SERDES Block
System Register
A
P
B
APB 32
Interface
APB
DECODER
I
N
T
E
R
F
A
C
E
PCIe SYSTEM
APB 32
PCIe Core Register
SERDES
APB 32
APB to SERDES
Interface
Native
8-bit
Interface
SERDES Macro
Register
Figure 6-2 • Address Decoder Logic Block Diagram
SERDES Block System Register
The SERDES block system register controls the SERDES block module for single protocol or multiprotocol support implementation. It occupies 1 KB of the configuration memory map. The physical offset
location of the SERDES block system register is 0x2000-0x23FF from the SERDES block subsystem
memory map. These registers can be accessed through the 32-bit APB interface, and the default values
of these registers can be configured using Libero SoC. These flash bits have the settings for registers
that require to be initialized quickly when the device powers up such as PLL and clock configurations,
PCIe configuration space, and resets. The flash bits are set by the Libero configuration GUI based on the
user selections, programmed into the device, and are statically set at device power-up. However, the
SERDES block system registers can be updated through the 32-bit APB interface, if required.
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Table 6-1 • Mode Settings Using the SERDES Block System APB Registers
SERDES Block System
APB 
Registers
Description
CONFIG_PHY_MODE[15:12] For each lane, this register selects the protocol default settings, which sets the reset
value of the register space.
CONFIG_PHY_MODE [15:12] - Defines lane3 settings
0000: PCIe mode lane3
0001: XAUI1 mode lane3
0011: Reserved lane3
0100: Reserved lane3
0101: EPCS (custom) mode lane3
1111: SERDES PHY lane3 is off
CONFIG_PHY_MODE[11:8] CONFIG_PHY_MODE [11:8] - Defines lane2 settings
0000: PCIe mode lane2
0001: XAUI mode lane2
0011: Reserved lane2
0100: Reserved lane2
0101: EPCS (custom) mode lane2
1111: SERDES PHY lane2 is off
CONFIG_PHY_MODE[7:4]
CONFIG_PHY_MODE [7:4] - Defines lane1 settings
0000: PCIe mode lane1
0001: XAUI mode lane1
0011: Reserved lane1
0100: Reserved lane1
0101: EPCS (custom) mode lane1
1111: SERDES PHY lane1 is off
CONFIG_PHY_MODE[3:0]
CONFIG_PHY_MODE [3:0] - Defines lane0 settings
0000: PCIe mode lane0
0001: XAUI mode lane0
0011: Reserved lane0
0100: Reserved lane0
0101: EPCS (custom) mode lane0
1111: SERDES PHY lane0 is off
Notes:
1. XAUI = 10 Gbps attachment unit interface
2. EPCS = External physical coding sub-layer including SGMII mode
3. 0010: Reserved Setting for all lanes
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Table 6-1 • Mode Settings Using the SERDES Block System APB Registers (continued)
SERDES Block System
APB 
Registers
CONFIG_EPCS_SEL[3:0]
Description
For each lane, one bit of this register defines whether the external PCS interface is
used or the PCIe PCS is enabled:
0: PCIe mode
1: External PCS mode
CONFIG_EPCS_SEL [3]: External PCS selection associated with lane3
CONFIG_EPCS_SEL [2]: External PCS selection associated with lane2
CONFIG_EPCS_SEL [1]: External PCS selection associated with lane1
CONFIG_EPCS_SEL [0]: External PCS selection associated with lane0
CONFIG_LINK2LANE[3:0]
This register is used in PCIe mode to select the association of lane to link. The four bits
refer to four lanes.
Notes:
1. XAUI = 10 Gbps attachment unit interface
2. EPCS = External physical coding sub-layer including SGMII mode
3. 0010: Reserved Setting for all lanes
Table 6-2 • SERDES Block System Registers
Register Name
Address Register
Offset
Type
Description
SYSTEM_SER_PLL_CONFIG_LO
W (0x2000)
0x00
R/W
Sets SERDES PLL (SPLL) configuration bits (LSBs).
SYSTEM_SER_PLL_CONFIG_HI
GH (0x2004)
0x04
R/W
Sets SPLL configuration bits (MSBs).
SYSTEM_SER_SOFT_RESET
(0x2008)
0x08
R/W
PCIe controller, XAUI, and SERDES lanes soft RESET
SYSTEM_SER_INTERRUPT_ENA
BLE (0x200C)
0x0C
R/W
SPLL lock interrupt enable
SYSTEM_CONFIG_AXI_AHB_BRI
DGE (0x2010)
0x10
R/W
Defines whether AXI3/AHB master interface is implemented
on the master interface to fabric.
SYSTEM_CONFIG_ECC_INTR_E
NABLE (0x2014)
0x14
R/W
Sets ECC enable and ECC interrupt enable for PCIe
memories.
Reserved
0x18
R/W
Reserved
Reserved
0x1C
R/W
Reserved
SYSTEM_CONFIG_PCIE_PM
(0x2020)
0x 20
R/W
Used to inform the configuration space, the slot power, PHY
reference clock, Power mode and so on.
SYSTEM_CONFIG_PHY_MODE_
0 (0x2024)
0x24
R/W
Selects the protocol default settings of the PHY.
SYSTEM_CONFIG_PHY_MODE_
1 (0x2028)
0x 28
R/W
Selects PCS mode, link to lane settings.
Notes:
1. Refer to the individual register description for the reset value.
2. R/W: Read and write allowed R/O: 0 Read only
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Table 6-2 • SERDES Block System Registers (continued)
Register Name
Address Register
Offset
Type
Description
SYSTEM_CONFIG_PHY_MODE_
2 (0x202C)
0x2C
R/W
Sets the equalization calibration performed by the PMA
control logic of the lane or use the calibration result of
adjacent lane.
SYSTEM_CONFIG_PCIE_0
(0x2030)
0x30
R/W
Defines PCIe vendor ID and device ID for PCIe identification
registers.
SYSTEM_CONFIG_PCIE_1
(0x2034)
0x34
R/W
Defines PCIe subsystem vendor ID and subsystem device ID
for PCIe identification registers.
SYSTEM_CONFIG_PCIE_2
(0x2038)
0x38
R/W
Defines PCIe subsystem revision ID and class code.
SYSTEM_CONFIG_PCIE_3
(0x203C)
0x3C
R/W
Sets PCIe link speed.
SYSTEM_CONFIG_BAR_SIZE_0_
1 (0x2040)
0x40
R/W
Sets BAR0 and BAR1 of PCIe core register map.
SYSTEM_CONFIG_BAR_SIZE_2_
3 (0x2044)
0x44
R/W
Sets BAR2 and BAR3 of PCIe core register map.
SYSTEM_CONFIG_BAR_SIZE_4_
5 (0x2048)
0x48
R/W
Sets BAR4 and BAR5 of PCIe core register map.
SYSTEM_SER_CLK_STATUS
(0x204C)
0x4C
R/O
This register describes SPLL lock information.
Reserved
0x50
R/O
–
Reserved
0x54
R/O
–
SYSTEM_SER_INTERRUPT
(0x2058)
0x58
R/O
SPLL/FPLL lock interrupt
SYSTEM_SERDES_INTR_STATU
S Register (0x205C)
0x5C
R/O
SECDED interrupt status for PCIe memories
Reserved
0x60
–
SYSTEM_REFCLK_SEL (0x2064)
0x64
R/W
Reference clock selection for the four lanes of PMA.
SYSTEM_PCLK_SEL Register
(0x2068)
0x68
R/W
PCIe core clock selection
SYSTEM_EPCS_RSTN_SEL
(0x206C)
0x6C
R/W
EPCS reset register selection from fabric
SYSTEM_PCIE_ENABLE (0x2070)
0x70
R/O
PCIE enable
SYSTEM_SERDES_TEST_OUT
(0x2074)
0x74
R/O
Status Test out output of PCIe PHY
SYSTEM_SERDES_FATC_RESET
(0x2078)
0x78
R/W
Fabric alignment test circuit – reset input
SYSTEM_RC_OSC_SPLL_REFCL
K_SEL (0x207C)
0x7C
R/W
Reference clock selection for SPLL
SYSTEM_SPREAD_SPECTRUM_
CLK (0x2080)
0x80
R/W
Spread spectrum clocking configuration
–
Notes:
1. Refer to the individual register description for the reset value.
2. R/W: Read and write allowed R/O: 0 Read only
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Table 6-2 • SERDES Block System Registers (continued)
Register Name
Address Register
Offset
Type
Description
SYSTEM_CONF_AXI_MSTR_WN
DW_0 (0x2084)
0x84
R/W
PCIe AXI3-master window0 configuration register – 0
SYSTEM_CONF_AXI_MSTR_WN
DW_1 (0x2088)
0x88
R/W
PCIe AXI3-master window0 configuration register – 2
SYSTEM_CONF_AXI_MSTR_WN
DW_2 (0x208C)
0x8C
R/W
PCIe AXI3-master window0 configuration register – 2
SYSTEM_CONF_AXI_MSTR_WN
DW_3 (0x2090)
0x90
R/W
PCIe AXI3-master window0 configuration register – 3
SYSTEM_CONF_AXI_SLV_WND
W_0 (0x2094)
0x94
R/W
PCIe AXI3-slave window0 configuration register – 0
SYSTEM_CONF_AXI_SLV_WND
W_1 (0x2098)
0x98
R/W
PCIe AXI3-slave window0 configuration register – 1
SYSTEM_CONF_AXI_SLV_WND
W_2 (0x209C)
0x9C
R/W
PCIe AXI3-slave window0 configuration register – 2
SYSTEM_CONF_AXI_SLV_WND
W_3 (0x20A0)
0xA0
R/W
PCIe AXI3-slave window0 configuration register – 4
SYSTEM_DESKEW_CONFIG
(0x20A4)
0xA4
R/W
PLL REF clock DESKEW register
SYSTEM_IDDQ (0x20b0)
0xb0
R/W
Puts the PMA in the IDDQ mode. IDDQ mode minimizes
power consumption when the PMA is not used. Bit0:Lane 0,
Bit1:Lane 1, Bit2:Lane2, Bit 3:Lane 3.
SYSTEM_ADVCONFIG (0x20b4)
0xb4
R/W
Advanced Mode setting for PCI controller.
SYSTEM_REFCLK_MSIO_CONFI
G (0x20c4)
0xc4
R/W
Configure Multi-Standard Reference clock.
SYSTEM_ENHANCEMENT
(0x20c8)
0xc8
R/W
Enhancement setting. This is used in conjunctions with the
RX_SLIP word alignment operation.
SYSTEM_TXFWF_CONFIG
(0x20cc)
0xcc
R/W
TX Fly-Wheel FIFO Configuration.
SYSTEM_RXFWF_CONFIG
(0x20d0)
0xd0
R/W
RX Fly-Wheel FIFO Configuration.
Notes:
1. Refer to the individual register description for the reset value.
2. R/W: Read and write allowed R/O: 0 Read only
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Table 6-3 • SYSTEM_SER_PLL_CONFIG_LOW (0x2000)
Bit
Number
18:16
Reset
Value
Name
PLL_OUTPUT_DIVISOR
0x1
Description
These bits set SPLL output divider value:
000: ÷1
001: ÷2
010: ÷4
011: ÷8
15:6
PLL_FEEDBACK_DIVISOR
0x2
These bits set SPLL feedback divider value (SSE = 0) 
(binary value + 1)
0000000000: ÷1
0000000001: ÷2
0000000010: ÷3
…
1111111111: ÷1,025
5:0
PLL_REF_DIVISOR
0x2
These bits set SPLL reference divider value (binary value+1):
000000: ÷1
000001: ÷2
000010: ÷3
…
111111: ÷65
Both REFCK and post-divide REFCK must be within the range
specified in the PLL datasheet.
Table 6-4 • SYSTEM_SER_PLL_CONFIG_HIGH (0x2004)
Bit
Number
Name
Reset
Value
16
PLL_PD
0x0
15
PLL_FSE
0x0
Description
A power-down (PD) register is provided for lowest quiescent current. When
PD is asserted, the PLL powers down and outputs are low. PD has
precedence over all other functions.
This register chooses between internal and external input paths:
0: Feedback (FB) pin input
1: Internal feedback
FB must be tied off (High or Low) and not left floating when FSE is High. FB
must connect directly or through the clock tree to PLLOUT when FSE is low.
SSE is ineffective when FSE = 0. If the FACC source multiplexer is
configured to select a clock other than the PLL output clock, then the
fddr_pll_fse register must be set to 1, when the PLL is powered up.
14
PLL_MODE_3V3
0x1
Analog voltage selection
1: 3.3 V
0: Reserved
Note: All the registers are 32-bit. Bits not shown in the table are reserved.
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Table 6-4 • SYSTEM_SER_PLL_CONFIG_HIGH (0x2004) (continued)
Bit
Number
13
Name
PLL_MODE_1V2
Reset
Value
0x1
Description
Core voltage selection
1: 1.2 V
0: Reserved
12
PLL_BYPASS
0x1
A bypass register is provided which both powers down the PLL core and
bypasses it as that PLLOUT tracks REFCK. Bypass has precedence over
reset. Microsemi recommends that either Bypass or reset are asserted until
all configuration controls are set in the desired working value; the power
supply and reference clocks are stable within operating range, and the
feedback path is functional. Either bypass or reset may be used for powerdown IDDQ testing.
11
PLL_RESET
0x1
PLL reset (asserted high).
10:7
PLL_LOCKCNT
0xF
These bits contain lock counter value (2^ (binary value + 5)):
0000: 32
0001: 64
…
1111: 1048576
The above mentioned lock counter values represent the number of reference
cycles present before the lock is asserted or detected.
Note: All the registers are 32-bit. Bits not shown in the table are reserved.
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Table 6-4 • SYSTEM_SER_PLL_CONFIG_HIGH (0x2004) (continued)
Bit
Number
6:4
Name
PLL_LOCKWIN
Reset
Value
0x0
Description
These bits contain phase error window for lock assertion as a fraction of
divided reference period:
000: 500 ppm
100: 8000 ppm
001: 1000 ppm
101: 16000 ppm
010: 2000 ppm
110: 32000 ppm
011: 4000 ppm
111: 64000 ppm
Values are at typical process, voltage, and temperature (PVT) only and are
not PVT compensated.
3:0
PLL_FILTER_RANGE
0x9
These bits contain PLL filter range (frequency range after PLL reference
input dividers to the phase-frequency detector):
0000: BYPASS
0111: 18–29 MHz
0001: 1–1.6 MHz
1000: 29–46 MHz
0010: 1.6–2.6 MHz
1001: 46–75 MHz
0011: 2.6–4.2 MHz
1010: 75–120 MHz
0100: 4.2–6.8 MHz
1011: 120–200 MHz
0101: 6.8–11 MHz
0110: 11–18 MHz
Note: All the registers are 32-bit. Bits not shown in the table are reserved.
Table 6-5 • SYSTEM_SER_SOFT_RESET (0x2008)
Bit
Number
Name
Reset
Value
Description
5
SERDES_LANE3_SOFTRESET
0x1
SERDES lane3 soft reset
4
SERDES_LANE2_SOFTRESET
0x1
SERDES lane2 soft reset
3
SERDES_LANE1_SOFTRESET
0x1
SERDES lane1 soft reset
2
SERDES_LANE0_SOFTRESET
0x1
SERDES lane0 soft reset
1
XAUI_CTLR_SOFTRESET
0x1
XAUI controller soft reset
0
PCIE_CTLR_SOFTRESET
0x1
PCIe controller soft reset
Note: All the registers are 32-bit. Bits not shown in the table are reserved.
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Table 6-6 • SYSTEM_SER_INTERRUPT_ENABLE (0x200C)
Bit
Number
Name
Reset
Value
3
FPLL_LOCKLOST_INT_ENABLE
0x0
This bit sets FPLL lock lost interrupt output enable.
2
FPLL_LOCK_INT_ENABLE
0x0
This bit sets FPLL lock interrupt output enable.
1
SPLL_LOCKLOST_INT_ENABLE
0x0
This bit sets SERDES PLL lock lost interrupt output enable.
0
SPLL_LOCK_INT_ENABLE
0x0
This bit sets SERDES PLL lock interrupt output enable.
Description
Table 6-7 • SYSTEM_CONFIG_AXI_AHB_BRIDGE (0x2010)
Bit
Number
1
Name
CFGR_AXI_AHB_MASTER
Reset
Value
0x1
Description
Defines whether AXI3/AHB slave interface is implemented on
the master interface to fabric.
0: AHB, 32-bit AHB slave implemented in fabric
1: AXI3, 64-bit AXI3 slave implemented in fabric
0
CFGR_AXI_AHB_SLAVE
0x1
Defines whether AXI3/AHB master interface is implemented
on the slave interface to fabric.
0: AHB, 32-bit AHB master implemented in fabric
1: AXI3, 64-bit AXI3 master implemented in fabric
Table 6-8 • SYSTEM_CONFIG_ECC_INTR_ENABLE (0x2014)
Bit
Number
7:4
Name
CFGR_PCIE_ECC_INTR_EN
Reset
Value
0x7
Description
This bit sets the ECC interrupt enable for PCIe Tx, Rx, and Rp
memories.
Bit 0
1: Rp - ECC interrupt enabled
0: ECC interrupt disabled
Bit 1
1: Rx - ECC interrupt enabled
0: ECC interrupt disabled
Bit 2
1: Tx - ECC interrupt enabled
0: ECC interrupt disabled
3:0
CFGR_PCIE_ECC_EN
0x7
This bit sets the ECC enable for PCIe Tx, Rx, and Rp
memories.
Bit 0
1 - Rp - ECC enabled- 1'b0: ECC – disabled
Bit-1: 1'b1 - Rx - ECC enabled- 1'b0: ECC – disabled
Bit-2: 1'b1 - Tx - ECC enabled- 1'b0: ECC – disabled
Table 6-9 • Reserved Register (0x2018)
Bit
Number
–
Name
Reset
Value
Description
Reserved
0x0
–
Note: All registers are 32-bit. Bits not shown in the table are reserved.
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Table 6-10 • Reserved Register (0x201C)
Bit
Number
–
Name
Reset
Value
Description
Reserved
0x0
–
Table 6-11 • SYSTEM_CONFIG_PCIE_PM (0x2020)
Bit
Number
3
Name
CFGR_TX_SWING
Reset
Value
0x0
Description
Transmit swing: This register is per-link, which is generated
by each link PCIe. The PCS logic performs the internal
mapping of link to lanes.
Note: This is only for PCIe Gen2 controller, not for PCIe
GEN1 controller.
2
CFGR_L2_P2_ENABLE
0x0
L2/P2 enable.
1'b1: Enable L2/P2 (Default-L2P2-Enabled)
1'b0: Disable L2/P2
If L2/P2 is enabled, cfgr_pm_auxpwr must also be enabled.
1
CFGR_PM_AUX_PWR
0x0
Slot auxiliary power: This register specifies whether the
device uses the slot auxiliary power source. This is used only
used if the core supports D3 cold.
1'b1: Auxiliary power source available. Default L2P2-Enabled.
1'b0: Auxiliary power source unavailable.
0
CFGR_SLOT_CONFIG
0x0
Slot clock configuration: This register is used only to inform
the configuration space, if the reference clock of the PHY is
same as that of the slot.
0: Independent clock
1: Slot clock
This is synchronous to CLK.
Note: All registers are 32-bit. Bits not shown in the table are reserved.
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Table 6-12 • SYSTEM_CONFIG_PHY_MODE_0 (0x2024)
Bit
Number
15:0
Name
CONFIG_PHY_MODE
Reset
Value
0x0
Description
For each lane, this register selects the protocol default settings of the
PHY, which sets the reset value of the registers space. For instance,
the following mapping is associated to a four lane PHY:
phy_mode[3:0]: Mode associated to lane0
phy_mode[7:4]: Mode associated to lane1
phy_mode[11:8]: Mode associated to lane2
phy_mode[15:12]: Mode associated to lane3
PHY_MODE settings:
4'b0000 - PCIE mode
4'b0001 - XAUI mode
4'b0010 - Reserved
4'b0011 - Reserved
4'b0100 - Reserved
4'b0101 - EPCS (custom) mode
4'b1111 - SERDES PHY lane is off
Table 6-13 • SYSTEM_CONFIG_PHY_MODE_1 (0x2028)
Bit
Number
Name
Reset
Value
11:8
CONFIG_REG_LANE_SEL
0xF
Lane select: This register defines which lanes are accessed and
must be one-hot encoded for read transaction. For write transaction,
one or several lanes can be written in the same time when several
bits are asserted. Each bit represents a SERDES Lane. The default
allows all lanes to be selected to be written. A 0b deselects the
registers for a specific lane to not be written.
7:4
CONFIG_LINKK2LANE
0xF
This register is used in PCIe mode in order to select the association
of lane to link and must be one-hot encoded (each lane can be
associated only to one link).
Description
For example, a four lane PHY, which can be configured in 1 or 2 link
might have
•
pipe_lk2ln[3:0]: lane associated to link 0
•
pipe_lk2ln[7:4]: lane associated to link 1
Note: This signal must be static at power-up or stable before reset
de-assertion.
3:0
CONFIG_EPCS_SEL
0x0
For each lane, one bit of this signal defines whether the external
PCS interface is used or the PCIe PCS is enabled:
0b: PCIe mode
1b: External PCS mode
For instance, the mapping associated to a four lane PHY is:
epcs_sel[0]: External PCS selection associated to lane0
epcs_sel[1]: External PCS selection associated to lane1
epcs_sel[2]: External PCS selection associated to lane2
epcs_sel[3]: External PCS selection associated to lane3
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Table 6-14 • SYSTEM_CONFIG_PHY_MODE_2 (0x202C)
Bit
Number
7:0
Name
CONFIG_REXT_SEL
Reset
Value
0x0
Description
For each lane, 2 bits of this signal select whether the Tx, Rx, and Rx
equalization calibration is performed by the PMA control logic of the
lane or use the calibration result of adjacent lane (upper or lower
lanes):
00b: perform calibration using the lane calibration algorithm, which
also requires that the Rext resistor is present on board
01b: use calibration result of lower lane
10b: use calibration result of upper lane
11b: reserved
Note: All registers are 32-bit. Bits not shown in the table are reserved.
Table 6-15 • SYSTEM_CONFIG_PCIE_0 (0x2030)
Bit
Number
Name
Reset
Value
Description
31:16
PCIE_DEVICE_ID
0x0
Specifies hardwired settings for PCIe identification registers: Defines
PCIe device ID.
15:0
PCIE_VENDOR_ID
0x0
Specifies hardwired settings for PCIe identification registers: Defines
PCIe vendor ID.
Table 6-16 • SYSTEM_CONFIG_PCIE_1 (0x2034)
Bit
Number
Name
Reset
Value
Description
31:16
PCIE_SUB_DEVICE_ID
0x0
Specifies hardwired settings for PCIe identification registers: Defines
PCIe subsystem device ID.
15:0
PCIE_SUB_VENDOR_ID
0x0
Specifies hardwired settings for PCIe identification registers: Defines
PCIe subsystem vendor ID.
Table 6-17 • SYSTEM_CONFIG_PCIE_2 (0x2038)
Bit
Number
Name
Reset
Value
Description
31:16
PCIE_CLASS_CODE
0x0
Specifies hardwired settings for PCIe identification registers: Defines
PCIe class code.
15:0
PCIE_REV_ID
0x0
Specifies hardwired settings for PCIe identification registers: Defines
PCIe revision ID.
Note: All registers are 32-bit. Bits not shown in the table are reserved.
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Table 6-18 • SYSTEM_CONFIG_PCIE_3 (0x203C)
Bit
Number
Name
Reset
Value
Description
5:2
K_BRIDGE_SPEC_REV
0x0
Reserved
1
K_BRIDGE_EMPH
0x0
Reserved
0
K_BRIDGE_SPEED
0x0
Reserved
Table 6-19 • SYSTEM_CONFIG_BAR_SIZE_0_1 (0x2040)
Bit
Number
17:13
Name
CONFIG_BAR_SIZE_1
Reset
Value
0x0
Description
These bits set the size of the BAR1 memory. For example, 32-bit
BAR:
CONFIG_BAR_SIZE_1 - 5'd21 translates to BAR0 - (2 MB)
"1111_1111_1110_0000_0000_0000_0000_CONFIG_BAR_CO
NTROL_1"
12:9
CONFIG_BAR_CONTROL_1
0x0
LSB bits of BAR1 register in PCIe core register map
Bit0: Memory/IO type indicator
Bit[2:1]: Size of memory, 00-32-bit memory, 10 - 64-bit memory
Bit3: Prefetchable/non-prefetchable memory
8:4
CONFIG_BAR_SIZE_0
0x0
These bits set the size of the BAR0 memory. For example, 32-bit
BAR:
CONFIG_BAR_SIZE_0 - 5'd20 translates to BAR0 - (1 MB)
"1111_1111_1111_0000_0000_0000_0000_CONFIG_BAR_CO
NTROL_0"
3:0
CONFIG_BAR_CONTROL_0
0x0
LSB bits of BAR 0 register in PCIe core register map
Bit0: Memory/IO type indicator
Bit[2:1]: Size of memory, 00-32-bit memory, 10 - 64-bit memory
Bit3: Prefetchable/non-prefetchable memory
Note: All registers are 32-bit. Bits not shown in the table are reserved.
Table 6-20 • SYSTEM_CONFIG_BAR_SIZE_2_3 (0x2044)
Bit
Number
17:13
Name
CONFIG_BAR_SIZE_3
Reset
Value
0x0
Description
These bits set the size of the BAR3 memory.
For example, 32-bit BAR:
CONFIG_BAR_SIZE_3 - 5'd23 translates to BAR3 - (8 MB)
"1111_1111_1000_0000_0000_0000_0000_CONFIG_BAR_CON
TROL_3"
12:9
CONFIG_BAR_CONTROL_
3
0x0
[3:0] LSB bits of BAR 3 register in PCIe core register map
Bit0: Memory/IO type indicator
Bit[2:1]: Size of memory, 00-32-bit memory, 10-64-bit memory
Bit3: Prefetchable/non-prefetchable memory
153
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Table 6-20 • SYSTEM_CONFIG_BAR_SIZE_2_3 (0x2044) (continued)
Bit
Number
8:4
Reset
Value
Name
CONFIG_BAR_SIZE_2
0x0
Description
These bits set the size of the BAR2 memory.
For example, 32-bit BAR:
CONFIG_BAR_SIZE_2 - 5'd22 translates to BAR0 - (4 MB)
"1111_1111_1100_0000_0000_0000_0000_CONFIG_BAR_CON
TROL_2"
3:0
CONFIG_BAR_CONTROL_
2
0x0
[3:0] LSB bits of BAR 2 register in PCIe core register map
Bit0: Memory/IO type indicator
Bit[2:1]: Size of memory, 00-32-bit memory, 10 - 64-bit memory
Bit3: Prefetchable/non-prefetchable memory
Table 6-21 • SYSTEM_CONFIG_BAR_SIZE_4_5 (0x2048)
Bit
Number
17:13
Name
Reset
Value
CONFIG_BAR_SIZE_5
0x0
Description
These bits set the size of the BAR5 memory.
For example, 32-bit BAR:
CONFIG_BAR_SIZE_5 - 5'd25 translates to BAR5 - (32 MB)
"1111_1110_0000_0000_0000_0000_0000_CONFIG_BAR_CONT
ROL_5"
12:9
CONFIG_BAR_CONTROL_
5
0x0
[3:0] LSB bits of BAR 5 register in PCIe core register map
Bit0: Memory/IO type indicator
Bit[2:1]: Size of memory, 00 - 32-bit memory, 10 - 64-bit memory
Bit3: Prefetchable/non-prefetchable memory
8:4
CONFIG_BAR_SIZE_4
0x0
These bits set the size of the BAR4 memory.
For example, 32-bit BAR:
CONFIG_BAR_SIZE_4 - 5'd24 translates to BAR4 - (16 MB)
"1111_1111_0000_0000_0000_0000_0000_CONFIG_BAR_CONT
ROL_4"
3:0
CONFIG_BAR_CONTROL_
4
0x0
[3:0] LSB bits of BAR 4 register in PCIe core register map
Bit0: Memory/IO type indicator
Bit[2:1]: Size of memory, 00-32 bit memory, 10 - 64-bit memory
Bit3: Prefetchable/non-prefetchable memory
Note: All registers are 32-bit. Bits not shown in the table are reserved.
Table 6-22 • SYSTEM_SER_CLK_STATUS (0x204C)
Bit
Number
Name
Reset
Value
Description
1
FAB_PLL_LOCK
0x0
Fabric PLL lock information, CLK BASE, 1:LOCKED
0
PLL_LOCK
0x0
SPLL lock information, 1:LOCKED
Table 6-23 • Reserved Register (0x2050)
Bit
Number
–
Name
Reset
Value
Reserved
0x0
Description
Reserved
Revision 3
154
SERDES Block Register Access Map
Table 6-24 • Reserved Register (0x2054)
Bit
Number
–
Name
Reset
Value
Reserved
0x0
Description
Reserved
Table 6-25 • SYSTEM_SER_INTERRUPT (0x2058)
Bit
Number
Name
Reset
Value
Description
1
PLL_LOCK_INT
0x0
SPLL/FPLL lock interrupt output
0
PLL_LOCKLOST_INT
0x0
SPLL/FPLL lock lost interrupt output
Table 6-26 • SYSTEM_SERDES_INTR_STATUS Register (0x205C)
Bit
Number
2:0
Reset
Value
Name
SERDES_INTR_STATUS
0x0
Description
ECC interrupt status for PCIe memories
Table 6-27 • Reserved Register (0x2060)
Bit
Number
–
Name
Reset
Value
Description
Reserved
0x0
–
Note: All registers are 32-bit. Bits not shown in the table are reserved.
Table 6-28 • SYSTEM_REFCLK_SEL (0x2064)
Bit
Number
3:2
Name
LANE23_REFCLK_SEL
Reset
Value
Description
0x0 Reference clock selection for lane2 and lane3 of PMA:
00: Selects refclk_io clock for lane2 and lane3 as reference clock
01: Reserved
10: Reserved
11: Selects fab_ref_clk clock for lane2 and lane3 as reference clock
1:0
LANE01_REFCLK_SEL
0x0 Reference clock selection for lane0 and lane1 of PMA:
00: Selects refclk_io clock for lane0 and lane1 as reference clock
01: Reserved
10: Reserved
11: Selects fab_ref_clk clock for lane0 and lane1 as reference clock
155
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RTG4 FPGA High-Speed Serial Interfaces
Table 6-29 • SYSTEM_PCLK_SEL Register (0x2068)
Bit
Number
5:4
Name
Reset
Value
PIPE_PCLKIN_LANE23_SEL
0x0
Description
PIPE clock input selection for lane2 and lane3, can be selected
from one of pipeclk_out[3:0]:
00: Selects pipeclk_out[0] clock as pipeclk_in for lane2 and lane3.
01: Selects pipeclk_out[1] clock as pipeclk_in for lane2 and lane3.
10: Selects pipeclk_out[2] clock as pipeclk_in for lane2 and lane3.
11: Selects pipeclk_out[3] clock as pipeclk_in for lane2 and lane3.
3:2
PIPE_PCLKIN_LANE01_SEL
0x0
PIPE clock input selection for lane0 and lane1, can be selected
from one of pipeclk_out[3:0]:
00: Selects pipeclk_out[0] clock as pipeclk_in for lane0 and lane1.
01: Selects pipeclk_out[1] clock as pipeclk_in for lane0 and lane1.
10: Selects pipeclk_out[2] clock as pipeclk_in for lane0 and lane1.
11: Selects pipeclk_out[3] clock as pipeclk_in for lane0 and lane1.
1:0
PCIE_CORECLK_SEL
0x0
PCIe core clock selection. PCIe core clock can be selected from
one of pipeclk_out[3:0]:
00: Selects pipeclk_out[0] clock as PCIe core clock.
01: Selects pipeclk_out[1] clock as PCIe core clock.
10: Selects pipeclk_out[2] clock as PCIe core clock.
11: Selects pipeclk_out[3] clock as PCIe core clock.
Note: All registers are 32-bit. Bits not shown in the table are reserved.
Table 6-30 • SYSTEM_EPCS_RSTN_SEL (0x206C)
Bit
Number
3:0
Name
FABRIC_EPCS_RSTN_SEL
Reset
Value
0x0
Description
EPCS reset signal selection from FABRIC
Table 6-31 • SYSTEM_PCIE_ENABLE (0x2070)
Bit
Number
0
Name
PCIE_ENABLE
Reset
Value
0x1
Description
PCIE Enabled
Revision 3
156
SERDES Block Register Access Map
Table 6-32 • SYSTEM_SERDES_TEST_OUT (0x2074)
Bit
Number
31:0
Name
SERDES_TEST_OUT
Reset
Value
0x0
Description
Status TESTOUT output of PCIe PHY.
SERDES_TEST_OUT[31:24] - Debug signal for lane3
SERDES_TEST_OUT[23:16] - Debug signal for lane2
SERDES_TEST_OUT[15:80] - Debug signal for lane1
SERDES_TEST_OUT[7:0] - Debug signal for lane0
Bit[0]: Tx PLL reset
Bit[1]: Rx PLL reset
Bit[2]: Activity detected
Bit[3]: CDR PLL locked on data
Bit[4]: Tx PLL locked
Bit[5]: Rx PLL locked
Bit[7:6]: reserved
Note: All registers are 32-bit. Bits not shown in the table are reserved.
Table 6-33 • SYSTEM_SERDES_FATC_RESET (0x2078)
Bit
Number
0
Name
Reset
Value
SERDES_FATC_RESET
0x1
Description
Fabric alignment test circuit - reset input
Table 6-34 • SYSTEM_RC_OSC_SPLL_REFCLK_SEL (0x207C)
Bit
Number
0
Name
Reset
Value
RC_OSC_REFCLK_SEL
0x1
Description
This bit sets RC OSC as reference clock selection for SPLL.
Table 6-35 • SYSTEM_SPREAD_SPECTRUM_CLK (0x2080)
Bit
Number
Name
Reset
Value
Description
7:3
PLL_SERDES_Block_SS
MF
0x0
Spread spectrum clocking configuration register for feedback divider.
2:1
PLL_SERDES__Block_S
SMD
0x0
Spread spectrum clocking configuration register for reference divider.
0
PLL_SERDES__Block_S
SE
0x0
Spread spectrum clocking configuration register.
Table 6-36 • SYSTEM_CONF_AXI_MSTR_WNDW_0 (0x2084)
Bit
Number
31:0
Name
Reset
Value
CONF_AXI_MSTR_WNDW_0
0x0
Description
PCIe AXI3-master Window0 configuration register – 0
Note: All registers are 32-bit. Bits not shown in the table are reserved.
157
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Table 6-37 • SYSTEM_CONF_AXI_MSTR_WNDW_1 (0x2088)
Bit
Number
31:0
Name
Reset
Value
CONF_AXI_MSTR_WNDW_1
0x0
Description
PCIe AXI3-master Window0 configuration register – 1
Note: All registers are 32-bit. Bits not shown in the table are reserved.
Table 6-38 • SYSTEM_CONF_AXI_MSTR_WNDW_2 (0x208C)
Bit
Number
31:0
Name
CONF_AXI_MSTR_WNDW_2
Reset
Value
0x0
Description
PCIe AXI3-master Window0 configuration register – 2
Note: All registers are 32-bit. Bits not shown in the table are reserved.
Table 6-39 • SYSTEM_CONF_AXI_MSTR_WNDW_3 (0x2090)
Bit
Number
31:0
Name
CONF_AXI_MSTR_WNDW_3
Reset
Value
0x0
Description
PCIe AXI3-master Window0 configuration register – 3
Note: All registers are 32-bit. Bits not shown in the table are reserved.
Table 6-40 • SYSTEM_CONF_AXI_SLV_WNDW_0 (0x2094)
Bit
Number
31:0
Name
CONF_AXI_SLV_WNDW_0
Reset
Value
0x0
Description
PCIe AXI3-slave Window0 configuration register – 0
Note: All registers are 32-bit. Bits not shown in the table are reserved.
Table 6-41 • SYSTEM_CONF_AXI_SLV_WNDW_1 (0x2098)
Bit
Number
31:0
Name
CONF_AXI_SLV_WNDW_1
Reset
Value
0x0
Description
PCIe AXI3-slave Window0 configuration register – 1
Note: All registers are 32-bit. Bits not shown in the table are reserved.
Table 6-42 • SYSTEM_CONF_AXI_SLV_WNDW_2 (0x209C)
Bit
Number
31:0
Name
CONF_AXI_SLV_WNDW_2
Reset
Value
0x0
Description
PCIe AXI3-slave Window0 configuration register – 2
Note: All registers are 32-bit. Bits not shown in the table are reserved.
Table 6-43 • SYSTEM_CONF_AXI_SLV_WNDW_3 (0x20A0)
Bit
Number
31:0
Name
CONF_AXI_SLV_WNDW_3
Reset
Value
0x0
Description
PCIe AXI3-slave Window0 configuration register – 3
Note: All registers are 32-bit. Bits not shown in the table are reserved.
Revision 3
158
SERDES Block Register Access Map
Table 6-44 • SYSTEM_DESKEW_CONFIG (0x20A4)
Bit
Number
3:2
Name
Reset
Value
DESKEW_PLL_FDB_CLK
0x0
Description
These bits set the PLL FEEDBACK clock DESKEW register. Delay
cells addition in the path of FEEDBACK clock to PLL.
00: Bypass delay cells
01: Add 1-cells
10: Add 2-cells
11: Add 3-cells
1:0
DESKEW_PLL_REF_CLK
0x0
These bits set the PLL REF clock DESKEW register. Delay cells
addition in the path of REFERENCE clock to PLL.
00: Bypass delay cells
01: Add 1-cells
10: Add 2-cells
11: Add 3-cells
Table 6-45 • SYSTEM_ADVCONFIG (0x20b4)
Bit
Number
Name
Reset
Value
Description
0
K_BRIDGE_MODE
0x0
1'b0: Device is Native Endpoint, 1'b1: Device is a Root-port.
1
K_BRIDGE_ADDR_DEC
0x0
Advanced Mode Setting - PCIE Controller 0 Address decoding type,
1'b0: address decoding is performed by the BAR (RP/EP)
1'b1: address decoding is performed by Windows (RP only). This bit
must be set to 0 for Endpoint.
2
K_INFER_ELEC_IDLE
0x0
Enables the Inferred Electrical idle function in the PCIE core
(k_glb[44])
3
DISABLE_PCIE_RESET
0x0
When '1' disables the ability for the internal DLUP/HOTRST and L2P2
reset generator to perform an automatic reset sequence of the main
PCIe core logic.
4
DISABLE_PIPE_RESET
0x0
When '1' disables the ability for the internal PERST monitor and L2P2
reset generator to perform an automatic reset sequence of the PIPE
logic and PMA block.
5
ENABLE_PERSTN_SUPP
ORT
0x0
When '1' enables the ability for the internal PERST monitor to enter
reset when PERSTN is asserted. When '0' PERSTN is only used to
detect the exit from L2P2 and initiate the reset sequence.
6
PCIE_CONFIG_NOSTALL
0x0
PCIE Enabled. When '1' if PCIe configuration space is read before the
PMA clock (PCLK) is stable an APB SLVERR will be generated,
otherwise the APB cycle is stalled until the PCLK is stable.
PCIe Disabled. When '1' an APB PSLVERR is generated if the PCIe
configuration space is accessed, otherwise the APB cycle is allowed to
complete with simple assertion of PREADY.
159
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RTG4 FPGA High-Speed Serial Interfaces
Table 6-46 • SYSTEM_REFCLK_MSIO_CONFIG (0x20c4)
Bit
Number
0
Name
REFCLK_MSIO_DISN
Reset
Value
0x0
Description
I/O N disable input
1 = disabled
0 = enabled
1
REFCLK_MSIO_DISP
0x0
I/O P disable input
1 = disabled
0 = enabled
4:2
REFCLK_MSIO_VSN
0x0
I/O N input decode bits
000 = ratio PCI, LVTTL, or LVCMOS
010 = reference SSTL or HSTL
110 = differential LVDS,RSDS, or LVPECL
7:5
REFCLK_MSIO_VSP
0x0
I/O P input decode bits
000 = ratio PCI, LVTTL, or LVCMOS
010 = reference SSTL or HSTL
110 = differential LVDS,RSDS, or LVPECL
10:8
REFCLK_MSIO_IMPN
0x0
I/O N impedance termination settings
000 = unterminated
001 = 75 Ω to vddi/2, single-ended 150up/150dn
010 = 150 Ω to vddi/2, single-ended 300up/300dn
011 = 50 Ω to vddi/2, single-ended 100up/100dn
100 = 100 Ω padp to padn differential
13:11
REFCLK_MSIO_IMPP
0x0
I/O P impedance termination settings
000 = unterminated
001 = 75 Ω to vddi/2, single-ended 150up/150dn
010 = 150 Ω to vddi/2, single-ended 300up/300dn
011 = 50 Ω to vddi/2, single-ended 100up/100dn
100 = 100 Ω padp to padn differential
14
REFCLK_MSIO_SCHMITT_SELN
0x0
I/O N
0 = Schmitt trigger receiver, hysteresis off.
1= single ended receiver, hysteresis on.
15
REFCLK_MSIO_SCHMITT_SELP
0x0
I/O P
0 = Schmitt trigger receiver, hysteresis off.
1 = single ended receiver, hysteresis on.
18:16
REFCLK_MSIO_RT_ENN
0x0
I/O N receiver RT ctrl
21:19
REFCLK_MSIO_RT_ENP
0x0
I/O P receiver RT ctrl
22
REFCLK_MSIO_WPDN
0x0
I/O N weak pull down.
0 = off
1 = on
23
REFCLK_MSIO_WPDP
0x0
I/O P weak pull down.
0 = off
1 = on
Revision 3
160
SERDES Block Register Access Map
Table 6-46 • SYSTEM_REFCLK_MSIO_CONFIG (0x20c4) (continued)
Bit
Number
24
Reset
Value
Name
REFCLK_MSIO_WPUN
0x0
Description
I/O N weak pull up.
0 = off
1 = on
25
REFCLK_MSIO_WPUP
0x0
I/O P weak pull up.
0 = off
1 = on
Table 6-47 • SYSTEM_ENHANCEMENT (0x20c8)
Bit
Number
Name
Reset
Value
Description
9:0
RSRV4
0x0
Reserved to maintain bit positions in register
10
EPCS_RXSKIP_ENABLE
0x0
When '1' enables the EPCS RXSKIP inputs to the PMA cores.
Functions for XAUI and EPCS modes
Table 6-48 • SYSTEM_TXFWF_CONFIG (0x20cc)
Bit
Number
0
Reset
Value
Name
TXFWF_WMARK
0x0
Description
1 = Underflow is detected if wptr/rptr gap reaches 0 locations,
overflow at 8
0 = underflow detected at 1 location, overflow at 7
Recommended setting is 0
2:1
TXFWF_FIFO_LANE_CTRL
0x0
00 = each lane controller controls its respective fifo storage
01 = controller 0 controls all 4 fifos
10 = controller 0 controls fifo 0 and fifo 1, while controller 2 controls
fifo 2 and fifo 3
11 = reserved
3
TXFWF_TXOOB_USE_FIFO
0x0
1 = txoob signal goes through fwf
0 = txoob signal goes around fwf
4
TXFWF_TXVAL_USE_FIFO
0x0
1 = txval signal goes through fwf
0 = txval signal goes around fwf
Table 6-49 • SYSTEM_RXFWF_CONFIG (0x20d0)
Bit
Number
0
Name
RXFWF_WMARK
Reset
Value
0x0
Description
1 = Underflow is detected if wptr/rptr gap reaches 0 locations, overflow
at 8
0 = underflow detected at 1 location, overflow at 7
Recommended setting is 0
2:1
Reserved
0x0
Reserved
3
RXFWF_CLK_COMP
0x0
1 = Use xaui xfifo in clock compensation mode
0 = use rxfwf/xfifo in flywheel mode
161
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RTG4 FPGA High-Speed Serial Interfaces
SERDES Block Register
The SERDES block register map contains control and status information for the SERDES block and
lanes. Each block uses 256 register bytes. However, these 256 bytes are mapped to 1 KB to format a 32bit APB output. The APB-to-SERDES programming interface bridge is implemented to convert the
system 32-bit APB bus transactions into appropriate 8 bits. Since the RTG4 devices map the 4 SERDES
lanes into 1KB Blocks., the overall register map size is 4 KB. The physical offset location of the SERDES
block registers from the SERDES block system memory map is as follows:
•
0x1000-0x13FF - 1 KB - SERDES programming interface (Lane0)
•
0x1400-0x17FF - 1 KB - SERDES programming interface (Lane1)
•
0x1800-0x1BFF - 1 KB - SERDES programming interface (Lane2)
•
0x1C00-0x1FFF - 1 KB - SERDES programming interface (Lane3)
The SERDES block system register memory map occupies 1 KB of configuration memory map. Physical
offset location of the SERDES block system registers is 0x2000-0x23FF from the SERDES block
memory map. Table 6-2 describes the SERDES block system registers.
The 1 Kbyte register space can be divided between the protocol-specific read/write register and generic
purpose register.
•
Configuration PHY registers (offset 0x000 to 0x03C): These 16 registers are protocol-specific,
with a reset value depending on the selected protocol, according to CONFIG_PHY_MODE
register settings. For example, PLL_F_PCLK_RATIO register may have different reset values for
PCIe and XAUI mode. PCIe Gen1 features are configured using these 16 8-bit registers.
•
Reserved registers (offset 0x040 to 0X0BC)
•
SERDES Electrical Parameter registers (offset 0X0C0 to 0X18C): These 48 registers are
internally reported values of parameters programmed inside the SERDES block. These register
descriptions are reserved for factory testing only.
•
SERDES Testing registers (offset 0X190 to 0x1FC): These registers are used for testing the
SERDES block. These register descriptions are reserved for factory testing only.
•
SERDES Recompute register (offset 0x200): This register is a command register that requires
PMA control logic to recompute the SERDES parameter based on the new set of register values
programmed.
•
SERDES PRBS Error Counter registers (offset 0x204 to 0x400): There are 14 registers that are
used for bit error rate testing. These registers are for lane0, lane1, lane2, or lane3 and the
only difference between lane0, lane1, lane2, and lane3 is the base address specifying which
lane it is for. The rest of the register spaces are unused.
Table 6-50 lists the SERDES block register mapping including reset values. Unused lanes default to 0x00
values.
Table 6-50 • SERDES Block Lane Registers
Register Name
CR0
Address
Offset (Hex)
0X000
Reset
Value
0x80
Type
Description
R/W Lane Control register 0
ERRCNT_DEC
0X004
0x20
R/W Clock count for error counter decrement
RXIDLE_MAX_ERRCNT_THR
0X008
0x48 or
0xF8
R/W Error counter threshold – RX0 idle detect
maximum latency
Reset value for PCIe mode: 0x48
IMPED_RATIO
0X00C
0x6D
Revision 3
Reset value for other mode: 0xF8
R/W TX impedance ratio
162
SERDES Block Register Access Map
Table 6-50 • SERDES Block Lane Registers (continued)
Register Name
PLL_F_PCLK_RATIO
Address
Offset (Hex)
0X010
Reset
Value
0x24,
0x34, or
0x00
Type
Description
R/W PLL F settings and PCLK ratio
Reset value for PCIe mode:
0x24: 16-bit pipe interface and 250 MHz
PCLK
0x34: 16-bit pipe interface and other PCLK
0x24: 8-bit pipe interface
PLL_M_N
0X014
0x04,
0x13, or
0x69
CNT250NS_MAX
0X018
0x7C,
0x27, or
0x1F
Reset value for other modes: 0x00
R/W PLL M and N settings
Reset value for PCIe mode: 0x04
Reset value for XAUI mode: 0x13
Reset value for EPCS mode: 0x69
R/W 250 ns timer base count
Reset value for PCIe mode: 0x7C Reset
value for XAUI mode: 0x27
RE_AMP_RATIO
0X01C
0x00
Reset value for EPCS mode: 0x1F
R/W RX equalization amplitude ratio
RE_CUT_RATIO
0X020
0x00
R/W RX equalization cut frequency
TX_AMP_RATIO
0X024
0x6D
TX_PST_RATIO
0X028
0x15 or
0x00
R/W TX amplitude ratio (Gen 1 PCIe and lower
data rates)
R/W TX post-cursor ratio
Reset value for PCIe mode: 0x15
Reset value for XAUI mode: 0x15
TX_PRE_RATIO
0X02C
0x00
Reset value for EPCS mode: 0x00
R/W TX pre-cursor ratio
ENDCALIB_MAX
0X030
0x10
R/W End of calibration counter
CALIB_STABILITY_COUNT
0X034
0x38
R/W Calibration stability counter
POWERDOWN
0X038
0x00
R/W Power-down feature
RX_OFFSET_COUNT
0X03C
0x70
R/W RX offset counter
Note: The published register syntax is prefixed by LANEn (where n is 0:3). The register bit is appended to the block
register name. Example: LANE0_CR0
Reserved
0X040
–
R/W Reserved
Reserved
0X044
0x09
R/W Reserved
Reserved
0X048
0x7C
R/W Reserved
Reserved
0X050
0x15
R/W Reserved
Reserved
0X054
0x00
R/W Reserved
Reserved
0X058
0x20
R/W Reserved
Reserved
0X05C
0x00
R/W Reserved
Reserved
0X060
0x80
R/W Reserved
Reserved
0X064
0x78
R/W Reserved
Reserved
0X068
0x68
R/W Reserved
Reserved
0X06C
0x60
R/W Reserved
163
R e vi s i o n 3
RTG4 FPGA High-Speed Serial Interfaces
Table 6-50 • SERDES Block Lane Registers (continued)
Address
Offset (Hex)
0X070
Reset
Value
0x58
Type
R/W Reserved
Reserved
0X074
0x50
R/W Reserved
Reserved
0X078
0x48
R/W Reserved
Reserved
0X07C
0x40
R/W Reserved
Reserved
0X080
0x00
R/W Reserved
Reserved
0X084
0x00
R/W Reserved
Reserved
0X088
0x00
R/W Reserved
Reserved
0X08C
0x00
R/W Reserved
Reserved
0X090
0x15
R/W Reserved
Reserved
0X094
0x00
R/W Reserved
Reserved
0X098
0x20
R/W Reserved
Reserved
0X09C
0x00
R/W Reserved
Reserved
0X0A0
0x50
R/W Reserved
Reserved
0X0A4
0x58
R/W Reserved
Reserved
0X0A8
0x48
R/W Reserved
Reserved
0X0AC
0x40
R/W Reserved
Reserved
0X0B0
0x38
R/W Reserved
Reserved
0X0B4
0x30
R/W Reserved
Reserved
0X0B8
0x28
R/W Reserved
Reserved
0X0BC
0x20
R/W Reserved
Register Name
Reserved
Note:
Description
Reserved R/W registers are listed with default values for reference only.
PMA_STATUS
0X0C0
0x80
R/O
PRBS_CTRL
0X190
0x00
PMA status register- correct read back value
= 0x80
R/W PRBS control register
PRBS_ERRCNT
0X194
0x00
R/O
PHY_RESET_OVERRIDE
0X198
0x00
R/W PHY reset override register
PHY_POWER_OVERRIDE
0X19C
0x00
R/W PHY power override register
CUSTOM_PATTERN_7_0
0X1A0
0x00
R/W Custom pattern byte 0
CUSTOM_PATTERN_15_8
0X1A4
0x00
R/W Custom pattern byte 1
CUSTOM_PATTERN_23_16
0X1A8
0x00
R/W Custom pattern byte 2
CUSTOM_PATTERN_31_24
0X1AC
0x00
R/W Custom pattern byte 3
PRBS error counter register
Note: Registers 49-99 are factory reserved for testing purposes.
CUSTOM_PATTERN_39_32
0X1B0
0x00
R/W Custom pattern byte 4
CUSTOM_PATTERN_47_40
0X1B4
0x00
R/W Custom pattern byte 5
CUSTOM_PATTERN_55_48
0X1B8
0x00
R/W Custom pattern byte 6
CUSTOM_PATTERN_63_56
0X1BC
0x00
R/W Custom pattern byte 7
Revision 3
164
SERDES Block Register Access Map
Table 6-50 • SERDES Block Lane Registers (continued)
Register Name
CUSTOM_PATTERN_71_64
Address
Offset (Hex)
0X1C0
Reset
Value
0x00
Type
Description
R/W Custom pattern byte 8
CUSTOM_PATTERN_79_72
0X1C4
0x00
R/W Custom pattern byte 9
CUSTOM_PATTERN_CTRL
0X1C8
0x00
R/W Custom pattern control
Reserved
0X1CC
0x00
R/O
PCS_LOOPBACK_CTRL
0X1D0
0x00
R/W PCS loopback control
GEN1_TX_PLL_CCP
0X1D4
0x06
R/W Gen1 transmit PLL current charge pump
GEN1_RX_PLL_CCP
0X1D8
0x66
R/W Gen1 receive PLL current charge pump
Reserved
0X1DC
0x00
R/W Reserved
Reserved
0X1E0
0x00
R/W Reserved
CDR_PLL_MANUAL_CR
0X1E4
0x00
R/W CDR PLL manual control
UPDATE_SETTINGS
0X200
0x00
W/O Update settings command register
PRBS_ERR_CYC_FIRST_7_0
0X280
0x00
R/O
PRBS_ERR_CYC_FIRST_15_8
0X284
0x00
R/O
PRBS_ERR_CYC_FIRST_23_16
0X288
0x00
R/O
PRBS_ERR_CYC_FIRST_31_24
0X28C
0x00
R/O
PRBS_ERR_CYC_FIRST_39_32
0X290
0x00
R/O
PRBS_ERR_CYC_FIRST_47_40
0X294
0x00
R/O
PRBS_ERR_CYC_FIRST_49_48
0X298
0x00
R/O
PRBS_ERR_CYC_FIRST_7_0
0X2A0
0x00
R/O
0x00
R/O
Custom pattern status register
PRBS first error cycle counter register
bits[7:0]
PRBS first error cycle counter register
bits[15:8]
PRBS first error cycle counter register
bits[23:16]
PRBS first error cycle counter register
bits[31:24]
PRBS first error cycle counter register
bits[39:32]
PRBS first error cycle counter register
bits[47:40]
PRBS first error cycle counter register bits
[49:48]
PRBS last error cycle counter register
bits[7:0]
Note: Registers 129 to 159 are Reserved for factory.
PRBS_ERR_CYC_FIRST_15_8
PRBS last error cycle counter register
bits[15:8]
PRBS_ERR_CYC_FIRST_23_16
0X2A8
0x00
R/O PRBS last error cycle counter register
bits[23:16]
PRBS_ERR_CYC_FIRST_31_24
0X2AC
0x00
R/O PRBS last error cycle counter register
bits[31:24]
PRBS_ERR_CYC_FIRST_39_32
0X2B0
0x00
R/O PRBS last error cycle counter register
bits[39:32]
PRBS_ERR_CYC_FIRST_47_40
0X2B4
0x00
R/O PRBS last error cycle counter register
bits[47:40]
PRBS_ERR_CYC_FIRST_49_48
0X2B8
0x00
R/O PRBS last error cycle counter register
bits[49:48]
Note: The published register syntax is prefixed by LANEn (where n is 0:3). The register bit is appended to the block
register name. Example: LANE0_CR0
165
0X2A4
R e vi s i o n 3
RTG4 FPGA High-Speed Serial Interfaces
SERDES Block Register Bit Definitions
The following tables give bit definitions for the registers of the SERDES block registers.
Table 6-51 • CR0
Bit
Number
Name
7
AUTO_SHIFT
Reset
Value
Description
0x1 Defines whether the electrical idle 1 pattern is automatically
shifted in the SERDES block after loading the drive pattern.
When set to 1, electrical idle I or Drive mode can be entered
within a single aTXClkp clock cycle. When set to 0, 23 clock
cycles are required to dynamically switch between electrical
idle I and Drive mode. In general, this bit is always set to 1.
Unused lanes are set to 0.
6
FORCE_RX_DETECT
0x0 Forces the result of PCIe receiver detect operation to be
always detected. This register can be used on unreliable
results of RX detect operations. When set to 1, the result of
the PCIe receiver detect operation is always positive and thus
makes the PHY non-compliant to PCIe.
[5:4]
CDR_REFERENCE
0x0 Defines the CDR reference PLL mode. By default, these two
bits must be set to 00 when RefClk is used for the CDR
reference clock.
3
PMA_DRIVEN_MODE
0x0 Puts the CDR PLL in PMA driven mode. When set to 0, the
PCS driven mode is selected for locking the SERDES CDR
circuitry and when set to 1, PMA driven mode is used.
2
CDR_PLL_DELTA
0x0 Defines the frequency comparator threshold value to switch
from fine grain locking to frequency lock and thus control the
input signal of the PMA block when CDR is configured in PMA
driven mode, and the equivalent function when the PMA is
configured in PCS driven mode. When set to 0, the RX clock
and TX clock must be in a 0.4% difference range; 0.8% when
set to 1.
1
SIGNAL_DETECT_THRESHOLD
0x0 Defines the Schmitt trigger signal detection threshold used to
detect electrical idle on RX. When set to 0, threshold is 125
mV (±40%), and when set to 1, threshold is 180 mV (±33%).
0
TX_SELECT_RX_FEEDBACK
0x0 Must be set to 0 when RefClk is used for TX PLL. Set to 1
when the CDR PLL is used as TX PLL reference clock.
Note: This register can be reprogrammed when the PHY is under reset or when calibration has completed (PMA is
ready).
Table 6-52 • ERRCNT_DEC
Bit
Reset
Number
Name
Value
Description
[7:0]
ERRCNT_DEC 0x20 In PCS driven mode, the PMA control logic counts the number of errors detected
by the PCS logic in order to decide to switch back to frequency lock mode of the
CDR PLL. This counter is used to decrement the error counter every
16*errcnt_dec[7:0] aTXClk clock cycles.
Note: This register can be reprogrammed when the PHY is under reset or when calibration has completed (PMA is
ready).
Revision 3
166
SERDES Block Register Access Map
Table 6-53 • RXIDLE_MAX_ERRCNT_THR
Bit
Number
[7:4]
Name
RXIDLE_MAX
Reset Value
0x4-PCIe
0xF-others
[3:0]
ERRCNT_THR
0x8
Description
Defines the number of clock cycles required before the activity
detected output of the PMA block and reports either electrical idle or
valid input data. This register must be set to at least 3 because the
activity detected signal is considered as metastable by the PCS
logic.
In PCS driven mode, the PMA control logic counts the number of
errors detected by the PCS logic in order to decide to switch back
to frequency lock mode of the CDR PLL. This register defines the
error counter threshold value after which the CDR PLL switches
Note: This register can be reprogrammed any time during operation.
Table 6-54 • IMPED_RATIO
Bit
Number
[7:0]
Name
IMPED_RATIO
Reset Value
0x8
Description
Fine-tunes the impedance ratio of the PMA block with a nominal
value of 100  corresponding to a multiplication factor of 1, which
is encoded 8'd128. A 150  impedance corresponds to 2/3 ratio,
encoded 8'd85.
Note: This register can be reprogrammed when the PHY is under reset or when calibration has completed (PMA is
ready).
Table 6-55 • PLL_F_PCLK_RATIO
Bit
Number
[7:6]
Name
Reserved
Reset Value
PCIe mode: 0x0
XAUI mode:0x0
EPCS mode:0x0
Description
[5:4]
DIV_MODE0
PCIe mode: 0x3
XAUI mode: 0x0
EPCS mode: 0x0
[3:0]
F
Defines the ratio between PCLK and aTXClk. PCLK is used by the
PCIe PCS logic as well as by the majority of the PMA control logic
and thus is also useful for other protocols in order to reduce the
amount of logic requiring a high aTXClk frequency. In non-PCIe
mode, this register is only useful if pipe_pclkout is used by any
logic. A value of 00 is used for divide-by-1, 10 for divide by-2 and 11
for divide-by-4.
Defines the aRXF[3:0] and aTXF[3:0] settings of the PMA block.
The same F value is applied to both RX and TX PLL.
PCIe mode: 0x4
XAUI mode: 0x0
EPCS mode: 0x0
Note: This register must only be reprogrammed when PHY is under reset or when both RX PLL and TX PLL are under
reset.
167
R e vi s i o n 3
RTG4 FPGA High-Speed Serial Interfaces
Table 6-56 • PLL_M_N
Bit
Number
7
Name
CNT250NS_MAX[8]
Reset Value
Description
PCIe mode: 0x0 This bit is concatenated to the Reg06 register as an MSB to
XAUI mode: 0x0 define the 250 ns base time.
EPCS mode: 0x0
[6:5]
M[1:0]
PCIe mode: 0x0 Defines the TX PLL M values and CDR PLL M value settings of
XAUI mode: 0x0 the PMA block. For PCIe, it corresponds to the Gen1 settings.
EPCS mode: 0x1 The same M value is applied to both RX and TX PLL.
[4:0]
N[4:0]
PCIe mode: 0x4 Defines the TX PLL N values and CDR PLL N value settings of
XAUI mode: 0x13 the PMA block. For PCIe, it corresponds to the Gen1 settings.
EPCS mode: 0x9 The same N value is applied to both RX and TX PLL.
Note: This register must only be reprogrammed when PHY is under reset or when both RX PLL and TX PLL are under
reset.
Table 6-57 • CNT250NS_MAX
Bit
Number
[7:0]
Name
CNT250NS_MAX
Reset Value
Description
PCIe mode: 0x7C Defines the base count of a 250 ns event based on the aTXClk
XAUI mode: 0x27 clock. This counter is used by the CDR PLL in PCS driven
mode and also by the PMA control logic for operations such as
EPCS mode: 0x20
receiver detect and electrical idle 2 and 3 states. In the case of
a non-integer value, the base count must be rounded up. This
register must be set correctly for all protocols.
Note: This register must only be reprogrammed when the PHY is under reset for proper operation. It impacts the PCSdriven CDR PLL mode as well as calibration and thus has no effect after calibration is completed (PMA is ready)
or if the PHY CDR PLL is used in PMA driven mode.
Table 6-58 • RE_AMP_RATIO
Bit
Number
[7:0]
Name
RE_AMP_RATIO
Reset Value
0x00
Description
Defines the RX equalization amplitude ratio where the
maximum value of 8’d128 corresponds to 100%. If RX
equalization is not used, this register can be set to zero.
Note: This register can be reprogrammed during normal operation but the effect only appears when the parameters for
the SERDES receiver are updated (at the end of calibration or when UPDATE_SETTINGS is programmed.
Table 6-59 • RE_CUT_RATIO
Bit
Number
[7:0]
Name
RE_CUT_RATIO
Reset Value
0x00
Description
Defines the RX equalization cut frequency ratio, used in the
computation of Rn[3:0] and Rd[3:0] equalization settings of the
PMA block. The encoding of this register is such that 
(Rn + Rd) = (RE_CUT_RATIO)/256*W_SETTING where
W_SETTING is the result of RX equalization calibration.
Note: This register can be reprogrammed during normal operation but the effect only appears when the parameters for
the SERDES receiver are updated (at the end of calibration or when UPDATE_SETTINGS is programmed).
Revision 3
168
SERDES Block Register Access Map
Table 6-60 • TX_AMP_RATIO
Bit
Number
[7:0]
Name
TX_AMP_RATIO
Reset Value
Description
0x80
Implements the TX amplitude ratio used by the TX driver. A value of
128 corresponds to 100% (full voltage); a value of 0 corresponds to
0%. Values higher than 128 are forbidden. For PCIe, this register is
used for Gen1 speed only.
Note: This register can be reprogrammed during normal operation but the effect only appears when the parameters for
the SERDES transmitter are updated (at the end of calibration, on entry or exit of TX electrical idle I or when
UPDATE_SETTINGS is programmed).
Table 6-61 • TX_PST_RATIO
Bit
Number
[7:0]
Name
TX_PST_RATIO
Reset Value
Description
0x15
Defines the TX post-cursor ratio for the Gen1 speed used for selecting
the de-emphasis of the switching bit versus non-switching bit. A value
of 128 corresponds to 100% (full voltage); a value of 0 corresponds to
0%. A value of –3.5 dB corresponds to 8’d21 encoding.
Note: This register can be reprogrammed during normal operation but the effect only appears when the parameters for
the SERDES transmitter are updated (at the end of calibration, on entry or exit of TX Electrical Idle I or when
UPDATE_SETTINGS is programmed).
Table 6-62 • TX_PRE_RATIO
Bit
Number
[7:0]
Name
TX_PRE_RATIO
Reset Value
Description
0x00
Defines the TX pre-cursor ratio for the Gen1 speed used for selecting
the de-emphasis of the switching bit versus non-switching bit. A value
of 128 corresponds to 100% (full voltage); a value of 0 corresponds to
0%.
Note: This register can be reprogrammed during normal operation but the effect appears only when the parameters for
the SERDES transmitter are updated (at the end of calibration, on entry or exit of TX electrical idle I or when
UPDATE_SETTINGS is programmed).
Table 6-63 • ENDCALIB_MAX
Bit
Number
[7:0]
Name
ENDCALIB_MAX
Reset Value
Description
0x10
Defines the amount of time in microseconds required by the PMA to
settle its electrical level after loading electrical idle 1 in the TX driver at
the end of calibration. All operations are automatically performed by
the PMA control logic but that the SERDES transmitter can start driving
data on the link immediately after the end of calibration. By default
(except if forbidden by protocol) a 10 µs delay between end of
Calibration and Mission mode is set (but any value might work as well).
Note: This register can be reprogrammed when the PHY is under reset or when calibration has completed (PMA is
ready).
169
R e vi s i o n 3
RTG4 FPGA High-Speed Serial Interfaces
Table 6-64 • CALIB_STABILITY_COUNT
Bit
Number
Name
[7:5]
CALIB_SETTLE_MAX
Reset
Value
0x1
[4:0]
0x18
CALIB_STABLE_MAX
Description
Defines the amount of time in microseconds required by the PMA to
settle its electrical level after loading electrical idle 1 in the TX driver at
the end of calibration. Note that all operation is automatically performed
by the PMA control logic but that the SERDES transmitter can start
driving data on the link immediately after end of calibration. By default,
except if forbidden by protocol, a 10 µs delay between end of
calibration and mission mode is set (but any value might work as well).
This register defines the number of clock cycles before which the
impedance calibrator results (aZCompOp = 1, impedance calibrator
result is greater than nominal; and aZCompOp = 0, impedance
calibrator result is less than nominal) signal can be checked for stability
after impedance calibration control values (aZCalib) modification.
aZCompOp = 1, when Impedance calibrator result > nominal
0, when Impedance calibrator result < nominal
This is used for TX, RX, and RX equalization calibration.
Note: This register can be reprogrammed when the PHY is under reset or when calibration has completed (PMA is
ready).
Table 6-65 • POWERDOWN
Bit
Number
Name
[7:6]
RXIDLE_MSB
Reset
Value
0x0
5
FORCE_SIGNAL
0x0
4
FORCE_IDLE
0x0
3
NO_FCMP
0x0
Description
These bits are used as the most significant bits (MSBs) of the activity
detector logic, to specify that no activity has been detected during up to
61 aTXClkp clock cycles. These bits are the two MSBs; the
rxidle_max[3:0] field of Reg02 represents the least significant bit (LSB)
part.
When this bit is set, the PHY disables the Idle detection circuitry and
forces signal detection on the receiver. This bit is generally always set
to disable (0) unless the activity detector logic must be bypassed. In that
case, the PMA control logic always reports activity detected on the link
(when set to 1). This bit can be used, for instance, if the activity detector
of the SERDES PMA block does not work for the selected protocol (as
outside range of functionality).
When this bit is set, the PHY disables the Idle detection circuitry and
forces electrical Idle detection on the receive side. By default, this bit is
generally cleared and might be set only for very specific conditions or
testing such as generating a fake loss of signal to the PCS or MAC
layer, forcing a retraining of word aligner or any training state machine.
As long as this bit is set, the activity detector logic of the PMA control
logic reports that no signal is detected on the receive side. If CDR PLL
PCS driven mode is selected, the CDR PLL is directed in lock to the
reference clock state, leading to potential wrong data received by the
SERDES (because the CDR PLL is not locked to incoming data).
When set, this bit disables the frequency comparator logic of the PCS
driven CDR PLL control logic. When not set, the frequency comparator
logic is no longer part of the condition for going from fine-grain lock state
to frequency acquisition. This mode locks to the refclk.
Revision 3
170
SERDES Block Register Access Map
Table 6-65 • POWERDOWN (continued)
Bit
Number
Name
2
PMFF_ALL
Reset
Value
0x0
1
CDR_ERR
0x0
0
CDR_P1
0x0
Description
Used with PCIe only, this register when set disables the function that
waits for every active lane to have valid data to transmit before
generating a global read enable. This bit is intended to be used in case
of any issue with this function. When set, each lane might start
transmitting data with one 500 MHz clock uncertainty (corresponding to
5 or 10 bits time, depending on the speed of the link). Even if violating
the protocol requirement, the PCIe standard is strong enough to
support this non-compliance.
When set, this register disables the error counter internally of the CDR
PLL state machine, which switches back the CDR PLL to frequency
mode acquisition when the number of errors counted is higher than the
predefined error threshold. This bit is intended for disabling this function
in the case of any issue with the PHY. This is available for all SERDES
modes.
Defines the state of the CDR PLL when the PHY is in P1 Low power
mode.
When set to zero, the CDR PLL is put in reset and low power, enabling
maximum power savings. When the opposite component sends the
TS1 ordered set to drive the link in recovery, only the
PIPE_RXELECIDLE signal is deasserted at the PIPE interface and the
PHY waits for the controller to change the pipe_powerdown[1:0] signal
back to P0 before retraining the CDR PLL (~6 µs) and sending received
data to the controller.
When set to 1, the CDR PLL is kept alive in Frequency lock mode in the
P1 state, which enables a faster recovery time from the P1 state but
which also consumes more power (all RX logic is kept alive and
consumes power in the P1 state). This register must not be set for
applications which remove the reference clock in P1 mode (generally
associated with the CLKREQ# signal, express card application, and
more generally power sensitive application).
Note: This register can be reprogrammed when the PHY is under reset or when calibration has completed (PMA is
ready), except for bit 2, which can only be modified under reset condition.
Table 6-66 • RX_OFFSET_COUNT
Bit
Number
[7:5]
[4:0]
171
Name
RXOFF_SETTLE_MAX
RXOFF_STABLE_MAX
Reset
Value
0x3
Description
Defines the number of clock cycles before which the aRXDNullDat
signal can be checked for stability after aRXDNull[3:0] modification. This is
used also for aRXD, aRXT, and Schmitt trigger calibration. The value of
this register expresses a number of (2*N+1) PCLK clock cycles.
0x10 Defines the number of clock cycles where the aRXDNullDat signal is
checked for stability.
R e vi s i o n 3
RTG4 FPGA High-Speed Serial Interfaces
Table 6-67 • PMA_STATUS
Bit
Number
[7]
Name
PMA_RDY
[6:0]
-
Reset
Value
0x01
-
Description
This read-only register indicates that the PMA has completed it internal
calibration sequence after power-up and PHY reset de-assertion.
Reserved
Table 6-68 • PRBS_CTRL
Bit
Number
7
6
Name
Reset
Value
Description
Unused
PRBS_CHK
0x0
[5:4]
Reserved
-
[3:2]
PRBS_TYP[1:0]
0x0
1
LPBK_EN
0x0
0
PRBS_GEN
0x0
When set, this signal starts the PRBS pattern checker. It can be set at the
same time as the PRBS generator while the PRBS checker logic waits for
256 clock cycles and CDR being in lock state to enable the PRBS pattern
comparison (allowing a total latency of 256 cycles to loop back the
transmitted data).
Reserved
Defines the type of PRBS pattern which is applied. PRBS7 when set to 00,
PRBS11 when set to 01, PRBS23 when set to 10, PRBS31 when set to 11.
When set, the PMA is put in near-end loopback (serial loopback from TX
back to RX). PRBS tests can be done using the near-end loopback of the
PMA, some load board, or any far-end loopback implemented in the
opposite component. When near-end loopback bit is set, the idle detector
always reports valid data, enabling the PCS driven CDR PLL locking logic to
lock on input data.
When set, this signal starts the PRBS pattern transmission.
Note: This register can be programmed any time but has functional impact because it can configure the SERDES in
loopback or generate the PRBS pattern.
Table 6-69 • PRBS_ERRCNT
Bit
Number
[7:0]
Name
PRBS_ERRCNT[7:0]
Reset
Value
0x00
Description
This test reports the number of PRBS errors detected when the
PRBS test is applied.
This register is automatically cleared when the PRBS_EN
register is cleared (requiring testing the value of this register
when the test is running).
The PRBS error counter saturates at 254 errors, the 255 count
value corresponding to an error code where the CDR PLL is
not locked to incoming data. When such an error code is
detected, the PRBS test must wait for a longer time for the CDR
PLL to synchronize on input data before enabling the PRBS
checker or simply timeout, reporting that no data has been
received at all.
Note: The PRBS error counter logic also counts errors when
the PRB Sinvariant (all zero value) is obtained,
considering input data as error data.
Revision 3
172
SERDES Block Register Access Map
Table 6-70 • PHY_RESET_OVERRIDE
Bit
Number
7
Name
RXHF_CLKDN
Reset
Value
0x0
6
TXHF_CLKDN
0x0
When set, this signal disables the TX PLL VCO by applying a static zero
to the PMA aTXHfClkDnb signal.
5
RXPLL_RST
0x0
When set, this signal resets the RX PLL settings by applying a static zero
to the PMA aCdrPllRstb signal.
4
TXPLL_RST
0x0
When set, this signal initializes the TX PLL settings by applying a static
zero to the PMA aTXPllRstb signal.
3
RXPLL_INIT
0x0
When set, this signal resets the RX PLL settings by applying a static zero
to the PMA aCdrPllRstb signal.
2
TXPLL_INIT
0x0
When set, this signal initializes the TX PLL settings by applying a static
one to the PMA aTXPllDivInit signal.
1
RX_HIZ
0x0
When set, this signal forces the RX driver to hiZ, applying a static one to
the PMA aForceRXHiZ signal.
0
TX_HIZ
0x0
When set, this signal forces the TX driver to hiZ, applying a static one to
the PMA aForceTXHiZ signal.
Description
When set, this signal disables the RX PLL VCO settings by applying a
static zero to the PMA aRXHfClkDnb signal.
Note: This register can be programmed any time but has functional impact on the SERDES because it can put the
PLL under reset or place part of the SERDES in Low power mode, bypassing the functional mode.
Table 6-71 • PHY_POWER_OVERRIDE
Bit
Number
[7:1]
-
0
RX_PWRDN
Name
Reset
Value
0x0
Description
Reserved
When set, this register forces the RX PMA logic to be in Power-down
mode.
Note: This register can be programmed any time but has functional impact on the SERDES because it can powerdown the receiver part of the SERDES, bypassing the functional mode.
Table 6-72 • CUSTOM_PATTERN_7_0
Bit
Number
[7:0]
Name
CUSTOM_PATTERN[7:0]
Reset
Value
0x00
Description
Enables bit 7 to bit 0 to program a custom pattern instead of the
implemented PRBS generator/checker. The PRBS mode must
still be selected to transmit this custom pattern on the transmit line
but this mode enables the generation of any repeated sequence
of data. It can be used, for instance, for single lane PCIe
compliance pattern generation (for the purpose of an eye diagram
compliance check) or can even be looped back to the receiver to
check if any error is detected on the line. In the latter case, the
PMA block function is used to perform a word alignment function.
Note: This register can be programmed any time but has no functional impact as long as the custom pattern
generation is not enabled and selected.
173
R e vi s i o n 3
RTG4 FPGA High-Speed Serial Interfaces
Table 6-73 • CUSTOM_PATTERN_15_8
Bit
Number
[7:0]
Name
CUSTOM_PATTERN [15:8]
Reset
Value
0x00
Description
Enables bit 15 to bit 8 to program a custom pattern instead of
the implemented PRBS generator/checker. The PRBS mode
must still be selected to transmit this custom pattern on the
transmit line, but this mode enables the generation of any
repeated sequence of data. It can be used, for instance, for
single lane PCIe compliance pattern generation (for the
purpose of an eye diagram compliance check) or can even
be looped back to the receiver to check if any error is
detected on the line. In the latter case, the PMA block
function is used to perform a word alignment function.
Note: This register can be programmed any time but has no functional impact as long as the custom pattern
generation is not enabled and selected.
Table 6-74 • CUSTOM_PATTERN_23_16
Bit
Number
[7:0]
Name
CUSTOM_PATTERN [23:16]
Reset
Value
0x00
Description
Enables bit 23 to bit 16 to program a custom pattern instead
of the implemented PRBS generator/checker. PRBS mode
must still be selected to transmit this custom pattern on the
transmit line but this mode enables the generation of any
repeated sequence of data. It can be used, for instance, for
single lane PCIe compliance pattern generation (for the
purpose of an eye diagram compliance check) or can even be
looped back to the receiver to check if any error is detected
on the line. In the latter case, the PMA block function is used
to perform a word alignment function.
Note: This register can be programmed any time but has no functional impact as long as the custom pattern
generation is not enabled and selected.
Table 6-75 • CUSTOM_PATTERN_31_24
Bit
Number
[7:0]
Name
CUSTOM_PATTERN [31:24]
Reset
Value
0x00
Description
This register enables bit 31 to bit 24 to program a custom
pattern instead of the implemented PRBS generator/checker.
PRBS mode must still be selected to transmit this custom
pattern on the transmit line, but this mode enables the
generation of any repeated sequence of data. It can be used,
for instance, for single lane PCIe compliance pattern
generation (for the purpose of an eye diagram compliance
check) or can even be looped back to the receiver to check if
any error is detected on the line. In the latter case, the PMA
block function is used to perform word alignment function.
Note: This register can be programmed any time but has no functional impact as long as the custom pattern
generation is not enabled and selected.
Revision 3
174
SERDES Block Register Access Map
Table 6-76 • CUSTOM_PATTERN_39_32
Bit
Number
[7:0]
Name
CUSTOM_PATTERN [39:32]
Reset
Value
0x00
Description
Enables bit 39 to bit 32 to program a custom pattern instead
of the implemented PRBS generator/checker. PRBS mode
must still be selected to transmit this custom pattern on the
transmit line, but this mode enables the generation of any
repeated sequence of data. It can be used, for instance, for
single lane PCIe compliance pattern generation (for the
purpose of an eye diagram compliance check) or can even
be looped back to the receiver to check if any error is
detected on the line. In the latter case, the PMA block
function is used to perform a word alignment function.
Note: This register can be programmed any time but has no functional impact as long as the custom pattern
generation is not enabled and selected.
Table 6-77 • CUSTOM_PATTERN_47_40
Bit
Number
[7:0]
Name
CUSTOM_PATTERN [47:40]
Reset
Value
0x00
Description
Enables bit 47 to bit 40 to program a custom pattern instead
of the implemented PRBS generator/checker. PRBS mode
must still be selected to transmit this custom pattern on the
transmit line, but this mode enables the generation of any
repeated sequence of data. It can be used, for instance, for
single lane PCIe compliance pattern generation (for purpose
of eye diagram compliance check) or can even be looped
back to the receiver to check if any error is detected on the
line. In the latter case, the PMA block function is used to
perform a word alignment function.
Note: This register can be programmed any time but has no functional impact as long as the custom pattern
generation is not enabled and selected.
Table 6-78 • CUSTOM_PATTERN_55_48
Bit
Number
[7:0]
Reset
Value
0x00
Description
Enables bit 55 to bit 48 to program a custom pattern instead
of the implemented PRBS generator/checker. The PRBS
mode must still be selected to transmit this custom pattern on
the transmit line but this mode enables the generation of any
repeated sequence of data. It can be used, for instance, for
single lane PCIe compliance pattern generation (for the
purpose of an eye diagram compliance check) or can even be
looped back to the receiver to check if any error is detected
on the line. In the latter case, the PMA block function is used
to perform a word alignment function.
Note: This register can be programmed any time but has no functional impact as long as the custom pattern
generation is not enabled and selected.
175
Name
CUSTOM_PATTERN [55:48]
R e vi s i o n 3
RTG4 FPGA High-Speed Serial Interfaces
Table 6-79 • CUSTOM_PATTERN_63_56
Bit
Number
[7:0]
Name
CUSTOM_PATTERN [63:56]
Reset
Value
0x00
Description
Enables bit 63 to bit 56 to program a custom pattern instead
of the implemented PRBS generator/checker. The PRBS
mode must still be selected to transmit this custom pattern
on the transmit line but this mode enables the generation of
any repeated sequence of data. It can be used, for instance,
for single lane PCIe compliance pattern generation (for the
purpose of an eye diagram compliance check) or can even
be looped back to the receiver to check if any error is
detected on the line. In the latter case, the PMA block
function is used to perform a word alignment function.
Note: This register can be programmed any time but has no functional impact as long as the custom pattern
generation is not enabled and selected.
Table 6-80 • CUSTOM_PATTERN_71_64
Bit
Number
[7:0]
Name
CUSTOM_PATTERN [71:64]
Reset
Value
0x00
Description
Enables bit 71 to bit 64 to program a custom pattern instead
of the implemented PRBS generator/checker. The PRBS
mode must still be selected to transmit this custom pattern
on the transmit line but this mode enables the generation of
any repeated sequence of data. It can be used, for instance,
for single lane PCIe compliance pattern generation (for the
purpose of an eye diagram compliance check) or can even
be looped back to the receiver to check if any error is
detected on the line. In the latter case, the PMA block
function is used to perform a word alignment function.
Note: This register can be programmed any time but has no functional impact as long as the custom pattern
generation is not enabled and selected.
Table 6-81 • CUSTOM_PATTERN_79_72
Bit
Number
[7:0]
Name
CUSTOM_PATTERN [79:72]
Reset
Value
0x00
Description
Enables bit 79 to bit 72 to program a custom pattern instead
of the implemented PRBS generator/checker. The PRBS
mode must still be selected to transmit this custom pattern on
the transmit line but this mode enables the generation of any
repeated sequence of data. It can be used, for instance, for
single lane PCIe compliance pattern generation (for the
purpose of an eye diagram compliance check) or can even
be looped back to the receiver to check if any error is
detected on the line. In the latter case, the PMA block
function is used to perform a word alignment function.
Note: This register can be programmed any time but has no functional impact as long as the custom pattern
generation is not enabled and selected.
Revision 3
176
SERDES Block Register Access Map
Table 6-82 • CUSTOM_PATTERN_CTRL
Bit
Number
7
Name
Reserved
Reset
Value
-
6
CUST_AUTO
0x0
5
Reserved
0x0
When this register is set, the word alignment is performed automatically
by a state machine that checks whether the received pattern is wordaligned with the transmitted pattern and automatically use the PMA CDR
PLL skip bit function to find the alignment. Once the word alignment is
detected, the custom pattern checker is now word-aligned and the
custom pattern checker can be enabled for detecting and counting any
error over time.
-
4
Reserved
0x0
-
[3:1]
CUST_TYP
0x0
Defines whether the custom pattern generated on the link is generated
by the custom pattern register or by one of the hard-coded patterns:
Description
Reserved
000: Custom pattern register
100: All-zero pattern (0000…00)
101: All-one pattern (1111…11)
110: Alternated pattern (1010…10)
111: Dual alternated pattern (1100…1100)
When set, this signal replaces the PRBS data transmitted on the link by
the custom pattern. The PRBS_SEL register must also be set for
transmitting the custom pattern on the link.
Note: This register can be programmed any time but has functional impact on the SERDES because it can directly
activate some part of the SERDES (aRXSkipBit), changing the current bitstream reception (thus creating
alignment errors).
0
CUST_SEL
0x0
Table 6-83 • Reserved
Bit
Number
[7:0]
177
Name
Reserved
Reset
Value
0x0
Description
-
R e vi s i o n 3
RTG4 FPGA High-Speed Serial Interfaces
Table 6-84 • PCS_LOOPBACK_CTRL
Bit
Number
[7:4]
Reset
Value
-
3
MESO_SYNC
0x0
2
MESO_LPBK
0x0
1
Reserved
0x0
Is read-only and reports whether the mesochronous clock alignment
state machine has completed its process, having thus aligned the CDR
receive clock to the transmit clock.
When set, this register enables Mesochronous loopback mode, which
forces PMA received data to be re-transmitted on the PMA TX
interface. This mode requires that no PPM exists between RX data
and TX data (thus, both sides of the link use the same reference clock)
and also performs alignment of the CDR clock to the transmit clock
using the PMA CDR PLL skip bit functionality. This alignment is
automatically performed by a state machine when this loopback
register is set.
-
0
Reserved
0x0
-
Name
-
Description
Unused
Table 6-85 • GEN1_TX_PLL_CCP
Bit
Number
[7:4]
-
[2:0]
ATXICP_RATE0[2:0]
Reset
Value
Name
-
Description
Reserved
0x0
Defines the TX PLL charge pump current when the PMA is running in
PCIe Gen1 speed or in any other protocol. This register is R/W in order
to enable changing the default value by register programming, which is
expected to be performed before reset deassertion.
Note: This register can be programmed when the PHY is under reset.
Table 6-86 • GEN1_RX_PLL_CCP
Bit
Number
7
-
[6:4]
ARXCDRICP_RATE0[2:0]
3
-
[2:0]
ARXICP_RATE0[2:0]
Reset
Value
Name
-
Description
Reserved
0x0
-
Defines the RX PLL charge pump current when the PMA is
frequency locked and running in PCIe Gen1 speed or in any
other protocol. This register is R/W in order to enable changing
the default value by register programming, which is expected to
be performed before reset deassertion.
Reserved
0x0
Defines the RX PLL charge pump current when the PMA is
CDR locked and running in PCIe Gen1 speed or in any other
protocol. This register is R/W in order to enable changing the
default value by register programming, which is expected to be
performed before reset deassertion.
Note: This register can be programmed when the PHY is under reset.
Revision 3
178
SERDES Block Register Access Map
Table 6-87 • CDR_PLL_MANUAL_CR
Bit
Number
[7:3]
-
2
FINE_GRAIN
0x0
In PCS-driven mode when this register is set, it enables forcing
the CDR PLL state machine in fine grain state. In this state, the
CDR PLL locks on receive data, making RX data and RX
CLOCKP valid on the PMA interface.
1
COARSE_GRAIN
0x0
0
FREQ_LOCK
0x0
When set, this register enables forcing the CDR PLL state
machine when used in PCS driven mode (see Reg00 bit 3 set to
0) in coarse grain state. In this state, the CDR PLL performs a
coarse grain lock on receive data, enabling adjustment of its
clock up to 5000 PPM.
When set, this register enables forcing the CDR PLL state
machine when used in PCS-driven mode (see Reg00 bit 3 set to
0) in frequency lock state. In this state, the CDR PLL does not
lock on receive data but on the reference clock.
Name
Reset
Value
Reserved
Description
Table 6-88 • UPDATE_SETTINGS
Bit
Number
[7:0]
Reset
Value
0x00
Description
Is a transient register (read always reports 0) where writing a 1
in bit 0 triggers a new computation of PMA settings based on
the value written in register space registers. Note that for PCIe,
Microsemi recommends not using this command register when
the link is not transitioning to low power state or changing rate.
Note: This register can be programmed any time, except during calibration, and triggers the RX/TX shift load logic to
load new programmed settings into the SERDES. Thus, it must be written 0x01 only after a coherent set of
register updates need to be loaded.
179
Name
UPDATE_SETTINGS[7:0]
R e vi s i o n 3
RTG4 FPGA High-Speed Serial Interfaces
Table 6-89 • PRBS_ERR_CYC_FIRST_7_0
Bit
Number
[7:0]
Name
PRBS_ERR_CYC_FIRST[7:0]
Reset
Value
0x00
Description
PRBS last error cycle counter register bits[7:0].
This read-only register reports on which clock cycle the error
counter has first been incremented after the PRBS error
counter is enabled. It is a 50-bit counter, enabling performance
of bit error rate testing (BERT).
Note: The first error cycle counter information complementing the total number of errors detected might give
information about bursts of errors or distributed errors, but statistics might also be required. The test can be
rerun several times with different test periods.
Table 6-90 • PRBS_ERR_CYC_FIRST_15_8
Bit
Number
[7:0]
Name
PRBS_ERR_CYC_FIRST[15:8]
Reset
Value
0x00
Description
PRBS last error cycle counter register bits[15:8].
This read-only register reports on which clock cycle the
error counter has first been incremented after the
PRBS error counter is enabled. It is a 50-bit counter,
enabling performance of bit error rate testing (BERT).
Note: The first error cycle counter information complementing the total number of errors detected might give
information about bursts of errors or distributed errors, but statistics might also be required. The test can be
rerun several times with different test periods.
Table 6-91 • PRBS_ERR_CYC_FIRST_23_16
Bit
Number
[7:0]
Name
PRBS_ERR_CYC_FIRST[23:16]
Reset
Value
0x00
Description
PRBS last error cycle counter register bits[23:16].
This read-only register reports on which clock cycle the
error counter has first been incremented after the
PRBS error counter is enabled. It is a 50-bit counter,
enabling performance of BERT.
Note: The first error cycle counter information complementing the total number of errors detected might give
information about bursts of errors or distributed errors, but statistics might also be required. The test can be
rerun several times with different test periods.
Table 6-92 • PRBS_ERR_CYC_FIRST_31_24
Bit
Number
[7:0]
Name
PRBS_ERR_CYC_FIRST[31:24]
Reset
Value
0x00
Description
PRBS last error cycle counter register bits[31:24].
This read-only register reports on which clock cycle the
error counter has first been incremented after the
PRBS error counter is enabled. It is a 50-bit counter,
enabling performance of BERT.
Note: The first error cycle counter information complementing the total number of errors detected might give
information about bursts of errors or distributed errors, but statistics might also be required. The test can be
rerun several times with different test periods.
Revision 3
180
SERDES Block Register Access Map
Table 6-93 • PRBS_ERR_CYC_FIRST_39_32
Bit
Number
[7:0]
Reset
Value
0x00
Name
PRBS_ERR_CYC_FIRST[39:32]
Description
PRBS last error cycle counter register bits[39:32].
This read-only register reports on which clock cycle the
error counter has first been incremented after the
PRBS error counter is enabled. It is a 50-bit counter,
enabling performance of BERT.
Note: The first error cycle counter information complementing the total number errors detected might give information
about bursts of errors or distributed errors, but statistics might also be required. The test can be rerun several
times with different test periods.
Table 6-94 • PRBS_ERR_CYC_FIRST_47_40
Bit
Number
[7:2]
-
[1:0]
PRBS_ERR_CYC_FIRST[47:40]
Reset
Value
Name
-
Description
Reserved
0x0
PRBS last error cycle counter register bits [47:40].
This read-only register reports on which clock cycle the
error counter has first been incremented after the
PRBS error counter is enabled. It is a 50-bit counter,
enabling performance of bit error rate testing (BERT).
Note: The first error cycle counter information complementing the total number of errors detected might give
information about bursts of errors or distributed errors, but statistics might also be required. The test can be
rerun several times with different test periods.
Table 6-95 • PRBS_ERR_CYC_FIRST_49_48
Bit
Number
[7:2]
-
[1:0]
PRBS_ERR_CYC_FIRST[49:48]
Reset
Value
Name
-
Description
Reserved
0x0
PRBS last error cycle counter register bits[49:48].
This read-only register reports on which clock cycle the
error counter has first been incremented after the
PRBS error counter is enabled. It is a 50-bit counter,
enabling performance of BERT.
Note: The first error cycle counter information complementing the total number of errors detected might give
information about bursts of errors or distributed errors, but statistics might also be required. The test can be
rerun several times with different test periods.
181
R e vi s i o n 3
RTG4 FPGA High-Speed Serial Interfaces
Table 6-96 • PRBS_ERR_CYC_FIRST_7_0
Bit
Number
[7:0]
Name
PRBS_ERR_CYC_LAST[7:0]
Reset
Value
0x0
Description
PRBS last error cycle counter register bits [7:0].
This read-only register reports on which clock cycle the
error counter has last been incremented after the PRBS
error counter is enabled. It is a 50-bit counter, enabling
performance of BERT.
Note: The last error cycle counter information complementing the total number of errors detected might give
information about bursts of errors or distributed errors, but statistics might also be required. The test can be
rerun several times with different test periods.
Table 6-97 • PRBS_ERR_CYC_FIRST_15_8
Bit
Number
[7:0]
Name
PRBS_ERR_CYC_LAST[15:8]
Reset
Value
0x00
Description
PRBS last error cycle counter register bits[15:8].
This read-only register reports on which clock cycle the
error counter has last been incremented after the PRBS
error counter is enabled. It is a 50-bit counter, enabling
performance of bit error rate testing (BERT).
Note: The last error cycle counter information complementing the total number of errors detected might give
information about bursts of errors or distributed errors, but statistics might also be required. The test can be
rerun several times with different test periods.
Table 6-98 • PRBS_ERR_CYC_FIRST_23_16
Bit
Number
[7:0]
Name
PRBS_ERR_CYC_LAST[23:16]
Reset
Value
0x00
Description
PRBS last error cycle counter register bits [23:16].
This read-only register reports on which clock cycle the
error counter has last been incremented after the PRBS
error counter is enabled. It is a 50-bit counter, enabling
performance of BERT.
Note: The last error cycle counter information complementing the total number of errors detected might give
information about bursts of errors or distributed errors, but statistics might also be required. The test can be
rerun several times with different test periods.
Table 6-99 • PPRBS_ERR_CYC_FIRST_31_24
Bit
Number
[7:0]
Name
PRBS_ERR_CYC_LAST[31:24]
Reset
Value
0x00
Description
PRBS last error cycle counter register bits[31:24].
This read-only register reports on which clock cycle the
error counter has last been incremented after the PRBS
error counter is enabled. It is a 50-bit counter, enabling
performance of BERT.
Note: The last error cycle counter information complementing the total number of errors detected might give
information about bursts of errors or distributed errors, but statistics might also be required. The test can be
rerun several times with different test periods.
Revision 3
182
SERDES Block Register Access Map
Table 6-100 • PRBS_ERR_CYC_FIRST_39_32
Bit
Number
[7:0]
Name
PRBS_ERR_CYC_LAST[39:32]
Reset
Value
0x0
Description
PRBS last error cycle counter register bits[39:32].
This read-only register reports on which clock cycle the
error counter has last been incremented after the PRBS
error counter is enabled. It is a 50-bit counter, enabling
performance of bit error rate testing (BERT).
Note: The last error cycle counter information complementing the total number of errors detected might give
information about bursts of errors or distributed errors, but statistics might also be required. The test can be
rerun several times with different test periods.
Table 6-101 • PRBS_ERR_CYC_FIRST_47_40
Bit
Number
[7:0]
Name
PRBS_ERR_CYC_LAST[47:40]
Reset
Value
0x0
Description
PRBS last error cycle counter register bits[47:40].
This read-only register reports on which clock cycle the
error counter has last been incremented after the PRBS
error counter is enabled. It is a 50-bit counter, enabling
performance of bit error rate testing (BERT).
Note: The last error cycle counter information complementing the total number of errors detected might give
information about bursts of errors or distributed errors, but statistics might also be required. The test can be
rerun several times with different test periods.
Table 6-102 • PRBS_ERR_CYC_FIRST_49_48
Bit
Number
[7:2]
Reserved
[1:0]
PRBS_ERR_CYC_LAST[49:48]
Name
Reset
Value
0x0
0x0
Description
Reserved
PRBS last error cycle counter register bits[49:48].
This read-only register reports on which clock cycle the
error counter has last been incremented after the PRBS
error counter is enabled. It is a 50-bit counter, enabling
performance of BERT.
Note: The last error cycle counter information complementing the total number of errors detected might give
information about bursts of errors or distributed errors, but statistics might also be required. The test can be
rerun several times with different test periods.
183
R e vi s i o n 3
List of Changes
The following table shows important changes made in this document for each revision.
Date
Changes
Page
Revision 3
(July 2015)
Updated Figure 2-15 in SERDES chapter (SAR 69180).
34
Revision 2
(June 2015)
Updated the SERDESIF name to SERDES block in the document (SAR
63210).
NA
Added the "Using SERDES Block in EPCS Mode" section (SAR 63210).
132
Deleted TX PLL and CDR PLL Operation section in SERDES Chapter (SAR
63210).
NA
Updated the Table 3-4 on page 55 and Table 3-5 on page 55 (SAR 63210).
55 and 55
Added the Table 6-45 on page 159, Table 6-46 on page 160, Table 6-47 on
page 161, Table 6-48 on page 161, and Table 6-49 on page 161 tables (SAR
63210).
159, 160,
161, 161,
and 161
Updated the Figure 1-1 on page 8,Figure 1-5 on page 15, Figure 1-6 on page
17, Figure 1-7 on page 18, Figure 3-1 on page 41, Figure 3-2 on page 43,
Figure 4-1 on page 107, Figure 4-2 on page 109, Figure 5-1 on page 129,
Figure 4-2 on page 109, Figure 5-1 on page 129, Figure 5-2 on page 130,
Figure 2-1 on page 21, and Figure 2-2 on page 23 (SAR 63210).
8,15, 17, 18,
41, 43, 107,
109, 129,
109, 129,
130, 21, and
23.
Re-organized the "Serializer/De-serializer" chapter from 5 to 2 (SAR 63210).
21
Initial release.
NA
Revision 1
(November 2014)
Revision 3
184
Product Support
Microsemi SoC Products Group backs its products with various support services, including Customer
Service, Customer Technical Support Center, a website, electronic mail, and worldwide sales offices.
This appendix contains information about contacting Microsemi SoC Products Group and using these
support services.
Customer Service
Contact Customer Service for non-technical product support, such as product pricing, product upgrades,
update information, order status, and authorization.
From North America, call 800.262.1060
From the rest of the world, call 650.318.4460
Fax, from anywhere in the world, 408.643.6913
Customer Technical Support Center
Microsemi SoC Products Group staffs its Customer Technical Support Center with highly skilled
engineers who can help answer your hardware, software, and design questions about Microsemi SoC
Products. The Customer Technical Support Center spends a great deal of time creating application
notes, answers to common design cycle questions, documentation of known issues, and various FAQs.
So, before you contact us, please visit our online resources. It is very likely we have already answered
your questions.
Technical Support
For Microsemi SoC Products Support, visit
http://www.microsemi.com/products/fpga-soc/designsupport/fpga-soc-support
Website
You can browse a variety of technical and non-technical information on the SoC home page, at
www.microsemi.com/soc.
Contacting the Customer Technical Support Center
Highly skilled engineers staff the Technical Support Center. The Technical Support Center can be
contacted by email or through the Microsemi SoC Products Group website.
Email
You can communicate your technical questions to our email address and receive answers back by email,
fax, or phone. Also, if you have design problems, you can email your design files to receive assistance.
We constantly monitor the email account throughout the day. When sending your request to us, please
be sure to include your full name, company name, and your contact information for efficient processing of
your request.
The technical support email address is [email protected].
Revision 3
185
Product Support
My Cases
Microsemi SoC Products Group customers may submit and track technical cases online by going to My
Cases.
Outside the U.S.
Customers needing assistance outside the US time zones can either contact technical support via email
([email protected]) or contact a local sales office. Sales office listings can be found at
www.microsemi.com/soc/company/contact/default.aspx.
ITAR Technical Support
For technical support on RH and RT FPGAs that are regulated by International Traffic in Arms
Regulations (ITAR), contact us via [email protected]. Alternatively, within My Cases, select
Yes in the ITAR drop-down list. For a complete list of ITAR-regulated Microsemi FPGAs, visit the ITAR
web page.
186
R e vi s i o n 3
Microsemi Corporation (MSCC) offers a comprehensive portfolio of semiconductor and system
solutions for communications, defense & security, aerospace and industrial markets. Products
include high-performance and radiation-hardened analog mixed-signal integrated circuits,
FPGAs, SoCs and ASICs; power management products; timing and synchronization devices
and precise time solutions, setting the world's standard for time; voice processing devices; RF
solutions; discrete components; security technologies and scalable anti-tamper products;
Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design
capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif., and has
approximately 3,600 employees globally. Learn more at www.microsemi.com.
Microsemi Corporate Headquarters
One Enterprise, Aliso Viejo,
CA 92656 USA
Within the USA: +1 (800) 713-4113
Outside the USA: +1 (949) 380-6100
Sales: +1 (949) 380-6136
Fax: +1 (949) 215-4996
E-mail: [email protected]
© 2015 Microsemi Corporation. All
rights reserved. Microsemi and the
Microsemi logo are trademarks of
Microsemi Corporation. All other
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property of their respective owners.
Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or
the suitability of its products and services for any particular purpose, nor does Microsemi assume any
liability whatsoever arising out of the application or use of any product or circuit. The products sold
hereunder and any other products sold by Microsemi have been subject to limited testing and should not
be used in conjunction with mission-critical equipment or applications. Any performance specifications are
believed to be reliable but are not verified, and Buyer must conduct and complete all performance and
other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely
on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's
responsibility to independently determine suitability of any products and to test and verify the same. The
information provided by Microsemi hereunder is provided "as is, where is" and with all faults, and the entire
risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or
implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such
information itself or anything described by such information. Information provided in this document is
proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this
document or to any products and services at any time without notice.
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