INTEGRAL IN74HC299

IN74HC299
8-BIT BIDIRECTIONAL UNIVERSAL
SHIFT REGISTER WITH PARALLEL I/O
High-Performance Silicon-Gate CMOS
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The IN74HC299 is identical in pinout to the LS/ALS299. The
device inputs are compatible with standard CMOS outputs; with
pullup resistors, they are compatible with LS/ALSTTL outputs.
The IN74HC299features a multiplexed parallel input/output
data port to achieve full 8-bit handling in a 20 pin package. Due
to the large output drive capability and the 3-state feature, this
device is ideally suited for interface with bus lines in a busoriented system.
Two Mode-Select inputs and two Output Enable inputs are
used to choose the mode of operation as listed in the Function
Table. Synchronous parallel loading is accomplished by taking
both Mode-Select lines, S1 and S2, high. This places the outputs
in the high-impedance state, which permits data applied to the
data port to be clocked into the register. Reading out of the
register can be accomplished when the outputs are enabled. The
active-low asynchronous Reset overrides all other inputs.
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
High Noise Immunity Characteristic of CMOS Devices
LOGIC DIAGRAM
PIN 20=VCC
PIN 10 = GND
1
ORDERING INFORMATION
IN74HC299N Plastic
IN74HC299DW SOIC
TA = -55° to 125° C for all
packages
PIN ASSIGNMENT
IN74HC299
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage (Referenced to GND)
-0.5 to +7.0
V
VIN
DC Input Voltage (Referenced to GND)
-1.5 to VCC +1.5
V
VOUT
DC Output Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
IIN
DC Input Current, per Pin
mA
±20
IOUT
DC Output Current, per Pin
mA
±35
ICC
DC Supply Current, VCC and GND Pins
mA
±75
PD
Power Dissipation in Still Air, Plastic DIP+
750
mW
SOIC Package+
500
Tstg
Storage Temperature
-65 to +150
°C
260
TL
Lead Temperature, 1 mm from Case for 10
°C
Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
DC Supply Voltage (Referenced to GND)
VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
t r, tf
Input Rise and Fall Time (Figure 1) VCC
=2.0
V
VCC
=4.5
V
VCC =6.0 V
Min
2.0
0
-55
0
0
0
Max
6.0
VCC
+125
1000
500
400
Unit
V
V
°C
ns
This device contains protection circuitry to guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications of any voltage
higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and
VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or
VCC). Unused outputs must be left open. I/O pins must be connected to a properly terminated line
or bus.
2
IN74HC299
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
Guaranteed Limit
VCC
Symbol Parameter
Test Conditions
V
≤85
≤125
25 °C
to
°C
°C
-55°C
1.5
1.5
VOUT=0.1 V or VCC-0.1 V 2.0
1.5
VIH
Minimum High3.15
3.15
3.15
Level Input
4.5
IOUT≤ 20 µA
4.2
4.2
4.2
Voltage
6.0
0.3
0.3
VOUT=0.1 V or VCC-0.1 V 2.0
0.3
VIL
Maximum Low 0.9
0.9
0.9
Level Input
4.5
IOUT ≤ 20 µA
1.2
1.2
1.2
Voltage
6.0
1.9
1.9
VIN=VIH or VIL
1.9
VOH
Minimum High2.0
4.4
4.4
4.4
Level Output
4.5
IOUT ≤ 20 µA
5.9
5.9
5.9
Voltage
6.0
VIN=VIH or VIL
3.7
3.84
3.98
4.5
IOUT ≤ 6.0 mA (P/Q)
5.2
5.34
5.48
6.0
IOUT ≤ 7.8 mA (P/Q)
VIN=VIH or VIL
3.7
3.84
3.98
4.5
IOUT ≤ 4.0 mA (Q’)
5.2
5.34
5.48
6.0
IOUT ≤ 5.2 mA (Q’)
0.1
0.1
VIN= VIL or VIH
0.1
VOL
Maximum Low2.0
0.1
0.1
0.1
Level Output
4.5
IOUT ≤ 20 µA
0.1
0.1
0.1
Voltage
6.0
VIN=VIH or VIL
0.4
0.33
0.26
4.5
IOUT ≤ 6.0 mA (P/Q)
0.4
0.33
0.26
6.0
IOUT ≤ 7.8 mA (P/Q)
VIN=VIH or VIL
0.4
0.33
0.26
4.5
IOUT ≤ 4.0 mA (Q’)
0.4
0.33
0.26
6.0
IOUT ≤ 5.2 mA (Q’)
IIN
Maximum Input
VIN=VCC or GND
6.0
±0.1
±1.0
±1.0
Leakage Current
IOZ
Maximum Three- Output in High6.0
±0.5
±5.0
±10
State Leakage
Impedance State
Current
VIN= VIL or VIH
(QA thru QH)
VOUT=VCC or GND
VIN=VCC or GND
ICC
Maximum
6.0
8.0
80
160
Quiescent Supply IOUT=0µA
Current
(per Package)
3
Unit
V
V
V
V
µA
µA
µA
IN74HC299
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
Guaranteed Limit
VCC
Symbol
Parameter
V
25 °C ≤85°C ≤125°
C
to
-55°C
3.4
4.0
5.0
fmax
Maximum Clock Frequency (50% Duty 2.0
17
20
25
Cycle) (Figures 1 and 5)
4.5
20
24
29
6.0
255
215
170
tPLH,
Maximum Propagation Delay, Clock to 2.0
51
43
34
tPHL
QA’ or QH’ (Figures 1 and 5)
4.5
43
37
29
6.0
240
200
160
tPLH,
Maximum Propagation Delay, Clock to 2.0
48
40
32
tPHL
QA thru QH (Figures 1 and 5)
4.5
41
34
27
6.0
265
220
175
tPHL
Maximum Propagation Delay, Reset to 2.0
53
44
35
QA’ or QH’ (Figures 2 and 5)
4.5
45
37
30
6.0
285
240
190
tPHL
Maximum Propagation Delay, Reset to 2.0
57
48
38
QA thru QH (Figures 2 and 5)
4.5
48
41
32
6.0
225
190
150
tPLZ,
Maximum Propagation Delay , OE1, 2.0
45
38
30
tPHZ
OE2, S1, or S2 to QA thru QH (Figures 3 4.5
38
33
26
6.0
and 6)
225
190
150
tPZL,
Maximum Propagation Delay , OE1, 2.0
45
38
30
tPZH
OE2, S1, or S2 to QA thru QH (Figures 3 4.5
38
33
26
6.0
and 6)
90
75
60
tTLH, tTHL Maximum Output Transition Time, QA 2.0
18
15
12
thru QH (Figures 1 and 5)
4.5
15
13
10
6.0
110
95
75
tTLH, tTHL Maximum Output Transition Time, QA’ 2.0
22
19
15
thru QH’ (Figures 1 and 5)
4.5
19
16
13
6.0
CIN
Maximum Input Capacitance)
10
10
10
15
15
15
COUT
Maximum Three-State I/O Capacitance
(I/O in High-Impedance State), QA thru
QH
CPD
Power Dissipation Capacitance (Per
Package), Output Enable
Used to determine the no-load dynamic
power
consumption:
PD=CPDVCC2f+ICCVCC
4
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
Typical @25°C,VCC=5.0 V
240
pF
IN74HC299
TIMING REQUIREMENTS(CL=50pF,Input tr=tf=6.0 ns)
Guaranteed Limit
VCC
Symbol
Parameter
V
25 °C to≤85°C ≤125°C
55°C
150
125
100
tsu
Minimum Setup Time, Mode 2.0
30
25
20
Select S1 or S2 to Clock 4.5
26
21
17
6.0
(Figure 4)
150
125
100
tsu
Minimum Setup Time, Data 2.0
30
25
20
Inputs SA, SH, PA thru PH to 4.5
26
21
17
6.0
Clock
(Figure 4)
180
150
120
th
Minimum Hold Time, Clock to 2.0
36
30
24
Mode Select S1 or S2 (Figure 4.5
31
26
20
6.0
4)
5
5
5
th
Minimum Hold Time, Clock to 2.0
5
5
5
Data Inputs, SA, SH, PA thru PH 4.5
5
5
5
6.0
(Figure 4)
75
65
50
trec
Minimum
Recovery
Time, 2.0
15
13
10
Reset Inactive to Clock (Figure 4.5
13
11
9
6.0
2)
120
100
80
tw
Minimum Pulse Width, Clock 2.0
24
20
16
(Figure 1)
4.5
20
17
14
6.0
120
100
80
tw
Minimum Pulse Width, Reset 2.0
24
20
16
(Figure 2)
4.5
20
17
14
6.0
1000
1000
1000
t r, tf
Maximum Input Rise and Fall 2.0
500
500
500
Times (Figure 1)
4.5
400
400
400
6.0
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
IN74HC299
FUNCTION TABLE
Inputs
Response
Mode Rese Mode
Output Clock Serial PA/ PB/ PC/ PD/ PE/ PF/ PG/ PH/ QA’ QH’
t
Select Enables
Inputs QA QB QC QD QE QF QG QH
S2 S1 OE1 OE2
DA DH
Reset
L
X L
L
L
X
X X L L L L L L L L L
L
L
L X
L
L
X
X X L L L L L L L L L
L
L
H H
X
X
X
X X
QA through QH=Z
L
L
Shift
H
L H
H
X
D X Shift Right: QA through QH=Z; D QG
Right
DA
FA; FA
FB; etc
H
L H
X
H
D X Shift Right: QA through QH=Z; D QG
DA
FA; FA FB; etc
H
L H
L
L
D X
Shift Right: DA FA =QA;
D QG
FA
FB =QB; etc
Shift
H
H L
H
X
X D Shift Left: QA through QH=Z; QB D
Left
DH
FH; FH
FG; etc
H
H L
X
H
X D Shift Left: QA through QH=Z; QB D
DH
FH; FH
FG; etc
H
H L
L
L
X D
Shift Left: DH
FH =QH;
QB D
FH
FG =QG; etc
Parallel H
H H
X
X
X X
Parallel Load:PN
FN
PA PH
Load
Hold
H
L L
H
X
X
X X Hold: QA through QH=Z; FN=FN PA PH
H
L L
X
H
X
X X Hold: QA through QH=Z; FN=FN PA PH
H
L L
L
L
X
X X
Hold: QN =QH
PA PH
Z = high impedance
D = data on serial input
F = flip-flop (see Logic Diagram)
When one or both output controls are high the eight input/output terminals are disabled to the
highimpedance state; however, sequential operation or clearing of the register is not affected.
6
IN74HC299
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3a. Switching Waveforms
Figure 3b. Switching Waveforms
Figure 4. Switching Waveforms
Figure 5. Test Circuit
Figure 6. Test Circuit
7
IN74HC299
EXPANDED LOGIC DIAGRAM
8