KODENSHI KK74AC323

TECHNICAL DATA
8-Bit Bidirectional Universal
Shift Register with Parallel I/O
KK74AC323
High-Speed Silicon-Gate CMOS
The KK74AC323 is identical in pinout to the LS/ALS323,
HC/HCT323. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LS/ALS outputs.
The KK74AC323 features a multiplexed parallel input/output data port
to achieve full 8-bit handling in a 20 pin package. Due to the large output
drive capability and the 3-state feature, this device is ideally suited for
interface with bus lines in a bus-oriented system.
Two Mode-Select inputs and two Output Enable inputs are used to
choose the mode of operation as listed in the Function Table.
Synchronous parallel loading is accomplished by taking both ModeSelect lines, S1 and S2, high. This places the outputs in the highimpedance state, which permits data applied to the data port to be clocked
into the register. Reading out of the register can be accomplished when
the outputs are enabled. The active-low synchronous Reset overrides all
other inputs.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA; 0.1 µA @ 25°C
• High Noise Immunity Characteristic of CMOS Devices
• Outputs Source/Sink 24 mA
ORDERING INFORMATION
KK74AC323N Plastic
KK74AC323DW SOIC
TA = -40° to 85° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 20=VCC
PIN 10 = GND
1
KK74AC323
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
-0.5 to +7.0
V
VCC
DC Supply Voltage (Referenced to GND)
VIN
DC Input Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
DC Output Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
DC Input Current, per Pin
±20
mA
IOUT
DC Output Sink/Source Current, per Pin
±50
mA
ICC
DC Supply Current, VCC and GND Pins
±50
mA
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
-65 to +150
°C
260
°C
VOUT
IIN
Tstg
TL
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIN, VOUT
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TJ
Junction Temperature (PDIP)
TA
Operating Temperature, All Package Types
IOH
Output Current - High
IOL
Output Current - Low
tr, tf
*
Parameter
Input Rise and Fall Time
(except Schmitt Inputs)
*
Min
Max
Unit
2.0
6.0
V
0
VCC
V
140
°C
+85
°C
-24
mA
24
mA
150
40
25
ns/V
-40
VCC =3.0 V
VCC =4.5 V
VCC =5.5 V
0
0
0
VIN from 30% to 70% VCC
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or
VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused
outputs must be left open.
2
KK74AC323
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC
Symbol
Parameter
Test Conditions
Guaranteed Limits
V
25 °C
-40°C to
85°C
Unit
VIH
Minimum HighLevel Input Voltage
VOUT=0.1 V or VCC-0.1 V
3.0
4.5
5.5
2.1
3.15
3.85
2.1
3.15
3.85
V
VIL
Maximum Low Level Input Voltage
VOUT=0.1 V or VCC-0.1 V
3.0
4.5
5.5
0.9
1.35
1.65
0.9
1.35
1.65
V
VOH
Minimum HighLevel Output Voltage
IOUT ≤ -50 µA
3.0
4.5
5.5
2.9
4.4
5.4
2.9
4.4
5.4
V
3.0
4.5
5.5
2.56
3.86
4.86
2.46
3.76
4.76
3.0
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
VIN= VIH or VIL
IOL=12 mA
IOL=24 mA
IOL=24 mA
3.0
4.5
5.5
0.36
0.36
0.36
0.44
0.44
0.44
*
VIN=VIH or VIL
IOH=-12 mA
IOH=-24 mA
IOH=-24 mA
VOL
Maximum LowLevel Output Voltage
IOUT ≤ 50 µA
V
*
IIN
Maximum Input
Leakage Current
VIN=VCC or GND
5.5
±0.1
±1.0
µA
IOZ
Maximum ThreeState Leakage
Current
VIN (OE)= VIH or VIL
VIN =VCC or GND
VOUT =VCC or GND
5.5
±0.6
±6.0
µA
IOLD
+Minimum Dynamic
Output Current
VOLD=1.65 V Max
5.5
75
mA
IOHD
+Minimum Dynamic
Output Current
VOHD=3.85 V Min
5.5
-75
mA
ICC
Maximum Quiescent
Supply Current
(per Package)
VIN=VCC or GND
5.5
80
µA
8.0
*
All outputs loaded; thresholds on input associated with output under test.
+Maximum test duration 2.0 ms, one output loaded at a time.
Note: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC
3
KK74AC323
AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input tr=tf=3.0 ns)
VCC*
Symbol
Parameter
Guaranteed Limits
25 °C
V
Min
Max
-40°C to
85°C
Min
Unit
Max
fmax
Maximum Clock Frequency (Figure 1)
3.3
5.0
90
130
80
105
tPLH
Propagation Delay, Clock to QA’ or QH’
(Figure 1)
3.3
5.0
8.5
5.5
20.5
14.0
7.0
4.5
22.0
15.0
ns
tPHL
Propagation Delay, Clock to QA’ or QH’
(Figure 1)
3.3
5.0
8.5
5.5
21.5
14.5
7.0
5.0
23.0
16.0
ns
tPLH
Propagation Delay, Clock to QA thru QH
(Figure 1)
3.3
5.0
9.0
6.0
20.5
14.5
7.5
5.0
22.5
16.0
ns
tPHL
Propagation Delay, Clock to QA thru QH
(Figure 1)
3.3
5.0
10.0
6.5
23.0
16.0
8.5
6.0
24.5
17.5
ns
tPZH
Propagation Delay , OE1, OE2 to QA thru QH
(Figure 3)
3.3
5.0
7.0
4.5
18.0
12.5
6.0
4.0
19.5
13.5
ns
tPZL
Propagation Delay , OE1, OE2 to QA thru QH
(Figure 3)
3.3
5.0
7.0
5.0
18.0
12.5
6.0
4.0
20.5
14.0
ns
tPHZ
Propagation Delay , OE1, OE2 to QA thru QH
(Figure 3)
3.3
5.0
6.5
3.5
18.5
14.0
5.5
3.0
19.5
15.0
ns
tPLZ
Propagation Delay , OE1, OE2 to QA thru QH
(Figure 3)
3.3
5.0
5.5
3.5
17.0
12.5
4.5
2.0
19.0
13.5
ns
CIN
Maximum Input Capacitance
5.0
4.5
MHz
4.5
pF
Typical @25°C,VCC=5.0 V
CPD
Power Dissipation Capacitance
170
pF
Voltage Range 3.3 V is 3.3 V ±0.3 V
Voltage Range 5.0 V is 5.0 V ±0.5 V
*
4
KK74AC323
TIMING REQUIREMENTS (CL=50pF,Input tr=tf=3.0 ns)
VCC*
Symbol
Parameter
Guaranteed Limits
V
25 °C
-40°C to
85°C
Unit
tsu
Minimum Setup Time, Mode Select S1 or S2
to Clock (Figure 4)
3.3
5.0
8.0
5.0
8.5
5.5
ns
tsu
Minimum Setup Time, Data Inputs PA thru PH
to Clock (Figure 4)
3.3
5.0
5.5
3.5
6.0
4.0
ns
tsu
Minimum Setup Time, Data Inputs SA, SH to
Clock (Figure 4)
3.3
5.0
6.5
4.0
7.0
4.5
ns
tsu
Minimum Setup Time, Reset to Clock (Figure
2)
3.3
5.0
6.5
4.0
7.0
4.5
ns
th
Minimum Hold Time, Clock to Mode Select
S1 or S2 (Figure 4)
3.3
5.0
0.5
1.0
0.5
1.0
ns
th
Minimum Hold Time, Clock to Data Inputs PA
thru PH (Figure 4)
3.3
5.0
0
1.0
0
1.0
ns
th
Minimum Hold Time, Clock to Data Inputs
SA, SH (Figure 4)
3.3
5.0
0
1.0
0.5
1.0
ns
th
Minimum Hold Time, Clock to Reset (Figure
2)
3.3
5.0
0
1.0
0
1.0
ns
tw
Minimum Pulse Width, Clock (Figure 1)
3.3
5.0
4.5
3.5
5.0
3.5
ns
tw
Minimum Pulse Width, Reset (Figure 2)
3.3
5.0
4.5
3.5
5.0
3.5
ns
Voltage Range 3.3 V is 3.3 V ±0.3 V
Voltage Range 5.0 V is 5.0 V ±0.5 V
*
5
KK74AC323
FUNCTION TABLE
Inputs
Mode
Reset
Mode
Select
Response
Output
Enables
Clock
Serial
Inputs
PA/ PB/ PC/ PD/ PE/ PF/ PG/ PH/ QA’ QH’
QA QB QC QD QE QF QG QH
S2
S1
OE1
OE2
L
X
L
L
L
X
X
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
X
X
L
L
L
L
L
L
L
L
L
L
L
H
H
X
X
X
X
QA through QH=Z
L
L
H
L
H
H
X
D
X
Shift Right: QA through QH=Z;
F A; F A
FB; etc
DA
D
QG
H
L
H
X
H
D
X
Shift Right: QA through QH=Z;
FA; FA FB; etc
DA
D
QG
H
L
H
L
L
D
X
Shift Right: DA FA =QA;
FB =QB; etc
FA
D
QG
H
H
L
H
X
X
D
Shift Left: QA through QH=Z;
FH; FH
FG; etc
DH
QB
D
H
H
L
X
H
X
D
Shift Left: QA through QH=Z;
F H; F H
FG; etc
DH
QB
D
H
H
L
L
L
X
D
Shift Left: DH
FH =QH;
FG =QG; etc
FH
QB
D
Parallel
Load
H
H
H
X
X
X
X
PA
PH
Hold
H
L
L
H
X
X
X
X
Hold: QA through QH=Z; FN=FN
PA
PH
H
L
L
X
H
X
X
X
Hold: QA through QH=Z; FN=FN
PA
PH
H
L
L
L
L
X
X
X
Hold: QN =QH
PA
PH
Reset
Shift
Right
Shift
Left
DA D H
X
Parallel Load:PN
FN
Z = high impedance
D = data on serial input
F = flip-flop (see Logic Diagram)
When one or both output controls are high the eight input/output terminals are disabled to the high-impedance state;
however, sequential operation or clearing of the register is not affected.
6
KK74AC323
Figure 1. Switching Waveform
Figure 2. Switching Waveform
Figure 3. Switching Waveform
Figure 4. Switching Waveform
7
KK74AC323
EXPANDED LOGIC DIAGRAM
8
KK74AC323
N SUFFIX PLASTIC DIP
(MS - 001AD)
A
Dimension, mm
11
20
B
1
10
Symbol
MIN
MAX
A
24.89
26.92
B
6.1
7.11
5.33
C
F
L
C
-T- SEATING
PLANE
D
0.36
0.56
F
1.14
1.78
G
2.54
H
7.62
N
G
K
M
J
H
D
0.25 (0.010) M T
NOTES:
1. Dimensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
J
0°
10°
K
2.92
3.81
L
7.62
8.26
M
0.2
0.36
N
0.38
D SUFFIX SOIC
(MS - 013AC)
A
20
11
H
Dimension, mm
B
1
P
10
G
R x 45
C
-TK
D
SEATING
PLANE
J
0.25 (0.010) M T C M
NOTES:
1. Dimensions A and B do not include mold flash or protrusion.
2. Maximum mold flash or protrusion 0.15 mm (0.006) per side
for A; for B ‑ 0.25 mm (0.010) per side.
F
M
Symbol
MIN
MAX
A
12.6
13
B
7.4
7.6
C
2.35
2.65
D
0.33
0.51
F
0.4
1.27
G
1.27
H
9.53
J
0°
8°
K
0.1
0.3
M
0.23
0.32
P
10
10.65
R
0.25
0.75
9