INTEGRAL IN74HC651N

IN74HC652
OCTAL 3-STATE BUS TRANSCEIVERS
AND D FLIP-FLOPS
High-Performance Silicon-Gate CMOS
•
•
•
•
The IN74HC652 is identical in pinout to the LS/ALS652. The
device inputs are compatible with standard CMOS outputs; with
pullup resistors, they are compatible with LS/ALSTTL outputs.
These devices consists of bus transceiver circuits, D-type flipflop, and control circuitry arranged for multiplex transmission of
data directly from the data bus or from the internal storage
registers. Direction and Output Enable are provided to select the
read-time or stored data function. Data on the A or B Data bus,
or both, can be stored in the internal D flip-flops by low-to-high
transitions at the appropriate clock pins (A-to-B Clock or B-to-A
Clock) regardless of the select or enable or enable control pins.
When A-to-B Source and B-to-A Source are in the real-time
transfer mode, it is also possible to store data without using the
internal D-type flip-flops by simulta-neously enabling Direction
and Output Enable. In this configuration each output reinforces
its input. Thus, when all other data sources to the two sets of bus
lines are at high impedance, each set of bus lines will remain at
its last state.
The IN74HC652 has noninverted outputs.
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
High Noise Immunity Characteristic of CMOS Devices
LOGIC DIAGRAM
PIN 24=VCC
PIN 12 = GND
1
ORDERING INFORMATION
IN74HC651N Plastic
IN74HC651DW SOIC
TA = -55° to 125° C for all
packages
PIN ASSIGNMENT
IN74HC652
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage (Referenced to GND)
-0.5 to +7.0
V
VIN
DC Input Voltage (Referenced to GND)
-1.5 to VCC +1.5
V
VOUT
DC Output Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
IIN
DC Input Current, per Pin
mA
±20
IOUT
DC Output Current, per Pin
mA
±35
ICC
DC Supply Current, VCC and GND Pins
mA
±75
PD
Power Dissipation in Still Air, Plastic DIP+
750
mW
SOIC Package+
500
Tstg
Storage Temperature
-65 to +150
°C
260
TL
Lead Temperature, 1 mm from Case for 10
°C
Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
DC Supply Voltage (Referenced to GND)
VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
t r, tf
Input
Rise
and
Fall
Time VCC =2.0 V
(Figures2,3)
VCC =4.5 V
VCC =6.0 V
Min
2.0
0
-55
0
0
0
Max
6.0
VCC
+125
1000
500
400
Unit
V
V
°C
ns
This device contains protection circuitry to guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications of any voltage
higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and
VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or
VCC). Unused outputs must be left open. I/O pins must be connected to a properly terminated line
or bus.
2
IN74HC652
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
Guaranteed Limit
VCC
Symbol Parameter
Test Conditions
V
≤85
≤125
25 °C
to
°C
°C
-55°C
1.5
1.5
VOUT=0.1 V or VCC-0.1 V 2.0
1.5
VIH
Minimum High3.15
3.15
3.15
Level Input
4.5
IOUT≤ 20 µA
4.2
4.2
4.2
Voltage
6.0
0.5
0.5
VOUT=0.1 V or VCC-0.1 V 2.0
0.5
VIL
Maximum Low 1.35
1.35
1.35
Level Input
4.5
IOUT ≤ 20 µA
1.8
1.8
1.8
Voltage
6.0
1.9
1.9
VIN=VIH or VIL
1.9
VOH
Minimum High2.0
4.4
4.4
4.4
Level Output
4.5
IOUT ≤ 20 µA
5.9
5.9
5.9
Voltage
6.0
VIN=VIH or VIL
3.7
3.84
3.98
4.5
IOUT ≤ 6.0 mA
5.2
5.34
5.48
6.0
IOUT ≤ 7.8 mA
0.1
0.1
VIN= VIL or VIH
0.1
VOL
Maximum Low2.0
0.1
0.1
0.1
Level Output
4.5
IOUT ≤ 20 µA
0.1
0.1
0.1
Voltage
6.0
VIN=VIH or VIL
0.4
0.33
0.26
4.5
IOUT ≤ 6.0 mA
0.4
0.33
0.26
6.0
IOUT ≤ 7.8 mA)
6.0
IIN
Maximum Input
VIN=VCC or GND
±0.1
±1.0
±1.0
Leakage Current
(Pins 1,2,3,21,22,and
23)
6.0
IOZ
Maximum Three- Output in High±0.5
±5.0
±10
Impedance State
State Leakage
VIN= VIL or VIH
Current
VOUT=VCC or GND,
I/O Pins
VIN=VCC or GND
ICC
Maximum
6.0
8.0
80
160
Quiescent Supply IOUT=0µA
Current
(per Package)
3
Unit
V
V
V
V
µA
µA
µA
IN74HC652
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
Guaranteed Limit
VCC
Symbol
Parameter
V
25 °C ≤85°C ≤125
to
°C
-55°C
270
225
180
tPLH,
Maximum Propagation Delay, Input A to 2.0
54
45
36
tPHL
Output B (or Input B to Output A) 4.5
46
38
31
6.0
(Figures 2,3 and 9)
360
300
240
tPLH,
Maximum Propagation Delay, A-to-B 2.0
72
60
48
tPHL
Clock to Output B (or B-to-A Clock to 4.5
61
51
41
Output
A) 6.0
(Figures 1 and 9)
330
275
220
tPLH,
Maximum Propagation Delay, A-to-B 2.0
66
55
44
tPHL
Source to Output B (or B-to-A Source to 4.5
56
47
37
6.0
Output A) (Figures 4 and 9)
255
215
170
tPLZ,
Maximum Propagation Delay , Direction 2.0
51
43
34
tPHZ
or Output Enable to Output A or B 4.5
43
37
29
6.0
(Figures 5,6 and 10)
270
225
180
tPZL,
Maximum Propagation Delay , Direction 2.0
54
45
36
tPZH
or Output Enable to Output A or B 4.5
46
38
31
6.0
(Figures 5,6 and 10)
90
75
60
tTLH, tTHL Maximum Output Transition Time, Any 2.0
18
15
12
4.5
Output
15
13
10
6.0
(Figure 2)
CIN
Maximum Input Capacitance
10
10
10
COUT
Maximum Three-State I/O Capacitance
15
15
15
(Output in High-Impedance State
CPD
Power Dissipation Capacitance (Per
Channel)
Used to determine the no-load dynamic
power
consumption:
PD=CPDVCC2f+ICCVCC
4
Unit
ns
ns
ns
ns
ns
ns
pF
pF
Typical @25°C,VCC=5.0 V
60
pF
IN74HC652
TIMING REQUIREMENTS(Input tr=tf=6.0 ns)
Parameter
tsu
Minimum Setup Time, Input A
to
A-to-B Clock (or Input B to Bto-A Clock) (Figure 7)
Minimum Hold Time, A-to-B
Clock to Input A (or B-to-A
Clock
to
Input B) (Figure 7)
Minimum Pulse Width, A-to-B
Clock (or B-to-A Clock)
(Figure 7)
Maximum Input Rise and Fall
Times (Figures 2 and 3)
th
tw
t r, tf
Guaranteed Limit
25 °C to≤85°C ≤125°C
55°C
75
65
50
15
13
10
13
11
9
VCC
V
Symbol
2.0
4.5
6.0
Unit
ns
2.0
4.5
6.0
25
5
5
30
6
5
40
8
7
ns
2.0
4.5
6.0
2.0
4.5
6.0
75
15
13
1000
500
400
95
19
16
1000
500
400
110
22
19
1000
500
400
ns
TIMING DIAGRAM
5
ns
IN74HC652
FUNCTION TABLE
Dir.
OE
L
H
CAB CBA SAB SBA
X
X*
L
L
X
X
X
X
X
X
L
X
L
X
H
X
H
X*
L
X
X*
L
X
X*
H
X
X*
H
X
X
H
H
H
H
X
X*
X*
X
X*
X
H
H
X
H
L
X
A
INPUTS
B
INPUTS
FUNCTION
Both the A bus and the B bus are
inputs.
Z
Z
The output functions of the A and B
bus are disabled.
INPUTS
INPUTS Both the A and B bus are used for
inputs to the internal flip-flops. Data at
the bus will be stored on low to high
transition of the clock inputs.
OUTPUTS INPUTS The A bus are outputs and the B bus
are inputs.
L
L
The data at the B bus are displayed
H
H
at the A bus.
L
L
The data at the B bus are displayed
H
H
at the A bus. The data of the B bus
are stored to the internal flip-flops on
low to high transition of the clock
pulse.
Qn
X
The data stored to the internal flipflops, are displayed at the A bus.
H
H
The data at the B bus are stored to
L
L
the internal flip-flops on low to high
transition of the clock pulse. The
states of the internal flip-flops output
directly to the A bus.
INPUTS OUTPUTS The A bus are inputs and the B bus
are outputs.
L
L
The data at the A bus are displayed
H
H
at the B bus.
L
L
The data at the B bus are displayed
H
H
at the A bus. The data of the B bus
are stored to the internal flip-flops on
low to high transition of the clock
pulse.
X
Qn
The data stored to the internal flipflops are displayed at the B bus.
L
L
The data at the A bus are stored to
H
H
the internal flip-flops on low to high
transition of the clock pulse. The
states of the internal flip-flops output
directly to the B bus.
OUTPUTS OUTPUTS Both the A bus and the B bus are
outputs
Qn
Qn
The data stored to the internal flipflops are displayed at the A and B bus
respectively.
Qn
Qn
The output at the A bus are displayed
at the B bus, the output at the B bus
are displayed at the A bus respec.
X : DON’T CARE
Z : HIGH IMPEDANCE
Qn : THE DATA STORED TO THE INTERNAL FLIP-FLOPS BY MOST RECENT LOW TO HIGH
TRANSITION OF THE CLOCK INPUTS
*
: THE DATA AT THE A AND B BUS WILL BE STORED TO THE INTERNAL FLIP-FLOPS ON EVERY
LOW TO TRANSITION OF THE CLOCK INPUTS
6
IN74HC652
SWITCHING DIAGRAMS
Figure 1. Switching Waveforms
Figure 2. A Data Port = Input, B Data Port
= Output
Figure 3. A Data Port = Output, B Data
Port = Input
Figure 4. Switching Waveforms
Figure 5. Switching Waveforms
7
IN74HC652
Figure 6. Switching Waveforms
Figure 7. Switching Waveforms
Figure 9. Test Circuit
Figure 10. Test Circuit
8
IN74HC652
EXPANDED LOGIC DIAGRAM
9