TECHNICAL DATA IN74LV86 Quad 2-Input Exclusive OR Gate The 74LV86 is a low–voltage Si–gate CMOS device and is pin and function compatible with the 74HC/HCT86. The 74LV86 provides the 2-input EXCLUSIVE-OR function. N SUFFIX PLASTIC 14 1 • Output voltage levels are compatible with input levels of CMOS, NMOS and TTL ICS • Supply voltage range: 1.2 to 5.5 V • Low input current: 1.0 µА; 0.1 µА at Т = 25 °С • Output current: 6 mA at Vcc = 3.0 V; 12 mA at Vcc = 4.5V • High Noise Immunity Characteristic of CMOS Devices D SUFFIX SOIC 14 1 ORDERING INFORMATION IN74LV86N Plastic IN74LV86D SOIC TA = -40° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs PIN 16=VCC PIN 08 = GND Outputs An Bn Yn L H H L L L H L H H H L H= high level L = low level 1 IN74LV86 MAXIMUM RATINGS* Symbol VCC Parameter Value Unit DC supply voltage -0.5 to +5.0 V 1 Input diode current ±20 mA 2 Output diode current ±50 mA Output source or sink current ±25 mA ICC VCC current ±50 mA IGND GND current ±50 mA IIK * IOK * IO * 3 PD Tstg TL Power dissipation per package: * Plastic DIP SO 4 mW 750 500 Storage Temperature -65 to +150 °C 260 °C Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm (SO Package) from Case for 4 Seconds * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. *1 VI < -0.5 V or VI > VCC + 0.5 V. *2 VO < -0.5 V or VO > VCC + 0.5 V. *3 -0.5 V < VO < VCC + 0.5 V. *4 Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C SO Package: : - 8 mW/°C from 70° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter DC Supply Voltage Min Max Unit 1.2 5.5 V VI DC Input Voltage 0 VCC V VO DC Output Voltage 0 VCC V TA Operating Temperature, All Package Types -40 +125 °C tr, tf Input Rise and Fall Time (Figure 1) 0 0 0 0 500 200 100 50 ns/V 1.0 В ≤VCC <2.0 В 2.0 В ≤VCC <2.7 В 2.7 В ≤VCC <3.6 В 3.6 В ≤VCC ≤5.5 В This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 IN74LV86 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter Test VCC conditions V Guaranteed Limit -40°C to 25°C 85°C Unit 125°C min max min max min max VIH HIGH level input voltage 1.2 2.0 2.7 3.0 3.6 4.5 5.5 0.9 1.4 2.0 2.0 2.0 3.15 3.85 - 0.9 1.4 2.0 2.0 2.0 3.15 3.85 - 0.9 1.4 2.0 2.0 2.0 3.15 3.85 - V VIL LOW level input voltage 1.2 2.0 2.7 3.0 3.6 4.5 5.5 - 0.3 0.6 0.8 0.8 0.8 1.35 1.65 - 0.3 0.6 0.8 0.8 0.8 1.35 1.65 - 0.3 0.6 0.8 0.8 0.8 1.35 1.65 V VOH HIGH level output voltage VI = VIH or VIL IO = -100 µА 1.2 2.0 2.7 3.0 3.6 4.5 5.5 1.05 1.85 2.55 2.85 3.45 4.35 5.35 - 1.0 1.8 2.5 2.8 3.4 4.3 5.3 - 1.0 1.8 2.5 2.8 3.4 4.3 5.3 - V VI = VIH or VIL IO = -6 mА 3.0 2.48 - 2.34 - 2.20 - V VI = VIH or VIL IO = -12 mА 4.5 3.70 - 3.60 - 3.50 - V VI = VIH or VIL IO = 100 µА 1.2 2.0 2.7 3.0 3.6 4.5 5.5 - 0.15 0.15 0.15 0.15 0.15 0.15 0.15 - 0.2 0.2 0.2 0.2 0.2 0.2 0.2 - 0.2 0.2 0.2 0.2 0.2 0.2 0.2 V VI = VIH or VIL IO = 6 mА 3.0 - 0.33 - 0.40 - 0.50 V VI = VIH or VIL IO = 12 mА 4.5 - 0.40 - 0.55 - 0.65 V Input current VI = VCC or 0 V 5.5 - ±0.1 - ±1.0 - ±1.0 µА ICC Supply current VI =VCC or 0 V IO = 0 µА 5.5 - 4.0 - 20 - 40 µА ICC1 Additional quiescent supply current per input VI =VCC – 0.6 V 2.7 3.6 - 0.2 0.2 - 0.5 0.5 - 0.85 0.85 mA VOL II LOW level output voltage 3 IN74LV86 AC ELECTRICAL CHARACTERISTICS (CL=50 pF, RL = 1 kΩ, tr=tf=2.5 ns) Symbol Parameter tPHL, tPLH Propagation delay , An ,Bn, to Yn CI CPD Test VCC conditions V Guaranteed Limit -40°C to 25°C 85°C 125°C min max min max min max Unit VI = 0 V or VCC Figure 1, 2 1.2 2.0 2.7 3.0 4.5 - 140 24 19 15 13 - 150 32 24 19 16 - 180 41 30 24 20 ns Input capacitance ТA = 25°C 5.0 - 7.0 - - - - pF Power dissipation capacitance (per gate) VI = 0 V or VCC 5.5 - 60 - - - - pF TA = 25°C tr INPUT A OR B tf 10% VM (1) GND t PLH OUTPUT Y (2) V1 90% t PHL VOH (1) VM VOL Figure 1. Switching Waveforms Note: (1) VM = 1.5 V at VCC = 2.7 V VM = 0.5 ⋅VCC at VCC =1.2 V, 2.0 V, 3.0 V, 4.5 V (2) V1 = VCC at VCC =1.2 V, 2.0 V, 2.7 V, 4.5 V V1 = 2.7 V at VCC = 3.0 V TEST POINT DEVICE UNDER TEST OUTPUT RL * CL * Includes all probe and jig capacitance Figure 4. Test Circuit 4 IN74LV86 N SUFFIX PLASTIC DIP (MS - 001AA) A Dimension, mm 8 14 B 7 1 Symbol MIN MAX A 18.67 19.69 B 6.1 7.11 5.33 C F L C -T- SEATING PLANE N G M K J H D 0.25 (0.010) M T NOTES: 1. Dimensions “A”, “B” do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side. D 0.36 0.56 F 1.14 1.78 G 2.54 H 7.62 J 0° 10° K 2.92 3.81 L 7.62 8.26 M 0.2 0.36 N 0.38 D SUFFIX SOIC (MS - 012AB) Dimension, mm A 14 8 H B 1 G P 7 R x 45 C -TK D SEATING PLANE M Symbol MIN MAX A 8.55 8.75 B 3.8 4 C 1.35 1.75 D 0.33 0.51 F 0.4 1.27 G 1.27 H 5.27 J 0° 8° K 0.1 0.25 1. Dimensions A and B do not include mold flash or protrusion. M 0.19 0.25 2. Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for B ‑ 0.25 mm (0.010) per side. P 5.8 6.2 R 0.25 0.5 J 0.25 (0.010) M T C M NOTES: F 5