TECHNICAL DATA KK74LV32 Quad 2-Input OR Gate The KK74LV32 is low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT32A. The KK74LV32 provides the 2-input AND function. • Optimized for Low Voltage applications: 1.2 to 3.6 V • Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V • Low Input Current ORDERING INFORMATION KK74LV32N Plastic KK74LV32D SOIC TA = -40° ÷ 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM A1 B1 A2 B2 A3 B3 A4 B4 PIN 14 =VCC PIN 7 = GND Y1 Y2 Y3 FUNCTION TABLE Y4 Input Output A B Y = A*B L L L L H H H L H H H H H - high level L - low level 1 KK74LV32 MAXIMUM RATINGS* Symbol VCC Parameter DC supply voltage (Referenced to GND) Value Unit -0.5 ÷ +5.0 V 1 DC input diode current ±20 mA 2 DC output diode current ±50 mA DC output source or sink current -bus driver outputs ±25 mA ICC DC VCC current for types with - bus driver outputs ±50 mA IGND DC GND current for types with - bus driver outputs ±50 mA Power dissipation per package, plastic DIP+ SOIC package+ 750 500 mW -65 ÷ +150 °C 260 °C IIK * IOK * IO *3 PD Tstg TL Storage temperature Lead temperature, 1.5 mm from Case for 10 seconds (Plastic DIP ), 0.3 mm (SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C SOIC Package: : - 8 mW/°C from 70° to 125°C *1: VI < -0.5V or VI > VCC+0.5V *2: Vo < -0.5V or Vo > VCC+0.5V *3: -0.5V < Vo < VCC+0.5V RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time VCC =1.2 V VCC =2.0 V VCC =3.0 V VCC =3.6 V Min Max Unit 1.2 3.6 V 0 VCC V -40 +125 °C 0 0 0 0 1000 700 500 400 ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 KK74LV32 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter Test Conditions Guaranteed Limit VCC, V 25°C min max Unit -40°C ÷ 85°C min max -40°C ÷ 125°C min max VIH High-Level Input Voltage 1.2 2.0 3.0 3.6 0.9 1.4 2.1 2.5 - 0.9 1.4 2.1 2.5 - 0.9 1.4 2.1 2.5 - V VIL Low -Level Input Voltage 1.2 2.0 3.0 3.6 - 0.3 0.6 0.9 1.1 - 0.3 0.6 0.9 1.1 - 0.3 0.6 0.9 1.1 V VOH High-Level Output Voltage VI = VIL or VIH IO = -50 µА 1.2 2.0 3.0 3.6 1.1 1.92 2.92 3.52 - 1.0 1.9 2.9 3.5 - 1.0 1.9 2.9 3.5 - V VI = VIL or VIH IO = -6.0 mА 3.0 2.48 - 2.34 - 2.20 - V Low-Level Output VI = VIL or VIH Voltage IO = 50 µА 1.2 2.0 3.0 3.6 - 0.09 0.09 0.09 0.09 - 0.1 0.1 0.1 0.1 - 0.1 0.1 0.1 0.1 V VI = VIL or VIH IO = 6.0 mА 3.0 - 0.33 - 0.4 - 0.5 V VOL IIL Low-Level Input VI = 0 V Leakage Current 3.6 - -0.1 - -1.0 - -1.0 µA IIН High-Level Input VI = VCC Leakage Current 3.6 - 0.1 - 1.0 - 1.0 µA IСС Quiescent Supply VI = 0 В or VCC Current IO = 0 µА (per Package) 3.6 - 2.0 - 20 - 40 µA 3 KK74LV32 AC ELECTRICAL CHARACTERISTICS (CL=50 pF, tLH = tHL = 6.0 ns, VIL = 0V, VIH=VCC, RL=1kΩ) Symbol Parameter Guaranteed Limit VCC V 25°C Unit -40°C ÷ 85°C -40°C ÷ 125°C min max min max min max tTHL, (tTLH) Output Transition Time, Any Output (Figure 1) 1.2 2.0 * - 60 16 10 - 75 20 13 - 90 24 15 tPHL, (tPLH) Propagation Delay, Input A to Output Y (Figure 1) 1.2 2.0 * - 125 20 12 - 360 25 15 - 360 30 18 Input Capacitance 3.0 - 7.0 - - - - CI CPD Power Dissipation Capacitance (Per Gate) ns pF ТА=25°С, VI=0V÷VCC pF 44 * - VCC= (3.3±0.3) V PD = CPDVCC2fI+ ∑(CLVCC2fo), fI-input frequency, fo- output frequency (MHz) ∑(CLVCC2fo) – sum of the outputs tLH Input А, B tHL 0.9 VCC 0.9 V1 V1 0.1 0.1 tPLH 0.9 VOH 0.9 V1 Output Y GND tPHL V1 0.1 0.1 tTLH VOL TTHL V1 = 0.5 VCC Figure 1. Switching Waveforms VCC VI PULSE GENERATOR VO RT DEVICE UNDER TEST CL RL Termination resistance RT should be equal to ZOUT pulse generators Figure 2. Test Circuit 4 KK74LV32 N SUFFIX PLASTIC DIP (MS - 001AA) A Dimension, mm 8 14 B 7 1 Symbol MIN MAX A 18.67 19.69 B 6.1 7.11 5.33 C F L C -T- SEATING PLANE N G M K J H D 0.25 (0.010) M T NOTES: 1. Dimensions “A”, “B” do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side. D 0.36 0.56 F 1.14 1.78 G 2.54 H 7.62 J 0° 10° K 2.92 3.81 L 7.62 8.26 M 0.2 0.36 N 0.38 D SUFFIX SOIC (MS - 012AB) Dimension, mm A 14 8 H B 1 G P 7 R x 45 C -TK D SEATING PLANE M Symbol MIN MAX A 8.55 8.75 B 3.8 4 C 1.35 1.75 D 0.33 0.51 F 0.4 1.27 G 1.27 H 5.27 J 0° 8° K 0.1 0.25 1. Dimensions A and B do not include mold flash or protrusion. M 0.19 0.25 2. Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for B ‑ 0.25 mm (0.010) per side. P 5.8 6.2 R 0.25 0.5 J 0.25 (0.010) M T C M NOTES: F 5