INTEL P28F010-65

28F010
1024K (128K x 8) CMOS FLASH MEMORY
Y
Flash Electrical Chip-Erase
Ð 1 Second Typical Chip-Erase
Y
Quick Pulse Programming Algorithm
Ð 10 ms Typical Byte-Program
Ð 2 Second Chip-Program
Y
100,000 Erase/Program Cycles
Y
12.0V g 5% VPP
Y
High-Performance Read
Ð 65 ns Maximum Access Time
Y
CMOS Low Power Consumption
Ð 10 mA Typical Active Current
Ð 50 mA Typical Standby Current
Ð 0 Watts Data Retention Power
Y
Y
Command Register Architecture for
Microprocessor/Microcontroller
Compatible Write Interface
Y
Noise Immunity Features
Ð g 10% VCC Tolerance
Ð Maximum Latch-Up Immunity
through EPI Processing
Y
ETOX TM Nonvolatile Flash Technology
Ð EPROM-Compatible Process Base
Ð High-Volume Manufacturing
Experience
Y
JEDEC-Standard Pinouts
Ð 32-Pin Plastic Dip
Ð 32-Lead PLCC
Ð 32-Lead TSOP
Integrated Program/Erase Stop Timer
(See Packaging Spec., Order Ý231369)
Y
Extended Temperature Options
Intel’s 28F010 CMOS flash memory offers the most cost-effective and reliable alternative for read/write
random access nonvolatile memory. The 28F010 adds electrical chip-erasure and reprogramming to familiar
EPROM technology. Memory contents can be rewritten: in a test socket; in a PROM-programmer socket; onboard during subassembly test; in-system during final test; and in-system after-sale. The 28F010 increases
memory flexibility, while contributing to time and cost savings.
The 28F010 is a 1024 kilobit nonvolatile memory organized as 131,072 bytes of 8 bits. Intel’s 28F010 is
offered in 32-pin plastic dip or 32-lead PLCC and TSOP packages. Pin assignments conform to JEDEC
standards for byte-wide EPROMs.
Extended erase and program cycling capability is designed into Intel’s ETOX (EPROM Tunnel Oxide) process
technology. Advanced oxide processing, an optimized tunneling structure, and lower electric field combine to
extend reliable cycling beyond that of traditional EEPROMs. With the 12.0V VPP supply, the 28F010 performs
100,000 erase and program cycles well within the time limits of the Quick Pulse Programming and Quick Erase
algorithms.
Intel’s 28F010 employs advanced CMOS circuitry for systems requiring high-performance access speeds, low
power consumption, and immunity to noise. Its 65 nanosecond access time provides no-WAIT-state performance for a wide range of microprocessors and microcontrollers. Maximum standby current of 100 mA translates into power savings when the device is deselected. Finally, the highest degree of latch-up protection is
achieved through Intel’s unique EPI processing. Prevention of latch-up is provided for stresses up to 100 mA
on address and data pins, from b 1V to VCC a 1V.
With Intel’s ETOX process base, the 28F010 builds on years of EPROM experience to yield the highest levels
of quality, reliability, and cost-effectiveness.
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
COPYRIGHT © INTEL CORPORATION, 1995
November 1995
Order Number: 290207-010
28F010
290207 – 1
Figure 1. 28F010 Block Diagram
Table 1. Pin Description
Symbol
2
Type
Name and Function
A0 –A16
INPUT
ADDRESS INPUTS for memory addresses. Addresses are internally
latched during a write cycle.
DQ0 –DQ7
INPUT/OUTPUT
DATA INPUT/OUTPUT: Inputs data during memory write cycles;
outputs data during memory read cycles. The data pins are active high
and float to tri-state OFF when the chip is deselected or the outputs
are disabled. Data is internally latched during a write cycle.
CEÝ
INPUT
CHIP ENABLE: Activates the device’s control logic, input buffers,
decoders and sense amplifiers. CEÝ is active low; CEÝ high
deselects the memory device and reduces power consumption to
standby levels.
OEÝ
INPUT
OUTPUT ENABLE: Gates the devices output through the data buffers
during a read cycle. OEÝ is active low.
WEÝ
INPUT
WRITE ENABLE: Controls writes to the control register and the array.
Write enable is active low. Addresses are latched on the falling edge
and data is latched on the rising edge of the WEÝ pulse.
Note: With VPP s 6.5V, memory contents cannot be altered.
VPP
ERASE/PROGRAM POWER SUPPLY for writing the command
register, erasing the entire array, or programming bytes in the array.
VCC
DEVICE POWER SUPPLY (5V g 10%)
VSS
GROUND
NC
NO INTERNAL CONNECTION to device. Pin may be driven or left
floating.
28F010
28F010
290207 – 3
290207 – 2
290207 – 17
290207 – 18
Figure 2. 28F010 Pin Configurations
3
28F010
APPLICATIONS
The 28F010 flash memory provides nonvolatility
along with the capability to perform over 100,000
electrical chip-erasure/reprogram cycles. These features make the 28F010 an innovative alternative to
disk, EEPROM, and battery-backed static RAM.
Where periodic updates of code and data-tables are
required, the 28F010’s reprogrammability and nonvolatility make it the obvious and ideal replacement
for EPROM.
Primary applications and operating systems stored
in flash eliminate the slow disk-to-DRAM download
process. This results in dramatic enhancement of
performance and substantial reduction of power
consumption Ð a consideration particularly important in portable equipment. Flash memory increases
flexibility with electrical chip erasure and in-system
update capability of operating systems and application code. With updatable code, system manufacturers can easily accommodate last-minute changes as
revisions are made.
In diskless workstations and terminals, network traffic reduces to a minimum and systems are instanton. Reliability exceeds that of electromechanical
media. Often in these environments, power interruptions force extended re-boot periods for all networked terminals. This mishap is no longer an issue
if boot code, operating systems, communication protocols and primary applications are flash-resident in
each terminal.
For embedded systems that rely on dynamic RAM/
disk for main system memory or nonvolatile backup
storage, the 28F010 flash memory offers a solid
state alternative in a minimal form factor. The
28F010 provides higher performance, lower power
consumption, instant-on capability, and allows an
‘‘execute in place’’ memory hierarchy for code and
data table reading. Additionally, the flash memory is
more rugged and reliable in harsh environments
where extreme temperatures and shock can cause
disk-based systems to fail.
The need for code updates pervades all phases of a
system’s life Ð from prototyping to system manufacture to after-sale service. The electrical chip-erasure
and reprogramming ability of the 28F010 allows incircuit alterability; this eliminates unnecessary handling and less-reliable socketed connections, while
adding greater test, manufacture, and update flexibility.
4
Material and labor costs associated with code
changes increases at higher levels of system integration Ð the most costly being code updates after
sale. Code ‘‘bugs’’, or the desire to augment system
functionality, prompt after-sale code updates. Field
revisions to EPROM-based code requires the removal of EPROM components or entire boards. With
the 28F010, code updates are implemented locally
via an edge-connector, or remotely over a communcation link.
For systems currently using a high-density static
RAM/battery configuration for data accumulation,
flash memory’s inherent nonvolatility eliminates the
need for battery backup. The concern for battery
failure no longer exists, an important consideration
for portable equipment and medical instruments,
both requiring continuous performance. In addition,
flash memory offers a considerable cost advantage
over static RAM.
Flash memory’s electrical chip erasure, byte programmability and complete nonvolatility fit well with
data accumulation and recording needs. Electrical
chip-erasure gives the designer a ‘‘blank slate’’ in
which to log or record data. Data can be periodically
off-loaded for analysis and the flash memory erased
producing a new ‘‘blank slate’’.
A high degree of on-chip feature integration simplifies memory-to-processor interfacing. Figure 4 depicts two 28F010s tied to the 80C186 system bus.
The 28F010’s architecture minimizes interface circuitry needed for complete in-circuit updates of
memory contents.
The outstanding feature of the TSOP (Thin Small
Outline Package) is the 1.2 mm thickness. With standard and reverse pin configurations, TSOP reduces
the number of board layers and overall volume necessary to layout multiple 28F010s. TSOP is particularly suited for portable equipment and applications
requiring large amounts of flash memory. Figure 3
illustrates the TSOP Serpentine layout.
With cost-effective in-system reprogramming, extended cycling capability, and true nonvolatility,
the 28F010 offers advantages to the alternatives:
EPROMs, EEPROMs, battery backed static RAM,
or disk. EPROM-compatible read specifications,
straight-forward interfacing, and in-circuit alterability
offers designers unlimited flexibility to meet the high
standards of today’s designs.
290207– 21
28F010
Figure 3. TSOP Serpentine Layout
5
28F010
290207 – 4
Figure 4. 28F010 in a 80C186 System
PRINCIPLES OF OPERATION
Flash-memory augments EPROM functionality with
in-circuit electrical erasure and reprogramming. The
28F010 introduces a command register to manage
this new functionality. The command register allows
for: 100% TTL-level control inputs; fixed power supplies during erasure and programming; and maximum EPROM compatibility.
In the absence of high voltage on the VPP pin, the
28F010 is a read-only memory. Manipulation of the
external memory-control pins yields the standard
EPROM read, standby, output disable, and Intelligent Identifier operations.
The same EPROM read, standby, and output disable
operations are available when high voltage is applied to the VPP pin. In addition, high voltage on VPP
enables erasure and programming of the device. All
functions associated with altering memory contentsÐIntelligent Identifier, erase, erase verify, program, and program verifyÐare accessed via the
command register.
Commands are written to the register using standard
microprocessor write timings. Register contents
serve as input to an internal state-machine which
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data
6
needed for programming or erase operations. With
the appropriate command written to the register,
standard microprocessor read timings output array
data, access the Intelligent Identifier codes, or output data for erase and program verification.
Integrated Stop Timer
Successive command write cycles define the durations of program and erase operations; specifically,
the program or erase time durations are normally
terminated by associated program or erase verify
commands. An integrated stop timer provides simplified timing control over these operations; thus eliminating the need for maximum program/erase timing
specifications. Programming and erase pulse durations are minimums only. When the stop timer terminates a program or erase operation, the device enters an inactive state and remains inactive until receiving the appropriate verify or reset command.
Write Protection
The command register is only active when VPP is at
high voltage. Depending upon the application, the
system designer may choose to make the VPP power supply switchableÐavailable only when memory
updates are desired. When VPP e VPPL, the con-
28F010
Table 2. 28F010 Bus Operations
VPP(1)
A0
A9
CEÝ
OEÝ
WEÝ
Read
VPPL
A0
A9
VIL
VIL
VIH
Data Out
Output Disable
VPPL
X
X
VIL
VIH
VIH
Tri-State
Tri-State
Mode
READ-ONLY
READ/WRITE
DQ0 –DQ7
Standby
VPPL
X
X
VIH
X
X
Intelligent Identifier (Mfr)(2)
VPPL
VIL
VID(3)
VIL
VIL
VIH
Data e 89H
VIL
VIL
VIH
Data e B4H
Intelligent Identifier (Device)(2)
VPPL
VIH
VID(3)
Read
VPPH
A0
A9
VIL
VIL
VIH
Data Out(4)
Output Disable
VPPH
X
X
VIL
VIH
VIH
Tri-State
Standby(5)
VPPH
X
X
VIH
X
X
Tri-State
Write
VPPH
A0
A9
VIL
VIH
VIL
Data In(6)
NOTES:
1. Refer to DC Characteristics. When VPP e VPPL memory contents can be read but not written or erased.
2. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 3. All other
addresses low.
3. VID is the Intelligent Identifier high voltage. Refer to DC Characteristics.
4. Read operations with VPP e VPPH may access array data or the Intelligent Identifier codes.
5. With VPP at high voltage, the standby current equals ICC a IPP (standby).
6. Refer to Table 3 for valid Data-In during a write operation.
7. X can be VIL or VIH.
tents of the register default to the read command,
making the 28F010 a read-only memory. In this
mode, the memory contents cannot be altered.
erase verification. When VPP is low (VPPL), the read
operation can only access the array data.
Or, the system designer may choose to ‘‘hardwire’’
VPP, making the high voltage supply constantly
available. In this case, all Command Register functions are inhibited whenever VCC is below the write
lockout voltage VLKO. (See Power Up/Down Protection) The 28F010 is designed to accommodate either design practice, and to encourage optimization
of the processor-memory interface.
Output Disable
The two-step program/erase write sequence to the
Command Register provides additional software
write protections.
BUS OPERATIONS
With OEÝ at a logic-high level (VIH), output from the
device is disabled. Output pins are placed in a highimpedance state.
Standby
With CEÝ at a logic-high level, the standby operation disables most of the 28F010’s circuitry and substantially reduces device power consumption. The
outputs are placed in a high-impedance state, independent of the OEÝ signal. If the 28F010 is deselected during erasure, programming, or program/
erase verification, the device draws active current
until the operation is terminated.
Read
The 28F010 has two control functions, both of which
must be logically active, to obtain data at the outputs. Chip-Enable (CEÝ) is the power control and
should be used for device selection. Output-Enable
(OEÝ) is the output control and should be used to
gate data from the output pins, independent of device selection. Refer to AC read timing waveforms.
Intelligent Identifier Operation
The Intelligent Identifier operation outputs the manufacturer code (89H) and device code (B4H). Programming equipment automatically matches the device with its proper erase and programming algorithms.
When VPP is high (VPPH), the read operation can be
used to access array data, to output the Intelligent
Identifier codes, and to access data for program/
7
28F010
With CEÝ and OEÝ at a logic low level, raising A9
to high voltage VID (see DC Characteristics) activates the operation. Data read from locations 0000H
and 0001H represent the manufacturer’s code and
the device code, respectively.
The manufacturer- and device-codes can also be
read via the command register, for instances where
the 28F010 is erased and reprogrammed in the target system. Following a write of 90H to the command register, a read from address location 0000H
outputs the manufacturer code (89H). A read from
address 0001H outputs the device code (B4H).
used to store the command, along with address and
data information needed to execute the command.
The command register is written by bringing WEÝ to
a logic-low level (VIL), while CEÝ is low. Addresses
are latched on the falling edge of WEÝ, while data is
latched on the rising edge of the WEÝ pulse. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/
Programming Waveforms for specific timing
parameters.
COMMAND DEFINITIONS
Write
Device erasure and programming are accomplished
via the command register, when high voltage is applied to the VPP pin. The contents of the register
serve as input to the internal state-machine. The
state-machine outputs dictate the function of the
device.
The command register itself does not occupy an addressable memory location. The register is a latch
When low voltage is applied to the VPP pin, the contents of the command register default to 00H, enabling read-only operations.
Placing high voltage on the VPP pin enables read/
write operations. Device operations are selected by
writing specific data patterns into the command register. Table 3 defines these 28F010 register
commands.
Table 3. Command Definitions
Command
Bus
First Bus Cycle
Second Bus Cycle
Cycles
Req’d Operation(1) Address(2) Data(3) Operation(1) Address(2) Data(3)
Read Memory
1
Write
X
00H
Read Intelligent Identifier
Codes(4)
3
Write
IA
90H
Read
IA
Set-up Erase/Erase(5)
2
Write
X
20H
Write
X
20H
Erase Verify(5)
2
Write
EA
A0H
Read
X
EVD
Set-up Program/Program(6)
2
Write
X
40H
Write
PA
PD
Program Verify(6)
2
Write
X
C0H
Read
X
PVD
Reset(7)
2
Write
X
FFH
Write
X
FFH
ID
NOTES:
1. Bus operations are defined in Table 2.
2. IA e Identifier address: 00H for manufacturer code, 01H for device code.
EA e Erase Address: Address of memory location to be read during erase verify.
PA e Program Address: Address of memory location to be programmed.
Addresses are latched on the falling edge of the WEÝ pulse.
3. ID e Identifier Data: Data read from location IA during device identification (Mfr e 89H, Device e B4H).
EVD e Erase Verify Data: Data read from location EA during erase verify.
PD e Program Data: Data to be programmed at location PA. Data is latched on the rising edge of WEÝ.
PVD e Program Verify Data: Data read from location PA during program verify. PA is latched on the Program command.
4. Following the Read inteligent ID command, two read operations access manufacturer and device codes.
5. Figure 6 illustrates the Quick Erase Algorithm.
6. Figure 5 illustrates the Quick Pulse Programming Algorithm.
7. The second bus cycle must be followed by the desired command register write.
8
28F010
Read Command
While VPP is high, for erasure and programming,
memory contents can be accessed via the read
command. The read operation is initiated by writing
00H into the command register. Microprocessor
read cycles retrieve array data. The device remains
enabled for reads until the command register contents are altered.
The default contents of the register upon VPP power-up is 00H. This default value ensures that no spurious alteration of memory contents occurs during
the VPP power transition. Where the VPP supply is
hard-wired to the 28F010, the device powers-up and
remains enabled for reads until the command-register contents are changed. Refer to the AC Read
Characteristics and Waveforms for specific timing
parameters.
Intelligent Identifier Command
Flash memories are intended for use in applications
where the local CPU alters memory contents. As
such, manufacturer- and device-codes must be accessible while the device resides in the target system. PROM programmers typically access signature
codes by raising A9 to a high voltage. However, multiplexing high voltage onto address lines is not a desired system-design practice.
The 28F010 contains an Intelligent Identifier operation to supplement traditional PROM-programming
methodology. The operation is initiated by writing
90H into the command register. Following the command write, a read cycle from address 0000H retrieves the manufacturer code of 89H. A read cycle
from address 0001H returns the device code of
B4H. To terminate the operation, it is necessary to
write another valid command into the register.
of this high voltage, memory contents are protected
against erasure. Refer to AC Erase Characteristics
and Waveforms for specific timing parameters.
Erase-Verify Command
The erase command erases all bytes of the array in
parallel. After each erase operation, all bytes must
be verified. The erase verify operation is initiated by
writing A0H into the command register. The address
for the byte to be verified must be supplied as it is
latched on the falling edge of the WEÝ pulse. The
register write terminates the erase operation with the
rising edge of its WEÝ pulse.
The 28F010 applies an internally-generated margin
voltage to the addressed byte. Reading FFH from
the addressed byte indicates that all bits in the byte
are erased.
The erase-verify command must be written to the
command register prior to each byte verification to
latch its address. The process continues for each
byte in the array until a byte does not return FFH
data, or the last address is accessed.
In the case where the data read is not FFH, another
erase operation is performed. (Refer to Set-up
Erase/Erase). Verification then resumes from the
address of the last-verified byte. Once all bytes in
the array have been verified, the erase step is complete. The device can be programmed. At this point,
the verify operation is terminated by writing a valid
command (e.g. Program Set-up) to the command
register. Figure 6, the Quick Erase algorithm, illustrates how commands and bus operations are combined to perform electrical erasure of the 28F010.
Refer to AC Erase Characteristics and Waveforms
for specific timing parameters.
Set-up Program/Program Commands
Set-up Erase/Erase Commands
Set-up Erase is a command-only operation that
stages the device for electrical erasure of all bytes in
the array. The set-up erase operation is performed
by writing 20H to the command register.
To commence chip-erasure, the erase command
(20H) must again be written to the register. The
erase operation begins with the rising edge of the
WEÝ pulse and terminates with the rising edge of
the next WEÝ pulse (i.e., Erase-Verify Command).
This two-step sequence of set-up followed by execution ensures that memory contents are not accidentally erased. Also, chip-erasure can only occur when
high voltage is applied to the VPP pin. In the absence
Set-up program is a command-only operation that
stages the device for byte programming. Writing 40H
into the command register performs the set-up
operation.
Once the program set-up operation is performed,
the next WEÝ pulse causes a transition to an active
programming operation. Addresses are internally
latched on the falling edge of the WEÝ pulse. Data
is internally latched on the rising edge of the WEÝ
pulse. The rising edge of WEÝ also begins the programming operation. The programming operation
terminates with the next rising edge of WEÝ, used
to write the program-verify command. Refer to AC
Programming Characteristics and Waveforms for
specific timing parameters.
9
28F010
Program-Verify Command
The 28F010 is programmed on a byte-by-byte basis.
Byte programming may occur sequentially or at random. Following each programming operation, the
byte just programmed must be verified.
The program-verify operation is initiated by writing
C0H into the command register. The register write
terminates the programming operation with the rising edge of its WEÝ pulse. The program-verify operation stages the device for verification of the byte
last programmed. No new address information is
latched.
The 28F010 applies an internally-generated margin
voltage to the byte. A microprocessor read cycle
outputs the data. A successful comparison between
the programmed byte and true data means that the
byte is successfully programmed. Programming then
proceeds to the next desired byte location. Figure 5,
the 28F010 Quick Pulse Programming algorithm, illustrates how commands are combined with bus operations to perform byte programming. Refer to AC
Programming Characteristics and Waveforms for
specific timing parameters.
Reset Command
A reset command is provided as a means to safely
abort the erase- or program-command sequences.
Following either set-up command (erase or program)
with two consecutive writes of FFH will safely abort
the operation. Memory contents will not be altered.
A valid command must then be written to place the
device in the desired state.
EXTENDED ERASE/PROGRAM CYCLING
EEPROM cycling failures have always concerned
users. The high electrical field required by thin oxide
EEPROMs for tunneling can literally tear apart the
oxide at defect regions. To combat this, some suppliers have implemented redundancy schemes, reducing cycling failures to insignificant levels. However, redundancy requires that cell size be doubledÐ
an expensive solution.
Intel has designed extended cycling capability into
its ETOX flash memory technology. Resulting improvements in cycling reliability come without increasing memory cell size or complexity. First, an
advanced tunnel oxide increases the charge carrying ability ten-fold. Second, the oxide area per cell
subjected to the tunneling electric field is one-tenth
that of common EEPROMs, minimizing the probability of oxide defects in the region. Finally, the peak
electric field during erasure is approximately
10
2 MV/cm lower than EEPROM. The lower electric
field greatly reduces oxide stress and the probability
of failure.
The 28F010 is capable or 100,000 program/erase
cycles. The device is programmed and erased using
Intel’s Quick Pulse Programming and Quick Erase
algorithms. Intel’s algorithmic approach uses a series of operations (pulses), along with byte verification, to completely and reliably erase and program
the device.
For further information, see Reliability Report RR-60.
QUICK PULSE PROGRAMMING ALGORITHM
The Quick Pulse Programming algorithm uses programming operations of 10 ms duration. Each operation is followed by a byte verification to determine
when the addressed byte has been successfully programmed. The algorithm allows for up to 25 programming operations per byte, although most bytes
verify on the first or second operation. The entire
sequence of programming and byte verification is
performed with VPP at high voltage. Figure 5 illustrates the Quick Pulse Programming algorithm.
QUICK ERASE ALGORITHM
Intel’s Quick Erase algorithm yields fast and reliable
electrical erasure of memory contents. The algorithm employs a closed-loop flow, similar to the
Quick Pulse Programming algorithm, to simultaneously remove charge from all bits in the array.
Erasure begins with a read of memory contents. The
28F010 is erased when shipped from the factory.
Reading FFH data from the device would immediately be followed by device programming.
For devices being erased and reprogrammed, uniform and reliable erasure is ensured by first programming all bits in the device to their charged state
(Data e 00H). This is accomplished, using the Quick
Pulse Programming algorithm, in approximately two
seconds.
Erase execution then continues with an initial erase
operation. Erase verification (data e FFH) begins at
address 0000H and continues through the array to
the last address, or until data other than FFH is encountered. With each erase operation, an increasing
number of bytes verify to the erased state. Erase
efficiency may be improved by storing the address of
the last byte verified in a register. Following the next
erase operation, verification starts at that stored address location. Erasure typically occurs in one second. Figure 6 illustrates the Quick Erase algorithm.
28F010
Bus
Command
Operation
Standby
Comments
Wait for VPP Ramp to VPPH(1)
Initialize Pulse-Count
Write
Set-up
Program
Data e 40H
Write
Program
Valid Address/Data
Standby
Write
Duration of Program
Operation (tWHWH1)
Program(2)
Verify
Data e C0H; Stops Program
Operation(3)
Standby
tWHGL
Read
Read Byte to Verify
Programming
Standby
Compare Data Output to Data
Expected
Write
Standby
Read
Data e 00H, Resets the
Register for Read Operations
Wait for VPP Ramp to VPPL(1)
290207 – 5
NOTES:
1. See DC Characteristics for the value of VPPH and
VPPL.
2. Program Verify is only performed after byte programming. A final read/compare may be performed (optional) after the register is written with the Read command.
3. Refer to principles of operation.
4. CAUTION: The algorithm MUST BE FOLLOWED
to ensure proper and reliable operation of the device.
Figure 5. 28F010 Quick Pulse Programming Algorithm
11
28F010
Bus
Command
Operation
Comments
Entire Memory Must e 00H
Before Erasure
Use Quick Pulse
Programming Algorithm
(Figure 5)
Wait for VPP Ramp to VPPH(1)
Standby
Initialize Addresses and
Pulse-Count
Write
Set-up
Erase
Data e 20H
Write
Erase
Data e 20H
Standby
Write
Duration of Erase Operation
(tWHWH2)
Erase(2)
Verify
Standby
Addr e Byte to Verify;
Data e A0H; Stops Erase
Operation(3)
tWHGL
Read
Read Byte to Verify Erasure
Standby
Compare Output to FFH
Increment Pulse-Count
Write
Read
Standby
Data e 00H, Resets the
Register for Read Operations
Wait for VPP Ramp to VPPL(1)
290207 – 6
1. See DC Characteristics for the value of VPPH and
VPPL.
2. Erase Verify is performed only after chip-erasure. A
final read/compare may be performed (optional) after
the register is written with the read command.
3. Refer to principles of operation.
4. CAUTION: The algorithm MUST BE FOLLOWED
to ensure proper and reliable operation of the device.
Figure 6. 28F010 Quick Erase Algorithm
12
28F010
DESIGN CONSIDERATIONS
Two-Line Output Control
Flash-memories are often used in larger memory arrays. Intel provides two read-control inputs to accommodate multiple memory connections. Two-line
control provides for:
a. the lowest possible memory power dissipation
and,
b. complete assurance that output bus contention
will not occur.
To efficiently use these two control inputs, an address-decoder output should drive chip-enable,
while the system’s read signal controls all flashmemories and other parallel memories. This assures
that only enabled memory devices have active outputs, while deselected devices maintain the low
power standby condition.
Power Supply Decoupling
Flash-memory power-switching characteristics require careful device decoupling. System designers
are interested in three supply current (ICC) issuesÐ
standby, active, and transient current peaks produced by falling and rising edges of chip-enable. The
capacitive and inductive loads on the device outputs
determine the magnitudes of these peaks.
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks.
Each device should have a 0.1 mF ceramic capacitor
connected between VCC and VSS, and between VPP
and VSS.
Place the high-frequency, low-inherent-inductance
capacitors as close as possible to the devices. Also,
for every eight devices, a 4.7 mF electrolytic capacitor should be placed at the array’s power supply
connection, between VCC and VSS. The bulk capacitor will overcome voltage slumps caused by printed-
circuit-board trace inductance, and will supply
charge to the smaller capacitors as needed.
VPP Trace on Printed Circuit Boards
Programming flash-memories, while they reside in
the target system, requires that the printed circuit
board designer pay attention to the VPP power supply trace. The VPP pin supplies the memory cell current for programming. Use similar trace widths and
layout considerations given the VCC power bus. Adequate VPP supply traces and decoupling will decrease VPP voltage spikes and overshoots.
Power Up/Down Protection
The 28F010 is designed to offer protection against
accidental erasure or programming during power
transitions. Upon power-up, the 28F010 is indifferent
as to which power supply, VPP or VCC, powers up
first. Power supply sequencing is not required. Internal circuitry in the 28F010 ensures that the command register is reset to the read mode on power
up.
A system designer must guard against active writes
for VCC voltages above VLKO when VPP is active.
Since both WEÝ and CEÝ must be low for a command write, driving either to VIH will inhibit writes.
The control register architecture provides an added
level of protection since alteration of memory contents only occurs after successful completion of the
two-step command sequences.
28F010 Power Dissipation
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during
system idle time. Flash nonvolatility increases the
usable battery life of your system because the
28F010 does not consume any power to retain code
or data when the system is off. Table 4 illustrates the
power dissipated when updating the 28F010.
Table 4. 28F010 Typical Update Power Dissipation(4)
Operation
Notes
Power Dissipation
(Watt-Seconds)
Array Program/Program Verify
1
0.171
Array Erase/Erase Verify
2
0.136
One Complete Cycle
3
0.478
NOTES:
1. Formula to calculate typical Program/Program Verify Power e [VPP c Ý Bytes c typical Ý Prog Pulses (tWHWH1 c IPP2
typical a tWHGL c IPP4 typical)] a [VCC c Ý Bytes c typical Ý Prog Pulses (tWHWH1 c ICC2 typical a tWHGL c ICC4
typical].
2. Formula to calculate typical Erase/Erase Verify Power e [VPP (VPP3 typical c tERASE typical a IPP5 typical c tWHGL c
Ý Bytes)] a [VCC (ICC3 typical c tERASE typical a ICC5 typical c tWHGL c Ý Bytes)].
3. One Complete Cycle e Array Preprogram a Array Erase a Program.
4. ‘‘Typicals’’ are not guaranteed, but based on a limited number of samples from production lots.
13
28F010
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This is a production data sheet. The specifications are subject to change without notice.
Operating Temperature
During Read ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0§ C to a 70§ C(1)
During Erase/Program ÀÀÀÀÀÀÀÀÀ0§ C to a 70§ C(1)
Operating Temperature
During Read ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b 40§ C to a 85§ C(2)
During Erase/Program ÀÀÀÀÀÀ b 40§ C to a 85§ C(2)
Temperature Under Bias ÀÀÀÀÀÀÀ b 10§ C to a 80§ C(1)
Temperature Under Bias ÀÀÀÀÀÀÀ b 50§ C to a 95§ C(2)
Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b 65§ C to a 125§ C
Voltage on Any Pin with
Respect to Ground ÀÀÀÀÀÀÀÀÀÀ b 2.0V to a 7.0V(3)
Voltage on Pin A9 with
Respect to Ground ÀÀÀÀÀÀÀ b 2.0V to a 13.5V(3, 4)
VPP Supply Voltage with
Respect to Ground
During Erase/Program ÀÀÀÀ b 2.0V to a 14.0V(3, 4)
VCC Supply Voltage with
Respect to Ground ÀÀÀÀÀÀÀÀÀÀ b 2.0V to a 7.0V(3)
Output Short Circuit CurrentÀÀÀÀÀÀÀÀÀÀÀÀÀ100 mA(5)
*WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
OPERATING CONDITIONS
Symbol
Limits
Parameter
Min
Unit
Max
TA
Operating Temperature(1)
0
70
TA
Operating Temperature(2)
b 40
a 85
§C
§C
VCC
VCC Supply Voltage (10%)(6)
4.50
5.50
V
VCC
VCC Supply Voltage (5%)(7)
4.75
5.25
V
NOTES:
1. Operating Temperature is for commercial product as defined by this specification.
2. Operating Temperature is for extended temperature products as defined by this specification.
3. Minimum DC input voltage is b 0.5V. During transitions, inputs may undershoot to b 2.0V for periods less
than 20 ns. Maximum DC voltage on output pins is VCC a 0.5V, which may overshoot to VCC a 2.0V for
periods less than 20 ns.
4. Maximum DC voltage on A9 or VPP may overshoot to a 14.0V for periods less than 20 ns.
5. Output shorted for no more than one second. No more than one output shorted at a time.
6. See High Speed AC Input/Output reference Waveforms and High Speed AC Testing Load Circuits for
testing characteristics.
7. See AC Input/Output reference Waveforms and AC Testing Load Circuits for testing characteristics.
DC CHARACTERISTICSÐTTL/NMOS COMPATIBLEÐCommercial Products
Symbol
Parameter
Limits
Notes
Min
Typical(4)
Unit
Test Conditions
Max
ILI
Input Leakage Current
1
g 1.0
mA
VCC e VCC Max
VIN e VCC or VSS
ILO
Output Leakage Current
1
g 10
mA
VCC e VCC Max
VOUT e VCC or VSS
ICCS
VCC Standby Current
1
0.3
1.0
mA
VCC e VCC Max
CEÝ e VIH
ICC1
VCC Active Read Current
1
10
30
mA
VCC e VCC Max, CEÝ e VIL
f e 6 MHz, IOUT e 0 mA
14
28F010
DC CHARACTERISTICSÐTTL/NMOS COMPATIBLEÐCommercial Products
(Continued)
Symbol
Parameter
Limits
Notes
Min Typical(4)
Unit
Test Conditions
Max
ICC2
VCC Programming Current
1, 2
1.0
10
mA Programming in Progress
ICC3
VCC Erase Current
1, 2
5.0
15
mA Erasure in Progress
ICC4
VCC Program Verify Current
1, 2
5.0
15
mA VPP e VPPH
Program Verify in Progress
ICC5
VCC Erase Verify Current
1, 2
5.0
15
mA VPP e VPPH
Erase Verify in Progress
IPPS
VPP Leakage Current
1
IPP1
VPPRead Current
or Standby Current
1
90
IPP2
VPP Programming Current
1, 2
8.0
30
mA VPP e VPPH
Programming in Progress
IPP3
VPP Erase Current
1, 2
6.0
30
mA VPP e VPPH
Erasure in Progress
IPP4
VPP Program Verify Current
1, 2
2.0
5.0
mA VPP e VPPH
Program Verify in Progress
IPP5
VPP Erase Verify Current
1, 2
2.0
5.0
mA VPP e VPPH
Erase Verify in Progress
VIL
Input Low Voltage
b 0.5
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VOH1
Output High Voltage
VID
A9 Intelligent Identifer Voltage
IID
A9 Intelligent Identifier Current
VPPL
VPP during Read-Only
Operations
0.00
6.5
V
VPPH
VPP during Read/Write
Operations
11.40
12.60
V
VLKO
VCC Erase/Write Lock Voltage
g 10
mA VPP s VCC
200
mA VPP l VCC
g 10.0
0.8
VCC a 0.5
V
0.45
V
VCC e VCC Min
IOL e 5.8 mA
V
VCC e VCC Min
IOH e b 2.5 mA
2.4
11.50
1, 2
13.00
90
VPP s VCC
V
V
mA A9 e VID
200
2.5
NOTE: Erase/Program are
Inhibited when VPP e VPPL
V
DC CHARACTERISTICSÐCMOS COMPATIBLEÐCommercial Products
Symbol
Parameter
Limits
Notes
Min
Typical(4)
Unit
Test Conditions
Max
ILI
Input Leakage Current
1
g 1.0
mA
VCC e VCC Max
VIN e VCC or VSS
ILO
Output Leakage Current
1
g 10
mA
VCC e VCC Max
VOUT e VCC or VSS
ICCS
VCC Standby Current
1
50
100
mA
VCC e VCC Max
CEÝ e VCC g 0.2V
ICC1
VCC Active Read Current
1
10
30
mA
VCC e VCC Max, CEÝ e VIL
f e 6 MHz, IOUT e 0 mA
15
28F010
DC CHARACTERISTICSÐCMOS COMPATIBLEÐCommercial Products (Continued)
Symbol
Parameter
Limits
Notes
Min
Typical(4)
Max
Unit
Test Conditions
ICC2
VCC Programming Current
1, 2
1.0
10
mA
Programming in Progress
ICC3
VCC Erase Current
1, 2
5.0
15
mA
Erasure in Progress
ICC4
VCC Program Verify Current
1, 2
5.0
15
mA
VPP e VPPH, Program
Verify in Progress
ICC5
VCC Erase Verify Current
1, 2
5.0
15
mA
VPP e VPPH, Erase
Verify in Progress
IPPS
VPP Leakage Current
1
g 10
mA
VPP s VCC
IPP1
VPP Read Current, ID
Current or Standby Current
1
200
mA
VPP l VCC
90
g 10
VPP s VCC
IPP2
VPP Programming
Current
1, 2
8.0
30
mA
VPP e VPPH
Programming in Progress
IPP3
VPP Erase Current
1, 2
6.0
30
mA
VPP e VPPH
Erasure in Progress
IPP4
VPP Program Verify
Current
1, 2
2.0
5.0
mA
VPP e VPPH, Program
Verify in Progress
IPP5
VPP Erase Verify
Current
1, 2
2.0
5.0
mA
VPP e VPPH, Erase
Verify in Progress
VIL
Input Low Voltage
b 0.5
0.8
V
VIH
Input High Voltage
0.7 VCC
VCC a 0.5
V
VOL
Output Low Voltage
0.45
V
VOH1
0.85 VCC
Output High Voltage
VOH2
VCC b 0.4
VID
A9 Intelligent Identifier
Voltage
IID
A9 Intelligent Identifier
Current
VPPL
VPP during Read-Only
Operations
VPPH
VLKO
16
V
VCC e VCC Min, IOH e b2.5 mA
VCC e VCC Min, IOH e b100 mA
11.50
13.00
V
200
mA
0.00
6.5
V
VPP during Read/Write
Operations
11.40
12.60
V
VCC Erase/Write Lock
Voltage
2.5
1, 2
VCC e VCC Min
IOL e 5.8 mA
90
V
A9 e VID
NOTE: Erase/Programs are
Inhibited when VPP e VPPL
28F010
DC CHARACTERISTICSÐTTL/NMOS COMPATIBLEÐExtended Temperature
Products
Symbol
Parameter
Limits
Notes
Min Typical(4)
Unit
Test Conditions
Max
ILI
Input Leakage Current
1
g 1.0
mA VCC e VCC Max
VIN e VCC or VSS
ILO
Output Leakage Current
1
g 10
mA VCC e VCC Max
VOUT e VCC or VSS
ICCS
VCC Standby Current
1
0.3
1.0
mA VCC e VCC Max
CEÝ e VIH
ICC1
VCC Active Read Current
1
10
30
mA VCC e VCC Max, CEÝ e VIL
f e 6 MHz, IOUT e 0 mA
ICC2
VCC Programming Current
1, 2
1.0
30
mA Programming in Progress
ICC3
VCC Erase Current
1, 2
5.0
30
mA Erasure in Progress
ICC4
VCC Program Verify Current
1, 2
5.0
30
mA VPP e VPPH
Program Verify in Progress
ICC5
VCC Erase Verify Current
1, 2
5.0
30
mA VPP e VPPH
Erase Verify in Progress
IPPS
VPP Leakage Current
1
IPP1
VPP Read Current
or Standby Current
1
90
IPP2
VPP Programming Current
1, 2
8.0
30
mA VPP e VPPH
Programming in Progress
IPP3
VPP Erase Current
1, 2
6.0
30
mA VPP e VPPH
Erasure in Progress
IPP4
VPP Program Verify Current
1, 2
2.0
5.0
mA VPP e VPPH
Program Verify in Progress
IPP5
VPP Erase Verify Current
1, 2
2.0
5.0
mA VPP e VPPH
Erase Verify in Progress
VIL
Input Low Voltage
b 0.5
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VOH1
Output High Voltage
VID
A9 Intelligent Identifer Voltage
IID
A9 Intelligent Identifier Current
VPPL
VPP during Read-Only
Operations
0.00
6.5
VPPH
VPP during Read/Write
Operations
11.40
12.60
VLKO
VCC Erase/Write Lock Voltage
g 10
mA VPP s VCC
200
mA VPP l VCC
g 10.0
0.8
V
VCC a 0.5 V
0.45
2.4
13.00
90
2.5
V VCC e VCC Min
IOL e 5.8 mA
V VCC e VCC Min
IOH e b 2.5 mA
11.50
1, 2
VPP s VCC
500
V
mA A9 e VID
V NOTE: Erase/Program are
Inhibited when VPP e VPPL
V
V
17
28F010
DC CHARACTERISTICSÐCMOS COMPATIBLEÐExtended Temperature
Products
Symbol
Parameter
Limits
Notes
Min
Typical(4)
Unit
Test Conditions
Max
ILI
Input Leakage
Current
1
g 1.0
mA VCC e VCC Max
VIN e VCC or VSS
ILO
Output Leakage
Current
1
g 10
mA VCC e VCC Max
VOUT e VCC or VSS
ICCS
VCC Standby
Current
1
50
100
mA VCC e VCC Max
CEÝ e VCC g 0.2V
ICC1
VCC Active Read
Current
1
10
30
mA VCC e VCC Max, CEÝ e VIL
f e 10 MHz, IOUT e 0 mA
ICC2
VCC Programming
Current
1, 2
1.0
10
mA Programming in Progress
ICC3
VCC Erase Current
1, 2
5.0
30
mA Erasure in Progress
ICC4
VCC Program Verify
Current
1, 2
5.0
30
mA VPP e VPPH
Program Verify in Progress
ICC5
VCC Erase Verify
Current
1, 2
5.0
30
mA VPP e VPPH
Erase Verify in Progress
IPPS
VPP Leakage Current
1
IPP1
VPP Read Current,
ID Current or
Standby Current
1
IPP2
VPP Programming
Current
1, 2
8.0
30
mA VPP e VPPH
Programming in Progress
IPP3
VPP Erase Current
1, 2
6.0
30
mA VPP e VPPH
Erasure in Progress
IPP4
VPP Program Verify
Current
1, 2
2.0
5.0
mA VPP e VPPH
Program Verify in Progress
IPP5
VPP Erase Verify
Current
1, 2
2.0
5.0
mA VPP e VPPH
Erase Verify in Progress
VIL
Input Low Voltage
b 0.5
VIH
Input High Voltage
0.7 VCC
VOL
Output Low Voltage
VOH1
Output High Voltage
mA VPP s VCC
200
mA VPP l VCC
g 10
VPP s VCC
0.8
VCC a 0.5
V
0.45
V
V
VCC b 0.4
VID
A9 Intelligent Identifer
Voltage
IID
A9 Intelligent Identifier
Current
V
0.85 VCC
VOH2
18
90
g 10
11.50
1, 2
13.00
90
500
VCC e VCC Min
IOL e 5.8 mA
VCC e VCC Min
IOH e b 2.5 mA
VCC e VCC Min
IOH e b 100 mA
V
mA A9 e VID
28F010
DC CHARACTERISTICSÐCMOS COMPATIBLEÐExtended Temperature
Products (Continued)
Symbol
Parameter
Limits
Notes
Min
Typical(4)
Unit
Test Conditions
NOTE: Erase/Programs are
Inhibited when VPP e VPPL
Max
VPPL
VPP during Read-Only
Operations
0.00
6.5
V
VPPH
VPP during Read/Write
Operations
11.40
12.60
V
VLKO
VCC Erase/Write Lock
Voltage
2.5
V
CAPACITANCE TA e 25§ C, f e 1.0 MHz
Symbol
Parameter
Notes
Limits
Min
Unit
Conditions
Max
CIN
Address/Control Capacitance
3
8
pF
VIN e 0V
COUT
Output Capacitance
3
12
pF
VOUT e 0V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at VCC e 5.0V, VPP e 12.0V, T e 25§ C. These currents
are valid for all product versions (packages and speeds).
2. Not 100% tested: characterization data available.
3. Sampled, not 100% tested.
4. ‘‘Typicals’’ are not guaranteed, but based on a limited number of samples from production lots.
19
28F010
AC TESTING INPUT/OUTPUT
WAVEFORM(1)
HIGH SPEED AC TESTING INPUT/OUTPUT
WAVEFORM(2)
290207 – 7
AC test inputs are driven at VOH (2.4 VTTL) for a Logic
‘‘1’’ and VOL (0.45 VTTL) for a Logic ‘‘0’’. Input timing
begins at VIH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10%
to 90%) k10 ns.
AC TESTING LOAD CIRCUIT(1)
CL e 100 pF
CL includes Jig Capacitance
RL e 3.3 KX
290207 – 8
AC test inputs are driven at 3.0V for a Logic ‘‘1’’ and
0.0V for a Logic ‘‘0’’. Input timing begins, and output
timing ends, at 1.5V. Input rise and fall times (10% to
90%) k10 ns.
HIGH SPEED AC TESTING LOAD CIRCUIT(2)
290207 –22
CL e 30 pF
CL includes Jig Capacitance
RL e 3.3 KX
290207 – 23
AC TEST CONDITIONS(1)
HIGH-SPEED AC TEST CONDITIONS(2)
Input Rise and Fall Times (10% to 90%)ÀÀÀÀÀÀ10 ns
Input Pulse Levels ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0.45V and 2.4V
Input Rise and Fall Times (10% to 90%) ÀÀÀÀÀÀ10 ns
Input Pulse Levels ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0.0V and 3.0V
Input Timing Reference Level ÀÀÀÀÀÀÀ0.8V and 2.0V
Output Timing Reference Level ÀÀÀÀÀÀ0.8V and 2.0V
Capacitive LoadÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ100 pF
Input Timing Reference Level ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5V
Output Timing Reference Level ÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5V
Capacitive LoadÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ30 pF
NOTES:
1. Testing characteristics for 28F010-65 in standard configuration, and 28F010-90, 28F010-120, and 28F010-150.
2. Testing characteristics for 28F010-65 in high speed configuration.
20
CEÝ Access Time
Address Access Time
OEÝ Access Time
CEÝ to Low Z
Chip Disable to Output
in High Z
OEÝ to Output
in Low Z
Output Disable to Output
in High Z
Output Hold from Address,
CEÝ, or OEÝ Change
Write Recovery Time
before Read
tAVQV/tACC
tGLQV/tOE
tELQX/tLZ
tEHQZ
tGLQX/tOLZ
tGHQZ/tDF
tOH
tWHGL
VCC g 5%
1, 2
2
2, 3
2
2, 3
Notes
VCC g 10%
6
0
0
0
65
Min
30
35
25
65
65
Max
28F010-65(4)
6
0
0
0
70
30
40
28
70
70
Max
28F010-65(5)
Min
6
0
0
0
90
30
45
35
90
90
Max
28F010-90(5)
Min
6
0
0
0
120
Min
30
55
50
120
120
Max
28F010-120(5)
NOTES:
1. Whichever occurs first.
2. Sampled, not 100% tested.
3. Guaranteed by design.
4. See High Speed AC Input/Output reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics.
5. See AC Input/Output reference Waveforms and AC Testing Load Circuits for testing characteristics.
Read Cycle Time
tELQV/tCE
Characteristic
tAVAV/tRC
Symbol
Versions
6
0
0
0
150
Min
35
55
55
150
150
Max
28F010-150(5)
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
28F010
AC CHARACTERISTICSÐRead Only OperationsÐCommercial and Extended
Temperature Products
21
290207– 9
28F010
Figure 7. AC Waveforms for Read Operations
22
Address Set-Up Time
Address Hold Time
Data Set-Up Time
Data Hold Time
Write Recovery Time
before Read
Read Recovery Time
before Write
Chip Enable Set-Up Time
before Write
Chip Enable Hold Time
Write Pulse Width
Write Pulse Width High
Duration of Programming
Operation
Duration of Erase
Operation
VPP Set-Up Time to
Chip Enable Low
tWLAX/tAH
tDVWH/tDS
tWHDX/tDH
tWHGL
tGHWL
tELWL/tCS
tWHEH/tCH
tWLWH/tWP
tWHWL/tWPH
tWHWH1
tWHWH2
tVPEL
VCC g 5%
2
3
3
6
2
6
6
Notes
VCC g 10%
1
9.5
10
20
40
0
15
0
6
10
40
40
0
65
Min
Max
28F010-65(4)
1
9.5
10
20
40
0
15
0
6
10
40
40
0
70
Max
28F010-65(5)
Min
1
9.5
10
20
55
40
0
15
0
6
10
55
40
55
40
0
90
Max
28F010-90(5)
Min
1
9.5
10
20
60
0
15
0
6
10
40
40
0
120
Min
Max
28F010-120(5)
1
9.5
10
20
60
0
15
0
6
10
40
40
0
150
Min
Max
28F010-150(5)
ms
ms
ms
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
Unit
NOTES:
1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only Operations.
2. Guaranteed by design.
3. The integrated stop timer terminates the programming/erase operations, thus eliminating the need for a maximum specification.
4. See High Speed AC Input/Output reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics.
5. See AC Input/Output reference Waveforms and AC Testing Load Circuits for testing characteristics.
6. Minimum specification for Extended Temperature product.
Write Cycle Time
tAVWL/tAS
Characteristic
tAVAV/tWC
Symbol
Versions
28F010
AC CHARACTERISTICSÐWrite/Erase/Program Only Operations(1)Ð
Commercial and Extended Temperature Products
23
28F010
290207 – 13
Figure 8. Typical Programming Capability
290207 – 14
Figure 9. Typical Program Time at 12V
24
290207 – 15
Figure 10. Typical Erase Capability
290207 – 16
Figure 11. Typical Erase Time at 12V
290207– 10
28F010
Figure 12. AC Waveforms for Programming Operations
25
290207– 11
28F010
Figure 13. AC Waveforms for Erase Operations
26
Address Set-Up Time
Address Hold Time
Data Set-Up Time
Data Hold Time
Write Recovery Time
before Read
Read Recovery Time
before Write
Write Enable Set-Up Time
before Chip Enable
Write Enable Hold Time
Write Pulse Width
Write Pulse Width High
Duration of Programming
Operation
Duration of Erase
Operation
VPP Set-Up Time to Chip
Enable Low
tELAX
tDVEH
tEHDX
tEHGL
tGHWL
tWLEL
tEHWH
tELEH
tEHEL
tEHEH1
tEHEH2
tVPEL
VCC g 5%
2
3
3
6
2
6
6
Notes
VCC g 10%
1
9.5
10
20
45
0
0
0
6
10
35
45
0
65
Min
Max
28F010-65(2, 4)
1
9.5
10
20
45
0
0
0
6
10
35
45
0
70
Max
28F010-65(5)
Min
1
9.5
10
20
60
45
0
0
0
6
10
50
35
60
45
0
90
Max
28F010-90(5)
Min
1
9.5
10
20
70
0
0
0
6
10
45
55
0
120
Min
Max
28F010-120(5)
1
9.5
10
20
70
0
0
0
6
10
45
55
0
150
Min
Max
28F010-150(5)
ms
ms
ms
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
Unit
NOTE:
1. Read timing characteristics during read/write operations are the same as during read-only operations. Refer to AC Characteristics for Read-Only Operations.
2. Guaranteed by design.
3. The integrated stop timer terminates the programming/erase operations, thus eliminating the need for a maximum specification.
4. See High Speed AC Input/Output reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics.
5. See AC Input/Output reference Waveforms and AC Testing Load Circuits for testing characteristics.
6. Minimum specification for Extended Temperature product.
Write Cycle Time
tAVEL
Characteristic
tAVAV
Symbol
Versions
28F010
AC CHARACTERISTICSÐAlternative CEÝ-Controlled WritesÐCommercial and
Extended Temperature
27
28F010
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Notes
Min
Chip Erase Time
1, 3, 4
Chip Program Time
1, 2, 4
Typical
1
2
Max
10
12.5
Unit
Sec
Sec
NOTES:
1. ‘‘Typicals’’ are not guaranteed, but based on samples from production lots. Data taken at 25§ C, 12.0V VPP.
2. Minimum byte programming time excluding system overhead is 16 msec (10 msec program a 6 msec write recovery),
while maximum is 400 msec/byte (16 msec x 25 loops allowed by algorithm). Max chip programming time is specified lower
than the worst case allowed by the programming algorithm since most bytes program significantly faster than the worst case
byte.
3. Excludes 00H programming prior to erasure.
4. Excludes system level overhead.
28
290207– 19
28F010
NOTE:
Alternative CEÝ-Controlled Write Timings also apply to erase operations.
Figure 14. Alternate AC Waveforms for Programming Operations
29
28F010
ORDERING INFORMATION
290207 – 20
VALID COMBINATIONS:
P28F010-65
N28F010-65
P28F010-90
N28F010-90
P28F010-120
N28F010-120
P28F010-150
N28F010-150
E28F010-65
E28F010-90
E28F010-120
E28F010-150
F28F010-65
F28F010-90
F28F010-120
F28F010-150
TN28F010-90
TE28F010-90
TF28F010-90
ADDITIONAL INFORMATION
ER-20,
ER-24,
‘‘ETOX Flash Memory Technology’’
‘‘Intel Flash Memory’’
Order
Number
294005
294008
ER-28,
RR-60,
AP-316,
‘‘ETOX III Flash Memory Technology’’
‘‘ETOX Flash Memory Reliability Data Summary’’
‘‘Using Flash Memory for In-System Reprogrammable Nonvolatile Storage’’
294012
293002
292046
AP-325
‘‘Guide to Flash Memory Reprogramming’’
292059
REVISION HISTORY
Number
30
Description
007
Removed 200 ns Speed Bin
Revised Erase Maximum Pulse Count for Figure 5 from 3000 to 1000
Clarified AC and DC Test Conditions
Added ‘‘dimple’’ to F TSOP Package
Corrected Serpentine Layout
008
Corrected AC Waveforms
Added Extended Temperature Options
009
Added 28F010-65 and 28F010-90 speeds
Revised Symbols, i.e., CE, OE, etc. to CEÝ, OEÝ, etc.
010
Completion of Read Operation Table
Labelling of Program Time in Erase/Program Table
Textual Changes or Edits
Corrected Erase/Program Times