CATALYST CAT28F102NA-55T

CAT28F102
Licensed Intel
second source
1 Megabit CMOS Flash Memory
FEATURES
■ Fast Read Access Time: 45/55/70/90 ns
■ 64K x 16 Word Organization
■ Low Power CMOS Dissipation:
■ Stop Timer for Program/Erase
–Active: 30 mA max (CMOS/TTL levels)
–Standby: 1 mA max (TTL levels)
–Standby: 100 µA max (CMOS levels)
■ On-Chip Address and Data Latches
■ JEDEC Standard Pinouts:
–40-pin DIP
–44-pin PLCC
–40-pin TSOP
■ High Speed Programming:
–10 µs per byte
–1 Sec Typ Chip Program
■ 100,000 Program/Erase Cycles
■ 0.5 Seconds Typical Chip-Erase
■ 12.0V
■ 10 Year Data Retention
± 5% Programming and Erase Voltage
■ Electronic Signature
■ Commercial,Industrial and Automotive
Temperature Ranges
DESCRIPTION
two write cycle scheme. Address and Data are latched
to free the I/O bus and address bus during the write
operation.
The CAT28F102 is a high speed 64K x 16-bit electrically
erasable and reprogrammable Flash memory ideally
suited for applications requiring in-system or after-sale
code updates. Electrical erasure of the full memory
contents is achieved typically within 0.5 second.
The CAT28F102 is manufactured using Catalyst’s advanced CMOS floating gate technology. It is designed to
endure 100,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 40-pin DIP, 44-pin PLCC, or 40-pin TSOP
packages.
It is pin and Read timing compatible with standard
EPROM and E2PROM devices. Programming and Erase
are performed through an operation and verify algorithm. The instructions are input via the I/O bus, using a
BLOCK DIAGRAM
I/O0–I/O15
I/O BUFFERS
ERASE VOLTAGE
SWITCH
WE
COMMAND
REGISTER
PROGRAM VOLTAGE
SWITCH
CE, OE LOGIC
DATA
LATCH
SENSE
AMP
CE
ADDRESS LATCH
OE
A0–A15
Y-GATING
Y-DECODER
X-DECODER
VOLTAGE VERIFY
SWITCH
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1,048,576-BIT
MEMORY
ARRAY
28F101-1
1
Doc. No. 25038-0A 2/98 F-1
CAT28F102
PIN CONFIGURATION
PIN FUNCTIONS
Pin Name
Type
Function
A0–A15
Input
Address Inputs for
memory addressing
I/O0–I/O15
A15
A14
A13
8
9
38
37
A12
10
36
11
35
12
13
34
33
VSS
14
32
A8
15
16
31
30
A7
A6
A5
7
I/O9
I/O8
VSS
A11
A10
A9
NC
A9
A10
A11
A12
A13
A14
A15
NC
WE
VCC
VPP
CE
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
DIP Package (P)
1
2
3
4
40
39
38
5
6
7
36
8
33
I/O9
I/O8
VSS
9
10
11
32
I/O7
I/O6
I/O5
12
I/O4
I/O3
15
I/O2
I/O1
17
I/O0
OE
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
Doc. No. 25038-0A 2/98 F-1
13
14
37
35
34
VCC
WE
NC
A15
A14
31
A10
A9
30
29
VSS
A8
28
27
A7
A6
A5
26
25
CE
Input
Chip Enable
OE
Input
Output Enable
WE
Input
Write Enable
VCC
Voltage Supply
VSS
Ground
VPP
Program/Erase
Voltage Supply
NC
No Connect
18
A4
A3
A2
19
20
22
21
A1
A0
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
VSS
A8
A7
A6
A5
A4
A3
A2
A1
A0
OE
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
VSS
28F101-3
Reverse TSOP Package (T14R)
A13
A12
A11
24
23
16
Data Input/Output
TSOP Package (T14)
28F101-2
VPP
CE
I/O
A1
A2
A3
A4
OE
NC
A0
29
17
18 19 20 21 22 23 24 25 26 27 28
I/O3
I/O2
I/O1
I/O0
I/O7
I/O6
I/O5
I/O4
6 5 4 3 2 1 44 43 42 41 40
39
I/O12
I/O11
I/O10
NC
VPP
NC
VCC
WE
NC
I/O13
I/O14
I/O15
CE
PLCC Package (N)
A0
A1
A2
A3
A4
A5
A6
A7
A8
GND
A9
A10
A11
A12
A13
A14
A15
NC
WE
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
OE
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
GND
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
VPP
CE
28F102 TSOP2
2
CAT28F102
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................... –55°C to +95°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground(1) ........... –0.6V to +VCC + 2.0V
Voltage on Pin A9 with
Respect to Ground(1) ................... –2.0V to +13.5V
VPP with Respect to Ground
during Program/Erase(1) .............. –0.6V to +14.0V
VCC with Respect to Ground(1) ............ –2.0V to +7.0V
Package Power Dissipation
Capability (TA = 25°C) .................................. 1.0 W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
NEND
(3)
Parameter
Endurance
Min.
Max.
Units
Test Method
100K
Cycles/Byte
MIL-STD-883, Test Method 1033
10
Years
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
TDR(3)
Data Retention
VZAP(3)
ESD Susceptibility
2000
Volts
ILTH(3)(4)
Latch-Up
100
mA
JEDEC Standard 17
CAPACITANCE TA = 25°C, f = 1.0 MHz
Limits
Symbol
Test
(3)
CIN
COUT(3)
CVPP
(3)
Min
Max.
Units
Conditions
Input Pin Capacitance
6
pF
VIN = 0V
Output Pin Capacitance
10
pF
VOUT = 0V
VPP Supply Capacitance
25
pF
VPP = 0V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
3
Doc. No. 25038-0A 2/98 F-1
CAT28F102
D.C. OPERATING CHARACTERISTICS
VCC = +5V ±10%, unless otherwise specified
Limits
Symbol
Parameter
Min.
Max.
Unit
Test Conditions
ILI
Input Leakage Current
±1
µA
VIN = VCC or VSS
VCC = 5.5V, OE = VIH
ILO
Output Leakage Current
±1
µA
VOUT = VCC or VSS,
VCC = 5.5V, OE = VIH
ISB1
VCC Standby Current CMOS
100
µA
CE = VCC ±0.5V,
VCC = 5.5V
ISB2
VCC Standby Current TTL
1
mA
CE = VIH, VCC = 5.5V
ICC1
VCC Active Read Current
50
mA
VCC = 5.5V, CE = VIL,
IOUT = 0mA, f = 6 MHz
ICC2(1)
VCC Programming Current
30
mA
VCC = 5.5V,
Programming in Progress
ICC3(1)
VCC Erase Current
30
mA
VCC = 5.5V,
Erasure in Progress
ICC4(1)
VCC Prog./Erase Verify Current
30
mA
VCC = 5.5V, Program or
Erase Verify in Progress
IPPS
VPP Standby Current
±10
µA
VPP = VPPL
IPP1
VPP Read Current
100
µA
VPP = VPPH
IPP2(1)
VPP Programming Current
50
mA
VPP = VPPH,
Programming in Progress
IPP3(1)
VPP Erase Current
30
mA
VPP = VPPH,
Erasure in Progress
IPP4(1)
VPP Prog./Erase Verify Current
5
mA
VPP = VPPH, Program or
Erase Verify in Progress
VIL
Input Low Level TTL
–0.5
0.8
V
VILC
Input Low Level CMOS
–0.5
0.8
V
VOL
Output Low Level
0.45
V
VIH
Input High Level TTL
2
VCC+0.5
V
VIHC
Input High Level CMOS
VCC*0.7
VCC+0.5
V
VOH1
Output High Level TTL
2.4
V
IOH = –2.5mA, VCC = 4.5V
VOH2
Output High Level CMOS
VCC-0.4
V
IOH = –400µA, VCC = 4.5V
VID
A9 Signature Voltage
13.0
V
A9 = VID
IID(1)
A9 Signature Current
200
µA
A9 = VID
VLO
VCC Erase/Prog. Lockout Voltage
11.4
2.5
IOL = 5.8mA, VCC = 4.5V
V
Supply Characteristics
VCC
VCC Supply Voltage
4.5
5.5
V
28F102-70, 90
VCC
VCC Supply Voltage
4.75
5.25
V
28F102-55, -45
VPPL
VPP During Read Operations
0
6.5
V
VPPH
VPP During Read/Erase/Program
11.4
12.6
V
Doc. No. 25038-0A 2/98 F-1
4
CAT28F102
A.C. CHARACTERISTICS, Read Operation
VCC = +5V ±10%, unless otherwise specified
JEDEC
28F102-45(7)
Standard
Vcc=5V+5%
Symbol
Parameter
tAVAV
tRC
Read Cycle Time
tELQV
tCE
CE Access Time
45
55
70
90
ns
tAVQV
tACC
Address Access Time
45
55
70
90
ns
tGLQV
tOE
OE Access Time
20
25
28
35
ns
tAXQX
tOH
Output Hold from Address
OE/CE Chan
0
0
0
0
ns
tGLQX
tOLZ(1)(6)
OE to Output in Low-Z
0
0
0
0
ns
tELQX
tLZ(1)(6)
CE to Output in Low-Z
0
0
0
0
ns
tGHQZ
tDF(1)(2)
OE High to Output High-Z
15
15
18
20
ns
-
CE High to Output High-Z
15
15
25
30
ns
tWHGL
Max.
Vcc=5V+5%
Symbol
tEHQZ(1)(2)
Min.
28F102-55(7) 28F102-70 (7) 28F102- 90 (8)
45
Write Recovery Time Before
Read
Min. Max. Min.
55
6
Max.
70
6
Min.
Max
90
6
6
Unit
ns
µs
Figure 1. A.C. Testing Input/Output Waveform(3)(4)(5)
2.4 V
2.0 V
INPUT PULSE LEVELS
REFERENCE POINTS
0.8 V
0.45 V
5108 FHD F03
Figure 2. A.C. Testing Load Circuit (example)
1.3V
1N914
3.3K
DEVICE
UNDER
TEST
OUT
CL = 100 pF
CL INCLUDES JIG CAPACITANCE
5108 FHD F04
Figure 3. High Speed A.C. Testing Input/Output Waveform(3)(4)(5)
3V V
2.4
2.0 V
1.5V
0.8 V
INPUT PULSE LEVELS
0.0 V
0.45
REFERENCE POINTS
Figure 4. High Speed A.C. Testing Load Circuit (example)
1.3V
1N914
3.3K
DEVICE
UNDER
TEST
OUT
CL = 100
30 pF
CL INCLUDES JIG CAPACITANCE
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer.
(3) Input Rise and Fall Times (10% to 90%) < 10 ns.
(4) Input Pulse Levels = 0.45V and 2.4V. For high speed input pulse levels 0.0V and 3.0V.
(5) Input and Output Timing Reference = 0.8V and 2.0V. For high speed input and output timing reference=1.5V.
(6) Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid.
(7) For Load and Reference Points see Figures 3 and 4
(8) For Load and Reference Points see Figures 1 and 2
5
Doc. No. 25038-0A 2/98 F-1
CAT28F102
A.C. CHARACTERISTICS, Program/Erase Operation
VCC = +5V ±10%, unless otherwise specified.
JEDEC
Standard
28F102-45
28F102-55
28F102-70 28F102-90
VCC = +5V ±5% VCC = +5V ±5%
Symbol
Symbol
Parameter
Min. Max.
Min.
Max.
Min. Max. Min.
Max.
Unit
tAVAV
tWC
Write Cycle Time
45
55
70
90
ns
tAVWL
tAS
Address Setup Time
0
0
0
0
ns
tWLAX
tAH
Address Hold Time
30
30
35
40
ns
tDVWH
tDS
Data Setup Time
30
30
35
40
ns
tWHDX
tDH
Data Hold Time
10
10
10
10
ns
tELWL
tCS
CE Setup Time
0
0
0
0
ns
tWHEH
tCH
CE Hold Time
0
0
0
0
ns
tWLWH
tWP
WE Pulse Width
30
30
35
40
ns
tWHWL
tWPH
WE High Pulse Width
20
20
20
20
ns
tWHWH1(2)
-
Program Pulse Width
10
10
10
10
µs
tWHWH2(2)
-
Erase Pulse Width
9.5
9.5
9.5
9.5
ms
tWHGL
-
Write Recovery Time
Before Read
6
6
6
6
µs
tGHWL
-
Read Recovery Time
Before Write
0
0
0
0
µs
tVPEL
-
VPP Setup Time to CE
100
100
100
100
ns
Erase and Programming Performance (1)
28F102-45
Parameter
Chip Erase Time (3)(5)
Chip Program Time(3)(4)
28F102-55
28F102-70
Min. Typ. Max. Min. Typ. Max. Min. Typ.
0.5
10
0.5
10
0.5
1
6.5
1
6.5
1
28F102-90
Max. Min. Typ.
Max.
Unit
10
0.5
10
sec
6.5
1
6.5
sec
Note:
(1) Please refer to Supply characteristics for the value of VPPH and VPPL. The VPP supply can be either hardwired or switched. If VPP is
switched, VPPL can be ground, less than VCC + 2.0V or a no connect with a resistor tied to ground.
(2) Program and Erase operations are controlled by internal stop timers.
(3) ‘Typicals’ are not guaranteed, but based on characterization data. Data taken at 25°C, 12.0V VPP.
(4) Minimum byte programming time (excluding system overhead) is 16 µs (10 µs program + 6 µs write recovery), while maximum is 400 µs/
byte (16 µs x 25 loops). Max chip programming time is specified lower than the worst case allowed by the programming algorithm since
most bytes program significantly faster than the worst case byte.
(5) Excludes 00H Programming prior to Erasure.
Doc. No. 25038-0A 2/98 F-1
6
CAT28F102
FUNCTION TABLE(1)
Pins
Mode
CE
OE
WE
VPP
I/O
Notes
Read
VIL
VIL
VIH
VPPL
DOUT
Output Disable
VIL
VIH
VIH
X
High-Z
Standby
VIH
X
X
VPPL
High-Z
Signature (MFG)
VIL
VIL
VIH
VPPL
0031H
A0 = VIL, A9 = 12V
Signature (Device)
VIL
VIL
VIH
X
0051H
A0 = VIH, A9 = 12V
Program/Erase
VIL
VIH
VIL
VPPH
DIN
See Command Table
Write Cycle
VIL
VIH
VIL
VPPH
DIN
During Write Cycle
Read Cycle
VIL
VIL
VIH
VPPH
DOUT
During Write Cycle
Output Disable
VIL
VIH
VIH
VPPH
High-Z
During Write Cycle
Standby
VIH
X
X
VPPH
High-Z
During Write Cycle
WRITE COMMAND TABLE
Commands are written into the command register in one or two write cycles. The command register can be altered
only when VPP is high and the instruction byte is latched on the rising edge of WE. Write cycles also internally latch
addresses and data required for programming and erase operations.
Pins
First Bus Cycle
Mode
Second Bus Cycle
Operation
Address
DIN
Operation
Address
DIN
DOUT
Set Read
Write
X
XX00H
Read
AIN
DOUT
Read Sig. (MFG)
Write
X
XX90H
Read
0000
0031H
Read Sig. (Device)
Write
X
XX90H
Read
0001
0051H
Erase
Write
X
XX20H
Write
X
Erase Verify
Write
AIN
XXA0H
Read
X
Program
Write
X
XX40H
Write
AIN
Program Verify
Write
X
XXC0H
Read
X
Reset
Write
X
XXFFH
Write
X
XX20H
DOUT
DIN
DOUT
XXFFH
Note:
(1) Logic Levels: X = Logic ‘Do not care’ (VIH, VIL, VPPL, VPPH)
7
Doc. No. 25038-0A 2/98 F-1
CAT28F102
READ OPERATIONS
Read Mode
The conventional mode is entered as a regular READ
mode by driving the CE and OE pins low (with WE high),
and applying the required high voltage on address pin A9
while all other address lines are held at VIL.
A Read operation is performed with both CE and OE low
and with WE high. VPP can be either high or low,
however, if VPP is high, the Set READ command has to
be sent before reading data (see Write Operations). The
data retrieved from the I/O pins reflects the contents of
the memory location corresponding to the state of the 16
address pins. The respective timing waveforms for the
read operation are shown in Figure 5. Refer to the AC
Read characteristics for specific timing parameters.
A Read cycle from address 0000H retrieves the binary
code for the IC manufacturer on outputs I/O0 to I/O15:
CATALYST Code = 0000 0000 0011 0001 (0031H)
A Read cycle from address 0001H retrieves the binary
code for the device on outputs I/O0 to I/O15.
Signature Mode
The signature mode allows the user to identify the IC
manufacturer and the type of device while the device
resides in the target system. This mode can be activated
in either of two ways; through the conventional method
of applying a high voltage (12V) to address pin A9 or by
sending an instruction to the command register (see
Write Operations).
28F102 Code = 0000 0000 0101 0001 (0051H)
Standby Mode
With CE at a logic-high level, the CAT28F102 is placed
in a standby mode where most of the device circuitry is
disabled, thereby substantially reducing power consumption. The outputs are placed in a high-impedance
state.
Figure 5. A.C. Timing for Read Operation
POWER UP
STANDBY
DEVICE AND
ADDRESS SELECTION
ADDRESSES
OUPUTS
ENABLED
DATA VALID
STANDBY
POWER DOWN
ADDRESS STABLE
tAVAV (tRC)
CE (E)
tEHQZ(tDF)
OE (G)
tWHGL
tGHQZ (tDF)
tGLQV (tOE)
WE (W)
tELQV (tCE)
tGLQX (tOLZ)
tELQX (tLZ)
tAXQX(tOH)
HIGH-Z
HIGH-Z
DATA (I/O)
OUTPUT VALID
tAVQV (tACC)
28F102 F05
28F102 Fig. 6
Doc. No. 25038-0A 2/98 F-1
8
CAT28F102
WRITE OPERATIONS
A Read cycle from address 0001H retrieves the binary
code for the device on outputs I/O0 to I/O7.
The following operations are initiated by observing the
sequence specified in the Write Command Table.
28F102 Code = 0000 0000 0101 0001 (0051H)
Read Mode
Erase Mode
The device can be put into a standard READ mode by
initiating a write cycle with XX00H on the data bus. The
subsequent read cycles will be performed similar to a
standard EPROM or E2PROM Read.
During the first Write cycle, the command XX20H is
written into the command register. In order to commence
the erase operation, the identical command of XX20H
has to be written again into the register. This two-step
process ensures against accidental erasure of the
memory contents. The final erase cycle will be stopped
at the rising edge of WE, at which time the Erase Verify
command (XXA0H) is sent to the command register.
During this cycle, the address to be verified is sent to the
address bus and latched when WE goes low. An integrated stop timer allows for automatic timing control over
this operation, eliminating the need for a maximum
erase timing specification. Refer to AC Characteristics
(Program/Erase) for specific timing parameters.
Signature Mode
An alternative method for reading device signature (see
Read Operations Signature Mode), is initiated by writing
the code XX90H into the command register while keeping VPP high. A read cycle from address 0000H with CE
and OE low (and WE high) will output the device signature.
CATALYST Code = 0000 0000 0011 0001 (0031H)
Figure 6. A.C. Timing for Erase Operation
VCC POWER-UP
& STANDBY
SETUP ERASE
COMMAND
ERASE
COMMAND
ERASING
ERASE VERIFY
COMMAND
ERASE
VCC POWER-DOWN/
VERIFICATION
STANDBY
ADDRESSES
tWC
tWC
tWC
tAS
tRC
tAH
CE (E)
tCH
tCS
tCH
tCS
tCH
tEHQZ
OE (G)
tGHWL
tWHWH2
tWPH
tDF
tWHGL
WE (W)
tWP
tDS
HIGH-Z
DATA IN
= XX20H
DATA (I/O)
tDH
tDS
tWP
tDH
tWP
tDS
tDH
tOE
DATA IN
= XXA0H
DATA IN
= XX20H
tLZ
tCE
VCC
VALID
DATA OUT
5.0V
0V
VPP
tOH
tOLZ
tVPEL
VPPH
VPPL
28F102 Fig. 6
28F102 F06
9
Doc. No. 25038-0A 2/98 F-1
CAT28F102
Figure 7. Chip Erase Algorithm(1)
BUS
OPERATION COMMAND
START ERASURE
COMMENTS
APPLY VPPH
VPP RAMPS TO VPPH
(OR VPP HARDWIRED)
PROGRAM ALL
BYTES TO 0000H
ALL BYTES SHALL BE
PROGRAMMED TO 00
BEFORE AN ERASE
OPERATION
STANDBY
INITIALIZE
ADDRESS
INITIALIZE ADDRESS
INITIALIZE
PLSCNT = 0
PLSCNT = PULSE COUNT
DATA = XX20H
WRITE ERASE
SETUP COMMAND
WRITE
ERASE
WRITE ERASE
COMMAND
WRITE
ERASE
DATA = XX20H
WAIT
TIME OUT 10ms
WRITE ERASE
VERIFY COMMAND
WRITE
ERASE
VERIFY
TIME OUT 6µs
ADDRESS = BYTE TO VERIFY
DATA = XXA0H
STOPS ERASE OPERATION
WAIT
INCREMENT
ADDRESS
READ DATA
FROM DEVICE
READ
READ BYTE TO
VERIFY ERASURE
STANDBY
COMPARE OUTPUT TO FF
INCREMENT PULSE COUNT
NO
DATA =
FFH?
YES
NO
NO
INC PLSCNT
= 1000 ?
YES
LAST
ADDRESS?
YES
WRITE READ
COMMAND
WRITE
APPLY VPPL
APPLY VPPL
ERASURE
COMPLETED
ERASE
ERROR
STANDBY
Note:
(1) The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device.
Doc. No. 25038-0A 2/98 F-1
10
READ
DATA = 0000H
RESETS THE REGISTER
FOR READ OPERATION
VPP RAMPS TO VPPL
(OR VPP HARDWIRED)
28F101-07
CAT28F102
Erase-Verify Mode
Program-Verify Mode
The Erase-verify operation is performed on every byte
after each erase pulse to verify that the bits have been
erased.
A Program-verify cycle is performed to ensure that all
bits have been correctly programmed following each
byte programming operation. The specific address is
already latched from the write cycle just completed, and
stays latched until the verify is completed. The Programverify operation is initiated by writing XXC0H into the
command register. An internal reference generates the
necessary high voltages so that the user does not need
to modify VCC. Refer to AC Characteristics (Program/
Erase) for specific timing parameters.
Programming Mode
The programming operation is initiated using the programming algorithm of Figure 9. During the first write
cycle, the command XX40H is written into the command
register. During the second write cycle, the address of
the memory location to be programmed is latched on the
falling edge of WE, while the data is latched on the rising
edge of WE. The program operation terminates with the
next rising edge of WE. An integrated stop timer allows
for automatic timing control over this operation, eliminating the need for a maximum program timing specification. Refer to AC Characteristics (Program/Erase) for
specific timing parameters.
Figure 8. A.C. Timing for Programming Operation
PROGRAM
VCC POWER-UP SETUP PROGRAM LATCH ADDRESS
COMMAND
& DATA
VERIFY
& STANDBY
PROGRAMMING COMMAND
PROGRAM
VCC POWER-DOWN/
VERIFICATION
STANDBY
ADDRESSES
tWC
tWC
tAS
tRC
tAH
CE (E)
tCH
tCS
tCH
tCS
tCH
tEHQZ
OE (G)
tGHWL
tWHWH1
tWPH
tDF
tWHGL
WE (W)
tWP
tDS
HIGH-Z
DATA IN
= XX 40H
DATA (I/O)
tDH
tDS
tWP
tDH
tWP
tDS
tDH
tOE
DATA IN
= XX C0H
DATA IN
tLZ
tCE
VCC
VALID
DATA OUT
5.0V
0V
VPP
tOH
tOLZ
tVPEL
VPPH
VPPL
28F102 F07
11
Doc. No. 25038-0A 2/98 F-1
CAT28F102
Figure 9. Programming Algorithm(1)
START
PROGRAMMING
BUS
OPERATION
APPLY VPPH
STANDBY
COMMAND
COMMENTS
VPP RAMPS TO VPPH
(OR VPP HARDWIRED)
INITIALIZE
ADDRESS
INITIALIZE ADDRESS
PLSCNT = 0
INITIALIZE PULSE COUNT
PLSCNT = PULSE COUNT
WRITE SETUP
PROG. COMMAND
1ST WRITE
CYCLE
WRITE
SETUP
DATA = XX40H
WRITE PROG. CMD
ADDR AND DATA
2ND WRITE
CYCLE
PROGRAM
VALID ADDRESS AND DATA
TIME OUT 10µs
WAIT
WRITE PROGRAM
VERIFY COMMAND
1ST WRITE
CYCLE
PROGRAM
VERIFY
TIME OUT 6µs
DATA = XXC0H
WAIT
READ DATA
FROM DEVICE
READ
READ BYTE TO VERIFY
PROGRAMMING
STANDBY
COMPARE DATA OUTPUT
TO DATA EXPECTED
NO
VERIFY
DATA ?
YES
INCREMENT
ADDRESS
NO
NO
INC
PLSCNT
= 25 ?
YES
LAST
ADDRESS?
YES
WRITE READ
COMMAND
1ST WRITE
CYCLE
APPLY VPPL
APPLY VPPL
PROGRAMMING
COMPLETED
PROGRAM
ERROR
STANDBY
READ
DATA = XX00H
SETS THE REGISTER FOR
READ OPERATION
VPP RAMPS TO VPPL
(OR VPP HARDWIRED)
Note:
(1) The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device.
28F101-09
Doc. No. 25038-0A 2/98 F-1
12
CAT28F102
Abort/Reset
POWER UP/DOWN PROTECTION
An Abort/Reset command is available to allow the user
to safely abort an erase or program sequence. Two
consecutive program cycles with XXFFH on the data
bus will abort an erase or a program operation. The
abort/reset operation can interrupt at any time in a
program or erase operation and the device is reset to the
Read Mode.
The CAT28F102 offers protection against inadvertent
programming during VPP and VCC power transitions.
When powering up the device there is no power-on
sequencing necessary. In other words, VPP and VCC
may power up in any order. Additionally VPP may be
hardwired to VPPH independent of the state of VCC and
any power up/down cycling. The internal command
register of the CAT28F102 is reset to the Read Mode on
power up.
DATA PROTECTION
1. Power Supply Voltage
POWER SUPPLY DECOUPLING
When the power supply voltage (VCC) is less than 2.5V,
the device ignores WE signal.
To reduce the effect of transient power supply voltage
spikes, it is good practice to use a 0.1µF ceramic
capacitor between VCC and VSS and VPP and VSS. These
high-frequency capacitors should be placed as close as
possible to the device for optimum decoupling.
2. Write Inhibit
When CE and OE are terminated to the low level, write
mode is not set.
Figure 10. Alternate A.C. Timing for Program Operation
PROGRAM
VCC POWER-UP SETUP PROGRAM LATCH ADDRESS
COMMAND
& DATA
VERIFY
& STANDBY
PROGRAMMING COMMAND
PROGRAM VCC POWER-DOWN/
VERIFICATION
STANDBY
ADDRESSES
tWC
tWC
tAVEL
tRC
tELAX
WE (E)
tWLEL
tEHWH
tWLEL
tEHWH
tEHWH
tEHQZ
tWLEL
OE (G)
tEHEH
tGHEL
tEHGL
tDF
tEHEL
CE (W)
tDVEH
HIGH-Z
DATA (I/O)
tEHDX
tELEH
tDVEH
DATA IN
= XX40H
tOE
tEHDX
tOLZ
tELEH
tEHDX
tDVEH
tOH
DATA IN
= XXC0H
DATA IN
tLZ
tCE
VALID
DATA OUT
VCC 5.0V
0V
tVPEL
VPP VPPH
VPPL
28F102 F10
13
Doc. No. 25038-0A 2/98 F-1
CAT28F102
ALTERNATE CE-CONTROLLED WRITES
VCC = +5V ±10%, unless otherwise specified.
JEDEC
Symbol
28F102-45
28F102-55
VCC = +5V ±5%
VCC = +5V ±5%
28F102-70
28F102-90
Min.
Min.
Standard
Symbol
Parameter
tAVAV
WC
Write Cycle Time
45
55
70
90
ns
tAVEL
tAS
Address Setup Time
0
0
0
0
ns
tELAX
tAH
Address Hold Time
30
30
35
40
ns
tDVEH
tDS
Data Setup Time
30
30
35
40
ns
tEHDX
tDH
Data Hold Time
10
10
10
10
ns
tEHGL
-
Write Recovery Time Before
Read
6
6
6
6
µs
tGHEL
-
Read Recovery Time Before
Write
0
0
0
0
µs
tWLEL
tWS
WE Setup Time Before CE
0
0
0
0
ns
tEHWH
tWH
WE Hold Time After CE
0
0
0
0
ns
tELEH
tCP
Write Pulse Width
30
30
35
40
ns
tEHEL
tCPH
Write Pulse Width High
20
20
20
20
ns
tVPEL
-
VPP Setup Time to CE Low
100
100
100
100
ns
Min.
Max.
Min.
Max.
Max.
Max.
ORDERING INFORMATION
Prefix
Device #
CAT
28F102
Product
Number
Optional
Company ID
Suffix
N
I
Temperature Range
Blank = Commercial (0˚ - 70˚C)
I = Industrial (-40˚ - 85˚C)
A = Automotive (-40˚ - 105˚C)*
-90
T
Tape & Reel
T: 500/Reel
Speed
45: 45ns
55: 55ns
70: 70ns
90: 90ns
Package
N: PLCC
P: PDIP
T14: TSOP
T14R: TSOP
*-40o to + 125oC is available upon request
Note:
(1) The device used in the above example is a CAT28F102NI-90T (PLCC, Industrial Temperature, 90 ns access time, Tape & Reel).
Doc. No. 25038-0A 2/98 F-1
14
Unit