IRF IRLML5103

PD - 91260E
IRLML5103
HEXFET® Power MOSFET
l
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Generation V Technology
Ultra Low On-Resistance
P-Channel MOSFET
SOT-23 Footprint
Low Profile (<1.1mm)
Available in Tape and Reel
Fast Switching
D
VDSS = -30V
G
RDS(on) = 0.60Ω
S
Description
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This benefit,
combined with the fast switching speed and ruggedized
device design that HEXFET Power MOSFETs are well
known for, provides the designer with an extremely efficient
and reliable device for use in a wide variety of applications.
A customized leadframe has been incorporated into the
standard SOT-23 package to produce a HEXFET Power
MOSFET with the industry's smallest footprint. This
package, dubbed the Micro3, is ideal for applications
where printed circuit board space is at a premium. The low
profile (<1.1mm) of the Micro3 allows it to fit easily into
extremely thin application environments such as portable
electronics and PCMCIA cards.
Micro3
Absolute Maximum Ratings
Parameter
I D @ TA = 25°C
I D @ TA = 70°C
IDM
PD @TA = 25°C
VGS
dv/dt
TJ, TSTG
Max.
Continuous Drain Current, VGS @ -10V
Continuous Drain Current, VGS @ -10V
Pulsed Drain Current 
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery dv/dt ‚
Junction and Storage Temperature Range
Units
-0.76
-0.61
-4.8
540
4.3
± 20
-5.0
-55 to + 150
A
mW
mW/°C
V
V/ns
°C
Thermal Resistance
Parameter
RθJA
Maximum Junction-to-Ambient „
Typ.
Max.
Units
–––
230
°C/W
04/29/03
IRLML5103
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
∆V(BR)DSS/∆TJ
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
RDS(ON)
Static Drain-to-Source On-Resistance
VGS(th)
g fs
Gate Threshold Voltage
Forward Transconductance
IDSS
Drain-to-Source Leakage Current
V(BR)DSS
I GSS
Qg
Qgs
Qgd
t d(on)
tr
t d(off)
tf
Ciss
Coss
C rss
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Min.
-30
–––
–––
–––
-1.0
0.44
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
-0.029
–––
–––
–––
–––
–––
–––
–––
–––
3.4
0.52
1.1
10
8.2
23
16
75
37
18
Max. Units
Conditions
–––
V
VGS = 0V, ID = -250µA
––– V/°C Reference to 25°C, ID = -1mA
0.60
VGS = -10V, ID = -0.60A ƒ
Ω
1.0
VGS = -4.5V, I D = -0.30A ƒ
–––
V
VDS = VGS, I D = -250µA
–––
S
VDS = -10V, ID = -0.30A
-1.0
VDS = -24V, VGS = 0V
µA
-25
VDS = -24V, VGS = 0V, TJ = 125°C
-100
VGS = -20V
nA
100
VGS = 20V
5.1
ID = -0.60A
0.78
nC VDS = -24V
1.7
VGS = -10V, See Fig. 6 and 9 ƒ
–––
VDD = -15V
–––
ID = -0.60A
ns
–––
RG = 6.2Ω
–––
RD = 25Ω, See Fig. 10 ƒ
–––
VGS = 0V
–––
pF
VDS = -25V
–––
ƒ = 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
IS
I SM
VSD
t rr
Q rr
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode) 
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Min. Typ. Max. Units
–––
––– -0.54
–––
–––
-4.8
–––
–––
–––
–––
26
20
-1.2
39
30
A
V
ns
nC
Conditions
MOSFET symbol
showing the
G
integral reverse
p-n junction diode.
TJ = 25°C, IS = -0.60A, VGS = 0V ƒ
TJ = 25°C, IF = -0.60A
di/dt = 100A/µs ƒ
Notes:
 Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
ƒ Pulse width ≤ 300µs; duty cycle ≤ 2%.
‚ ISD ≤ -0.60A, di/dt ≤ 110A/µs, VDD ≤ V(BR)DSS, „ Surface mounted on FR-4 board, t ≤ 5sec.
TJ ≤ 150°C
D
S
IRLML5103
10
10
VGS
- 15V
- 10V
- 7.0V
- 5.5V
- 4.5V
- 4.0V
- 3.5V
BOTTOM - 3.0V
VGS
- 15V
- 10V
- 7.0V
- 5.5V
- 4.5V
- 4.0V
- 3.5V
BOTTOM - 3.0V
TOP
-I D , Drain-to-Source Current (A)
-I D , Drain-to-Source Current (A)
TOP
1
-3.0V
20µs PULSE WIDTH
TJ = 25°C
A
0.1
0.1
1
1
-3.0V
20µs PULSE WIDTH
TJ = 150°C
A
0.1
10
0.1
1
-VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
2.0
R DS(on) , Drain-to-Source On Resistance
(Normalized)
-ID , Drain-to-Source Current (A)
10
TJ = 25°C
TJ = 150°C
1
VDS = -10V
20µs PULSE WIDTH
0.1
3.0
4.0
5.0
6.0
7.0
-VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
10
-VDS , Drain-to-Source Voltage (V)
8.0
A
I D = -0.60A
1.5
1.0
0.5
VGS = -10V
0.0
-60
-40
-20
0
20
40
60
80
A
100 120 140 160
TJ , Junction Temperature (°C)
Fig 4. Normalized On-Resistance
Vs. Temperature
IRLML5103
140
100
-VGS , Gate-to-Source Voltage (V)
120
C, Capacitance (pF)
20
V GS = 0V,
f = 1MHz
C iss = Cgs + C gd , Cds SHORTED
C rss = C gd
Ciss C oss = C ds + C gd
Coss
80
60
Crss
40
20
0
A
1
10
I D = -0.60A
VDS = -24V
VDS = -15V
16
12
8
4
0
0.0
100
-VDS , Drain-to-Source Voltage (V)
1.0
2.0
3.0
4.0
A
5.0
Q G , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
10
10
OPERATION IN THIS AREA LIMITED
BY RDS(on)
-I D , Drain Current (A)
-ISD , Reverse Drain Current (A)
FOR TEST CIRCUIT
SEE FIGURE 9
TJ = 150°C
1
TJ = 25°C
VGS = 0V
0.1
0.4
0.6
0.8
1.0
1.2
1.4
-VSD , Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
A
1.6
100µs
1
1ms
TA = 25°C
TJ = 150°C
Single Pulse
0.1
1
10ms
A
10
-VDS , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
100
IRLML5103
VDS
QG
V GS
-10V
QGS
QGD
RD
D.U.T.
RG
-
+
VG
VDD
-10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Charge
Fig 9a. Basic Gate Charge Waveform
Fig 10a. Switching Time Test Circuit
Current Regulator
Same Type as D.U.T.
VDS
50KΩ
90%
.2µF
12V
.3µF
D.U.T.
+VDS
VGS
10%
VGS
-3mA
IG
tr
td(on)
ID
t d(off)
tf
Current Sampling Resistors
Fig 9b. Gate Charge Test Circuit
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJA )
1000
100
D = 0.50
0.20
0.10
10
0.05
0.02
PDM
0.01
1
0.1
0.00001
t1
SINGLE PULSE
(THERMAL RESPONSE)
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJA + TA
0.0001
0.001
0.01
0.1
1
10
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
100
IRLML5103
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T
ƒ
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
‚
-
-
„
+
**

RG
• dv/dt controlled by RG
• I SD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
VGS*
+
-
*
VDD
* Reverse Polarity for P-Channel
** Use P-Channel Driver for P-Channel Measurements
Driver Gate Drive
P.W.
Period
D=
P.W.
Period
[VGS=10V ] ***
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
[VDD]
Forward Drop
Inductor Curent
Ripple ≤ 5%
*** VGS = 5.0V for Logic Level and 3V Drive Devices
Fig 13. For P-Channel HEXFETS
[ISD]
IRLML5103
Package Outline
SOT-23 Outline
Dimensions are shown in millimeters (inches)
D
-B-
3
E
-A-
LEAD ASSIGNMENTS
1 - GATE
2 - SOURCE
3 - DRAIN
3
3
DIM
H
1
0.20 ( .008 )
2
M
A M
e
e1
θ
A
INCHES
MILLIMETERS
A
MIN
.032
MAX
.044
MIN
0.82
MAX
1.11
A1
.001
.004
0.02
0.10
B
.015
.021
0.38
0.54
C
.004
.006
0.10
0.15
D
.105
.120
2.67
3.05
e
.0750 BASIC
1.90 BASIC
e1
.0375 BASIC
0.95 BASIC
E
.047
.055
1.20
1.40
H
.083
.098
2.10
2.50
L
.005
.010
0.13
0.25
θ
0°
8°
0°
8°
MINIMUM RECOMMENDED FOOTPRINT
-CB
A1
3X
0.10 (.004)
M
0.80 ( .031 )
3X
0.008 (.003)
C AS B S
NOTES:
1. DIMENSIONING & TOLERANCING PER ANSI Y14.5M-1982.
2. CONTROLLING DIMENSION : INCH.
3 DIMENSIONS DO NOT INCLUDE MOLD FLASH.
L
3X
C
3X
0.90
( .035 )
3X
2.00
( .079 )
0.95 ( .037 )
2X
IRLML5103
Part Marking Information
SOT-23
Notes : T his part marking information applies to devices produced before 02/26/2001
WW = (1-26) IF PRECEDED BY LAS T DIGIT OF CALENDAR YEAR
EXAMPLE: T HIS IS AN IRLML6302
PART NUMBER
DATE
CODE
PART NUMBER CODE REFERENCE:
1A =
1B =
1C =
1D =
1E =
1F =
1G =
1H =
IRLML2402
IRLML2803
IRLML6302
IRLML5103
IRLML6402
IRLML6401
IRLML2502
IRLML5203
YEAR
Y
2001
2002
2003
1994
1995
1996
1997
1998
1999
2000
1
2
3
4
5
6
7
8
9
0
WORK
WEEK
W
01
02
03
04
A
B
C
D
24
25
26
X
Y
Z
WW = (27-52) IF PRECEDED BY A LETT ER
DAT E CODE EXAMPLES:
YWW = 9503 = 5C
YWW = 9532 = EF
YEAR
Y
2001
2002
2003
1994
1995
1996
1997
1998
1999
2000
A
B
C
D
E
F
G
H
J
K
WORK
WEEK
W
27
28
29
30
A
B
C
D
50
51
52
X
Y
Z
Notes : T his part marking information applies to devices produced after 02/26/2001
W = (1-26) IF PRECE DED BY LAS T DIGIT OF CALENDAR YEAR
PART NUMBER
Y = YEAR
W = WEEK
LOT
CODE
PART NUMBER CODE REFERENCE:
A=
B=
C=
D=
E=
F=
G=
H=
IRLML2402
IRLML2803
IRLML6302
IRLML5103
IRLML6402
IRLML6401
IRLML2502
IRLML5203
YEAR
Y
2001
2002
2003
1994
1995
1996
1997
1998
1999
2000
1
2
3
4
5
6
7
8
9
0
WORK
WEEK
W
01
02
03
04
A
B
C
D
24
25
26
X
Y
Z
W = (27-52) IF PRECEDED BY A LETTER
YEAR
Y
2001
2002
2003
1994
1995
1996
1997
1998
1999
2000
A
B
C
D
E
F
G
H
J
K
WORK
WEEK
W
27
28
29
30
A
B
C
D
50
51
52
X
Y
Z
IRLML5103
Tape & Reel Information
SOT-23
Dimensions are shown in millimeters (inches)
2.05 ( .080 )
1.95 ( .077 )
1.6 ( .062 )
1.5 ( .060 )
4.1 ( .161 )
3.9 ( .154 )
TR
FEED DIRECTION
1.85 ( .072 )
1.65 ( .065 )
3.55 ( .139 )
3.45 ( .136 )
4.1 ( .161 )
3.9 ( .154 )
1.32 ( .051 )
1.12 ( .045 )
8.3 ( .326 )
7.9 ( .312 )
0.35 ( .013 )
0.25 ( .010 )
1.1 ( .043 )
0.9 ( .036 )
178.00
( 7.008 )
MAX.
9.90 ( .390 )
8.40 ( .331 )
NOTES:
1. CONTROLLING DIMENSION : MILLIMETER.
2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 04/03