IS41C16100 IS41LV16100 ISSI ® 1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE April 2003 FEATURES DESCRIPTION • TTL compatible inputs and outputs; tristate I/O The ISSI IS41C16100 and IS41LV16100 are 1,048,576 x 16-bit high-performance CMOS Dynamic Random Access Memories. These devices offer an accelerated cycle access called EDO Page Mode. EDO Page Mode allows 1,024 random accesses within a single row with access cycle time as short as 20 ns per 16-bit word. The Byte Write control, of upper and lower byte, makes the IS41C16100 ideal for use in 16-bit and 32-bit wide data bus systems. • Refresh Interval: — Auto refresh Mode: 1,024 cycles /16 ms — RAS-Only, CAS-before-RAS (CBR), and Hidden — Self refresh Mode - 1,024 cycles / 128ms • JEDEC standard pinout • Single power supply: — 5V ± 10% (IS41C16100) — 3.3V ± 10% (IS41LV16100) These features make the IS41C16100and IS41LV16100 ideally suited for high-bandwidth graphics, digital signal processing, highperformance computing systems, and peripheral applications. • Byte Write and Byte Read operation via two CAS The IS41C16100 and IS41LV16100 are packaged in a 42-pin 400mil SOJ and 400-mil 50- (44-) pin TSOP (Type II). The lead-free 400mil 50- (44-) option is available too. • Industrail Temperature Range -40oC to 85oC KEY TIMING PARAMETERS PIN CONFIGURATIONS Parameter -50 -60 Unit 50(44)-Pin TSOP (Type II) Max. RAS Access Time (tRAC) 50 60 ns Max. CAS Access Time (tCAC) 13 15 ns Max. Column Address Access Time (tAA) 25 30 ns Min. EDO Page Mode Cycle Time (tPC) 20 25 ns Min. Read/Write Cycle Time (tRC) 84 104 ns 42-Pin SOJ VCC 1 44 GND VCC 1 42 GND I/O0 2 43 I/O15 I/O0 2 41 I/O15 I/O1 3 42 I/O14 I/O1 3 40 I/O14 I/O2 4 41 I/O13 I/O2 4 39 I/O13 I/O3 5 40 I/O12 VCC 6 39 GND I/O3 5 38 I/O12 I/O4 7 38 I/O11 VCC 6 37 GND I/O5 8 37 I/O10 I/O4 7 36 I/O11 I/O6 9 36 I/O9 I/O5 8 35 I/O10 I/O7 10 35 I/O8 I/O6 9 34 I/O9 NC 11 34 NC I/O7 10 33 I/O8 NC 11 32 NC NC 12 33 NC NC 12 31 LCAS PIN DESCRIPTIONS A0-A9 Address Inputs I/O0-15 Data Inputs/Outputs WE Write Enable OE Output Enable RAS Row Address Strobe NC 13 32 LCAS WE 13 30 UCAS WE 14 31 UCAS RAS 14 29 OE RAS 15 30 OE NC 16 29 A9 NC 15 28 A9 NC 17 28 A8 NC 16 27 A8 UCAS Upper Column Address Strobe A0 18 27 A7 A0 17 26 A7 26 A6 18 25 A6 Lower Column Address Strobe 19 A1 LCAS A1 A2 20 25 A5 A2 19 24 A5 Vcc Power A3 21 24 A4 A3 20 23 A4 VCC 22 23 GND VCC 21 22 GND GND Ground NC No Connection Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. IIntegrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. I 04/16/03 1 ISSI IS41C16100 IS41LV16100 ® FUNCTIONAL BLOCK DIAGRAM OE WE LCAS UCAS CAS CLOCK GENERATOR WE CONTROL LOGICS CAS WE OE CONTROL LOGIC OE DATA I/O BUS COLUMN DECODERS SENSE AMPLIFIERS ADDRESS BUFFERS A0-A9 2 ROW DECODER REFRESH COUNTER MEMORY ARRAY 1,048,576 x 16 DATA I/O BUFFERS RAS CLOCK GENERATOR RAS RAS I/O0-I/O15 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. I 04/16/03 ISSI IS41C16100 IS41LV16100 ® TRUTH TABLE Function RAS LCAS UCAS WE OE Address tR/tC Standby H H H X X X High-Z Read: Word L L L H L ROW/COL DOUT Read: Lower Byte L L H H L ROW/COL Lower Byte, DOUT Upper Byte, High-Z Read: Upper Byte L H L H L ROW/COL Lower Byte, High-Z Upper Byte, DOUT Write: Word (Early Write) L L L L X ROW/COL DIN Write: Lower Byte (Early Write) L L H L X ROW/COL Lower Byte, DIN Upper Byte, High-Z Write: Upper Byte (Early Write) L H L L X ROW/COL Lower Byte, High-Z Upper Byte, DIN Read-Write(1,2) L L L H→L L→H ROW/COL DOUT, DIN I/O EDO Page-Mode Read(2) 1st Cycle: 2nd Cycle: Any Cycle: L L L H→L H→L L→H H→L H→L L→H H H H L L L ROW/COL NA/COL NA/NA DOUT DOUT DOUT EDO Page-Mode Write(1) 1st Cycle: 2nd Cycle: L L H→L H→L H→L H→L L L X X ROW/COL NA/COL DIN DIN EDO Page-Mode(1,2) Read-Write 1st Cycle: 2nd Cycle: L L H→L H→L H→L H→L H→L H→L L→H L→H ROW/COL NA/COL DOUT, DIN DOUT, DIN Hidden Refresh Read(2) Write(1,3) L→H→L L→H→L L L L L H L L X ROW/COL ROW/COL DOUT DOUT L H H X X ROW/NA High-Z H→L L L X X X High-Z RAS-Only Refresh CBR Refresh(4) Notes: 1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active). 2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active). 3. EARLY WRITE only. 4. At least one of the two CAS signals must be active (LCAS or UCAS). Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. I 04/16/03 3 ISSI IS41C16100 IS41LV16100 Functional Description The IS41C16100 and IS41LV16100 is a CMOS DRAM optimized for high-speed bandwidth, low power applications. During READ or WRITE cycles, each bit is uniquely addressed through the 16 address bits. These are entered ten bits (A0-A9) at time. The row address is latched by the Row Address Strobe (RAS). The column address is latched by the Column Address Strobe (CAS). RAS is used to latch the first nine bits and CAS is used to latch the latter nine bits. The IS41C16100 and IS41LV16100 has two CAS controls, LCAS and UCAS. The LCAS and UCAS inputs internally generates a CAS signal functioning in an identical manner to the single CAS input on the other 1M x 16 DRAMs. The key difference is that each CAS controls its corresponding I/O tristate logic (in conjunction with OE and WE and RAS). LCAS controls I/O0 through I/O7 and UCAS controls I/O8 through I/O15. The IS41C16100 and IS41LV16100 CAS function is determined by the first CAS (LCAS or UCAS) transitioning LOW and the last transitioning back HIGH. The two CAS controls give the IS41C16100 and IS41LV16100 both BYTE READ and BYTE WRITE cycle capabilities. Memory Cycle A memory cycle is initiated by bring RAS LOW and it is terminated by returning both RAS and CAS HIGH. To ensures proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum tRAS time has expired. A new cycle must not be initiated until the minimum precharge time tRP, tCP has elapsed. Read Cycle A read cycle is initiated by the falling edge of CAS or OE, whichever occurs last, while holding WE HIGH. The column address must be held for a minimum time specified by tAR. Data Out becomes valid only when tRAC, tAA, tCAC and tOEA are all satisfied. As a result, the access time is dependent on the timing relationships between these parameters. Write Cycle A write cycle is initiated by the falling edge of CAS and WE, whichever occurs last. The input data must be valid at or before the falling edge of CAS or WE, whichever occurs first. Auto Refresh Cycle To retain data, 1,024 refresh cycles are required in each 16 ms period. There are two ways to refresh the memory. 1. By clocking each of the 1,024 row addresses (A0 through A9) with RAS at least once every 128 ms. Any read, write, readmodify-write or RAS-only cycle refreshes the addressed row. 2. Using a CAS-before-RAS refresh cycle. CAS-beforeRAS refresh is activated by the falling edge of RAS, 4 ® while holding CAS LOW. In CAS-before-RAS refresh cycle, an internal 9-bit counter provides the row addresses and the external address inputs are ignored. CAS-before-RAS is a refresh-only mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle. Self Refresh Cycle The Self Refresh allows the user a dynamic refresh, data retention mode at the extended refresh period of 128 ms. i.e., 125 µs per row when using distributed CBR refreshes. The feature also allows the user the choice of a fully static, low power data retention mode. The optional Self Refresh feature is initiated by performing a CBR Refresh cycle and holding RAS LOW for the specified tRAS. The Self Refresh mode is terminated by driving RAS HIGH for a minimum time of tRP. This delay allows for the completion of any internal refresh cycles that may be in process at the time of the RAS LOW-to-HIGH transition. If the DRAM controller uses a distributed refresh sequence, a burst refresh is not required upon exiting Self Refresh. However, if the DRAM controller utilizes a RAS-only or burst refresh sequence, all 1,024 rows must be refreshed within the average internal refresh rate, prior to the resumption of normal operation. Extended Data Out Page Mode EDO page mode operation permits all 1,024 columns within a selected row to be randomly accessed at a high data rate. In EDO page mode read cycle, the data-out is held to the next CAS cycle’s falling edge, instead of the rising edge. For this reason, the valid data output time in EDO page mode is extended compared with the fast page mode. In the fast page mode, the valid data output time becomes shorter as the CAS cycle time becomes shorter. Therefore, in EDO page mode, the timing margin in read cycle is larger than that of the fast page mode even if the CAS cycle time becomes shorter. In EDO page mode, due to the extended data function, the CAS cycle time can be shorter than in the fast page mode if the timing margin is the same. The EDO page mode allows both read and write operations during one RAS cycle, but the performance is equivalent to that of the fast page mode in that case. Power-On After application of the VCC supply, an initial pause of 200 µs is required followed by a minimum of eight initialization cycles (any combination of cycles containing a RAS signal). During power-on, it is recommended that RAS track with VCC or be held at a valid VIH to avoid current surges. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. I 04/16/03 ISSI IS41C16100 IS41LV16100 ® ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameters Rating Unit VT Voltage on Any Pin Relative to GND 5V 3.3V –1.0 to +7.0 –0.5 to +4.6 V VCC Supply Voltage 5V 3.3V –1.0 to +7.0 –0.5 to +4.6 V IOUT Output Current 50 mA PD Power Dissipation 1 W TA Commercial Operation Temperature Industrial Operationg Temperature 0 to +70 -40 to +85 °C °C TSTG Storage Temperature –55 to +125 °C Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.) Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 5V 3.3V 4.5 3.0 5.0 3.3 5.5 3.6 V VIH Input High Voltage 5V 3.3V 2.4 2.0 — — VCC + 1.0 VCC + 0.3 V VIL Input Low Voltage 5V 3.3V –1.0 –0.3 — — 0.8 0.8 V TA Commercial Ambient Temperature Industrial Ambient Temperature 0 –40 — — 70 85 °C °C CAPACITANCE(1,2) Symbol Parameter Max. Unit CIN1 Input Capacitance: A0-A9 5 pF CIN2 Input Capacitance: RAS, UCAS, LCAS, WE, OE 7 pF CIO Data Input/Output Capacitance: I/O0-I/O15 7 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. I 04/16/03 5 ISSI IS41C16100 IS41LV16100 ® ELECTRICAL CHARACTERISTICS(1) (Recommended Operating Conditions unless otherwise noted.) Symbol Parameter Test Condition IIL Input Leakage Current IIO Speed Min. Max. Unit Any input 0V ≤ VIN ≤ Vcc Other inputs not under test = 0V –5 5 µA Output Leakage Current Output is disabled (Hi-Z) 0V ≤ VOUT ≤ Vcc –5 5 µA VOH Output High Voltage Level IOH = –5.0 mA (5V) IOH = –2.0 mA (3.3V) 2.4 — V VOL Output Low Voltage Level IOL = 4.2 mA (5V) IOL = 2.0 mA (3.3V) — 0.4 V ICC1 Standby Current: TTL RAS, LCAS, UCAS ≥ VIH Commerical — — — — 3 3 4 4 mA 5V 3.3V Industrial 5V 3.3V mA ICC2 Standby Current: CMOS RAS, LCAS, UCAS ≥ VCC – 0.2V 5V 3.3V — — 2 2 mA ICC3 Operating Current: Random Read/Write(2,3,4) Average Power Supply Current RAS, LCAS, UCAS, Address Cycling, tRC = tRC (min.) -50 -60 — — 160 145 mA ICC4 Operating Current: EDO Page Mode(2,3,4) Average Power Supply Current RAS = VIL, LCAS, UCAS, Cycling tPC = tPC (min.) -50 -60 — — 90 80 mA ICC5 Refresh Current: RAS-Only(2,3) Average Power Supply Current RAS Cycling, LCAS, UCAS ≥ VIH tRC = tRC (min.) -50 -60 — — 160 145 mA ICC6 Refresh Current: CBR(2,3,5) Average Power Supply Current RAS, LCAS, UCAS Cycling tRC = tRC (min.) -50 -60 — — 160 145 mA Notes: 1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded. 2. Dependent on cycle rates. 3. Specified values are obtained with minimum cycle time and the output open. 4. Column-address is changed once each EDO page cycle. 5. Enables on-chip refresh and address counters. 6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. I 04/16/03 ISSI IS41C16100 IS41LV16100 ® AC CHARACTERISTICS(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) Symbol Parameter Min. -50 Max. Min. -60 Max. Units t RC Random READ or WRITE Cycle Time 84 — 104 — ns t RAC Access Time from RAS — 50 — 60 ns t CAC Access Time from CAS — 13 — 15 ns (6, 7) (6, 8, 15) (6) tAA Access Time from Column-Address — 25 — 30 ns tRAS RAS Pulse Width 50 10K 60 10K ns t RP RAS Precharge Time 30 — 40 — ns tCAS CAS Pulse Width 8 10K 10 10K ns t CP CAS Precharge Time 9 — 9 — ns t CSH CAS Hold Time 38 — 40 — ns t RCD RAS to CAS Delay Time 12 37 14 45 ns tASR Row-Address Setup Time 0 — 0 — ns t RAH Row-Address Hold Time 8 — 10 — ns 0 — 0 — ns tASC (26) (9, 25) (21) (10, 20) Column-Address Setup Time (20) (20) t CAH Column-Address Hold Time 8 — 10 — ns t AR 30 — 40 — ns t RAD Column-Address Hold Time (referenced to RAS) RAS to Column-Address Delay Time(11) 10 25 12 30 ns t RAL Column-Address to RAS Lead Time 25 — 30 — ns t RPC RAS to CAS Precharge Time 5 — 5 — ns t RSH RAS Hold Time 8 — 10 — ns t RHCP RAS Hold Time from CAS Precharge 37 — 37 — ns tCLZ CAS to Output in Low-Z 0 — 0 — ns t CRP CAS to RAS Precharge Time 5 — 5 — ns 3 15 3 15 ns — 13 — 15 ns tOD (27) Output Disable Time (15, 29) (21) (19, 28, 29) (15, 16) tOE Output Enable Time tOED Output Enable Data Delay (Write) 20 — 20 — ns tOEHC OE HIGH Hold Time from CAS HIGH 5 — 5 — ns tOEP OE HIGH Pulse Width 10 — 10 — ns tOES OE LOW to CAS HIGH Setup Time 5 — 5 — ns (17, 20) t RCS Read Command Setup Time 0 — 0 — ns t RRH Read Command Hold Time (referenced to RAS)(12) Read Command Hold Time (referenced to CAS)(12, 17, 21) Write Command Hold Time(17, 27) 0 — 0 — ns 0 — 0 — ns 8 — 10 — ns 40 — 50 — ns t RCH t WCH t WCR Write Command Hold Time (referenced to RAS)(17) Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. I 04/16/03 7 ISSI IS41C16100 IS41LV16100 ® AC CHARACTERISTICS (Continued)(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) Symbol Min. (17) -50 Max. Min. -60 Max. Units tWP Write Command Pulse Width 8 — 10 — ns tWPZ WE Pulse Widths to Disable Outputs 10 — 10 — ns t RWL Write Command to RAS Lead Time(17) 13 — 15 — ns t CWL Write Command to CAS Lead Time 8 — 10 — ns tWCS Write Command Setup Time (14, 17, 20) 0 — 0 — ns t DHR Data-in Hold Time (referenced to RAS) 39 — 39 — ns t ACH Column-Address Setup Time to CAS Precharge during WRITE Cycle 15 — 15 — ns tOEH OE Hold Time from WE during READ-MODIFY-WRITE cycle(18) 8 — 10 — ns t DS Data-In Setup Time(15, 22) 0 — 0 — ns t DH Data-In Hold Time(15, 22) 8 — 10 — ns t RWC READ-MODIFY-WRITE Cycle Time 108 — 133 — ns t RWD RAS to WE Delay Time during READ-MODIFY-WRITE Cycle(14) 64 — 77 — ns t CWD CAS to WE Delay Time(14, 20) 26 — 32 — ns tAWD Column-Address to WE Delay Time(14) 39 — 47 — ns t PC EDO Page Mode READ or WRITE Cycle Time(24) 20 — 25 — ns t RASP RAS Pulse Width in EDO Page Mode 50 100K 60 100K ns t CPA Access Time from CAS Precharge — 30 — 35 ns t PRWC EDO Page Mode READ-WRITE Cycle Time(24) 56 — 68 — ns t COH Data Output Hold after CAS LOW 5 — 5 — ns tOFF Output Buffer Turn-Off Delay from CAS or RAS(13,15,19, 29) 1.6 12 1.6 15 ns tWHZ Output Disable Delay from WE 3 10 3 10 ns t CLCH Last CAS going LOW to First CAS returning HIGH(23) 10 — 10 — ns t CSR CAS Setup Time (CBR REFRESH)(30, 20) 5 — 5 — ns t CHR CAS Hold Time (CBR REFRESH) 8 — 10 — ns t ORD OE Setup Time prior to RAS during HIDDEN REFRESH Cycle 0 — 0 — ns tREF Auto Refresh Period (1,024 Cycles) — 16 — 16 ms tREF Self Refresh Period (1,024 Cycles) — 128 — 128 ms 1 50 1 50 ns tT 8 Parameter (17, 21) (15) Transition Time (Rise or Fall) (2, 3) (30, 21) Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. I 04/16/03 IS41C16100 IS41LV16100 ISSI ® AC TEST CONDITIONS Output load: Two TTL Loads and 50 pF (Vcc = 5.0V ±10%) One TTL Load and 50 pF (Vcc = 3.3V ±10%) Input timing reference levels: VIH = 2.4V, VIL = 0.8V (Vcc = 5.0V ±10%); VIH = 2.0V, VIL = 0.8V (Vcc = 3.3V ±10%) Output timing reference levels: VOH = 2.0V, VOL = 0.8V (Vcc = 5V ±10%, 3.3V ±10%) Notes: 1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded. 2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH and VIL (or between VIL and VIH) and assume to be 1 ns for all inputs. 3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 4. If CAS and RAS = VIH, data output is High-Z. 5. If CAS = VIL, data output may contain data from the last valid READ cycle. 6. Measured with a load equivalent to one TTL gate and 50 pF. 7. Assumes that tRCD - tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. 8. Assumes that tRCD • tRCD (MAX). 9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the data output buffer, CAS and RAS must be pulsed for tCP. 10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC. 11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD is greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA. 12. Either tRCH or tRRH must be satisfied for a READ cycle. 13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. 14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS • tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD • tRWD (MIN), tAWD • tAWD (MIN) and tCWD • tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to VIH) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle. 15. Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS. 16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE WRITE or READ-MODIFY-WRITE is not possible. 17. Write command is defined as WE going low. 18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW and OE is taken back to LOW after tOEH is met. 19. The I/Os are in open during READ cycles once tOD or tOFF occur. 20. The first χCAS edge to transition LOW. 21. The last χCAS edge to transition HIGH. 22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READMODIFY-WRITE cycles. 23. Last falling χCAS edge to first rising χCAS edge. 24. Last rising χCAS edge to next cycle’s last rising χCAS edge. 25. Last rising χCAS edge to first falling χCAS edge. 26. Each χCAS must meet minimum pulse width. 27. Last χCAS to go LOW. 28. I/Os controlled, regardless UCAS and LCAS. 29. The 3 ns minimum is a parameter guaranteed by design. 30. Enables on-chip refresh and address counters. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. I 04/16/03 9 ISSI IS41C16100 IS41LV16100 ® READ CYCLE tRC tRAS tRP RAS tCSH tCRP tRSH tCAS tCLCH tRCD tRRH UCAS/LCAS tAR tRAD tRAH tASR ADDRESS tRAL tCAH tASC Row Column Row tRCS tRCH WE tAA tRAC tCAC tCLC I/O tOFF(1) Open Open Valid Data tOE tOD OE tOES Undefined Don’t Care Note: 1. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last. 10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. I 04/16/03 ISSI IS41C16100 IS41LV16100 ® EARLY WRITE CYCLE (OE = DON'T CARE) tRC tRAS tRP RAS tCSH tCRP tRSH tCAS tCLCH tRCD UCAS/LCAS tAR tRAD tRAH tASR ADDRESS tRAL tCAH tACH tASC Row Column Row tCWL tRWL tWCR tWCS tWCH tWP WE tDHR tDS I/O tDH Valid Data Don’t Care Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. I 04/16/03 11 ISSI IS41C16100 IS41LV16100 ® READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles) tRWC tRAS tRP RAS tCSH tCRP tRSH tCAS tCLCH tRCD UCAS/LCAS tAR tRAD tASR tRAH tRAL tCAH tASC tACH ADDRESS Row Column Row tRWD tCWL tRWL tCWD tRCS tAWD tWP WE tAA tRAC tCAC tCLZ I/O tDS Open Valid DOUT tOE tOD tDH Valid DIN Open tOEH OE Undefined Don’t Care 12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. I 04/16/03 ISSI IS41C16100 IS41LV16100 ® EDO-PAGE-MODE READ CYCLE tRASP tRP RAS tCSH tCRP tPC(1) tCAS, tCLCH tRCD tCAS, tCLCH tCP tCP tRSH tCAS, tCLCH tCP UCAS/LCAS tAR tRAD tASR ADDRESS tASC tCAH tASC Row Column tRAL tCAH tCAH tASC Column Column Row tRAH tRRH tRCS tRCH WE tAA tRAC tCAC tCLZ I/O Open tAA tCPA tCAC tCOH tCAC tCLZ Valid Data tOE tAA tCPA tOFF Valid Data tOEHC tOES Valid Data Open tOE tOD tOES tOD OE tOEP Undefined Don’t Care Note: 1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both measurements must meet the tPC specifications. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. I 04/16/03 13 ISSI IS41C16100 IS41LV16100 ® EDO-PAGE-MODE EARLY-WRITE CYCLE tRASP tRP tRHCP RAS tCSH tCRP tPC tCAS, tCLCH tRCD tCP tCAS, tCLCH tCP tRSH tCAS, tCLCH tCP UCAS/LCAS tAR tACH tCAH tASC tRAD tASR ADDRESS tASC Row Column tRAH tACH tRAL tCAH tACH tCAH tASC Column tCWL tWCS Column tCWL tWCS tWCH tCWL tWCS tWCH tWCH tWP tWP Row tWP WE tWCR tDHR tRWL tDS tDS tDH I/O Valid Data tDS tDH Valid Data tDH Valid Data OE Don’t Care 14 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. I 04/16/03 ISSI IS41C16100 IS41LV16100 ® EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY WRITE Cycles) tRASP tRP RAS tCSH tCRP tCAS, tCLCH tRCD tCP tPC / tPRWC(1) tCAS, tCLCH tRSH tCAS, tCLCH tCP tCP UCAS/LCAS tASR tRAH ADDRESS tAR tRAD tASC tCAH Row tASC tCAH Column tRWD tRCS tRAL tCAH tASC Column tCWL tWP Column tRWL tCWL tWP tCWL tWP tAWD tCWD Row tAWD tCWD tAWD tCWD WE tAA tAA tCPA tDH tRAC tDS tDS tCAC tCLZ I/O Open tCAC tCLZ DOUT DIN tDH tDS tCAC tCLZ DOUT tOD tOE tAA tCPA tDH DIN DOUT tOD tOE Open DIN tOD tOE tOEH OE Undefined Don’t Care Note: 1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both measurements must meet the tPC specifications. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. I 04/16/03 15 ISSI IS41C16100 IS41LV16100 ® EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Psuedo READ-MODIFY WRITE) tRASP tRP RAS tCSH tPC tPC tCRP tCAS tRCD tCAS tCP tRSH tCAS tCP tCP UCAS/LCAS tASR tRAH ADDRESS tAR tRAD tASC Row tCAH tASC tCAH Column (A) tASC Column (B) tRCS tACH tRAL tCAH Column (N) Row tRCH tWCS tWCH WE tAA tRAC tCAC I/O Open tCPA tCAC tCOH Valid Data (A) tAA tWHZ tDS Valid Data (B) tDH DIN Open tOE OE Don’t Care 16 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. I 04/16/03 ISSI IS41C16100 IS41LV16100 ® AC WAVEFORMS READ CYCLE (With WE-Controlled Disable) RAS tCSH tCRP tRCD tCP tCAS UCAS/LCAS tAR tRAD tASR ADDRESS tRAH tCAH tASC Row tASC Column Column tRCS tRCH tRCS WE tAA tRAC tCAC tCLZ Open I/O tWHZ tCLZ Valid Data Open tOE tOD OE Undefined Don’t Care RAS RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE) tRC tRAS tRP RAS tCRP tRPC UCAS/LCAS tASR ADDRESS I/O tRAH Row Row Open Don’t Care Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. I 04/16/03 17 ISSI IS41C16100 IS41LV16100 ® CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE) tRP tRAS tRP tRAS RAS tCHR tRPC tCP tCHR tRPC tCSR tCSR UCAS/LCAS Open I/O HIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW) tRAS tRP tRAS RAS tCRP tRCD tASR tRAD tRAH tASC tRSH tCHR UCAS/LCAS tAR ADDRESS Row tRAL tCAH Column tAA tRAC tOFF(2) tCAC tCLZ I/O Open Valid Data tOE Open tOD tORD OE Undefined Don’t Care Notes: 1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH. 2. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last. 18 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. I 04/16/03 ISSI IS41C16100 IS41LV16100 ® ORDERING INFORMATION : 5V Commercial Range: 0°°C to 70°°C Speed (ns) Order Part No. Package 50 IS41C16100-50K IS41C16100-50T 400-mil SOJ 400-mil TSOP (Type II) 60 IS41C16100-60K IS41C16100-60T 400-mil SOJ 400-mil TSOP (Type II) Industrial Range: -40°°C to 85°°C Speed (ns) Order Part No. Package 50 IS41C16100-50KI IS41C16100-50TI 400-mil SOJ 400-mil TSOP (Type II) 60 IS41C16100-60KI IS41C16100-60TI 400-mil SOJ 400-mil TSOP (Type II) Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. I 04/16/03 19 ISSI IS41C16100 IS41LV16100 ® ORDERING INFORMATION : 3.3V Commercial Range: 0°°C to 70°°C Speed (ns) Order Part No. Package 50 IS41LV16100-50K IS41LV16100-50T IS41LV16100-50TL 400-mil SOJ 400-mil TSOP (Type II) 400-mil TSOP (Type II), Lead-free 60 IS41LV16100-60K IS41LV16100-60T IS41LV16100-60TL 400-mil SOJ 400-mil TSOP (Type II) 400-mil TSOP (Type II), Lead-free Industrial Range: -40°°C to 85°°C Speed (ns) 20 Order Part No. Package 50 IS41LV16100-50KI IS41LV16100-50TI IS41LV16100-50TLI 400-mil SOJ 400-mil TSOP (Type II) 400-mil TSOP (Type II), Lead-free 60 IS41LV16100-60KI IS41LV16100-60TI IS41LV16100-60TLI 400-mil SOJ 400-mil TSOP (Type II) 400-mil TSOP (Type II), Lead-free Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. I 04/16/03