IS41C44002C IS41LV44002C 4Mx4 16Mb DRAM WITH EDO PAGE MODE ADVANCED INFORMATION AUGUST 2010 FEATURES DESCRIPTION • Extended Data-Out (EDO) Page Mode access cycle The ISSI IS41C/41LV44002C is 4,194,304 x 4-bit high-performance CMOS Dynamic Random Access Memory. These devices offer an accelerated cycle access called EDO Page Mode. EDO Page Mode allows 2,048 random accesses within a single row with access cycle time as short as 20 ns per 4-bit word. • TTL compatible inputs and outputs • Refresh Interval: – 2,048 cycles/32 ms • Refresh Mode: RAS-Only, CAS-before-RAS (CBR), and Hidden • Single power supply: 5V ± 10% (IS41C44002C) 3.3V ± 10% (IS41LV44002C) These features make the IS41C/41LV44002C ideally suited for high-bandwidth graphics, digital signal processing, high-performance computing systems, and peripheral applications. The IS41C/41LV44002C is packaged in a 24/26-pin 300-mil TSOP2 with JEDEC standard pinout. • Byte Write and Byte Read operation via two CAS • Industrial Temperature Range: -40°C to +85°C • RoHS compliant PIN CONFIGURATION: 24/26-pin TSOP2 VDD 1 24 GND I/O0 2 23 I/O3 I/O1 3 22 I/O2 WE 4 21 CAS RAS 5 20 OE NC 6 19 A9 A10 7 18 A8 A0 8 17 A7 A1 9 16 A6 A2 10 15 A5 A3 11 14 A4 VDD 12 13 GND KEY TIMING PARAMETERS Parameter RAS Access Time (trac) CAS Access Time (tcac) Column Address Access Time (taa) EDO Page Mode Cycle Time (tpc) Read/Write Cycle Time (trc) -50 50 13 25 20 84 Unit ns ns ns ns ns PIN DESCRIPTIONS A0-A10 I/O0-3 WE OE RAS CAS Vdd GND NC Address Inputs Data Inputs/Outputs Write Enable Output Enable Row Address Strobe Column Address Strobe Power Ground No Connection Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00B 08/09/2010 1 IS41C44002C IS41LV44002C FUNCTIONAL BLOCK DIAGRAM OE WE CAS CAS CONTROL LOGIC WE CONTROL LOGICS CAS WE OE CONTROL LOGIC OE DATA I/O BUS COLUMN DECODERS SENSE AMPLIFIERS A0-A10 ADDRESS BUFFERS ROW DECODER REFRESH COUNTER DATA I/O BUFFERS RAS CLOCK GENERATOR RAS RAS MEMORY ARRAY 4,194,304 x 4 I/O0-I/O3 TRUTH TABLE Function Standby Read Write: Word (Early Write) Read-Write EDO Page-Mode Read EDO Page-Mode Write EDO Page-Mode Read-Write Hidden Refresh RAS-Only Refresh CBR Refresh 1st Cycle: 2nd Cycle: 1st Cycle: 2nd Cycle: 1st Cycle: 2nd Cycle: Read Write(1) RAS H L L L L L L L L L L→H→L L→H→L L H→L CAS H L L L H→L H→L H→L H→L H→L H→L L L H L WE X H L H→L H H L L H→L H→L H L X X OE X L X L→H L L X X L→H L→H L X X X Address tr/tc X ROW/COL ROW/COL ROW/COL ROW/COL NA/COL ROW/COL NA/COL ROW/COL NA/COL ROW/COL ROW/COL ROW/NA X I/O High-Z Dout Din Dout, Din Dout Dout Din Din Dout, Din Dout, Din Dout Dout High-Z High-Z Note: 1. EARLY WRITE only. 2 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00B 08/09/2010 IS41C44002C IS41LV44002C Functional Description Auto Refresh Cycle The IS41C/41LV44002C is a CMOS DRAMs optimized for high-speed bandwidth, low power applications. During READ or WRITE cycles, each bit is uniquely addressed through the 11 address bits. These are entered 11 bits (A0-A10) at a time for the 2K refresh device. The row address is latched by the Row Address Strobe (RAS). The column address is latched by the Column Address Strobe (CAS). RAS is used to latch the first nine bits and CAS is used the latter ten bits. To retain data, 2,048 refresh cycles are required in each 32 ms period. There are two ways to refresh the memory: Memory Cycle A memory cycle is initiated by bringing RAS LOW and it is terminated by returning both RAS and CAS HIGH. To ensures proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum tras time has expired. A new cycle must not be initiated until the minimum precharge time trp, tcp has elapsed. Read Cycle A read cycle is initiated by the falling edge of CAS or OE, whichever occurs last, while holding WE HIGH. The column address must be held for a minimum time specified by tar. Data Out becomes valid only when trac, taa, tcac and toea are all satisfied. As a result, the access time is dependent on the timing relationships between these parameters. 1.By clocking each of the 2,048 row addresses (A0 through A10) with RAS at least once every 32 ms. Any read, write, read-modify-write or RAS-only cycle refreshes the addressed row. 2. Using a CAS-before-RAS refresh cycle. CAS-before-RAS refresh is activated by the falling edge of RAS, while holding CAS LOW. In CAS-before-RAS refresh cycle, an internal 9-bit counter provides the row addresses and the external address inputs are ignored. CAS-before-RAS is a refresh-only mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle. Power-On After application of the Vdd supply, an initial pause of 200 µs is required followed by a minimum of eight initialization cycles (any combination of cycles containing a RAS signal). During power-on, it is recommended that RAS track with Vdd or be held at a valid Vih to avoid current surges. Write Cycle A write cycle is initiated by the falling edge of CAS and WE, whichever occurs last. The input data must be valid at or before the falling edge of CAS or WE, whichever occurs last. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00B 08/09/2010 3 IS41C44002C IS41LV44002C ABSOLUTE MAXIMUM RATINGS(1) Symbol Vt Vdd Iout Pd Ta Tstg Parameters Voltage on Any Pin Relative to GND 5V 3.3V Supply Voltage 5V 3.3V Output Current Power Dissipation Operating Temperature Storage Temperature Rating –1.0 to +7.0 –0.5 to +4.6 –1.0 to +7.0 –0.5 to +4.6 50 1 -40 to +85 –55 to +125 Unit V V mA W °C °C Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.) Symbol Parameter Test Condition Min. Typ. Vdd Supply Voltage 5V 4.5 5.0 3.3V 3.0 3.3 Vih Input High Voltage 5V 2.0 — 3.3V 2.0 — Vil Input Low Voltage 5V –1.0 — 3.3V –0.3 — Iil Input Leakage Current Any input 0V ≤ Vin ≤ Vdd –5 Other inputs not under test = 0V Max. Unit 5.5 V 3.6 Vdd + 1.0 V Vdd + 0.3 0.8 V 0.8 5 µA Iio Output Leakage Current Output is disabled (Hi-Z) –5 0V ≤ Vout ≤ Vdd 5 µA Voh Output High Voltage Level Ioh = –5.0 mA Ioh = –2.0 mA 5V 3.3V 2.4 2.4 — — V Vol Output Low Voltage Level Iol = 4.2 mA Iol = 2 mA 5V 3.3V — — 0.4 0.4 V 0 -40 — — +70 +85 °C Ta Commercial Ambient Temperature Industrial Ambient Temperature CAPACITANCE(1,2) Symbol Cin1 Cin2 Cio Parameter Input Capacitance: A0-A10 Input Capacitance: RAS, CAS, WE, OE Data Input/Output Capacitance: I/O0-I/O3 Max. 5 7 7 Unit pF pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25°C, f = 1 MHz. 4 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00B 08/09/2010 IS41C44002C IS41LV44002C ELECTRICAL CHARACTERISTICS(1) (Recommended Operating Conditions unless otherwise noted.) Symbol Parameter Test Condition Vdd/Speed Min. Idd1 Standby Current: TTL RAS, CAS ≥ VihCom. 5V — 3.3V — Ind. 5V — 3.3V — Idd2 Standby Current: CMOS Idd3 RAS, CAS ≥ Vdd – 0.2V Max. 2 2 3 2 Unit mA 5V 3.3V — — 1 0.5 mA Operating Current: RAS, CAS, Random Read/Write(2,3,4) Address Cycling, trc = trc (min.) Average Power Supply Current -50 — 120 mA Idd4 Operating Current: RAS = Vil, CAS, EDO Page Mode(2,3,4) Cycling tpc = tpc (min.) Average Power Supply Current -50 — 90 mA Idd5 Refresh Current: RAS-Only(2,3) Average Power Supply Current RAS Cycling, CAS ≥ Vih trc = trc (min.) -50 — 120 mA Idd6 Refresh Current: CBR(2,3,5) Average Power Supply Current RAS, CAS Cycling trc = trc (min.) -50 — 120 mA Notes: 1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tref refresh requirement is exceeded. 2. Dependent on cycle rates. 3. Specified values are obtained with minimum cycle time and the output open. 4. Column-address is changed once each EDO page cycle. 5. Enables on-chip refresh and address counters. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00B 08/09/2010 5 IS41C44002C IS41LV44002C AC CHARACTERISTICS(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) Symbol trc trac tcac taa tras trp tcas tcp tcsh trcd tasr trah tasc tcah tar trad tral trpc trsh trhcp tclz tcrp tod toe toed toehc toep toes trcs trrh trch twch twcr twp twpz 6 Parameter Random READ or WRITE Cycle Time Access Time from RAS(6, 7) Access Time from CAS(6, 8, 15) Access Time from Column-Address(6) RAS Pulse Width RAS Precharge Time CAS Pulse Width(23) CAS Precharge Time(9) CAS Hold Time (21) -50 Min. Max. 84 — — 50 — 13 — 25 50 10K 30 — 8 10K 9 — 38 — RAS to CAS Delay Time(10, 20) 12 37 Row-Address Setup Time 0 — Row-Address Hold Time 8 — Column-Address Setup Time(20) 0 — (20) Column-Address Hold Time 8 — Column-Address Hold Time 30 — (referenced to RAS) RAS to Column-Address Delay Time(11) 10 25 Column-Address to RAS Lead Time 25 — RAS to CAS Precharge Time 5 — RAS Hold Time 8 — RAS Hold Time from CAS Precharge 30 — (15, 24) CAS to Output in Low-Z 0 — (21) CAS to RAS Precharge Time 5 — (19, 24) Output Disable Time 3 15 Output Enable Time(15, 16) — 12 Output Enable Data Delay (Write) 12 — OE HIGH Hold Time from CAS HIGH 5 — OE HIGH Pulse Width 10 — OE LOW to CAS HIGH Setup Time 5 — Read Command Setup Time(17, 20) 0 — Read Command Hold Time 0 — (referenced to RAS)(12) Read Command Hold Time 0 — (referenced to CAS)(12, 17, 21) Write Command Hold Time(17) 8 — Write Command Hold Time 40 — (referenced to RAS)(17) Write Command Pulse Width(17) 8 — WE Pulse Widths to Disable Outputs 7 — Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00B 08/09/2010 IS41C44002C IS41LV44002C AC CHARACTERISTICS (Continued)(1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) Symbol trwl tcwl twcs tdhr tach toeh tds tdh trwc trwd tcwd tawd tpc trasp tcpa tprwc tcoh toff twhz tcsr tchr tord tref tt Parameter Write Command to RAS Lead Time(17) (17, 21) Write Command to CAS Lead Time (14, 17, 20) Write Command Setup Time Data-in Hold Time (referenced to RAS) Column-Address Setup Time to CAS Precharge during WRITE Cycle OE Hold Time from WE during READ-MODIFY-WRITE cycle(18) Data-In Setup Time(15, 22) Data-In Hold Time(15, 22) READ-MODIFY-WRITE Cycle Time RAS to WE Delay Time during READ-MODIFY-WRITE Cycle(14) CAS to WE Delay Time(14, 20) Column-Address to WE Delay Time(14) EDO Page Mode READ or WRITE Cycle Time RAS Pulse Width in EDO Page Mode (15) Access Time from CAS Precharge EDO Page Mode READ-WRITE Cycle Time Data Output Hold after CAS LOW Output Buffer Turn-Off Delay from CAS or RAS(13,15,19, 24) Output Disable Delay from WE CAS Setup Time (CBR REFRESH)(20, 25) CAS Hold Time (CBR REFRESH)( 21, 25) OE Setup Time prior to RAS during HIDDEN REFRESH Cycle Auto Refresh Period 2,048 Cycles Transition Time (Rise or Fall)(2, 3) -50 Min. Max. 13 — 8 — 0 — 39 — 15 — Units ns ns ns ns ns 8 — ns 0 8 — — ns ns 108 64 — — ns ns 26 39 20 — — — ns ns ns 50 — 56 100K 30 — ns ns ns 5 0 — 12 ns ns 3 5 8 0 10 — — — ns ns ns ns — 1 32 50 ms ns AC TEST CONDITIONS Output load: Two TTL Loads and 50 pF (Vdd = 5.0V ±10%) One TTL Load and 50 pF (Vdd = 3.3V ±10%) Input timing reference levels: Vih = 2.0V, Vil = 0.8V (Vdd = 5.0V ±10%); Vih = 2.0V, Vil = 0.8V (Vdd = 3.3V ±10%) Output timing reference levels: Voh = 2.4V, Vol = 0.4V (Vdd = 5V ±10%, 3.3V ±10%) Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00B 08/09/2010 7 IS41C44002C IS41LV44002C Notes: 1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the tref refresh requirement is exceeded. 2. Vih (MIN) and Vil (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between Vih and Vil (or between Vil and Vih) and assume to be 1 ns for all inputs. 3. In addition to meeting the transition rate specification, all input signals must transit between Vih and Vil (or between Vil and Vih) in a monotonic manner. 4. If CAS and RAS = Vih, data output is High-Z. 5. If CAS = Vil, data output may contain data from the last valid READ cycle. 6. Measured with a load equivalent to one TTL gate and 50 pF. 7. Assumes that trcd ≤ trcd (MAX). If trcd is greater than the maximum recommended value shown in this table, trac will increase by the amount that trcd exceeds the value shown. 8. Assumes that trcd ≥ trcd (MAX). 9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the data output buffer, CAS and RAS must be pulsed for tcp. 10.Operation with the trcd (MAX) limit ensures that trac (MAX) can be met. trcd (MAX) is specified as a reference point only; if trcd is greater than the specified trcd (MAX) limit, access time is controlled exclusively by tcac. 11.Operation within the trad (MAX) limit ensures that trcd (MAX) can be met. trad (MAX) is specified as a reference point only; if trad is greater than the specified trad (MAX) limit, access time is controlled exclusively by taa. 12.Either trch or trrh must be satisfied for a READ cycle. 13.toff (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to Voh or Vol. 14.twcs, trwd, tawd and tcwd are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If twcs ≥ twcs (MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If trwd ≥ trwd (MIN), tawd ≥ tawd (MIN) and tcwd ≥ tcwd (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to Vih) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle. 15.Output parameter (I/O) is referenced to corresponding CAS input. 16.During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE WRITE or READ-MODIFY-WRITE is not possible. 17.Write command is defined as WE going low. 18.LATE WRITE and READ-MODIFY-WRITE cycles must have both tod and toeh met (OE HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW and OE is taken back to LOW after toeh is met. 19.The I/Os are in open during READ cycles once tod or toff occur. 20.Determined by falling edge of CAS. 21.Determined by rising edge of CAS. 22.These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READMODIFY-WRITE cycles. 23.CAS must meet minimum pulse width. 24.The 3 ns minimum is a parameter guaranteed by design. 8 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00B 08/09/2010 IS41C44002C IS41LV44002C READ CYCLE tRC tRAS tRP RAS tCSH tCRP tRSH tCAS tCLCH tRCD tRRH CAS tAR tRAD tRAH tASR ADDRESS tRAL tCAH tASC Row Column Row tRCS tRCH WE tAA tRAC tCAC tCLC I/O tOFF(1) Open Open Valid Data tOE tOD OE tOES Don’t Care Note: 1. toff is referenced from rising edge of RAS or CAS, whichever occurs last. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00B 08/09/2010 9 IS41C44002C IS41LV44002C EARLY WRITE CYCLE (OE = DON'T CARE) tRC tRAS tRP RAS tCSH tCRP tRSH tCAS tCLCH tRCD CAS tAR tRAD tRAH tASR ADDRESS tRAL tCAH tACH tASC Row Column Row tCWL tRWL tWCR tWCS tWCH tWP WE tDHR tDS I/O tDH Valid Data Don’t Care 10 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00B 08/09/2010 IS41C44002C IS41LV44002C READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles) tRWC tRAS tRP RAS tCSH tCRP tRSH tCAS tCLCH tRCD CAS tAR tRAD tASR tRAH tRAL tCAH tASC tACH ADDRESS Row Column Row tRWD tCWL tRWL tCWD tRCS tAWD tWP WE tAA tRAC tCAC tCLZ I/O tDS Open Valid DOUT tOE tOD tDH Valid DIN Open tOEH OE Don’t Care Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00B 08/09/2010 11 IS41C44002C IS41LV44002C EDO-PAGE-MODE READ CYCLE tRASP tRP RAS tCSH tCRP tCAS, tCLCH tRCD tPC(1) tCAS, tCLCH tCP tCP tRSH tCAS, tCLCH tCP CAS tAR tRAD tASR ADDRESS tASC tCAH tASC Row Column tRAL tCAH tCAH tASC Column Column Row tRAH tRRH tRCS tRCH WE tAA tRAC tCAC tCLZ I/O Open tAA tCPA tCAC tCOH Valid Data tOE tOES tAA tCPA tCAC tCLZ tOFF Valid Data tOEHC Valid Data Open tOE tOD tOES tOD OE tOEP Don’t Care Note: 1. tpc can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both measurements must meet the tpcspecifications. 12 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00B 08/09/2010 IS41C44002C IS41LV44002C EDO-PAGE-MODE EARLY-WRITE CYCLE tRASP tRP RAS tCSH tCRP tPC tCAS, tCLCH tRCD tCP tCAS, tCLCH tCP tRSH tCAS, tCLCH tCP CAS tAR tACH tCAH tASC tRAD tASR ADDRESS tASC Row Column tRAH tACH tRAL tCAH tACH tCAH tASC Column tCWL tWCS Column tCWL tWCS tWCH tCWL tWCS tWCH tWCH tWP tWP Row tWP WE tWCR tDHR tRWL tDS tDS tDH I/O Valid Data tDS tDH Valid Data tDH Valid Data OE Don’t Care Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00B 08/09/2010 13 IS41C44002C IS41LV44002C EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY WRITE Cycles) tRASP tRP RAS tCSH tCRP tCAS, tCLCH tRCD tCP tPC / tPRWC(1) tCAS, tCLCH tRSH tCAS, tCLCH tCP tCP CAS tASR tRAH ADDRESS tAR tRAD tASC tCAH Row tASC tCAH Column tRWD tRCS tRAL tCAH tASC Column tCWL tWP Column tRWL tCWL tWP tCWL tWP tAWD tCWD Row tAWD tCWD tAWD tCWD WE tAA tRAC tCAC tCLZ I/O Open tAA tCPA tDH tDS DOUT tCAC tCLZ DIN DOUT tOD tOE tAA tCPA tDH tDS tCAC tCLZ DIN DOUT tOD tOE tDH tDS Open DIN tOD tOE tOEH OE Don’t Care Note: 1. tpc can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both measurements must meet the tpc specifications. 14 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00B 08/09/2010 IS41C44002C IS41LV44002C EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Pseudo READ-MODIFY WRITE) tRASP tRP RAS tCSH tPC tPC tCRP tCAS tRCD tCAS tCP tRSH tCAS tCP tCP CAS tASR tRAH ADDRESS tAR tRAD tASC Row tCAH tASC tCAH Column (A) tASC Column (B) tRCS tACH tRAL tCAH Column (N) Row tRCH tWCS tWCH WE tRAC tCAC I/O tAA Open tCPA tCAC tAA tWHZ tCOH Valid Data (A) tDS Valid Data (B) tDH DIN Open tOE OE Don’t Care Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00B 08/09/2010 15 IS41C44002C IS41LV44002C AC WAVEFORMS READ CYCLE (With WE-Controlled Disable) RAS tCSH tCRP tRCD tCP tCAS CAS tAR tRAD tASR ADDRESS tRAH tCAH tASC Row tASC Column Column tRCS tRCH tRCS WE tAA tRAC tCAC tCLZ Open I/O tWHZ tCLZ Valid Data Open tOE tOD OE Don’t Care RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE) tRC tRAS tRP RAS tCRP tRPC CAS tASR ADDRESS I/O tRAH Row Row Open Don’t Care 16 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00B 08/09/2010 IS41C44002C IS41LV44002C CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE) tRP tRAS tRP tRAS RAS tRPC tCP tCHR tCHR tRPC tCSR tCSR CAS Open I/O Don’t Care HIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW) tRAS tRP tRAS RAS tCRP tRCD tRSH tCHR CAS tAR tRAD tRAH tASC tASR ADDRESS Row tRAL tCAH Column tAA tRAC tOFF(2) tCAC tCLZ I/O Open Valid Data tOE Open tOD tORD OE Don’t Care Notes: 1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH. 2. toff is referenced from rising edge of RAS or CAS, whichever occurs last. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00B 08/09/2010 17 IS41C44002C IS41LV44002C ORDERING INFORMATION: 5V Industrial Range: -40°C to +85°C peed (ns) S 50 Order Part No. Refresh IS41C44002C-50CTGI 2K Package 300-mil TSOP-II, Cu leadframe plated with matte SnBi ORDERING INFORMATION: 3.3V Industrial Range: -40°C to +85°C peed (ns) S 50 Order Part No. Refresh IS41LV44002C-50CTGI 2K Package 300-mil TSOP-II, Cu leadframe plated with matte SnBi Notes: 1. Part number with TLI or CTGI are lead-free, and RoHS compliant. 2. For the "G" option, Bi is 3% or less of SnBi plating. 18 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00B 08/09/2010 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00B 08/09/2010 Θ Package Outline 4. REFERENCE DOCUMENT : JEDEC SPEC. MS-025 , A 07/07/2008 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. 2. DIMENSION D AND E1 DO NOT INCLUDE MOLD PROTRUSION. 1. CONTROLLING DIMENSION : MM NOTE : Θ IS41C44002C IS41LV44002C 19