TI TPIC6273DW

TPIC6273
POWER LOGIC OCTAL D-TYPE LATCH
SLIS011A – APRIL 1992 – REVISED OCTOBER 1995
•
•
•
•
•
•
Low rDS(on) . . . 1.3 Ω Typ
Avalanche Energy . . . 75 mJ
Eight Power DMOS Transistor Outputs of
250-mA Continuous Current
1.5-A Pulsed Current Per Output
Output Clamp Voltage up to 45 V
Low Power Consumption
DW OR N PACKAGE
(TOP VIEW)
CLR
D1
D2
DRAIN1
DRAIN2
DRAIN3
DRAIN4
D3
D4
GND
description
The TPIC6273 is a monolithic high-voltage
high-current power logic octal D-type latch with
DMOS transistor outputs designed for use in
systems that require relatively high load power.
The device contains a built-in voltage clamp on the
outputs for inductive transient protection. Power
driver applications include relays, solenoids, and
other medium-current or high-voltage loads.
The TPIC6273 contains eight positive-edgetriggered D-type flip-flops with a direct clear input.
Each flip-flop features an open-drain power
DMOS transistor output.
The TPIC6273 is characterized for operation over
the operating case temperature range of – 40°C
to 125°C.
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
D8
D7
DRAIN8
DRAIN7
DRAIN6
DRAIN5
D6
D5
CLK
logic symbol†
CLR
CLK
D1
D2
D3
When clear (CLR) is high, information at the D
inputs meeting the setup time requirements is
transferred to the DRAIN outputs on the positivegoing edge of the clock pulse. Clock triggering
occurs at a particular voltage level and is not
directly related to the transition time of the
positive-going pulse. When the clock input (CLK)
is at either the high or low level, the D input signal
has no effect at the output. An asynchronous CLR
is provided to turn all eight DMOS-transistor
outputs off.
1
D4
D5
D6
D7
D8
1
R
11
C1
2
4
1D
3
5
8
6
9
7
12
14
13
15
18
16
19
17
DRAIN1
DRAIN2
DRAIN3
DRAIN4
DRAIN5
DRAIN6
DRAIN7
DRAIN8
† This symbol is in accordance with ANSI/IEEE Standard 91-1984
and IEC Publication 617-12.
FUNCTION TABLE
(each channel)
INPUTS
CLR
CLK
D
OUTPUT
DRAIN
L
H
H
H
X
↑
↑
L
X
H
L
X
H
L
H
Latched
H = high level, L = low level, X = irrelevant
Copyright  1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
TPIC6273
POWER LOGIC OCTAL D-TYPE LATCH
SLIS011A – APRIL 1992 – REVISED OCTOBER 1995
logic diagram (positive logic)
4
CLR
D1
CLK
1
2
DRAIN1
R
1D
11
C1
5
DRAIN2
R
D2
3
1D
C1
6
DRAIN3
R
D3
8
1D
C1
7
DRAIN4
R
D4
9
1D
C1
14
DRAIN5
R
D5
12
1D
C1
15
DRAIN6
R
D6
13
1D
C1
16
DRAIN7
R
D7
18
1D
C1
17
DRAIN8
R
D8
19
1D
10
C1
2
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GND
TPIC6273
POWER LOGIC OCTAL D-TYPE LATCH
SLIS011A – APRIL 1992 – REVISED OCTOBER 1995
schematic of inputs and outputs
EQUIVALENT OF EACH INPUT
TYPICAL OF ALL DRAIN OUTPUTS
VCC
DRAIN
45 V
Input
25 V
12 V
12 V
GND
GND
absolute maximum ratings over recommended operating case temperature range (unless
otherwise noted)†
Logic supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Logic input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Power DMOS drain-to-source voltage, VDS (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 V
Continuous source-drain diode anode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A
Pulsed source-drain diode anode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 A
Pulsed drain current, each output, all outputs on, IDn, TA = 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . 750 mA
Continuous drain current, each output, all outputs on, IDn, TA = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . 250 mA
Peak drain current single output, IDM,TA = 25°C (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 A
Single-pulse avalanche energy, EAS (see Figure 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 mJ
Avalanche current, IAS (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. Each power DMOS source is internally connected to GND.
3. Pulse duration ≤ 100 µs, duty cycle ≤ 2%
4. DRAIN supply voltage = 15 V, starting junction temperature (TJS) = 25°C, L = 100 mH, IAS = 1 A (see Figure 4).
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 125°C
POWER RATING
DW
1125 mW
9.0 mW/°C
225 mW
N
1150 mW
9.2 mW/°C
230 mW
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TPIC6273
POWER LOGIC OCTAL D-TYPE LATCH
SLIS011A – APRIL 1992 – REVISED OCTOBER 1995
recommended operating conditions over recommended operating temperature range (unless
otherwise noted)
Logic supply voltage, VCC
High-level input voltage, VIH
MIN
MAX
4.5
5.5
UNIT
V
0.85 VCC
Low-level input voltage, VIL
V
0.15 VCC
Pulsed drain output current, TC = 25°C, VCC = 5 V (see Notes 3 and 5)
– 1.8
1.5
V
A
Setup time, D high before CLK↑, tsu (see Figure 2)
10
ns
Hold time, D high after CLK↑, th (see Figure 2)
15
ns
Pulse duration, tw (see Figure 2)
25
Operating case temperature, TC
– 40
ns
°C
125
electrical characteristics, VCC = 5 V, TC = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
V(BR)DSX
VSD
Drain-source breakdown voltage
IIH
IIL
High-level input current
ICC
Logic supply current
ID = 1 mA
IF = 250 mA, See Note 3
Source-drain diode forward voltage
IN
Nominal current
VDS(on) = 0.5 V,
IN = ID,
TC = 85°C
IDSX
Off state drain current
Off-state
VDS = 40 V
VDS = 40 V,
Static drain-source on-state
resistance
ID = 250 mA, VCC = 4.5 V
ID = 250 mA, TC = 125°C,
VCC = 4.5 V
ID = 500 mA, VCC = 4.5 V
TYP
MAX
45
15
See Notes 5, 6, and 7
1
V
1
µA
–1
µA
100
µA
250
TC = 125°C
See Notes 5 and 6
and Figures 8 and 9
UNIT
V
0.85
VCC = 5.5 V, VI = VCC
VCC = 5.5 V, VI = 0
IO = 0,
All inputs low
Low-level input current
rDS(on)
MIN
mA
0.05
1
0.15
5
1.3
2
2
3.2
1.3
2
TYP
MAX
µA
Ω
switching characteristics, VCC = 5 V, TC = 25°C
PARAMETER
TEST CONDITIONS
MIN
UNIT
tPLH
tPHL
Propagation delay time, low-to-high-level output from CLK
625
ns
Propagation delay time, high-to-low-level output from CLK
150
ns
tr
tf
Rise time, drain output
675
ns
400
ns
ta
trr
Reverse-recovery-current rise time
CL = 30 pF,,
ID = 250 mA,,
See Figures 1, 2, and 10
Fall time, drain output
µ
IF = 250 mA,
di/dt = 20 A/µs,
See Notes 5 and 6 and Figure 3
Reverse-recovery time
NOTES: 3.
5.
6.
7.
100
ns
300
Pulse duration ≤ 100 µs, duty cycle ≤ 2%
Technique should limit TJ – TC to 10°C maximum.
These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a
voltage drop of 0.5 V at TC = 85°C.
thermal resistance
PARAMETER
RθJA
4
TEST CONDITIONS
Thermal resistance,
resistance junction-to-ambient
junction to ambient
DW package
N package
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All 8 outputs with equal power
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MIN
MAX
111
108
UNIT
°C/W
TPIC6273
POWER LOGIC OCTAL D-TYPE LATCH
SLIS011A – APRIL 1992 – REVISED OCTOBER 1995
PARAMETER MEASUREMENT INFORMATION
5V
20
24 V
5V
VCC
11
Word
Generator
(see Note A)
CLK
ID
0V
RL = 95 Ω
DUT
CLK
DRAIN
4 –7,
14 –17
5V
D
Output
0V
D
1
5V
CL = 30 pF
(see Note B)
CLR
CLR
0V
GND
24 V
10
Output
0.5 V
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 1. Resistive Load Normal Operation
5V
D
5V
VCC
Word
Generator
(see Note A)
Word
Generator
(see Note A)
D
11
CLK
CLK
24 V
1
20
0V
5V
50%
50%
0V
CLR
tPLH
tPHL
ID
95 Ω
DUT
Output
DRAIN
GND
4 –7,
14 –17
Output
90%
24 V
90%
10%
10%
tr
0.5 V
tf
SWITCHING TIMES
CL = 30 pF
(see Note B)
10
5V
50%
CLK
0V
tsu
TEST CIRCUIT
D
th
5V
50%
50%
0V
tw
INPUT SETUP AND HOLD WAVEFORMS
Figure 2. Test Circuit, Switching Times, and Voltage Waveforms
NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, tw = 300 ns, pulsed repetition rate (PRR) = 5 KHz,
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
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TPIC6273
POWER LOGIC OCTAL D-TYPE LATCH
SLIS011A – APRIL 1992 – REVISED OCTOBER 1995
PARAMETER MEASUREMENT INFORMATION
TP K
DRAIN
0.25 A
2500 µF
250 V
Circuit
Under
Test
di/dt = 20 A/µs
+
25 V
L = 1 mH
IF
(see Note B)
IF
–
0
TP A
25% of IRM
t2
t1
t3
Driver
IRM
RG
VGG
(see Note A)
ta
50 Ω
trr
CURRENT WAVEFORM
TEST CIRCUIT
NOTES: A. The VGG amplitude and RG are adjusted for di/dt = 20 A/µs. A VGG double-pulse train is used to set IF = 0.25 A, where t1 = 10 µs,
t2 = 7 µs, and t3 = 3 µs.
B. The DRAIN terminal under test is connected to the TP K test point. All other terminals are connected together and connected to the
TP A test point.
Figure 3. Reverse-Recovery-Current Test Circuit and Waveforms of Source-Drain Diode
5V
15 V
tw
20
1
Word
Generator
(see Note A)
11
VCC
0.11 Ω
CLR
CLK
5V
Input
See Note B
ID
100 mH
DUT
DRAIN
D
4 –7,
14 –17
IAS = 1 A
V(BR)DSX = 45 V
MIN
VDS
10
0V
ID
VDS
GND
tav†
Input
VOLTAGE AND CURRENT WAVEFORMS
TEST CIRCUIT
† Non-JEDEC symbol for avalanche ftime.
NOTES: A. The word generator A has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω.
B. Input pulse duration, tw, is increased until peak current IAS = 1 A.
Energy test is defined as EAS = IAS x V(BR)DSX x tav/2 = 75 mJ, where tav = avalanche time.
Figure 4. Single-Pulse Avalanche Energy Test Circuit and Waveforms
6
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TPIC6273
POWER LOGIC OCTAL D-TYPE LATCH
SLIS011A – APRIL 1992 – REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS
MAXIMUM CONTINUOUS
DRAIN CURRENT OF EACH OUTPUT
vs
NUMBER OF OUTPUTS CONDUCTING
SIMULTANEOUSLY
PEAK AVALANCHE CURRENT
vs
TIME DURATION OF AVALANCHE
10
800
I D – Maximum Continuous Drain Current
of Each Output – mA
4
2
1
0.4
0.2
0.1
0.1
0.2
0.4
1
2
4
VCC = 5 V
700
600
500
TA = 25°C
400
300
TA = 100°C
200
TA = 125°C
100
0
10
0
1
2
3
4
5
6
7
8
N – Number of Outputs Conducting Simultaneously
tav – Time Duration of Avalanche – ms
Figure 5
Figure 6
MAXIMUM PEAK DRAIN CURRENT
OF EACH OUTPUT
vs
NUMBER OF OUTPUTS CONDUCTING
SIMULTANEOUSLY
2
I D – Peak Drain Current – A
IAS – Peak Avalanche Current – A
TJS = 25°C
VCC = 5 V
TA = 25°C
d = tw/tperiod
= 1 ms/tperiod
1.5
d = 5%
1
d = 50%
d = 10%
0.5
d = 80%
0
6
7
8
0
1
2
3
4
5
N – Number of Outputs Conducting Simultaneously
Figure 7
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TPIC6273
POWER LOGIC OCTAL D-TYPE LATCH
SLIS011A – APRIL 1992 – REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS
STATIC DRAIN-SOURCE
ON-STATE RESISTANCE
vs
LOGIC SUPPLY VOLTAGE
r DS(on) – Static Drain-Source On-State Resistance – Ω
r DS(on) – Static Drain-Source On-State Resistance – Ω
STATIC DRAIN-SOURCE
ON-STATE RESISTANCE
vs
DRAIN CURRENT
4
3.5
VCC = 5 V
See Note A
3
TC = 125 °C
2.5
2
TC = 25 °C
1.5
1
TC = – 40 °C
0.5
0
0.25
0.5
0.75
1
1.25
1.5
3
2.5
2
TC = 25 °C
1.5
1
TC = – 40 °C
0.5
0
3
4
5
Figure 8
Figure 9
SWITCHING TIME
vs
FREE-AIR TEMPERATURE
700
tr
600
Switching Time – ns
6
VCC – Logic Supply Voltage – V
ID – Drain Current – A
tPLH
ID = 250 mA
See Note A
500
tf
400
300
200
tPHL
100
– 50
0
50
100
TA – Free-Air Temperature – °C
Figure 10
NOTE A: Technique should limit TJ – TC to 10°C maximum.
8
ID = 250 mA
See Note A
TC = 125 °C
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7
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