TI SN74TVC3306DCTR

SN74TVC3306
DUAL VOLTAGE CLAMP
www.ti.com
SCDS112C – MARCH 2001 – REVISED MARCH 2005
FEATURES
•
DCT OR DCU PACKAGE
(TOP VIEW)
Designed to Be Used in Voltage-Limiting
Applications
3.5-Ω On-State Connection Between Ports A
and B
Flow-Through Pinout for Ease of Printed
Circuit Board Trace Routing
Direct Interface With GTL+ Levels
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
•
•
•
•
•
GND
A1
A2
A3
1
8
2
7
3
6
4
5
GATE
B1
B2
B3
DESCRIPTION/ORDERING INFORMATION
The SN74TVC3306 provides three parallel NMOS pass transistors with a common unbuffered gate. The low
on-state resistance of the switch allows connections to be made with minimal propagation delay.
The device can be used as a dual switch, with the gates cascaded together to a reference transistor. The
low-voltage side of each pass transistor is limited to a voltage set by the reference transistor. This is done to
protect components with inputs that are sensitive to high-state voltage-level overshoots.
ORDERING INFORMATION
PACKAGE (1)
TA
–40°C to 85°C
(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
SSOP – DCT
Tape and reel
SN74TVC3306DCTR
FA6
VSSOP – DCU
Tape and reel
SN74TVC3306DCUR
FA6
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
LOGIC DIAGRAM (POSITIVE LOGIC)
GATE
8
1
GND
B1
7
B2
6
B3
5
2
3
4
A1
A2
A3
NOTE A: The SN74TVC3306 has bidirectional capability across many voltage levels. The voltage levels documented in this data sheet are
examples.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2001–2005, Texas Instruments Incorporated
SN74TVC3306
DUAL VOLTAGE CLAMP
www.ti.com
SCDS112C – MARCH 2001 – REVISED MARCH 2005
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VI
Input voltage range (2)
–0.5
7
V
VI/O
Input/output voltage range (2)
–0.5
7
V
Continuous channel current
IIK
Input clamp current
θJA
Package thermal impedance (3)
Tstg
Storage temperature range
(1)
(2)
(3)
UNIT
128
mA
VI < 0
–50
mA
DCT package
220
DCU package
227
–65
°C/W
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and input/output negative-voltage ratings may be exceeded if the input and input/output clamp-current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions
MIN
MAX
VI/O
Input/output voltage
0
5
V
VGATE
GATE voltage
0
5
V
IPASS
Pass transistor current
64
mA
TA
Operating free-air temperature
85
°C
MAX
UNIT
–40
UNIT
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
II = -18 mA,
VGATE = 0
–1.2
V
IIH
VI = 5 V,
VGATE = 0
5
µA
VI = 3 V or 0
11
Cio(off)
VO = 3 V or 0,
VGATE = 0
Cio(on)
VO = 3 V or 0,
VGATE = 3 V
VI = 0,
IO = 64 mA
ron (2)
2
TYP (1)
VIK
Ci(GATE)
(1)
(2)
MIN
VI = 2.4 V,
IO = 15 mA
VI = 1.7 V,
IO = 15 mA
pF
4
6
pF
10.5
12.5
pF
VGATE = 4.5 V
3.5
5.5
VGATE = 3 V
4.7
7
VGATE = 2.3 V
6.3
9.5
VGATE = 1.5 V
25.5
32
VGATE = 4.5 V
4.8
7.5
VGATE = 3 V
14.7
23
VGATE = 2.3 V
11.3
16.5
All typical values are at TA = 25°C.
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is
determined by the lowest voltage of the two (A or B) terminals.
Ω
SN74TVC3306
DUAL VOLTAGE CLAMP
www.ti.com
SCDS112C – MARCH 2001 – REVISED MARCH 2005
AC Performance (Translating Down)
Switching Characteristics
over recommended operating free-air temperature range, VGATE = 3.3 V, VIH = 3.3 V, VIL = 0, and VM = 1.15 V
(unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
A or B
B or A
CL = 50 pF
CL = 30 pF
CL = 15 pF
MIN
MAX
MIN
MAX
MIN
MAX
0
0.8
0
0.6
0
0.3
0
1.2
0
1
0
0.5
UNIT
ns
Switching Characteristics
over recommended operating free-air temperature range, VGATE = 2.5 V, VIH = 2.5 V, VIL = 0, and VM = 0.75 V
(unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
A or B
B or A
CL = 50 pF
CL = 30 pF
CL = 15 pF
MIN
MAX
MIN
MAX
MIN
MAX
0
1
0
0.7
0
0.4
0
1.3
0
1
0
0.6
UNIT
ns
AC Performance (Translating Up)
Switching Characteristics
over recommended operating free-air temperature range, VGATE = 3.3 V, VIH = 2.3 V, VIL = 0, VT = 3.3 V, VM = 1.15 V, and
RL = 300 Ω (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
A or B
B or A
CL = 50 pF
CL = 30 pF
CL = 15 pF
MIN
MAX
MIN
MAX
MIN
MAX
0
0.9
0
0.6
0
0.4
0
1.4
0
1.1
0
0.7
UNIT
ns
Switching Characteristics
over recommended operating free-air temperature range, VGATE = 2.5 V, VIH = 1.5 V, VIL = 0, VT = 2.5 V, VM = 0.75 V, and
RL = 300 Ω (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
A or B
B or A
CL = 50 pF
CL = 30 pF
CL = 15 pF
MIN
MAX
MIN
MAX
MIN
MAX
0
1
0
0.6
0
0.4
0
1.3
0
1.3
0
0.8
UNIT
ns
3
SN74TVC3306
DUAL VOLTAGE CLAMP
www.ti.com
SCDS112C – MARCH 2001 – REVISED MARCH 2005
PARAMETER MEASUREMENT INFORMATION
VT
USAGE
Translating up
Translating down
RL
SWITCH
S1
S2
S1
Open
From Output
Under Test
S2
VIH
Input
VM
VM
CL
(see Note A)
VIL
VOH
Output
VM
LOAD CIRCUIT
VM
VOL
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
C. The outputs are measured one at a time, with one transition per measurement.
Figure 1. Load Circuit for Outputs
4
SN74TVC3306
DUAL VOLTAGE CLAMP
www.ti.com
SCDS112C – MARCH 2001 – REVISED MARCH 2005
APPLICATION INFORMATION
VDDREF = 3.3 V
Motherboard
Interface
GATE(1)
8
VDPU = 2.5 V
200 kΩ
150 Ω
150 Ω
B1 (VBIAS)(1)
7
B2
6
B3
5
2
A1
3
A2
4
A3
TVC3306
1
VREF(1) = 1.5 V
Open-Drain
CPU Interface
(1) VREF and VBIAS can be applied to any one of the pass transistors. GATE must be connected externally to VBIAS.
Figure 2. Typical Application Circuit
For the clamping configuration, the common GATE input must be connected to one side (An or Bn) of any one of
the pass transistors, making that the VBIAS connection of the reference transistor and the opposite side (Bn or
An) the VREF connection. When VBIAS is connected through a 200-kΩ resistor to a 3-V to 5.5-V VCC supply and
VREF is set to 0 V to VCC – 0.6 V, the output of each switch has a maximum clamp voltage equal to VREF. A filter
capacitor on VBIAS is recommended.
Application Operating Conditions
see Figure 2
MIN TYP (1)
MAX
UNIT
VBIAS
BIAS voltage
VREF + 0.6
2.1
5
V
VGATE
GATE voltage
VREF + 0.6
2.1
5
V
VREF
Reference voltage
0
1.5
4.4
V
VDPU
Drain pullup voltage
2.36
2.5
2.64
V
IPASS
Pass-transistor current
IREF
Reference-transistor current
TA
Operating free-air temperature
(1)
14
mA
µA
5
–40
85
°C
All typical values are at TA = 25°C.
5
PACKAGE OPTION ADDENDUM
www.ti.com
29-May-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74TVC3306DCTR
ACTIVE
SM8
DCT
8
3000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
SN74TVC3306DCTRE4
ACTIVE
SM8
DCT
8
3000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
SN74TVC3306DCUR
ACTIVE
US8
DCU
8
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74TVC3306DCURE4
ACTIVE
US8
DCU
8
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74TVC3306DCURG4
ACTIVE
US8
DCU
8
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-May-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
Device
SN74TVC3306DCUR
19-May-2007
Package Pins
DCU
8
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
HNT
180
9
2.25
3.35
1.05
4
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
SN74TVC3306DCUR
DCU
8
HNT
202.0
201.0
28.0
Pack Materials-Page 2
W
Pin1
(mm) Quadrant
8
NONE
MECHANICAL DATA
MPDS049B – MAY 1999 – REVISED OCTOBER 2002
DCT (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
0,65
8
0,13 M
5
0,15 NOM
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
2,90
2,70
4,25
3,75
Gage Plane
PIN 1
INDEX AREA
1
0,25
4
0° – 8°
3,15
2,75
0,60
0,20
1,30 MAX
Seating Plane
0,10
0,10
0,00
NOTES: A.
B.
C.
D.
4188781/C 09/02
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion
Falls within JEDEC MO-187 variation DA.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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