TI TAS5028APAGRG4

TM
TAS5028A
8 Channel Digital Audio PWM Processor
Data Manual
2004
DAV−Digital Audio/Speaker
SLES120
IMPORTANT NOTICE
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Contents
Contents
Section
1
2
Page
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1
TAS5028A System Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2
TAS5028A Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2.1
Audio Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2.2
Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2.3
PWM Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.4
General Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3
Physical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3.1
Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3.2
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3.3
Terminal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4
TAS5028A Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4.1
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4.2
Clock, PLL, and Serial Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4.3
I2C Serial Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.4.4
Device Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.4.5
Digital Audio Processor (DAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.5
TAS5028A DAP Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.5.1
TAS5028A DAP Architecture Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.5.2
I2C Coefficient Number Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.6
Input Crossbar Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.7
Bass and Treble Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.8
Volume, Auto Mute, and Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.8.1
Auto Mute and Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.9
Output Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.10
PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.10.1
DC Blocking (High-Pass Enable / Disable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.10.2
De-Emphasis Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.10.3
AM Interference Avoidance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
TAS5028A Controls and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.1
I2C Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.1.1
General Status Register (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.1.2
Error Status Register (0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.2
TAS5028A Pin Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.2.1
Reset (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2.2.2
Power Down (PDN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.2.3
Backend Error (BKND_ERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.2.4
Speaker/Headphone Selector (HP_SEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.2.5
Mute (MUTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.3
Device Configuration Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.3.1
Channel Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.3.2
Headphone Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.3.3
Audio System Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.3.4
Recovery from Clock Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.3.5
Volume and Mute Update Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.3.6
Modulation Index Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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Contents
2.3.7
Inter-channel Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master Clock and Serial Data Rate Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.1
PLL Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5
Bank Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.1
Manual Bank Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.2
Automatic Bank Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.3
Bank Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.4
Bank Switch Timeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.5
Bank Switching Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.6
Bank Switching Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
Dynamic Performance (At Recommended Operating Conditions at 25°C) . . . . . . . . . . . . . . . . . . . .
3.3
Recommended Operating Conditions (Over 0°C to 70°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4
Electrical Characteristics Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . .
3.5
PWM Operation at Recommended Operating Conditions Over 0°C to 70°C . . . . . . . . . . . . . . . . . . .
3.6
Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1
Clock Signals Over Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.2
Serial Audio Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.3
I2C Serial Control Port Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.4
Reset Timing (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.5
Power-Down (PDN) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.6
Backend Error (BKND_ERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.7
MUTE Timing—MUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.8
Headphone Select (HP_SEL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.9
Volume Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7
Serial Audio Interface Control and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.1
I2S Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.2
Left Justified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.3
Right Justified . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Serial Control Interface (Slave Address 0x36) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1
General I2C Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2
Single and Multiple Byte Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3
Single Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4
Multiple Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5
Incremental Multiple Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6
Single Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7
Multiple Byte Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Control I2C Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Control Interface Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1
Clock Control Register (0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2
General Status Register 0 (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3
Error Status Register (0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4
System Control Register 1 (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5
System Control Register 2 (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6
Channel Configuration Control Register (0x05−X0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7
Headphone Configuration Control Register (0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8
Serial Data Interface Control Register (0x0E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.9
Soft Mute Register (0x0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4
3
4
5
6
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33
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34
35
35
35
35
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36
36
36
37
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39
40
40
41
42
42
42
43
44
45
45
45
46
46
46
47
47
49
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53
53
53
54
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List of Illustrations
7
6.10
Automute Control Register(0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.11
Automute PWM Threshold and Backend Reset Period (0x15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12
Modulation Index Limit Register (0x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13
Interchannel Channel Delay Registers (0x1B − 0x22) and Offset Register (0x23) . . . . . . . . . . . . . .
6.14
Bank Switching Command (0x40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.15
Input Mixer Registers (0x41 – 0x48, Channels 1 − 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.16
Bass and Treble Bypass Register (0x89 – 0x90, Channels 1 − 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.17
8x2 Output Mixer Registers (0xAA – 0xAF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.18
8x3 Output Mixer Registers (0xB0 – 0xB1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.19
Volume Treble and Bass Slew Rates (0xD0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.20
Volume Registers (0xD1 − 0xD9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.21
Bass Filter Set Register (0xDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.22
Bass Filter Index Register (0xDB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.23
Treble Filter Set Register (0xDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.24
Treble Filter Index (0xDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.25
AM Mode Register (0xDE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.26
General Control Register (0xE0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.27
Incremental Multiple Write Append Register (0xFE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TAS5028A Example Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
56
57
57
58
59
60
63
63
64
65
66
67
68
69
70
71
71
71
73
List of Illustrations
Figure
Title
Page
1−1 TAS5028A Functional Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1−2 Typical TAS5028A Application (DVD Receiver) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1−3 Recommended TAS5028A + TAS5121 Channel Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1−4 TAS5028A DAP Architecture With I2C Registers (Fs ≤ 96 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1−5 TAS5028A Architecture With I2C Registers (Fs = 176.4 kHz or Fs = 192 kHz) . . . . . . . . . . . . . . . . . . . . . . 13
1−6 TAS5028A Detailed Channel Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1−7 5.23 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1−8 Conversion Weighting Factors—5.23 Format to Floating Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1−9 Alignment of 5.23 Coefficient in 32-Bit I2C Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1−10 25.23 Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1−11 Alignment of 523 Coefficient in 32-Bit I2C Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1−12 Alignment of 2523 Coefficient in Two 32-Bit I2C Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1−13 TAS5028A Digital Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1−14 Input Crossbar Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1−15 Auto Mute Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1−16 Output Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1−17 De-emphasis Filter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1−18 Block Diagrams of Typical Systems Requiring TAS5028A Automatic AM Interference
Avoidance Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3−1 Slave Mode Serial Data Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3−2 SCL and SDA Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3−3 Start and Stop Conditions Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3−4 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
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3−5 Power-Down Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−6 Error Recovery Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−7 Mute Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−8 HP_SEL Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−9 I2S Format 64 Fs Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−10 Left Justified 64 Fs Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−11 Right Justified 64 Fs Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−1 Typical I2C Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−2 Single Byte Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−3 Multiple Byte Write Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−4 Single Byte Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−5 Multiple Byte Read Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
40
40
41
42
43
44
45
46
46
47
47
List of Tables
Table
Title
Page
1−1 Serial Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1−2 TAS5028A Audio Processing Feature Sets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1−3 Bass and Treble Filter Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1−4 Linear Gain Step Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2−1 Device Outputs During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
2−2 Values Set During Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2−3 Device Outputs During Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2−4 Device Outputs During Backend Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2−5 Description of the Channel Configuration Registers (0x05 to 0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2−6 Recommended TAS5028A Configurations for Texas Instruments Power Stages . . . . . . . . . . . . . . . . . . . . . 29
2−7 Audio System Configuration (General Control Register 0xE0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2−8 Volume Ramp Rates in ms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2−9 Inter-Channel Delay Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6−1 Clock Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6−2 General Status Register (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6−3 Error Status Register (0X02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6−4 System Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6−5 System Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6−6 Channel Configuration Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6−7 Headphone Configuration Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6−8 Serial Data Interface Control Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6−9 Soft Mute Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6−10 Automute Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6−11 Automute PWM Threshold and Backend Reset Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6−12 Modulation Index Limit Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6−13 Interchannel Channel Delay Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6−14 Channel Offset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6−15 Bank Switching Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6−16 Input Mixer Registers Format (0x41 – 0x48, Channels 1 − 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6−17 Bass and Treble Bypass Register Format (0x89−0x90) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6−18 Output Mixer Control Register Format (Upper 4 Bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
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6−19
6−20
6−21
6−22
6−23
6−24
6−25
6−26
6−27
6−28
6−29
6−30
6−31
6−32
6−33
6−34
6−35
6−36
6−37
6−38
6−39
6−40
6−41
6−42
Output Mixer Control (Lower 4 Bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Mixer Control (Upper 4 Bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Mixer Control (Middle 4 Bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Mixer Control (Lower 4 Bytes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Volume Gain Update Rate (Slew Rate) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Treble and Bass Gain Step Size (Slew Rate) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Volume Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master and Individual Volume Controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel 8 Sub Woofer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel 6 and 5 (Right and Left Lineout in Six Channel Configuration Right and
Left Surround in Eight Channel Configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel 4 and 3 (Right and Left Rear) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel 7, 2, 1 (Center, Right Front, and Left Front) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bass Filter Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bass Filter Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel 8 Sub Woofer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel 6 and 5 (Right and Left Lineout in Six Channel Configuration or Right
and Left Surround in Eight Channel Configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel 4 and 3 (Right and Left Rear) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Channel 7, 2, 1 (Center, Right Front, and Left Front) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Treble Filter Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Treble Filter Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AM Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AM Tuned Frequency Register in BCD Mode (Lower 2 Bytes of 0xDE) . . . . . . . . . . . . . . . . . . . . . . . . . . .
AM Tuned Frequency Register in Binary Mode (Lower 2 Bytes of 0xDE) . . . . . . . . . . . . . . . . . . . . . . . . . .
General Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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64
65
65
65
66
66
67
67
68
68
68
68
69
69
69
70
70
70
70
71
71
71
71
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Introduction
1
Introduction
The TAS5028A is an eight channel digital pulse width modulator (PWM) that provides both advanced
performance and a high level of system integration. The TAS5028A is designed to interface seamlessly with
most audio digital signal processors. The TAS5028A automatically adjusts control configurations in response
to clock and data rate changes and idle conditions. This enables the TAS5028A to provide an easy to use
control interface with relaxed timing requirements.
The TAS5028A can drive eight channels of H-bridge power stages. Texas Instruments H-bridge parts
TAS5111, TAS5112, or TAS5182 + FETs are designed to work seamlessly with the TAS5028A. The TAS5028A
supports both single-ended or bridge tied load configurations. The TAS5028A also provides a high
performance differential output to drive an external differential input analog headphone amplifier (such as the
TPA112).
The TAS5028A’s uses an AD modulation operating at a 384-kHz switching rate for 48-, 96-, and 192-kHz data.
The 8x oversampling combined with the 5th order noise shaper provides a broad flat noise floor and excellent
dynamic range from 20 Hz to 20 kHz.
VR_PLL
AVDD_PLL
AVSS_PLL
AVDD_REF
VBGAP
VRA_PLL
VRD_PLL
DVDD
DVSS
AVDD
AVSS
The TAS5028A is clock slave only device. The TAS5028A receives MCLK, SCLK and LRCLK from other
system components. The TAS5028A accepts master clock rates of 128, 192, 256, 384, 512, and 768 Fs. The
TAS5028A accepts a 64-Fs bit clock.
Power Supply
RESET
PDN
PWM Control
MUTE
HP_SEL
BKND_ERR
Soft Soft
Tone Vol
DC
De
Interpo
SRC NS PWM
Block Emph late
0
Det
Soft Soft
Tone Vol
DC
De
Interpo
SRC NS PWM
Block Emph late
0
Det
Soft Soft
Tone Vol
0
Det
Soft Soft
Tone Vol
0
Det
Soft Soft
Tone Vol
0
Det
Soft Soft
Tone Vol
0
Det
0
Det
DC
De
Interpo
SRC NS PWM
Block Emph late
DC
De
Interpo
SRC NS PWM
Block Emph late
PWM AP& AM2 R
PWM AP& AM3 L Sur
PWM AP& AM4 R Sur
PWM AP& Am7 Center
DC
De
Interpo
SRC NS PWM
Block Emph late
PWM AP& AM8 Sub woofer
Soft Soft
Tone Vol
DC
De
Interpo
SRC NS PWM
Block Emph late
PWM AP& AM5 L Back Sur
PWM L Line Out
Soft Soft
Tone Vol
DC
De
Interpo
SRC NS PWM
Block Emph late
PWM AP& AM6 R Back Sur
PWM R Line Out
4
9
DC
De
Interpo
SRC NS PWM
Block Emph late
PWM AP& AM1 L
Output Control
0
Det
8
PWM_HPP& MR
PWM_HPP & ML
PWM Section
8 x 2 Crossbar Mixer
8 x 8 Crossbar Mixer
SCL
Serial
Cntrl
IF
DAP Control
SDA
Control
System Control
SDIN1
SDIN2
SDIN3
SDIN4
Clock, PLL, &
Serial Data I/F
Digital Audio Processor
MCLK
XTL_ OUT
XTL_ IN
PLL_FLTM
PLL_FLTP
OSC CAP
SCLK
LRCLK
8
8
8
8
VALID
Volume
Control
Figure 1−1. TAS5028A Functional Structure
SLES112 — June 2004
TAS5028A
1
Introduction
1.1
TAS5028A System Diagrams
Typical applications for the TAS5028A are 6- to 8-channel audio systems such as DVD receiver or AV receiver.
Figure 1−2 shows the basic system diagram of the DVD receiver.
AM
Texas Instruments
Digital Audio Amplifier
FM
Tuner
Power Supply
TAS5028A
DVD Loader
MPEG Decoder
Front-Panel Controls
Figure 1−2. Typical TAS5028A Application (DVD Receiver)
Figure 1−3 shows the recommended channel configuration when using the TAS5028A with the TAS5121
power stage. Note that each channel is normally dedicated to a particular function.
LEFT
−
+
TAS5121
PWM_P_1
TAS5121
PWM_M_1
−
PWM_HPML
TAS5121
RIGHT
+
PWM_HPPL
−
PWM_HPMR PWM_M_2
+
TAS5028A
Lineout Right
PWM to Analog
(Headphone
Level)
Headphone
Out Right
Headphone
Out Left
HW Control
& Status
Clocks
SDIN1,2,3,4
(8 chan. PCM)
PWM to Analog
(Line Level)
I2C Control
& Status
Lineout Left
LEFT
SURROUND
PWM_P_2
TAS5121
PWM_M_4
TAS5121
−
PWM_HPPR
+
PWM_M_3
−
PWM_P_3
RIGHT
SURROUND
CENTER
+
PWM_P_4
PWM_M_8
PWM_P_5
PWM_P_5
PWM_M_6
PWM_M_6
PWM_P_6
PWM_P_6
−
PWM_M_7
TAS5121
TAS5121
+
PWM_P_7
TAS5121
−
+
PWM_P_8
−
SUBWOOFER
PWM_M_5
+
LEFT BACK
SURROUND
PWM_M_5
RIGHT BACK
SURROUND
Figure 1−3. Recommended TAS5028A + TAS5121 Channel Configuration
2
TAS5028A
SLES112 — June 2004
Introduction
1.2
TAS5028A Features
1.2.1 Audio Input / Output
•
Automatic Master Clock Rate and Data Sample Rate Detection
•
Eight Serial Audio Input Channels
•
Eight PWM Audio Output Channels Configurable as Six Channels With Stereo Line Out or Eight Channels
•
Line Output is a PWM Output to Drive an External Differential Input Operational Amplifier
•
Headphone PWM Output to Drive an External Differential Amplifier Like the TPA112
•
PWM Outputs Support Single Ended and Bridge Tied Loads
•
32-, 38-, 44.1-, 48-, 88.2-, 96-, 176.4-, and 192-kHz Sampling Rates
•
Data Formats: 16-, 20-, or 24-bit input Data Left, Right and I2S,
•
64 x Fs Bit Clock Rate
•
128, 192, 256, 384, 512, and 768 x Fs Master Clock Rates (Up to a Maximum of 50 MHz)
1.2.2 Audio Processing
•
48-Bit Processing Architecture With 76 bits of Precision for Most Audio Processing Features
•
Volume Control Range +36 dB to – 127 dB
−
Master Volume Control Range of +18 dB to –100 dB
−
Eight Individual Channel Volume Control Range of +18-dB to −127-dB
•
Programmable Soft Volume and Mute Update Rates
•
Four Bass and Treble Tone Controls with ±18-dB Range, Selectable Corner Frequencies, and 2nd Order
Slopes
−
L, R, and C
−
LS, RS
−
LR, RR
−
Sub
•
Full 8x8 Input Crossbar Mixer. Each Signal Processing Channel Input Can Be Any Ratio of the Eight Input
Channels
•
8x2 Output Mixer – Channels 1−6. Each Output Can Be Any Ratio of Any Two Signal Processed Channels
•
8x3 Output mixer – Channels 7 and 8. Each Output can be Any Ratio of Any Three Signal Processed
Channels
•
Three Coefficient Sets Stored on the Device Can be Selected Manually or Automatically (Based on
Specific Data Rates)
•
DC Blocking Filters
•
Able to Support a Variety of Bass Management Algorithms
SLES112 — June 2004
TAS5028A
3
Introduction
1.2.3 PWM Processing
•
32-Bit Processing PWM Architecture With 40 Bits of Precision
•
8x Oversampling With 5th Order Noise Shaping at 32 – 48 kHz, 4x Oversampling at 88.2 kHz, and 96 kHz
and 2x Oversampling at 176.4 kHz and 192 kHz
•
>102-dB Dynamic Range
•
THD+N < 0.1%
•
20 – 20-kHz Flat Noise Floor for 44.1-, 48-, 88.2-, 96-, 176.4-, and 192-kHz Data Rates
•
Digital De-emphasis for 32-, 44.1-, and 48-kHz Data Rates
•
Flexible Automute Logic With Programmable Threshold and Duration for Noise Free Operation
•
Intelligent AM Interference Avoidance System Provides Clear AM Reception
•
Adjustable Modulation Limit
1.2.4 General Features
4
•
Automated Operation With an Easy to Use Control Interface
•
I2C Serial Control Slave Interface
•
Integrated AM Interference Avoidance Circuitry
•
Single 3.3-V Power Supply
•
64-Pin TQFP Package
•
5-V Tolerant Inputs
TAS5028A
SLES112 — June 2004
Introduction
1.3
Physical Characteristics
1.3.1 Terminal Assignments
RESERVED
MCLK
PWM_HPPR
PWM_HPMR
PWM_HPPL
PWM_HPML
PWM_P_6
PWM_M_6
PWM_P_5
PWM_M_5
DVDD_PWM
DVSS_PWM
PWM_P_8
PWM_M_8
PWM_P_7
PWM_M_7
TQFP PACKAGE
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VRA_PLL
PLL_FLT_RET
PLL_FLTM
PLL_FLTP
AVSS
AVSS
VRD_PLL
AVSS_PLL
AVDD_PLL
VBGAP
RESET
HP_SEL
PDN
MUTE
DVDD
DVSS
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
VR_PWM
PWM_P_4
PWM_M_4
PWM_P_3
PWM_M_3
PWM_P_2
PWM_M_2
PWM_P_1
PWM_M_1
VALID
DVSS
BKND_ERR
DVDD
DVSS
DVSS
VR_DIG
VR_DPLL
OSC_CAP
XTL_OUT
XTL_IN
RESERVED
RESERVED
RESERVED
SDA
SCL
LRCLK
SCLK
SDIN4
SDIN3
SDIN2
SDIN1
RESERVED
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
1.3.2 Ordering Information
TA
PLASTIC 64-PIN PQFP (PN)
0°C to 70°C
TAS5028APAG
1.3.3 Terminal Descriptions
TERMINAL
NO.
NAME
I/O
5-V
TOLERANT
TERMINATION
DESCRIPTION
1
VRA_PLL
2
PLL_FLT_RET
AO
PLL external filter return
3
PLL_FLTM
AO
PLL negative input. Connected to PLL_FLT_RTN via an RC network
4
PLL_FLTP
AI
PLL positive input. Connected to PLL_FLT_RTN via an RC network
5
AVSS
P
Analog ground
6
AVSS
P
Analog ground
SLES112 — June 2004
Voltage reference for PLL analog supply 1.8 V. A pin-out of the internally regulated
1.8-V power used by PLL logic. A 0.1-µF low ESR capacitor should be connected
between this terminal and AVSS_PLL. This terminal must not be used to power
external devices.
TAS5028A
5
Introduction
TERMINAL
NO.
6
NAME
I/O
5-V
TOLERANT
TERMINATION
DESCRIPTION
7
VRD_PLL
P
Voltage reference for PLL digital supply 1.8 V. A pin-out of the internally regulated
1.8-V power used by PLL logic. A 0.1-µF low ESR capacitor should be connected
between this terminal and AVSS_PLL. This terminal must not be used to power
external devices.
8
AVSS_PLL
P
Analog ground for PLL. This terminal should reference the same ground as power
terminal DVSS, but to achieve low PLL jitter; ground noise at this terminal must be
minimized. The availability of the AVSS terminal allows a designer to use
optimizing techniques such as star ground connections, separate ground planes,
or other quiet ground distribution techniques to achieve a quiet ground reference
at this terminal.
9
AVDD_PLL
P
3.3-V analog power supply for PLL This terminal can be connected to the same
power source used to drive power terminal DVSS, but to achieve low PLL jitter, this
terminal should be bypassed to AVSS_PLL with a 0.1-µF low-ESR capacitor.
10
VBGAP
P
Band gap voltage reference. A pin-out of the internally regulated 1.2-V reference.
Typically has a 1-nF low ESR capacitor between VBGAP and AVSS_PLL. This
terminal must not be used to power external devices.
11
RESET
DI
5V
Pullup
System reset input, active low. A system reset is generated by applying a logic low
to this terminal. RESET is an asynchronous control signal that restores the
TAS5028A to its default conditions, sets the valid output low, and places the PWM
in the hard mute (M) state. Master volume is immediately set to full attenuation.
Upon the release of RESET, if PDN is high, the system performs a 4−5 ms. device
initialization and sets the volume at mute.
12
HP_SEL
DI
5V
Pullup
Headphone in/out selector. When a logic low is applied, the headphone is selected
(speakers are off). When a logic high is applied, speakers are selected –
headphone is off.
13
PDN
DI
5V
Pullup
Power down, active low. PDN powers down all logic and stops all clocks whenever
a logic low is applied. The internal parameters are preserved through a power down
cycle, as long as a RESET is not active. The duration for system recovery from
power down is 100 ms.
14
MUTE
DI
5V
Pullup
Soft mute of outputs, active low (Muted signal = a logic low, normal operation = a
logic high) The mute control provides a noiseless volume ramp to silence.
Releasing mute provides a noiseless ramp to previous volume.
15
DVDD
P
Digital power 3.3-V supply for digital core and most of I/O buffers
16
DVSS
P
Digital ground for digital core and most of I/O buffers
17
VR_DPLL
P
Voltage reference for digital PLL supply 1.8 V. A pin-out of the internally regulated
1.8-V power used by digital PLL logic. A 0.1−µF low ESR capacitor should be
connected between this terminal and DVSS_CORE. This terminal must not be
used to power external devices.
18
OSC_CAP
AO
Oscillator capacitor
19
XTL_OUT
AO
XTL_OUT and XTL_IN are the only LVCMOS terminals on the device. They
provide a reference clock for the TAS5028A via use of an external fundamental
mode crystal. XTL_OUT is the 1.8-V output drive to the crystal. See Note 4 for the
recommended crystal type.
20
XTL_IN
AI
XTL_OUT and XTL_IN are the only LVCMOS terminals on the device. They
provide a reference clock for the TAS5028A via use of an external fundamental
mode crystal. XTL_IN is the 1.8-V input port for the oscillator circuit. See Note 4
for the recommended crystal type.
21
RESERVED
Connect to digital ground
22
RESERVED
Connect to digital ground
23
RESERVED
Connect to digital ground
24
SDA
DIO
5V
I2C serial control data interface input / output
25
SCL
DI
5V
I2C serial control clock input output
26
LRCLK
DI
5V
Serial audio data left / right clock (sampling rate clock)
27
SCLK
DI
5V
Serial audio data clock (shift clock) SCLKIN is the serial audio port (SAP) input data
bit clock that is supplied to the serial bit clock to other I2S bus.
TAS5028A
SLES112 — June 2004
Introduction
TERMINAL
NO.
NAME
I/O
5-V
TOLERANT
TERMINATION
DESCRIPTION
28
SDIN4
DI
5V
Pulldown
Serial audio data 4 input is one of the serial data input ports. SDIN4 supports four
discrete (stereo) data formats and is capable of inputting data at 64 Fs.
29
SDIN3
DI
5V
Pulldown
Serial audio data 3 input is one of the serial data input ports. SDIN3 supports four
discrete (stereo) data formats and is capable of inputting data at 64 Fs.
30
SDIN2
DI
5V
Pulldown
Serial audio data 2 input is one of the serial data input ports. SDIN2 supports four
discrete (stereo) data formats and is capable of inputting data at 64 Fs.
31
SDIN1
DI
5V
Pulldown
Serial audio data 1 input is one of the serial data input ports. SDIN1 supports four
discrete (stereo) data formats and is capable of inputting data at 64 Fs.
32
RESERVED
O
33
VR_DIG
P
Voltage reference for digital core supply 1.8 V. A pin-out of the internally regulated
1.8-V power used by digital core logic. A 0.47-µF low ESR capacitor should be
connected between this terminal and DVSS. This terminal must not be used to
power external devices
34
DVSS
P
Digital ground
35
DVSS
P
Digital ground
36
DVDD
P
3.3-V digital power supply
37
BKND_ERR
DI
38
DVSS
P
39
VALID
DO
Output indicating validity of PWM outputs active high
40
PWM_M_1
DO
PWM 1 output (differential –)
41
PWM_P_1
DO
PWM 1 output (differential +)
42
PWM_M_2
DO
PWM 2 output (differential –)
43
PWM_P_2
DO
PWM 2 output (differential +)
44
PWM_M_3
DO
PWM 3 output (differential –)
45
PWM_P_3
DO
PWM 3 output (differential +)
46
PWM_M_4
DO
PWM 4 output (differential –)
47
PWM_P_4
DO
PWM 4 output (differential +)
48
VR_PWM
P
49
PWM_M_7
DO
PWM 7 (Line out L) output (differential –)
50
PWM_P_7
DO
PWM 7 (Line out L) output (differential +)
51
PWM_M_8
DO
PWM 8 (Line out R) output (differential –)
52
PWM_P_8
DO
PWM 8 (Line out R) output (differential +)
53
DVSS_PWM
54
DVDD_PWM
55
PWM_M_5
DO
PWM 5 output (differential –)
56
PWM_P_5
DO
PWM 5 output (differential +)
57
PWM_M_6
DO
PWM 6 output (differential –)
58
PWM_P_6
DO
PWM 6 output (differential +)
59
PWM_HPML
DO
PWM left channel headphone (differential –)
60
PWM_HPPL
DO
PWM left channel headphone (differential +)
61
PWM_HPMR
DO
PWM right channel headphone (differential –)
62
PWM_HPPR
DO
PWM right channel headphone (differential +)
SLES112 — June 2004
Pullup
Active low. A backend error sequence is generated by applying logic low to this
terminal. The BKND_ERR results in all system parameters unaffected, while all
H-bridge drive signals going to a hard mute (M) state.
Digital ground
Voltage reference for digital PWM core supply 1.8 V. A pin-out of the internally
regulated 1.8-V power used by digital PWM core logic. A 0.1-µF low ESR capacitor
should be connected between this terminal and DVSS_PWM. This terminal must
not be used to power external devices.
P
Digital ground for PWM
P
3.3-V digital power supply for PWM
TAS5028A
7
Introduction
TERMINAL
NO.
NAME
63
MCLK
64
RESERVED
I/O
5-V
TOLERANT
TERMINATION
DI
5V
Pulldown
DESCRIPTION
MCLK is a 3.3-V clock master clock input. The input frequency of this clock can
range from 4 MHz to 50 MHz.
Connect to digital ground
NOTES: 1. Type: A = analog; D = 3.3-V digital; P = power / ground / decoupling; I = input; O = output
2. All pullups are 20-µA weak pullups and all pulldowns are 20-µA weak pull downs. The pullups and pulldowns are included to assure
proper input logic levels if the terminals are left unconnected (pullups => logic 1 input; pulldowns => logic 0 input). Devices that drive
inputs with pull ups must be able to sink 20 µA, while maintaining a logic 0 drive level. Devices that drive inputs with pulldowns must
be able to source 20 µA, while maintaining a logic ‘1’ drive level.
3. If desired, low ESR capacitance values can be implemented by paralleling two or more ceramic capacitors of equal value. Paralleling
capacitors of equal value provide an extended high frequency supply decoupling. This approach avoids the potential of producing
parallel resonance circuits that have been observed when paralleling capacitors of different values.
4. 13.5-MHz crystal (HCM49)
1.4
TAS5028A Functional Description
Figure 1−4 shows the TAS5028A functional structure. The next sections describe the TAS5028A functional
blocks:
•
Power Supply
•
Clock, PLL, and Serial Data Interface
•
Serial Control Interface
•
Device Control
•
Digital Audio Processor (DAP)
•
Pulse Width Modulation (PWM) Processor
1.4.1 Power Supply
The power supply section contains supply regulators that provide analog and digital regulated power for
various sections of the TAS5028A. The analog supply supports the analog PLL, while digital supplies support
the digital PLL, the digital audio processor (DAP), the pulse width modulator (PWM), and the output control
(reclocker). The regulators can also be turned off when terminals RESET and PDN are both low.
1.4.2 Clock, PLL, and Serial Data Interface
The TAS5028A is a clock slave only device and it requires the use of an external 13.5 MHz crystal. It accepts
MCLK, SCLK, and LRCLK as inputs only.
The TAS5028A uses the external crystal to provide a time base for:
•
Continuous data and clock error detection and management
•
Automatic data rate detection and configuration
•
Automatic MCLK rate detection and configuration (automatic bank switching)
•
Supporting I2C operation/ communication while MCLK is absent
The TAS5028A automatically handles clock errors, data rate changes, and master clock frequency changes
without requiring intervention from an external system controller. This feature significantly reduces system
complexity and design.
8
TAS5028A
SLES112 — June 2004
Introduction
1.4.2.1
Serial Audio Interface
The TAS5028A operates as a slave only / receive only serial data interface in all modes. The TAS5028A has
four PCM serial data interfaces to permit eight channels of digital data to be received though the SDIN1,
SDIN2, SDIN3, and SDIN4 inputs. The serial audio data is in MSB first, two’s complement format.
The serial data input interface of the TAS5028A can be configured in right justified, I2S, or left-justified modes.
The serial data interface format is specified using the I2C data interface control register. The supported formats
and word lengths are shown in Table 1−1.
Table 1−1. Serial Data Formats
RECEIVE SERIAL DATA
INTERFACE FORMAT
WORD LENGTHS
Right justified
16
Right justified
20
Right justified
24
I2S
16
I2S
20
I2S
24
Left Justified
16
Left Justified
20
Left Justified
24
Serial data is input on SDIN1, SDIN2, SDIN3, and SDIN4. The TAS5028A accepts 32-, 38-, 44.1-, 48-, 88.2-,
96-, 176.4-, and 192-kHz serial data in 16-, 20-, or 24-bit data in left, right, and I2S serial data formats using
a 64-Fs SCLK clock and a 128, 192, 256, 384, 512, or 768 x Fs MCLK rates (up to a maximum of 50 MHz).
The parameters of this clock and serial data interface are I2C configurable.
1.4.3 I 2C Serial Control Interface
The TAS5028A has an I2C serial control slave interface (address 0x36) to receive commands from a system
controller. The serial control interface supports both normal-speed (100 kHz) and high-speed (400 kHz)
operations without wait states. Since the TAS5028A has a crystal time base, this interface operates even when
MCLK is absent.
The serial control interface supports both single byte and multi-byte read / write operations for status registers
and the general control registers associated with the PWM. However, for the DAP data processing registers,
the serial control interface also supports multiple byte (4 byte) write operations.
The I2C supports a special mode which permits I2C write operations to be broken up into multiple data write
operations that are multiples of 4 data bytes. These are 6 byte, 10 byte, 14 byte, 18 byte ... etc write operations
that are composed of a device address, read/write bit, and subaddress and any multiple of 4 bytes of data.
This permits the system to incrementally write large register values without blocking other I2C transactions.
In order to use this feature, the first chunk of data is written to the target I2C address and each chunk of
subsequent data is written to a special append register (0xFE), until all the data is written and a stop bit is sent.
An incremental read operation is not supported.
1.4.4 Device Control
The TAS5028A control section provides the control and sequencing for the TAS5028A. The device control
provides both high and low level control for the serial control interface, clock and serial data interfaces, digital
audio processor, and pulse width modulator sections.
1.4.5 Digital Audio Processor (DAP)
The DAP arithmetic unit is used to implement all audio processing functions – soft volume, bass and treble
processing, and input and output mixing. Figure 1−6 shows the TAS5028A DAP architecture.
SLES112 — June 2004
TAS5028A
9
Introduction
The DAP accepts 24-bit data signal from the serial data interface and outputs 32-bit data to the PWM section.
The DAP supports two configurations, one for 32−kHz to 96−kHz data and one for 176.4−kHz to 192−kHz data.
1.4.5.1
TAS5028A Audio Processing Configurations
The 32−kHz–96−kHz configuration supports eight channels of data processing that can be configured as eight
channels or six channels with two channels for separate stereo line outputs.
The 176.4 − 192 kHz configuration supports three channels of signal processing with five channels passed
though (or derived from the three processed channels).
To efficiently support the processing requirements of both multi-channel 32 – 96-kHz data and the two channel
176.4 and 192-kHz data, the TAS5028A supports separate audio processing features for 32 –96-kHz data
rates and for 176.4 and 192 kHz. See Table 2 for a summary of TAS5028A processing feature sets.
1.4.5.2
TAS5028A Audio Signal Processing Functions
The DAP provides 7 primary signal processing functions.
1. The data processing input has a full 8x8 input crossbar mixer. This enables each input to be any ratio of
the eight input channels.
2. Two I2C programmable threshold detectors in each channel support automute.
3. Four soft bass and treble tone controls with ±18 dB range, programmable corner frequencies, and 2nd
order slopes. In 8-channel mode, bass and treble controls are normally configured as follows:
a. Bass and treble 1: channel 1 (Left), channel 2 (right), and channel 7 (center)
b. Bass and treble 2: channel 3 (left surround) and channel 4 (right surround)
c.
Bass and treble 3: channel 5 (left back surround) and channel 6 (right back surround)
d. Bass and treble 4: channel 8 (subwoofer)
4. Individual channel and master volume controls. Each control provides an adjustment range of +18 dB to
–127 dB. This permits a total volume device control range of +36 dB to –127 dB plus mute. The master
volume control can be configured to control six or eight channels. The DAP soft volume and mute update
interval is I2C programmable. The update is performed at a fixed rate regardless of the sample rate.
5. 8x2 output mixer (channels 1−6). Each output can be any ratio of any two signal processed channels.
6. 8x3 output mixer (channels 7 and 8). Each output can be any ratio of any three signal processed channels.
7. The DAP maintains three sets of coefficient banks that are used to maintain separate sets of sample rate
dependent parameters for the tone controls in RAM. These can be set to be automatically selected for
one or more data sample rates or can be manually selected under I2C program control. This feature
enables coefficients for different sample rates to be stored in the TAS5028A and then select when needed.
10
TAS5028A
SLES112 — June 2004
Introduction
Table 1−2. TAS5028A Audio Processing Feature Sets
FEATURE
Signal processing
channels
32 − 96 kHz
8 CHANNEL FEATURE SET
32 − 96 kHz
6 + 2 LINE OUT FEATURE SET
176.4- AND 192-kHz
FEATURE SET
8
6+2
3
Pass through channels
Master volume
N/A
1 for eight channels
Individual channel
volume controls
Bass and treble tone
controls
Input output
mapping/mixing
5
1 for six channels
1 for three channels
8
3
Four Bass and Treble tone controls
with ±18 dB range, programmable
corner frequencies, and 2nd order
slopes
Four Bass and Treble tone controls
with ±18 dB range, programmable
corner frequencies, and 2nd order
slopes
L, R and C (Ch 1, 2, and 7)
L, R and C (Ch 1, 2, and 7)
Two Bass and Treble tone controls
with ±18 dB range, programmable
corner frequencies, and 2nd order
slopes
LS, RS (Ch 3 and 4)
LS, RS (Ch 3 and 4)
L and R (Ch 1 and 2)
LBS, RBS (Ch 5 and 6)
Sub, (Ch 8)
Sub (Ch 8)
Sub (Ch 8)
Line L and R (Ch 5 and 6)
Each of the eight signal-processing channels input can be any ratio of the
eight input channels.
Each of the eight outputs can be any ratio of any two processed channels.
Each of the three
signal-processing channels or the
five pass-though channels inputs
can be any ratio of the eight input
channels.
Each of the eight outputs can be
any ratio of any of the three
processed or five bypass
channels.
DC blocking filters
Eight channels
(Implemented in PWM
Section)
Digital de-emphasis
(Implemented in PWM
Section)
Eight channels for 32 kHz, 44.1 kHz,
and 48 kHz
Number of Coefficient
sets Stored
1.5
Six channels for 32 kHz, 44.1 kHz,
and 48 kHz
N/A
Three additional coefficient sets can be stored in memory
TAS5028A DAP Architecture
1.5.1 TAS5028A DAP Architecture Diagrams
Figure 1−4 shows the TAS5028A DAP architecture for Fs = 96 kHz. Note the TAS5028A bass management
architecture shown in channels 1, 2, 7, and 8. Note that the I2C registers are shown to help the designer
configure the TAS5028A.
Figure 1−5 shows the TAS5028A architecture for Fs = 176.4 kHz or Fs = 192 kHz. Note that only channels
1, 2, and 8 contain all the features. Channels 3−7 are pass-through except for master volume control.
Figure 1−6 shows TAS5028A detailed channel processing. The output mixer is 8X2 for channels 1−6 and *X3
for channels 7 and 8.
SLES112 — June 2004
TAS5028A
11
Introduction
Default Input Is BOLD
SDIN1−L(L)
A
A
B
B
C
C
D
D
E
E
F
G
F
H
G
H
SDIN1−R (R)
SDIN2−L (LS)
SDIN2−R (RS)
SDIN3−L (LBS)
SDIN3−R (RBS)
SDIN4−L (C)
SDIN4−R (LFE)
IP Mixer 1
(I2C 0x41)
Master Vol
(0xD9)
Bass &
Treble 1
(0xDA−
0xDD)
DAP1
Volume
(0xD1)
OP Mixer 1
(I2C 0xAA)
8X2 Output
Mixer
L to
PWM1
OP Mixer 2
(I2C 0xAB)
8X2 Output
Mixer
R to
PWM2
OP Mixer 3
(I2C 0xAC)
8X2 Output
Mixer
LS to
PWM3
OP Mixer 4
(I2C 0xAD)
8X2 Output
Mixer
RS to
PWM4
OP Mixer 5
(I2C 0xAE)
8X2 Output
Mixer
LBS to
PWM5
OP Mixer 6
(I2C 0xAF)
8X2 Output
Mixer
RBS to
PWM6
OP Mixer 7
(I2C 0xB0)
8X3 Output
Mixer
C to
PWM7
OP Mixer 8
(I2C 0xB1)
8X3 Output
Mixer
Sub to
PWM8
Master Vol
(0xD9)
SDIN1−L(L)
SDIN1−R(R)
SDIN2−L (LS)
SDIN2−R (RS)
SDIN3−L (LBS)
SDIN3−R (RBS)
SDIN4−L (C)
SDIN4−R (LFE)
A
A
B
B
C
C
D
D
E
E
F
G
F
H
G
H
IP Mixer 2
(I2C 0x42)
Bass &
Treble 1
(0xDA−
0xDD)
DAP2
Volume
(0xD2)
Master Vol
(0xD9)
SDIN1−L(L)
SDIN1−R(R)
SDIN2−L(LS)
SDIN2−R (RS)
SDIN3−L (LBS)
SDIN3−R (RBS)
SDIN4−L (C)
SDIN4−R (LFE)
A
A
B
B
C
C
D
D
E
E
F
G
F
H
G
H
IP Mixer 3
(I2C 0x43)
Bass &
Treble 2
(0xDA−
0xDD)
DAP3
Volume
(0xD3)
Master Vol
(0xD9)
SDIN1−L(L)
SDIN1−R(R)
SDIN2−L(LS)
SDIN2−R(RS)
SDIN3−L (LBS)
SDIN3−R (RBS)
SDIN4−L (C)
SDIN4−R (LFE)
A
A
B
B
C
C
D
D
E
E
F
G
F
H
G
H
IP Mixer 4
(I2C 0x44)
Bass &
Treble 2
(0xDA−
0xDD)
DAP4
Volume
(0xD4)
Master Vol
(0xD9)
SDIN1−L(L)
SDIN1−R(R)
SDIN2−L(LS)
SDIN2−R (RS)
SDIN3−L(LBS)
SDIN3−R (RBS)
SDIN4−L (C)
SDIN4−R (LFE)
SDIN1−L(L)
SDIN1−R(R)
SDIN2−L(LS)
SDIN2−R (RS)
SDIN3−L (LBS)
SDIN3−R(RBS)
SDIN4−L (C)
SDIN4−R (LFE)
A
A
B
B
C
C
D
D
E
E
F
G
F
H
G
H
IP Mixer 5
(I2C 0x45)
Bass &
Treble 3
(0xDA−
0xDD)
DAP5
Volume
(0xD5)
Master Vol
(0xD9)
IP Mixer 6
(I2C 0x46)
Bass &
Treble 3
(0xDA−
0xDD)
DAP6
Volume
(0xD6)
Master Vol
(0xD9)
SDIN1−L(L)
SDIN1−R(R)
SDIN2−L(LS)
SDIN2−R (RS)
SDIN3−L (LBS)
SDIN3−R(RBS)
SDIN4−L(C)
SDIN4−R (LFE)
SDIN1−L(L)
SDIN1−R(R)
SDIN2−L(LS)
SDIN2−R (RS)
SDIN3−L (LBS)
SDIN3−R(RBS)
SDIN4−L (C)
A
A
B
B
C
C
D
D
E
E
F
G
F
H
G
H
A
A
B
B
C
C
D
D
E
E
F
G
F
H
G
H
IP Mixer 7
(I2C 0x47)
Bass &
Treble 1
(0xDA−
0xDD)
DAP7
Volume
(0xD7)
Master Vol
(0xD9)
SDIN4−R(LFE)
A
A
B
B
C
C
D
D
E
E
F
G
F
H
G
H
IP Mixer 8
(I2C 0x48)
Bass &
Treble 4
(0xDA−
0xDD)
DAP8
Volume
(0xD8)
Figure 1−4. TAS5028A DAP Architecture With I2C Registers (Fs ≤ 96 kHz)
12
TAS5028A
SLES112 — June 2004
Introduction
Default input is BOLD
A
A
B
B
C
C
D IP Mixer 1
D
E
E
F (I2C 0x41)
G
F
H
G
H
SDIN1−L (L)
SDIN1−R (R)
SDIN2−L (LS)
SDIN2−R (RS)
SDIN3−L (LBS)
SDIN3−R (RBS)
SDIN4−L (C)
SDIN4−R (LFE)
SDIN1−L (L)
A
A
B
B
C
C
D IP Mixer 2
D
E
E
F (I2C 0x42)
G
F
H
G
H
SDIN1−R (R)
SDIN2−L (LS)
SDIN2−R (RS)
SDIN3−L (LBS)
SDIN3−R (RBS)
SDIN4−L (C)
SDIN4−R (LFE)
SDIN1−L (L)
SDIN1−R (R)
Master Vol
(0xD9)
Bass &
Treble 1
(0xDA−
0xDD)
SDIN2−R (RS)
SDIN3−L (LBS)
SDIN3−R (RBS)
SDIN4−L (C)
SDIN4−R (LFE)
SDIN1−L (L)
SDIN1−R (R)
SDIN2−L (LS)
SDIN2−R (RS)
SDIN3−L (LBS)
SDIN3−R (RBS)
SDIN4−L (C)
SDIN4−R (LFE)
SDIN1−L (L)
SDIN1−R (R)
SDIN2−L (LS)
SDIN2−R (RS)
SDIN3−L (LBS)
SDIN3−R (RBS)
SDIN4−L (C)
SDIN4−R (LFE)
SDIN1−L (L)
SDIN1−R (R)
SDIN2−L (LS)
SDIN2−R (RS)
SDIN3−L (LBS)
SDIN3−R (RBS)
SDIN4−L (C)
SDIN4−R (LFE)
Bass &
Treble 1
(0xDA−
0xDD)
SDIN4−L (C)
SDIN4−R (LFE)
SDIN1−L (L)
SDIN1−R (R)
SDIN2−L (LS)
SDIN2−R (RS)
SDIN3−L (LBS)
SDIN3−R (RBS)
SDIN4−L (C)
SDIN4−R (LFE)
DAP2
Volume
(0xD2)
OP Mixer 2
(I2C 0xAB)
8X2 Output
Mixer
R to
PWM2
OP Mixer 3
(I2C 0xAC)
8X2 Output
Mixer
LS to
PWM3
Master Vol
(0xD9)
A
A
B
B
C
C
D IP Mixer 4
D
E
E
F (I2C 0x44)
G
F
H
G
H
OP Mixer 4
(I2C 0xAD)
8X2 Output
Mixer
RS to
PWM4
Master Vol
(0xD9)
A
A
B
B
C
C
D IP Mixer 5
D
E
E
F (I2C 0x45)
G
F
H
G
H
OP Mixer 5
(I2C 0xAE)
8X2 Output
Mixer
LBS to
PWM5
Master Vol
(0xD9)
A
A
B
B
C
C
D IP Mixer 6
D
E
E
F (I2C 0x46)
G
F
H
G
H
A
A
B
B
C
C
D IP Mixer 8
D
E
E
F (I2C 0x48)
G
F
H
G
H
L to
PWM1
Master Vol
(0xD9)
OP Mixer 6
(I2C 0xAF)
8X2 Output
Mixer
RBS to
PWM6
Master Vol
(0xD9)
A
A
B
B
C
C
D IP Mixer 7
D
E
E
F (I2C 0x47)
G
F
H
G
H
SDIN1−L (L)
SDIN1−R (R)
SDIN2−L (LS)
SDIN2−R (RS)
SDIN3−L (LBS)
SDIN3−R (RBS)
(0xD1)
OP Mixer 1
(I2C 0xAA)
8X2 Output
Mixer
Master Vol
(0xD9)
A
A
B
B
C
C
D
D IP Mixer 3
E
E
F (I2C 0x43)
G
F
H
G
H
SDIN2−L (LS)
DAP1
Volume
OP Mixer 7
(I2C 0xB0)
8X3 Output
Mixer
C to
PWM7
Master Vol
(0xD9)
Bass &
Treble 4
(0xDA−
0xDD)
DAP8
Volume
(0xD8)
OP Mixer 8
(I2C 0xB1)
8X3 Output
Mixer
Sub to
PWM8
Figure 1−5. TAS5028A Architecture With I2C Registers (Fs = 176.4 kHz or Fs = 192 kHz)
SLES112 — June 2004
TAS5028A
13
Introduction
Master
Volume
A_to_ipmix
Left
SDIN1
Right
A
Channel
Volume
Bass and Treble
Bypass
B
B_to_ipmix
C_to_ipmix
Left
SDIN2
Right
C
Bass and
Treble
D_to_ipmix
E_to_ipmix
Left
SDIN3
Right
Output
Gain
Input Mixer
D
E
Left
Right
32-Bit
Trunc
Bass and Treble
In-Line
F
One or Two Other
Channel Outputs
From Seven Available
F_to_ipmix
G_to_ipmix
SDIN4
Output Mixer Sums
Any Two Or
Three Channels
G
PWM
Proc
PWM
Output
Volume
H
H_to_ipmix
Figure 1−6. TAS5028A Detailed Channel Processing
1.5.2 I 2C Coefficient Number Formats
The architecture of the TAS5028A is contained in ROM resources within the TAS5028A and cannot be altered.
However, mixer gain, level offset, and filter tap coefficients, which can be entered via the I2C bus interface,
provide a user with the flexibility to set the TAS5028A to a configuration that achieves the system level goals.
The firmware is executed in a 48-bit signed fixed-point arithmetic machine. The most significant bit of the 48-bit
data path is a sign bit, and the 47 lower bits are data bits. Mixer gain operations are implemented by multiplying
a 48-bit signed data value by a 28-bit signed gain coefficient. The 76-bit signed output product is then truncated
to a signed 48-bit number. Level offset operations are implemented by adding a 48-bit signed offset coefficient
to a 48-bit signed data value. In most cases, if the addition results in overflowing the 48-bit signed number
format, saturation logic is used. This means that if the summation results in a positive number that is greater
than 0x7FFF FFFF FFFF (the spaces are used to ease the reading of the hexadecimal number), the number
is set to 0x7FFF FFFF FFFF. If the summation results in a negative number that is less than
0x8000 0000 0000 0000, the number is set to 0x8000 0000 0000 0000.
1.5.2.1
28-Bit 5.23 Number Format
All mixer gain coefficients are 28-bit coefficients using a 5.23 number format. Numbers formatted as 5.23
numbers means that there are 5 bits to the left of the decimal point and 23 bits to the right of the decimal point.
This is shown in the Figure 1−7.
2−23 Bit
2−4 Bit
2−1 Bit
20 Bit
23 Bit
Sign Bit
S_xxxx.xxxx_xxxx_xxxx_xxxx_xxx
Figure 1−7. 5.23 Format
14
TAS5028A
SLES112 — June 2004
Introduction
The decimal value of a 5.23 format number can be found by following the weighting shown in Figure 1−8. If
the most significant bit is logic 0, the number is a positive number, and the weighting shown yields the correct
number. If the most significant bit is a logic 1, then the number is a negative number. In this case every bit must
be inverted, a 1 added to the result, and then the weighting shown in Figure 1−8 applied to obtain the
magnitude of the negative number.
23 Bit
22 Bit
20 Bit
2−1 Bit
2−4 Bit
2−23 Bit
(1 or 0) x 23 + (1 or 0) x 22 + … + (1 or 0) x 20 + (1 or 0) x 2−1 + … + (1 or 0) x 2−4 + … + (1 or 0) x 2−23
Figure 1−8. Conversion Weighting Factors—5.23 Format to Floating Point
Gain coefficients, entered via the I2C bus, must be entered as 32-bit binary numbers. The format of the 32-bit
number (4-byte or 8-digit hexadecimal number) is shown in Figure 1−9.
Fraction
Digit 6
Sign
Bit
Integer
Digit 1
u
u
u
u
Coefficient
Digit 8
S
x
x
x
Coefficient
Digit 7
Fraction
Digit 1
x. x
x
x
Coefficient
Digit 6
Fraction
Digit 2
x
x
x
x
Coefficient
Digit 5
Fraction
Digit 3
x
x
x
x
Coefficient
Digit 4
Fraction
Digit 4
x
x
x
x
Coefficient
Digit 3
Fraction
Digit 5
x
x
x
x
Coefficient
Digit 2
0
x
x
x
x
Coefficient
Digit 1
u = unused or don’t care bits
Digit = hexadecimal digit
Figure 1−9. Alignment of 5.23 Coefficient in 32-Bit I2C Word
As Figure 1−9 shows, the hex value of the integer part of the gain coefficient cannot be concatenated with the
hex value of the fractional part of the gain coefficient to form the 32-bit I2C coefficient. The reason is that the
28-bit coefficient contains 5 bits of integer, and thus the integer part of the coefficient occupies all of one hex
digit and the most significant bit of the second hex digit. In the same way, the fractional part occupies the lower
3 bits of the second hex digit, and then occupies the other five hex digits (with the eighth digit being the
zero-valued most significant hex digit).
1.5.2.2
48-Bit 25.23 Number Format
All level adjustment and threshold coefficients are 48-bit coefficients using a 25.23 number format. Numbers
formatted as 25.23 numbers means that there are 25 bits to the left of the decimal point and 23 bits to the right
of the decimal point. This is shown in Figure 1−10.
SLES112 — June 2004
TAS5028A
15
Introduction
2−23 Bit
2−10 Bit
2−1 Bit
20 Bit
216 Bit
222 Bit
223 Bit
Sign Bit
S_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx.xxxx_xxxx_xxxx_xxxx_xxxx_xxx
Figure 1−10. 25.23 Format
Figure 1−11 shows the derivation of the decimal value of a 48-bit 25.23 format number.
223 Bit
222 Bit
20 Bit
2−1 Bit
2−23 Bit
(1 or 0) x 223 + (1 or 0) x 222 + … + (1 or 0) x 20 + (1 or 0) x 2−1 + … + (1 or 0) x 2−23
Figure 1−11. Alignment of 5.23 Coefficient in 32-Bit I2C Word
Two 32-bit words must be sent over the I2C bus to download a level or threshold coefficient into the TAS5028A.
The alignment of the 48-bit, 25.23 formatted coefficient in the 8-byte (two 32-bit words) I2C word is shown in
Figure 1−12.
16
TAS5028A
SLES112 — June 2004
Introduction
Integer
Digit 4
(Bits 23 − 21)
Sign
Bit
Integer
Digit 1
u
u
u
u
u
Coefficient
Digit 16
u
u
u
u
Coefficient
Digit 15
u
u
u
Coefficient
Digit 14
u
u
u
u
Coefficient
Digit 13
S
x
x
x
Coefficient
Digit 12
Integer
Digit 2
x
x
x
x
Coefficient
Digit 11
Integer
Digit 3
x
x
x
x
Coefficient
Digit 10
x
x
Word 1
(Most
Significant
Word)
x
Coefficient
Digit 9
Integer
Digit 4
(Bit 20)
Fraction
Digit 6
Integer
Digit 5
x
x
x
x
Integer
Digit 6
x
x
Coefficient
Digit 8
x
x
x
Fraction
Digit 1
x. x
Coefficient
Digit 7
x
x
Coefficient
Digit 6
Fraction
Digit 2
x
x
x
x
Coefficient
Digit 5
Fraction
Digit 3
x
x
x
x
Coefficient
Digit 4
Fraction
Digit 4
x
x
x
x
Coefficient
Digit 3
Fraction
Digit 5
x
x
x
x
Coefficient
Digit 2
0
x
x
x
x
Word 2
(Least
Significant
Word)
Coefficient
Digit 1
u = unused or don’t care bits
Digit = hexadecimal digit
Figure 1−12. Alignment of 25.23 Coefficient in Two 32-Bit I2C Words
1.5.2.3
TAS5028A Audio Processing
The TAS5028A digital audio processing is designed such that noise produced by filter operations is
maintained below the smallest signal amplitude of interest, as shown in Figure 1−13. The TAS5028A achieves
this by increasing the precision of the signal representation substantially above the number of bits that are
absolutely necessary to represent the input signal.
Ideal Input
Possible Outputs
Maximum Signal
Amplitude
Overflow
Filter
Operation
Signal bits
input
Desired Output
Reduced
SNR signal
output
Values retained by
overflow bits
Signal bits
output
Noise Floor with no
additional precision
Noise Floor as a
result of additional
precision
Figure 1−13. TAS5028A Digital Audio Processing
SLES112 — June 2004
TAS5028A
17
Introduction
Similarly, the TAS5028A carries additional precision in the form of overflow bits to permit the value of
intermediate calculations to exceed the input precision without clipping. The TAS5028A advanced digital
audio processor achieves both of these important performance capabilities by using a high performance digital
audio processing architecture with a 48-bit data path, 28-bit filter coefficients, and a 76-bit accumulator.
1.6
Input Crossbar Mixer
The TAS5028A has a full 8x8 input crossbar mixer. This mixer permits each signal processing channel input
to be any ratio of any of the eight input channels. The control parameters for the input crossbar mixer are
programmable via the I2C interface. See Section 6.15,.
Gain Coefficient
28
Input 1
48
Gain Coefficient
28
48
Input 2
48
48
Gain Coefficient
28
SUM
48
Input 8
48
Figure 1−14. Input Crossbar Mixer
1.7
Bass and Treble Controls
From 32-kHz to 96-kHz data, the TAS5028A has four Bass and Treble tone controls. Each control has a
±18-dB control range with selectable corner frequencies and 2nd order slopes. These controls operate four
channel groups:
•
L, R, and C (channels 1, 2, and 7)
•
LS, RS (channels 3 and 4)
•
LBS, RBS (or alternately called L and R lineout.) (channels 5 and 6)
•
Sub (channel 8)
For 176.4 kHz and 192 kHz data, the TAS5028A has two bass and treble tone controls. Each control has a
±18-dB I2C control range with selectable corner frequencies and 2nd order slopes. These controls operate
two channel groups:
•
L and R
•
Sub
The bass and treble filters utilize a soft update rate that does not produce artifacts during adjustment.
18
TAS5028A
SLES112 — June 2004
Introduction
Table 1−3. Bass and Treble Filter Selections
FS
(kHz)
3-dB CORNER FREQUENCIES
FILTER
SET 1
FILTER
SET 1
FILTER
SET 2
FILTER
SET 2
FILTER
SET 3
FILTER
SET 3
FILTER
SET 4
BASS
TREBLE
BASS
TREBLE
BASS
TREBLE
BASS
FILTER
SET 4
FILTER
SET 5
FILTER
SET 5
TREBLE
BASS
TREBLE
32
42
917
83
1833
125
3000
146
3667
167
4333
38
49
1088
99
2177
148
3562
173
4354
198
5146
44.1
57
1263
115
2527
172
4134
201
5053
230
5972
48
63
1375
125
2750
188
4500
219
5500
250
6500
88.2
115
2527
230
5053
345
8269
402
10106
459
11944
96
125
2750
250
5500
375
9000
438
11000
500
13000
176.4
230
5053
459
10106
689
16538
804
20213
919
23888
192
250
5500
500
11000
750
18000
875
22000
1000
26000
The I2C registers that control Bass and Treble are:
1.8
•
Bass and treble by-pass register (0x89 – 0x90, channels 1−8)
•
Bass and treble slew rates (0xD0)
•
Bass filter sets 1−5 (0xDA)
•
Bass Filter Index (0xDB)
•
Treble filter sets 1−5 (0xDC)
•
Treble filter index (0xDD)
Volume, Automute, and Mute
The TAS5028A provides individual channel and master volume controls. Each control provides an adjustment
range of +18.0618 dB to –100 dB in 0.25 dB increments. This permits a total volume device control range of
+36 dB to –100 dB plus mute. The master volume control can be configured to control six or eight channels.
The TAS5028A has a master soft mute control that can be enabled by a terminal or I2C command. The device
also has individual channel soft mute controls that can are enabled via I2C.
The soft volume and mute update rates are programmable. The soft adjustments are performed using a soft
gain linear update with an I2C programmable linear step size at a fixed temporal rate. The linear soft gain step
size can be varied from 0.5 to 0.003906.
Table 1−4. Linear Gain Step Size
0.5
0.25
0.125
0.0625
0.03125
0.015625
0.007813
0.003906
Time to go from 36.124 db to −127 dB in ms
STEP SIZE (GAIN)
10.67
21.33
42.67
85.34
170.67
341.35
682.70
1365.4
Time to go from 18.062 db to −127 dB in ms
1.33
2.67
5.33
10.67
21.33
42.67
85.33
170.67
Time to go from 0 db to −127 dB in ms
0.17
0.33
0.67
1.33
2.67
5.33
10.67
21.33
SLES112 — June 2004
TAS5028A
19
Introduction
1.8.1 Automute and Mute
The TAS5028A has individual channel automute controls that are enabled via the I2C interface. There are two
separate detectors used to trigger the automute:
•
Input automute: All channels are muted when all 8 inputs to the TAS5028A are less in magnitude than the
input threshold value for a programmable amount of time.
•
Output automute: A single channel is muted when the output of the DAP section is less in magnitude than
the input threshold value for a programmable amount of time.
The detection period and thresholds for these two detectors are the same.
This time interval is selectable via I2C to be from 1 ms. to 110 ms. The increments of time are 1, 2, 3, 4, 5, 10,
20, 30, 40, 50, 60, 70, 80, 90, 100, and 110 ms. This interval is independent of the sample rate. The default
value is mask programmable.
The input threshold value is an unsigned magnitude that is expressed as a bit position. This value is adjustable
via I2C. The range of the input threshold adjustment is from below the LSB (bit position 0) to below bit position
12 in a 24 bit input data word (bit positions 8 to 20 in the DSPE). This provides an input threshold that can be
adjusted for 12 to 24 bits of data. The default value is mask programmable.
DVD Data Range
CD Data Range
24-Bit Input
32-Bit in DSPE
Representation
23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Threshold Range
Figure 1−15. Automute Threshold
The automute state is exited when the TAS5028A receives one sample that is greater that the output threshold.
The output threshold can be one of two values:
•
Equal to the input threshold
•
6 dB (one bit position) greater than the input threshold
The value for the output threshold is selectable via I2C. The default value is mask programmable.
The system latency enables the data value that is above the threshold to be preserved and output.
A mute command initiated by automute, master mute, individual I2C mute, the AM interference mute
sequence, or the bank switch mute sequence overrides an unmute command or a volume command. While
a mute command is activated, the commanded channels transition to the mute state. When a channel is
unmuted, it goes to the last commanded volume setting that has been received for that channel.
1.9
Output Mixer
The TAS5028A provides an 8×2 output mixer for channels 1, 2, 3, 4, 5, and 6. For channels 7 and 8 the
TAS5028A provides an 8×3 output mixer. These mixers allow each output to be any ratio of any two (three)
signal processed channels. The control parameters for the output crossbar mixer are programmable via the
I2C interface.
20
TAS5028A
SLES112 — June 2004
Introduction
Gain Coefficient
28
Select
Output
N
48
Gain Coefficient
28
Select
Output
N
48
Output
1, 2, 3, 4, 7 or 8
Output
5 or 6
48
48
Gain Coefficient
28
Select
Output
N
48
Gain Coefficient
28
Select
Output
N
48
48
48
Gain Coefficient
28
Select
Output
N
48
48
Figure 1−16. Output Mixers
1.10 PWM
The TAS5028A has eight channels of high performance digital PWM Modulators that are designed to drive
switching output stages (backends) in both single-ended (SE) and H-bridge (bridge tied load) configuration.
The TAS5028A device uses noise-shaping and sophisticated error correction algorithms to achieve high
power efficiency and high-performance digital audio reproduction. The TAS5028A uses an AD1 PWM
modulation combined with a 5th order noise shaper to provide a 102-dB SNR from 20 to 20 kHz.
The PWM section accepts 32-bit PCM data from the DAP and outputs eight PWM audio output channels
configurable as either:
•
Six channels to drive power stages + two channels to drive a differential input active filter to provide a
separately controllable stereo line out
•
Eight channels to drive power stages
The TAS5028A PWM section output supports both single-ended and bridge-tied loads.
The PWM section provides a headphone PWM output to drive an external differential amplifier like the
TPA112. The headphone circuit uses the PWM modulator for channels 1 and 2. The headphone will not
operate while the six or eight backend drive channels are operating. The headphone will be enabled via a
headphone select terminal or I2C command.
The PWM section has individual channel dc blocking filters that can be enabled and disabled. The filter cutoff
frequency is less than 1 Hz.
The PWM section has individual channel de-emphasis filters for 32, 44.1, and 48 kHz that can be enabled and
disabled.
SLES112 — June 2004
TAS5028A
21
Introduction
The interpolator, noise shaper, and PWM sections provide a PWM output with the following features:
•
Up to 8× oversampling.
−
8× at FS = 32 kHz, 38 kHz, 44.1 kHz, 48 kHz
−
4× at FS = 88.2 kHz, 96 kHz
−
2× at FS = 176.4 kHz, 192 kHz
•
5th order noise shaping
•
100-dB dynamic range 0 – 20 kHz (TAS5028A + TAS5111 system measured at speaker terminals)
•
THD < 0.01%
•
Adjustable maximum modulation limit of 93.8% to 99.2%
•
3.3-V digital signal
1.10.1
DC Blocking (High-Pass Enable / Disable)
Each input channel incorporates a first order digital high-pass filter to block potential dc components. The filter
–3 dB point is approximately 0.89-Hz at 44.1-kHz sampling rate. The high-pass filter can be enabled and
disabled via the I2C interface.
1.10.2
De-Emphasis Filter
For audio sources that have been pre-emphasized, a precision 50 µs/15 µs de-emphasis filter is provided to
support the sampling rates of 32 kHz, 44.1 kHz, and 48 kHz. Figure 1−17 shows a graph of the de-emphasis
filtering characteristics. De-emphasis is set using two bits in the system control register.
Response − dB
0
−10
3.18 (50 µs)
10.6 (15 µs)
Frequency − kHz
Figure 1−17. De-emphasis Filter Characteristics
1.10.3
AM Interference Avoidance
Digital amplifiers can degrade AM reception as a result of their RF emissions. Texas Instruments’ patented
AM interference avoidance circuit provides a flexible system solution for a wide variety of digital audio
architectures. During AM reception, the TAS5028A adjusts the radiated emissions to provide an emission
clear zone for the tuned AM frequency. The inputs to the TAS5028A for this operation are the tuned AM
frequency, the IF frequency, and the sample rate. The sample rate is automatically detected.
22
TAS5028A
SLES112 — June 2004
Introduction
Analog
Receiver
ADC
PCM1802
Audio
DSP
TAS5508A
TAS5111
TAS5111
TAS5111
Audio DSP provides the master
and bit clocks
TAS5111
TAS5111
TAS5111
TAS5111
TAS5111
Digital
Receiver
Audio
DSP
TAS5508A
TAS5111
TAS5111
TAS5111
TAS5111
The Digital Receiver or the Audio
DSP provides the Master and Bit
clocks
TAS5111
TAS5111
TAS5111
TAS5111
Figure 1−18. Block Diagrams of Typical Systems Requiring TAS5028A Automatic AM Interference
Avoidance Circuit
SLES112 — June 2004
TAS5028A
23
TAS5028A Controls and Status
2
TAS5028A Controls and Status
The TAS5028A provides control and status information from both the I2C registers and device pins.
This section describes some of these controls and status functions. The I2C summary and detailed register
descriptions are contained in sections at the end of this document.
2.1
I2C Status Registers
The TAS5028A has two status registers that provide general device information. These are the general status
register 0 (0x01) and the error status register (0x02).
2.1.1 General Status Register (0x01)
•
•
•
Device identification code
Clip indicator – The TAS5028A has a clipping indicator. Writing to the register clears the indicator.
Bank switching is busy
2.1.2 Error Status Register (0x02)
2.2
•
No internal errors (the valid signal is high)
•
A clock error has occurred – These are sticky bits that are cleared by writing to the register.
− LRCLK error – When the number of MCLKs per LRCLK is incorrect
− SCLK error – When the number of SCLKS per LRCLK is incorrect
− Frame slip – When the number of MCLKs per LRCLK changes by more than 10 MCLK cycles
− PLL phase-lock error
•
This error status register is normally used for system development only.
TAS5028A Pin Controls
The TAS5028A provide a number of terminal controls to manage the device operation. These controls are:
•
•
•
•
•
RESET
PDN
BKND_ERR
HP_SEL
MUTE
2.2.1 Reset (RESET)
The TAS5028A is placed in the reset mode by setting the RESET terminal low or by the power up reset circuitry
when power is applied.
RESET is an asynchronous control signal that restores the TAS5028A to the hard mute state (M). Master
volume is immediately set to full attenuation (there is no ramp down). Reset initiates the device reset without
an MCLK input. As long as the RESET terminal is held low, the device is in the reset state. During reset, all
I2C and serial data bus operations are ignored.
Table 2−1 shows the device output signals while RESET is active.
Table 2−1. Device Outputs During Reset
SIGNAL
SLES112 — June 2004
SIGNAL STATE
Valid
Low
PWM P-outputs
Low (M-state)
PWM M-outputs
Low (M-state)
SDA
Signal input (not driven)
TAS5028A
25
TAS5028A Controls and Status
Because RESET is an asynchronous signal, clicks and pops produced during the application (the leading
edge) of RESET cannot be avoided. However, the transition from the hard mute state (M) to the operational
state is performed using a quiet start up sequence to minimize noise. This control uses the PWM reset and
unmute sequence to shut down and start up the PWM. A detailed description of these sequences is contained
in the PWM section. If a completely quiet reset or power down sequence is desired, MUTE should be applied
before applying RESET.
The rising edge of the reset pulse begins device initialization before the transition to the operational mode.
During device initialization, all controls are reset to their initial states. Table 2−2 shows the default control
settings following a reset.
Table 2−2. Values Set During Reset
CONTROL
26
TAS5028A
SETTING
Clock register
Not valid
High pass
Disabled
Unmute from clock error
Hard unmute
Post DAP detection automute
Enabled
Eight Ch PreDAP detection automute
Enabled
De−emphasis
De-emphasis disabled
Channel configuration control
Configured for the default setting
Headphone configuration control
Configured for the default setting
Serial data interface format
I2S 24 bit
Individual channel mute
No channels are muted
Automute delay
5 ms
Automute threshold 1
< 8 bits
Automute threshold 2
Same as automute threshold 1
Modulation limit
Maximum modulation limit of 97.7%
Six (or eight – low) channel configuration
Eight channels
Slew rate limit
Disengaged for all channels
Interchannel delay
−32, 0, –16, 16, –24, 8, –8, −24
Shutdown PWM on error
Enabled
Volume and mute update rate
Volume ramp 85 ms
Treble and bass slew rate
Update every 1.31 ms
Bank switching
Manual bank selection is enabled
Auto bank switching map
All channels use bank 1
Input mixer coefficients
Input N −> channel N, no attenuation
Output mixer coefficients
Channel N −> output N, no attenuation
Subwoofer sum into Ch1 and 2 (5508)
Gain of 0
Ch1 and 2 sum in subwoofer (5508)
Gain of 0
Bass and treble bypass
Gain of 1
Bass and treble Inline
Gain of 0
Master volume
Mute
Individual channel volumes
0 dB
All bass and treble Indexes
0x12 neutral
Treble filter sets
Filter set 3
Bass filter sets
Filter set 3
AM interference enable
Disabled
AM interference IF
455
AM interference select sequence
1
Tuned freq and mode
0000 , BCD
SLES112 — June 2004
TAS5028A Controls and Status
After the initialization time, the TAS5028A starts the transition to the operational state with the Master volume
set at mute.
Because the TAS5028A has an external crystal time base, following the release of RESET, the TAS5028A sets
the MCLK and data rates and perform the initialization sequences. The PWM outputs are held at a mute state
until the master volume is set to a value other than mute via I2C.
2.2.2 Power Down (PDN)
TheTAS5028A can be placed into the power down mode by holding the PDN terminal low. When power down
mode is entered, both the PLL and the oscillator are shut down. Volume is immediately set to full attenuation
(there is no ramp down). This control uses the PWM mute sequence that provides a low click and pop transition
to the hard mute state (M). A detailed description of the PWM mute sequence is contained in the PWM section.
Power down is an asynchronous operation that does not require MCLK to go into the power down state. To
initiate the power-up sequence requires MCLK to be operational and the TAS5028A to receive 5 MCLKs prior
to the release of PDN.
As long as the PDN terminal is held low the device is in the power down state with the PWM outputs in a hard
mute (M) state. During power down, all I2C and serial data bus operations are ignored. Table 2−3 shows the
device output signals while PDN is active.
Table 2−3. Device Outputs During Power Down
SIGNAL
SIGNAL STATE
Valid
Low
PWM P-outputs
M-state = low
PWM M-outputs
M-state = low
SDA
Signal input
Following the application of PDN, the TAS5028A does not perform a quiet shutdown to prevent clicks and pops
produced during the application (the leading edge) of this command. The application of PDN immediately
performs a PWM stop. A quiet stop sequence can be performed by first applying MUTE before PDN.
When PDN is released, the system goes to the end state specified by MUTE and BKND_ERR pins and the
I2C register settings.
The crystal time base allows the TAS5028A to determine the CLK rates. Once these rates are determined,
the TAS5028A unmutes the audio.
2.2.3 Backend Error (BKND_ERR)
Backend error is used to provide error management for backend error conditions. Backend error is a level
sensitive signal. Backend error can be initiated by bringing the BKND_ERR terminal low for a minimum 5
MCLK cycles. When BKND_ERR is brought low, the PWM sets either six or eight channels into the PWM
backend error state. This state is described in the PWM section. Once the backend error sequence is initiated,
a delay of 5 ms is performed before the system starts the output re−initialization sequence. After the
initialization time, the TAS5028A begins normal operation. Backend error does not affect other PWM
modulator operations
The number of channels that are affected by the BKND_ERR signal is dependent upon the 6-channel
configuration signal. If the I2C setting 6-channel configuration is false, the TAS5028A places all eight PWM
outputs in the PWM backend error state, while not affecting any other internal settings or operations. If the
I2C setting six configuration is true, the TAS5028A brings the PWM outputs 1−6 to a backend error state, while
not affecting any other internal settings or operations. Table 2−4 shows the device output signal states during
backend error.
SLES112 — June 2004
TAS5028A
27
TAS5028A Controls and Status
Table 2−4. Device Outputs During Backend Error
SIGNAL
SIGNAL STATE
Valid
Low
PWM P-outputs
M-State − low
PWM M-outputs
M-State − low
HPPWM P-outputs
M-State − low
HPPWM M-outputs
M-State − low
SDA
Signal Input (not driven)
2.2.4 Speaker / Headphone Selector (HP_SEL)
The HP_SEL terminal enables the headphone output or the speaker outputs. The headphone output receives
the processed data output from DAP and PWM channels 1 and 2.
In 6-channel configuration this feature does not affect the two lineout channels.
When low, the headphone output is enabled. In this mode the speaker outputs are disabled. When high, the
speaker outputs are enabled and the headphone is disabled.
Changes in the pin logic level results in a state change sequence using soft mute to the hard mute (M) state
for both speaker and headphone followed by a soft unmute.
When HP_SEL is low, the configuration of channels 1 and 2 are defined by the headphone configuration
register. When HP_SEL is high, the channel 1 and 2 configuration registers define the configuration of
channels 1 and 2.
2.2.5 Mute (MUTE)
The mute control provides a noiseless volume ramp to silence. Releasing mute provides a noiseless ramp
to previous volume. The TAS55508 has both a master and individual channel mute commands. A terminal
is also provided for the master MUTE. The low active master Mute I2C register and the MUTE terminal are
logically Or’ed together. If either is set to low, a mute on all channels is performed. The master mute command
operates on all channels regardless on whether the system is in six or eight channel configuration.
When MUTE is invoked, the PWM output stops switching and then goes to an idle state.
The master Mute terminal is used to support a variety of other operations in the TAS5028A, such as setting
the inter-channel delay, the serial interface format, and the clock rates. A mute command by the master mute
terminal, individual I2C mute, the AM interference mute sequence, the bank switch mute sequence, or
automute overrides an unmute command or a volume command. While a mute is active, the commanded
channels will be placed in a mute state. When a channel is unmuted, it goes to the last commanded volume
setting that has been received for that channel.
2.3
Device Configuration Controls
The TAS5028A provides a number of system configuration controls that are set at initialization and following
a reset.
•
•
•
•
•
•
•
•
•
28
Channel configuration
Headphone configuration
Audio system configurations
Recovery from clock error
Volume and mute update rate
Modulation index limit
Inter-channel delay
Master clock and data rate controls
Bank controls
TAS5028A
SLES112 — June 2004
TAS5028A Controls and Status
2.3.1 Channel Configuration Registers
In order for the TAS5028A to have full control of the power stages, registers 0x05 to 0x0C must be programmed
to reflect the proper power stage and how each one should be controlled. Channel configuration registers
consist of eight registers, one for each channel.
The primary reason for using these registers is that different power stages require different handling during
start up, mute/unmute, shutdown, and error recovery. The TAS5028A must select the sequence that gives the
best click and pop performance and insure that the bootstrap capacitor is charged correctly during start up.
This sequence depends on which power stage is present at the TAS5028A output.
Table 2−5. Description of the Channel Configuration Registers (0x05 to 0x0C)
BIT
DESCRIPTION
D7
Enable/disable error recovery sequence. In case the BKND_RECOVERY pin is pulled low, this register determines if this channel is
to follow the error recovery sequence or to continue with no interruption.
D6
Determines if the power stage needs the TAS5028A VALID pin to go low to reset the power stage. Some power stages can be reset
by a combination of PWM signals. For these devices, it is recommended to set this bit low, since the VALID pin is shared for power
stages. This provides better control of each power stage.
D5
Determines if the power stage needs the TAS5028A VALID pin to go low to mute the power stage. Some power stages can be muted
by a combination of PWM signals. For these devices, it is recommended to set this bit low, since the VALID pin is shared for power
stages. This provides better control of each power stage.
D4
Inverts the PWM output. Inverting the PWM output can be an advantage if the power stage input pin are opposite the TAS5028A PWM
pinout. This makes routing on the PCB easier. To keep the phase of the output the speaker terminals must also be inverted.
D3
The power stage TAS5182 has a special PWM input. To ensure that the TAS5028A has full control in all occasions, the PWM output
must be remapped.
D2
Can be used to handle click and pop for some applications.
D1
This bit is normally used together with D2. For some power stages, both PWM signals must be high to get the desired operation of
both speaker outputs to be low. This bit sets the PWM outputs high-high during mute.
D0
Not used
Table 2−6 lists the optimal setting for each output stage configuration. Note that the default value is applicable
in all configurations except the TAS5182 SE/BTL configuration.
Table 2−6. Recommended TAS5028A Configurations for Texas Instruments Power Stages
DEVICE
ERROR RECOVERY
CONFIGURATION
D7
D6
D5
D4
D3
D2
D1
D0
Default
RES
BTL
1
1
1
0
0
0
0
0
BTL
1
1
1
0
0
0
0
0
RES
TAS5111
AUT
RES
TAS5112
AUT
TAS5182
RES
SE
1
1
1
0
0
0
0
0
BTL
0
1
1
0
0
0
0
0
SE
0
1
1
0
0
0
0
0
BTL
1
1
0
0
0
0
0
0
SE
1
1
0
0
0
0
0
0
BTL
0
1
0
0
0
0
0
0
SE
0
1
0
0
0
0
0
0
BTL
1
1
1
0
1
0
0
0
SE
1
1
1
0
1
0
0
0
RES: The output stage requires VALID to go low to recover from a shutdown.
AUT: The power stage can auto recover from a shutdown.
BTL: Bridge tied load configuration
SE: Single-ended configuration
2.3.2 Headphone Configuration Registers
The headphone configuration controls are identical to the speaker configuration controls. The headphone
configuration control settings are used in place of the speaker configuration control settings for channels 1
and 2 when the headphones are selected. In reality however, there is only one used configuration setting for
headphones and that is the default setting.
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TAS5028A
29
TAS5028A Controls and Status
2.3.3 Audio System Configurations
The TAS5028A can be configured to comply with various audio systems: 5.1-channel system, 6-channel
system, 7.1-channel system and 8-channel system.
The audio system configuration is set in the general control register (0xE0). Bits D31 – D2 must be zero and
D0 is don’t care.
D1
Sets number of speakers in the system, including possible line outputs
D1 must be configured as the following according to the audio system in the application:
Table 2−7. Audio System Configuration (General Control Register 0xE0)
2.3.3.1
AUDIO SYSTEM
D31−D2
D1
D0
DEFAULT
0
0
X
6 channel or 5.1
0
1
X
8 channel or 7.1
0
0
X
Using Line Outputs in 6-Channel Configurations
The audio system can be configured for a 6-channel configuration (with 2 line outs) by writing a 1 to bit D1
of register 0xE0 (General Control Register). In this configuration, channel 5 and 6 processing are exactly the
same as the other channels, except that Master Volume has no effect.
Note that in 6-channel configuration, channels 5 and 6 are unaffected by backend error (BKND_ERR goes
low).
To use channels 5 and 6 as dry unprocessed line outs, the following setup is recommended:
•
Channel 5 volume and channel 6 volume should be set for a constant output such as 0 dB.
•
Bass and treble for channels 5 and 6 can be used if desired.
•
If a down mix is desired on the channel 5 and 6 as line out, the down mixing can be performed using the
channel 5 and channel 6 input mixers.
2.3.4 Recovery from Clock Error
The TAS5028A can be set to either perform a volume ramp up during the recovery sequence of a clock error
or to simply come up in the last state (or desired state if a volume or tone update was in progress). This feature
is enabled via I2C system control register 0x03.
30
TAS5028A
SLES112 — June 2004
TAS5028A Controls and Status
2.3.5 Volume and Mute Update Rate
The TAS5028A has fixed soft volume and mute ramp durations. The ramps are linear. The soft volume and
mute ramp rates are adjustable by programming the I2C register 0xD0 for the appropriate number of steps
to be 512, 1024, or 2048. The update is performed at a fixed rate regardless of the sample rate.
•
In normal speed, the update rate is 1 step every 4 / Fs seconds.
•
In double speed, the update is 1 step every 8 / Fs seconds.
•
In quad speed, the update is 1 step every 16 / Fs seconds.
Because of processor loading, the update rate can increase for some increments by +1/Fs to +3/Fs. However,
the variance of the total time to go from +18 dB to mute is less than 25%.
Table 2−8. Volume Ramp Rates in ms
NUMBER OF STEPS
512
SAMPLE RATE (KHZ)
44.1, 88.2, 176.4
32, 48, 96, 192
46.44 ms
42.67 ms
1024
92.88 ms
85.33 ms
2048
185.76 ms
170.67 ms
2.3.6 Modulation Index Limit
PWM modulation is a linear function of the audio signal. When the audio signal is 0, the PWM modulation is
50%. When the audio signal increases towards full scale, the PWM modulation increases towards 100%. For
negative signals, the PWM modulations fall below 50% towards 0%.
However, there is a limit to the maximum modulation possible. During the off-time period, the power stage
connected to the TAS5028A output needs to get ready for he next on-time period. The maximum possible
modulation is then set by the power stage requirements. All Texas Instruments power stages need maximum
modulation to be 97.7%. This is also the default setting of the TAS5028A. Default settings can be changed
in the modulation index register (0x16).
Note that no change should be made to this register when using Texas Instruments power stages.
2.3.7 Inter-channel Delay
An 8-bit value can be programmed to each of the eight PWM inter-channel delay registers to add a delay per
channel from 0 to 255 clock cycles. The delays correspond to cycles of the high-speed internal clock, DCLK.
The default values are shown in Table 2−9.
Table 2−9. Interchannel Delay Default Values
I2C SUB-ADDRESS
CHANNEL
INTERCHANNEL DELAY DEFAULT (DCLK PERIODS)
0x1B
1
−24
0x1C
2
0
0x1D
3
−16
0x1E
4
+16
0x1F
5
−24
0x20
6
+8
0x21
7
−8
0x22
8
+24
SLES112 — June 2004
TAS5028A
31
TAS5028A Controls and Status
This delay is generated in the PWM and can be changed at any time through the serial control interface I2C
registers 0x1B – 0x22. The absolute offset for channel 1 is set in I2C sub-address 0x23.
NOTE: If used correctly, setting the PWM channel delay can optimize the performance of a
pure path digital amplifier system. The setting is based upon the type of backend power device
that is used and the layout. These values are set during initialization using the I2C serial
interface. Unless otherwise noted, use the default values given in Table 2−9.
2.4
Master Clock and Serial Data Rate Controls
The TAS5028A function only as a receiver of the MCLK (master clock), SCLK (shift clock), and LRCLK
(left/right clock) signals that controls the flow of data on the four serial data interfaces. The 13.5-MHz external
crystal allows the TAS5028A to automatically detect MCLK and the data rate.
The MCLK frequency can be 64 x Fs, 128 x Fs, 196 x Fs, 256 x Fs, 384 x Fs, 512 x Fs, or 768 x Fs.
The TAS5028A operates with the serial data interface signals LRCLK and SCLK synchronized to MCLK.
However, there is no constraint as to the phase relationship of these signals. The TAS5028A accepts a 64 x
Fs SCLK rate and a 1 x Fs LRCLK.
If the phase of SCLK or LRCLK drifts more than ±10 MCLK cycles since the last RESET, the TAS5028A
performs a clock error and resynchronize the clock timing.
The clock and serial data interface have several control parameters:
•
MCLK ratio 64 Fs, 128 Fs, 196 Fs, 256 Fs, 384 Fs, 512 Fs, or 768 Fs) − I2C parameter
•
Data rate 32, 38, 44.1,48, 88.2, 96, 176.4, 192 kHz − I2C parameter
•
AM mode enable / disable − I2C parameter
During AM interference avoidance, the clock control circuitry utilizes three other configuration inputs:
•
Tuned AM frequency (for AM interference avoidance) (550 − 1750 kHz) − I2C parameter
•
Frequency set select (1−4) − I2C parameter
•
Sample rate − I2C parameter or auto detected
2.4.1 PLL Operation
The TAS5028A uses two internal clocks generated by two internal phase-locked loops (PLLs), the digital PLL
(DPLL) and the analog PLL (APLL). The analog PLL provides the reference clock for the PWM. The digital
PLL provides the reference clock for the digital audio processor and the control logic.
The master clock MCLK input provides the input reference clock for the APLL. The external 13.5-MHz crystal
provides the input reference clock for the digital PLL. The crystal provides a time base to support a number
of operations, including the detection of the MCLK ratio, the data rate, and clock error conditions. The crystal
time base provides a constant rate for all controls and signal timing.
Even if MCLK is not present, the TAS5028A can receive and store I2C commands and provide status.
2.5
Bank Controls
The TAS5028A permits the user to specify and assign sample rate dependent parameters for Tone in one of
three banks that can be manually selected or selected automatically based upon the data sample rate. Each
bank can be enabled for one or more specific sample rates via I2C bank control register 0x40. Each bank set
holds the following values:
•
Five bass filter-set selections (register 0xDA)
•
Five treble filter-set selections (register 0xDC)
The default selection for bank control is manual bank with bank 1 selected. Note that if bank switching is used,
bank 2 and bank 3 must be programmed on power−up since the default values are all zeroes. If bank switching
is used and bank 2 and bank 3 are not programmed correctly, then the output of the TAS5028A could be muted
when switching to those banks.
32
TAS5028A
SLES112 — June 2004
TAS5028A Controls and Status
2.5.1 Manual Bank Selection
The three bank selection bits of the bank control register allow the appropriate bank to be manually selected
(000 = bank 1, 001 = bank 2, 010 = bank 3). In the manual mode, when a write occurs to the bass or treble
coefficients, the current selected bank is updated. If audio data is streaming to the TAS5028A, during a manual
bank selection, the TAS5028A first performs a mute sequence, then performs the bank switch, and finally
restores the volume using an unmute sequence.
A mute command initiated by the bank switch mute sequence overrides an un−mute command or a volume
command. While a mute is active, the commanded channels are muted. When a channel is unmated, the
volume level goes to the last commanded volume setting that has been received for that channel.
If MCLK or SCLK is stopped, the TAS5028A performs a bank switch operation. If the clocks should start up
once the manual bank switch command has been received, the bank switch operation is performed during
the 5-ms silent start sequence.
2.5.2 Automatic Bank Selection
To enable automatic bank selection, a value of 3 is written into in the bank selection bits of the bank control
register. Banks are associated with one or more sample rates by writing values into the Bank 1 or Bank 2 data
rate selection registers. The automatic base selection is performed when a frequency change is detected
according to the following scheme:
1. The system scans bank 1 data rate associations to see if the bank 1 is assigned for that data rate.
2. If bank 1 is assigned, then the bank 1 coefficients will be loaded.
3. If it is not then, the system scans the bank 2 to see if bank 1 is assigned for that data rate.
4. If bank 2 is assigned, then the bank 2 coefficients will be loaded.
5. If it is not then, the system loads the bank 3 coefficients.
The default is that all frequencies are enabled for Bank 1. This default is expressed as a value of all 1s in the
Bank 1 auto-selection byte and all 0s in the bank 2 auto−section byte.
2.5.2.1
Coefficients Write Operations While Automatic Bank Switch Is Enabled
In automatic mode if a write occurs to the Tone coefficient, the bank that is written to is the current bank.
2.5.3 Bank Set
Bank set is used to provide a secure way to update the bank coefficients in both the manual and automatic
switching modes without causing a bank switch to occur. Bank set mode does not alter the current bank
register mapping. It simply enables any bank’s coefficients to be updated while inhibiting any bank switches
from taking place. In manual mode, this enables the coefficients to be set without switching banks. In automatic
mode this prevents a clock error or data rate change from corrupting a bank coefficient write.
To update the coefficients of a bank, a value of 4, 5, or 6 is written into in the bank selection bits of the bank
control register. This enables the tone coefficient values of bank 1, 2, or 3 to be respectively updated.
Once the coefficients of the bank have been updated, the bank selection bits are then returned to the desired
manual or automatic bank selection mode.
2.5.4 Bank Switch Timeline
After a bank switch is initiated (manual or automatic), no I2C writes to the TAS5028A should occur before a
minimum of 186 ms. This value is determined by the volume ramp rates for a particular sample rate.
2.5.5 Bank Switching Example 1
Problem: The audio unit containing a TAS5028A needs to handle different audio formats with different sample
rates. Format #1 requires Fs = 32 kHz, Format #2 requires Fs = 44.1 kHz, and Format #3 requires Fs = 48 kHz.
The sample-rate dependent parameters in the TAS5028A require different coefficients and data depending
on the sample rate.
SLES112 — June 2004
TAS5028A
33
TAS5028A Controls and Status
Strategy: Use the TAS5028A bank switching feature to allow for managing and switching three banks
associated with the three sample rates, 32 kHz (Bank 1), 44.1 kHz (Bank 2), and 48 kHz (Bank 3).
One possible algorithm is to generate, load, and automatically manage bank switching for this problem:
•
Generate bank-related coefficients (see above) for sample rates 32 kHz, 44.1 kHz, and 48 kHz and include
the same in the micro-based TAS5028A I2C firmware.
•
On TAS5028A power up or reset, the micro runs the following TAS5028A Initialization code:
•
−
Update bank 1 (Write 0x00048040 to register 0x40).
−
Write bank-related I2C registers with appropriate values for bank 1.
−
Write bank 2 (Write 0x00058040 to register 0x40).
−
Load bank-related I2C registers with appropriate values for bank 2.
−
Write bank 3 (Write 0x00068040 to register 0x40).
−
Load bank-related I2C registers with appropriate values for bank 3.
−
Select automatic bank switching (write 0x00038040 to register 0x40)
Now when the audio media changes, the TAS5028A automatically detects the incoming sample rate and
automatically switches to the appropriate bank.
In this example any sample rates other then 32 kHz and 44.1 kHz will use bank 3. If other sample rates are
used, then the banks need to be set up differently.
2.5.6 Bank Switching Example 2
Problem: The audio system uses all of the sample rates supported by the TAS5028A. How can the automatic
bank switching be set up to handle this situation?
Strategy: Use the TAS5028A bank switching feature to allow for managing and switching three banks
associated with sample rates as follows:
•
Bank 1: Coefficients for 32 kHz, 38 kHz, 44.1 kHz, and 48 kHz
•
Bank 2: Coefficients for 88.2kHz and 96 kHz
•
Bank 3: Coefficients for 176.4 kHz and 192 kHz
One possible algorithm is to generate, load, and automatically manage bank switching for this problem:
•
Generate bank-related coefficients for sample rates 48 kHz (bank 1), 96 kHz (bank 2), and 192 kHz
(bank 3) and include the same in the micro-based TAS5028A I2C firmware.
•
On TAS5028A power−up or reset, the micro runs the following TAS5028A initialization code:
•
34
−
Update bank 1 (Write 0x0004F00C to register 0x40).
−
Write bank-related I2C registers with appropriate values for bank 1.
−
Write bank 2 (Write 0x0005F00C to register 0x40).
−
Load bank-related I2C registers with appropriate values for bank 2.
−
Write bank 3 (Write 0x0006F00C to register 0x40).
−
Load bank-related I2C registers with appropriate values for bank 3.
−
Select automatic bank switching (Write 0x0003F00C to register 0x40)
Now when the audio media changes, the TAS5028A automatically detects the incoming sample rate and
automatically switches to the appropriate bank.
TAS5028A
SLES112 — June 2004
Electrical Specifications
3
Electrical Specifications
3.1
Absolute Maximum Ratings{
UNITS
Supply voltage, DVDD and DVD_PWM
–0.3 V to 3.6 V
Supply voltage, AVDD_PLL
–0.3 V to 3.6 V
3.3-V digital input
–0.5 V to DVDD + 0.5 V
5 V tolerant(2) digital input
Input voltage
–0.5 V to 6 V
1.8 V LVCMOS(3)
–0.5 V to VREF(1) + 0.5 V
Input clamp current, IIK (VI < 0 or VI > 1.8 V
±20 mA
Output clamp current, IOK (VO < 0 or VO > 1.8 V)
±20 mA
Operating free air temperature
0°C to 70°C
Storage temperature range, Tstg
–65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. VREF is a 1.8-V supply derived from regulators internal to the TAS5028A chip. VREF is on terminals VRA_PLL, VRD_PLL,
VR_DPLL, VR_DIG, and VR_PWM. These terminals are provided to permit use of external filter capacitors, but should not be used
to source power to external devices.
2. 5-V tolerant inputs are RESET, PDN, MUTE, HP_SEL, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDIN3, SDIN4, SDA, and SCL.
3. VRA_PLL, VRD_PLL, VR_DPLL, VR_DIG, VR_PWM
DISSIPATION RATING TABLE (High-k Board, 1055C Junction)
3.2
PACKAGE
TA ≤ 255C
POWER RATING
DERATING FACTOR
ABOVE TA = 255C
TA = 705C
POWER RATING
PAG
1869 mW
23.36 mW/°C
818 mW
Dynamic Performance (At Recommended Operating Conditions at 255C)
PARAMETER
Dynamic range
Total harmonic distortion
Frequency response
3.3
TEST CONDITIONS
MIN
TAS5028A + TAS5111 A-weighted (Fs = 48 kHz)
NOM
MAX
102
TAS5111 A at 1 W
0.1%
TAS5028A ouput
0.01%
32-kHz to 96-kHz sample rates
±0.1
176.4, 192-kHz sample rates
±0.2
UNITS
dB
dB
Recommended Operating Conditions (Over 05C to 705C)
Digital supply voltage, DVDD and DVDD_PWM
Analog supply voltage, AVDD_PLL
High-level
High
level input voltage, VIH
NOM
MAX
3
3.3
3.6
V
3
3.3
3.6
V
3.3 V
2
5−V tolerant(4)
2
1.8−V LVCMOS (XTL_IN)
Low-level
Low
level input voltage, VIL
MIN
UNITS
V
1.26
3.3 V
0.8
5-V tolerant(4)
0.8
1.8−V (XTL_IN)
V
0.54
Operating ambient air temperature range, TA
0
Operating junction temperature range, TJ
0
25
70
°C
105
°C
NOTE 4: 5-V tolerant inputs are SDA, SCL, RESET, PDN, MUTE, HP_SEL, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDIN3, and SDIN4.
SLES120 − September 2004
TAS5028A
35
Electrical Specifications
3.4
Electrical Characteristics Over Recommended Operating Conditions (Unless
Otherwise Noted)
PARAMETER
VOH
High level output voltage
High-level
VOL
Low level output voltage
Low-level
IOZ
High-impedance output current
IIL
Low-level
Low
level input current
High-level
High
level input current
TYP
MAX
1.8-V LVCMOS (XTL_OUT)
IOH = –0.55 mA
3.3-V TTL and 5 V(6) tolerant
IOL = 4 mA
0.5
1.8-V LVCMOS (XTL_OUT)
IOL = 0.75 mA
0.5
2.4
±20
3.3-V TTL
VI = VIL
±1
1.8-V LVCMOS (XTL_IN)
VI = VIL
±1
tolerant(5)
VI = 0 V DVDD = 3 V
±1
3.3-V TTL
VI = VIH
±1
1.8-V LVCMOS (XTL_IN)
VI = VIH
±1
tolerant(5)
VI = 5.5 V DVDD = 3 V
Digital supply voltage,
voltage DVDD
Input supply current
V
µA
µA
µA
±20
Fs = 48 kHz
140
Fs = 96 kHz
150
Fs = 192kHz
155
Power down
voltage AVDD
Analog supply voltage,
UNITS
V
1.44
3.3-V TTL
5V
IDD
MIN
IOH = –4 mA
5V
IIH
TEST CONDITIONS
3.3 V TTL and 5 V(6) tolerant
mA
8
Normal
20
Power down
mA
2
NOTES: 5. 5-V tolerant inputs are SDA, SCL, RESET, PDN, MUTE, HP_SEL, SCLK, LRCLK, MCLK, SDIN1, SDIN2, SDIN3, and SDIN4.
6. 5-V tolerant outputs are SCL and SDA
3.5
PWM Operation at Recommended Operating Conditions Over 05C to 705C
PARAMETER
Output sample rate 1× – 8× oversampled
3.6
TEST CONDITIONS
MODE
VALUE
UNITS
384
kHz
44.1-, 88.2-, 176.4-kHz data rate ±4%
8×, 4×, and 2× sample
rates
352.8
kHz
48, 96, 192 kHz data rate ±4%
8×, 4×, and 2× sample
rates
384
kHz
32-kHz data rate ±4%
12× sample rate
Switching Characteristics
3.6.1 Clock Signals Over Recommended Operating Conditions (Unless Otherwise
Noted)
3.6.1.1
PLL Input Parameters and External Filter Components{
PARAMETER
fXTALI
Frequency, XTAL IN
fMCLKI
Frequency, MCLK (1 / tcyc2)
TEST CONDITIONS
MIN
Only use 13.5-MHz crystal ≤1000 ppm
TYP
2
MCLK duty cycle duty cycle
MAX
13.5
40%
MHz
50
50%
UNITS
MHz
60%
MCLK minimum high time
≥2-V MCLK = 49.152 MHz, Within the min
and max duty cycle constraints
5
ns
MCLK minimum low time
≤0.8-V MCLK = 49.152 MHz,
Within the min and max duty cycle constraints
5
ns
LRCLK allowable drift before LRCLK reset
10
MCLKs
External PLL filter cap C1
SMD 0603 Y5V
100
nF
External PLL filter cap C2
SMD 0603 Y5V
10
nF
External PLL filter resistor R
SMD 0603, metal film
200
Ω
External VRA_PLL decoupling
SMD, Y5V
100
nF
See the TAS5028A example application schematic in Section 7.
36
TAS5028A
SLES120 − September 2004
Electrical Specifications
3.6.2 Serial Audio Port
3.6.2.1
Serial Audio Ports Slave Mode Over Recommended Operating Conditions (Unless
Otherwise Noted)
PARAMETER
TEST CONDITIONS
MIN
CL = 30 pF
TYP
2.048
MAX
Frequency, SCLK 64 × fs
tsu1
Setup time, LRCLK to SCLK rising edge
10
ns
th1
Hold time, LRCLK from SCLK rising edge
10
ns
tsu2
Setup time, SDIN to SCLK rising edge
10
ns
th2
Hold time, SDIN from SCLK rising edge
10
ns
LRCLK frequency
12.288
UNITS
fSCLKIN
32
48
192
SCLK duty cycle
40%
50%
60%
LRCLK duty cycle
40%
50%
60%
kHz
64
64
SCLK
edges
–1/4
1/4
SCLK
period
SCLK rising edges between LRCLK rising edges
LRCLK clock edge with respect to the falling edge of SCLK
MHz
SCLK
(Input)
th1
tsu1
LRCLK
(Input)
th2
tsu2
SDIN1
SDIN2
SDIN3
Figure 3−1. Slave Mode Serial Data Interface Timing
SLES120 − September 2004
TAS5028A
37
Electrical Specifications
3.6.3 I 2C Serial Control Port Operation
3.6.3.1
Timing Characteristics for I2C Interface Signals Over Recommended Operating
Conditions (Unless Otherwise Noted)
PARAMETER
TEST CONDITIONS
MIN
No wait states
MAX
UNITS
400
kHz
fSCL
Frequency, SCL
tw(H)
Pulse duration, SCL high
0.6
tw(L)
Pulse duration, SCL low
1.3
tr
Rise time, SCL and SDA
300
ns
tf
Fall time, SCL and SDA
300
ns
tsu1
Setup time, SDA to SCL
th1
Hold time, SCL to SDA
t(buf)
tsu2
µs
µs
100
ns
0
ns
Bus free time between stop and start condition
1.3
µs
Setup time, SCL to start condition
0.6
µs
th2
Hold time, start condition to SCL
0.6
µs
tsu3
Setup time, SCL to stop condition
0.6
CL
Load capacitance for each bus line
µs
400
tw(L)
tw(H)
tr
pF
tf
SCL
tsu1
th1
SDA
Figure 3−2. SCL and SDA Timing
SCL
th2
t(buf)
tsu2
tsu3
Start Condition
Stop Condition
SDA
Figure 3−3. Start and Stop Conditions Timing
38
TAS5028A
SLES120 − September 2004
Electrical Specifications
3.6.4 Reset Timing (RESET)
3.6.4.1
Control Signal Parameters Over Recommended Operating Conditions (Unless
Otherwise Noted)
PARAMETER
tr(DMSTATE)
Time to M-STATE low
tw(RESET)
Pulse duration, RESET active
MIN
TYP
400
I2C
tr(I2C_ready)
Time to enable
tr(run)
Device startup time
MAX
UNITS
370
ns
None
ns
3
ms
10
RESET
ms
Earliest time
that M-State
could be exited
tw(RESET)
M-State
tr(I2C_ready)
tr(run)
tr(DMSTATE) = ~ < 300 ns
Determine SCLK rate
and MCLK ratio Enable I2C
Start system
Figure 3−4. Reset Timing
Since a crystal time base is used, the system determines the CLK rates. Once the data rate and master clock
ratio is determined, the system outputs audio if a master volume command is issued.
3.6.5 Power-Down (PDN) Timing
3.6.5.1
Control Signal Parameters Over Recommended Operating Conditions (Unless Otherwise
Noted)
PARAMETER
tp(DMSTATE)
MIN
Time to M-STATE low
Number of MCLKs preceding the release of PDN
tsu
TYP
MAX
UNITS
300
µs
5
Device startup time
120
ms
PDN
M-State
tp(DMSTATE) = ~ < 300 µs
tsu
Figure 3−5. Power-Down Timing
SLES120 − September 2004
TAS5028A
39
Electrical Specifications
3.6.6 Backend Error (BKND_ERR)
3.6.6.1
Control Signal Parameters Over Recommended Operating Conditions (Unless
Otherwise Noted)
PARAMETER
tw(ER)
MIN
Pulse duration, BKND_ERR active
350
tp(valid_low)
tp(valid_high)
I2C programmable to be between 1 to 10 ms
TYP
MAX
UNITS
None
ns
<100
µs
–25
25
% of interval
tw(ER)
ERR_RCVRY
M-State
Normal
Operation
Normal
Operation
tp(valid_high)
tp(valid_low)
Figure 3−6. Error Recovery Timing
3.6.7 MUTE Timing—MUTE
3.6.7.1
Control Signal Parameters Over Recommended Operating Conditions (Unless
Otherwise Noted)
PARAMETER
td(VOL
MIN
TYP
MAX
Defined by rate setting(1)
Volume ramp time
UNITS
ms
NOTE 1: See Section 6.19.
MUTE
VOLUME
M-State
Normal
Operation
Normal
Operation
td(VOL)
td(VOL)
Figure 3−7. Mute Timing
40
TAS5028A
SLES120 − September 2004
Electrical Specifications
3.6.8 Headphone Select (HP_SEL)
3.6.8.1
Control Signal Parameters Over Recommended Operating Conditions (Unless
Otherwise Noted)
PARAMETER
tw(MUTE)
Pulse duration, HP_SEL active
td(VOL)
Soft volume update time
t(SW)
Switch-over time
MIN
MAX
350
None
Defined by rate setting(2)
0.2
UNITS
ns
ms
1 ms
ms
NOTE 2: See Section 6.19.
HP_SEL
Spkr Volume
td(VOL)
HP Volume
td(VOL)
t(SW)
M-State
(Internal Device State)
HP_SEL
HP Volume
td(VOL)
Spkr Volume
td(VOL)
t(SW)
M-State
Figure 3−8. HP_SEL Timing
SLES120 − September 2004
TAS5028A
41
Serial Audio Interface Control and Timing
3.6.9 Volume Control
3.6.9.1
Control Signal Parameters Over Recommended Operating Conditions (Unless
Otherwise Noted)
PARAMETER
TEST CONDITIONS
MIN
Maximum attenuation before mute
Individual volume, master volume or a
combination of both
Maximum gain
Individual volume, master volume
Maximum volume before the onset of clipping
0-dB input, any modulation limit
MAX
UNITS
–127
dB
18
dB
0
dB
3.7 Serial Audio Interface Control and Timing
3.7.1 I 2S Timing
I2S timing uses an LRCLK to define when the data being transmitted is for the left channel and when it is for
the right channel. The LRCLK is low for the left channel and high for the right channel. A bit clock running at
64 × Fs is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes
state to the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of
bit clock. The TAS5028A masks unused trailing data bit positions.
2-Channel I2S (Philips Format) Stereo Input
32 Clks
LRCLK (Note Reversed Phase)
32 Clks
Left Channel
Right Channel
SCLK
SCLK
MSB
24-Bit Mode
23 22
LSB
9
8
5
4
5
4
1
0
1
0
1
0
MSB
LSB
23 22
9
8
5
4
19 18
5
4
1
0
15 14
1
0
1
0
20-Bit Mode
19 18
16-Bit Mode
15 14
NOTE: All data presented in 2s complement form with MSB first.
Figure 3−9. I2S Format 64−Fs Format
42
TAS5028A
SLES120 − September 2004
Serial Audio Interface Control and Timing
3.7.2 Left Justified
Left justified (LJ) timing uses an LRCLK to define when the data being transmitted is for the left channel and
when it is for the right channel. The LRCLK is high for the left channel and low for the right channel. A bit clock
running at 64 × Fs is used to clock in the data. The first bit of data appears on the data lines at the same time
the LRCLK toggles. The data is written MSB first and is valid on the rising edge of bit clock. The TAS5028A
masks unused trailing data bit positions.
2-Channel Left-Justified Stereo Input
32 Clks
32 Clks
LRCLK
LRCLK
Right Channel
Left Channel
SCLK
MSB
24-Bit Mode
23 22
LSB
9
8
5
4
5
4
1
0
1
0
1
0
MSB
LSB
23 22
9
8
5
4
19 18
5
4
1
0
15 14
1
0
1
0
20-Bit Mode
19 18
16-Bit Mode
15 14
NOTE: All data presented in 2s complement form with MSB first.
Figure 3−10. Left−Justified 64−Fs Format
SLES120 − September 2004
TAS5028A
43
Serial Audio Interface Control and Timing
3.7.3 Right Justified
Right justified (RJ) timing uses an LRCLK to define when the data being transmitted is for the left channel and
when it is for the right channel. The LRCLK is high for the left channel and low for the right channel. A bit clock
running at 64 × Fs is used to clock in the data. The first bit of data appears on the data 8-bit clock periods (for
24-bit data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before
L/RCLK transitions. The data is written MSB first and is valid on the rising edge of bit clock. The TAS5028A
masks unused leading data bit positions.
2-Channel Right-Justified (Sony Format) Stereo Input
32 Clks
32 Clks
LRCLK
Right Channel
Left Channel
SCLK
MSB
24-Bit Mode
LSB
23 22
19 18
15 14
1
0
19 18
15 14
1
0
15 14
1
0
MSB
LSB
23 22
19 18
15 14
1
0
19 18
15 14
1
0
15 14
1
0
20-Bit Mode
16-Bit Mode
NOTE: All data presented in 2s complement form with MSB first.
Figure 3−11. Right−Justified 64−Fs Format
44
TAS5028A
SLES120 − September 2004
I 2C Serial Control Interface (Slave Address 0x36)
4
I2C Serial Control Interface (Slave Address 0x36)
The TAS5028A has a bidirectional I2C interface that compatible with the I2C (Inter IC) bus protocol and
supports both 100 Kbps and 400 Kbps data transfer rates for single− and multiple−write and read operations.
This is a slave only device that does not support a multi-master bus environment or wait state insertion. The
control interface is used to program the registers of the device and to read device status.
The TAS5028A supports the standard-mode I2C bus operation (100 kHz maximum) and the fast I2C bus
operation (400 kHz maximum). The TAS5028A performs all I2C operations without I2C wait cycles.
4.1
General I2C Operation
The I2C bus employs two signals; SDA (data) and SCL (clock), to communicate between integrated circuits
in a system. Data is transferred on the bus serially one bit at a time. The address and data can be transferred
in byte (8 bit) format, with the most significant bit (MSB) transferred first. In addition, each byte transferred on
the bus is acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with
the master device driving a start condition on the bus and ends with the master device driving a stop condition
on the bus. The bus uses transitions on the data terminal (SDA) while the clock is high to indicate a start and
stop conditions. A high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop.
Normal data bit transitions must occur within the low time of the clock period. These conditions are shown in
Figure 4−1. The master generates the 7-bit slave address and the read/write (R/W) bit to open communication
with another device and then wait for an acknowledge condition. The TAS5028A holds SDA low during
acknowledge clock period to indicate an acknowledgement. When this occurs, the master transmits the next
byte of the sequence. Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All
compatible devices share the same signals via a bidirectional bus using a wired-AND connection. An external
pullup resistor must be used for the SDA and SCL signals to set the high level for the bus.
SDA
R/
A 8 Bit Register Address (N)
W
7 Bit Slave Address
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
8 Bit Register Data For
Address (N)
A
7
6
5
4
3
2
1
8 Bit Register Data For
Address (N)
A
0
7
6
5
4
3
2
1
A
0
SCL
Start
Stop
Figure 4−1. Typical I2C Sequence
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the
last word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence
is shown in Figure 4−1.
The 7-bit address for the TAS5028A is 0011011.
4.2
Single− and Multiple−Byte Transfers
The serial control interface supports both single−byte and multiple−byte read/write operations for status
registers and the general control registers associated with the PWM. However, for the DAP data processing
registers, the serial control interface supports only multiple−byte (4 bytes) read/write operations.
During multiple−byte read operations, the TAS5028A responds with data, a byte at a time, starting at the
subaddress assigned, as long as the master device continues to respond with acknowledges. If a particular
subaddress does not contain 32 bits, the unused bits are read as logic 0.
During multiple−byte write operations, the TAS5028A compares the number of bytes transmitted to the
number of bytes that are required for each specific sub address. If a write command is received for a mixer
coefficient, the TAS5028A expects to receive one 32-bit word. If fewer than 32 bits are required when a stop
command (or another start command) is received, the data received is discarded.
SLES120 − September 2004
TAS5028A
45
I 2C Serial Control Interface (Slave Address 0x36)
Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. The
TAS5028A also supports sequential I2C addressing. For write transactions, if a subaddress is issued followed
by data for that subaddress and the fifteen subaddresses that follow, a sequential I2C write transaction has
taken place, and the data for all 16 subaddresses is successfully received by the TAS5028A. For I2C
sequential write transactions, the subaddress then serves as the start address and the amount of data
subsequently transmitted, before a stop or start is transmitted, determines how many subaddresses are
written. As was true for random addressing, sequential addressing requires that a complete set of data be
transmitted. If only a partial set of data is written to the last subaddress, the data for the last subaddress is
discarded. However, all other data written is accepted; just the incomplete data is discarded.
4.3
Single−Byte Write
As shown in Figure 4−2, a single−byte data write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction
of the data transfer. For a write data transfer, the read/write bit will be a 0. After receiving the correct I2C device
address and the read/write bit, the TAS5028A device responds with an acknowledge bit. Next, the master
transmits the address byte or bytes corresponding to the TAS5028A internal memory address being
accessed. After receiving the address byte, the TAS5028A again responds with an acknowledge bit. Next, the
master device transmits the data byte to be written to the memory address being accessed. After receiving
the data byte, the TAS5028A again responds with an acknowledge bit. Finally, the master device transmits
a stop condition to complete the single−byte data−write transfer.
Start
Condition
Acknowledge
A6
A5
A4
A3
A2
A1
A0 R/W ACK A7
Acknowledge
A6
A5
I2C Device Address and
Read/Write Bit
A4
A3
A2
A1
Acknowledge
A0 ACK D7
D6
Sub-Address
D5
D4
D3
D2
D1
D0 ACK
Stop
Condition
Data Byte
Figure 4−2. Single−Byte Write Transfer
4.4
Multiple−Byte Write
A multiple−byte data write transfer is identical to a single−byte data write transfer except that multiple data
bytes are transmitted by the master device to TAS5028A as shown in Figure 4−3. After receiving each data
byte, the TAS5028A responds with an acknowledge bit.
Start
Condition
Acknowledge
A6
A5
A1
A0 R/W ACK A7
I2C Device Address and
Read/Write Bit
A6
A5
A4
A3
Sub-Address
A1
Acknowledge
Acknowledge
Acknowledge
Acknowledge
A0 ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
First Data Byte
Other Data Bytes
Last Data Byte
Stop
Condition
Figure 4−3. Multiple−Byte Write Transfer
4.5
Incremental Multiple−Byte Write
The I2C supports a special mode which permits I2C write operations to be broken up into multiple data write
operations that are multiples of 4 data bytes. These are 6−byte, 10−byte, 14−byte, 18−byte, ... etc., write
operations that are composed of a device address, read/write bit, and subaddress and any multiple of 4 bytes
of data. This permits the system to incrementally write large register values without blocking other I2C
transactions.
This feature is enabled by the append subaddress function in the TAS5028A. This function enables the
TAS5028A to append 4 bytes of data to a register that was opened by a previous I2C register write operation
but has not received its complete number of data bytes. Because the length of the long registers is a multiple
of 4 bytes, using 4-byte transfers has only an integer number of append operations.
46
TAS5028A
SLES120 − September 2004
I 2C Serial Control Interface (Slave Address 0x36)
When the correct number of bytes has been received, the TAS5028A starts processing the data.
The procedure to perform an incremental multibyte−write operation is as follows:
1. Start a normal I2C write operation by sending the device address, write bit, register subaddress, and the
first four bytes of the data to be written. At the end of that sequence, send a stop condition. At this point,
the register has been opened and accepts the remaining data that is sent by writing 4−byte blocks of data
to the append subaddress (0xFE).
2. At a later time, one or more append data transfers are performed to incrementally transfer the remaining
number of bytes in sequential order to complete the register write operation. Each of these append
operations will be composed of the device address, write bit, append subaddress (0xFE), and four bytes
of data followed by a stop condition.
3. The operation will be terminated due to an error condition and the data will be flushed:
a. If a new subaddress is written to the TAS5028A before the correct number of bytes have been written.
b. If more or fewer than 4 bytes are data written at the beginning or during any of the append operations.
c.
4.6
If a read bit is sent.
Single−Byte Read
As shown in Figure 4−4, a single−byte data read transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. For the data read transfer, both a write
followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal
memory address to be read. As a result, the read/write bit will be a 0. After receiving the TAS5028A address
and the read/write bit, the TAS5028A responds with an acknowledge bit. In addition, after sending the internal
memory address byte or bytes, the master device transmits another start condition followed by the TAS5028A
address and the read/write bit again. This time the read/write bit will be a 1, indicating a read transfer. After
receiving the TAS5028A and the read/write bit the TAS5028A again responds with an acknowledge bit. Next,
the TAS5028A transmits the data byte from the memory address being read. After receiving the data byte,
the master device transmits a not acknowledge followed by a stop condition to complete the single−byte
data−read transfer.
Repeat Start
Condition
Start
Condition
Acknowledge
A6
A5
A1
Acknowledge
A0 R/W ACK A7
A6
I2C Device Address and
Read/Write Bit
A5
A4
A0 ACK
Not
Acknowledge
Acknowledge
A6
A5
A1
A0 R/W ACK D7
I2C Device Address and
Read/Write Bit
Sub-Address
D6
D1
D0 ACK
Stop
Condition
Data Byte
Figure 4−4. Single−Byte Read Transfer
4.7
Multiple−Byte Read
A multiple−byte data−read transfer is identical to a single−byte data read transfer except that multiple data
bytes are transmitted by the TAS5028A to the master device as shown in Figure 4−5. Except for the last data
byte, the master device responds with an acknowledge bit after receiving each data byte.
Repeat Start
Condition
Start
Condition
Acknowledge
A6
A0 R/W ACK A7
I2C Device Address and
Read/Write Bit
Acknowledge
A6
A0 ACK
A5
Sub-Address
A6
Acknowledge
Acknowledge
Acknowledge
Not
Acknowledge
A0 R/W ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
I2C Device Address and
Read/Write Bit
First Data Byte
Other Data Bytes
Last Data Byte
Stop
Condition
Figure 4−5. Multiple Byte Read Transfer
SLES120 − September 2004
TAS5028A
47
Serial Control I 2C Register Summary
5
Serial Control I2C Register Summary
The TAS5028A slave address is 0x36. See the Serial Control I2 C Register Bit Definitions chapter for complete
bit definitions.
Note that u indicates unused bits.
I2C
SUBADDRESS
TOTAL
BYTES
0x00
1
Clock control register
Set data rate and MCLK frequency
1. Fs = 48 kHz
2. MCLK = 256 Fs = 12.288 MHz
0x01
1
General status register
Clip indicator and ID code for the
TAS5028A
0x01
0x02
1
Error status register
PLL, SCLK, LRCLK, and frame slip
errors
No errors
0x03
1
System control register 1
0x04
0x05–0x0C
1
1
REGISTER FIELDS
System control register 2
Channel configuration registers
DESCRIPTION OF CONTENTS
DEFAULT STATE
PWM high pass, clock set, un-mute
select
1. PWM high pass disabled
2. Auto clock set
3. Hard un-mute on clock error
recovery
Automute and de-emphasis control
1. Automute timeout disable
2. Post-DAP detection automute
enabled
3. 8-Ch device input detection
automute enabled
4. Un-mute threshold 6 dB over input
5. No de-emphasis
Configure channels 1, 2, 3, 4, 5, 6, 7,
and 8
1. Enable backend reset
2. Valid low for reset
3. Valid low for mute
4. Normal BEPolarity
5. Don’t remap the output for the
TAS5182
6. Don’t go low-low in mute
7. Don’t remap Hi-Z state to
low-low state
Configure headphone output
1. Disable backend reset sequence
2 Valid does not have to be low for
reset
3. Valid does not have to be low for
mute
4. Normal BEPolarity
5. Do not remap output to comply
with 5182
6. Do not go low-low in mute
7. Do not remap Hi−Z state to
low-low state
0x0D
1
Headphone configuration
register
0x0E
1
Serial data interface register
Set serial data interface to right
justified, I2S, or left justified
24-bit I2S
0x0F
1
Soft mute register
Soft mute for channels 1, 2, 3, 4, 5, 6,
7, and 8
Un-mute all channels
0x14
1
Automute control
Set auto-mute delay and threshold
1. Set auto-mute delay = 5 ms
2. Set auto-mute threshold less
than bit 8
0x15
1
Automute PWM threshold and
backend reset period
Set PWM auto-mute threshold, set
backend reset period
1. Set the PWM threshold the same
as the TAS5028A input threshold
2. Set backend reset
period = 5 ms
0x16
1
Modulation limit register
Set modulation index
97.7%
0x10–0x13
0x17–0x1A
SLES112 — June 2004
RESERVED
RESERVED
TAS5028A
49
Serial Control I 2C Register Summary
I2C
SUBADDRESS
TOTAL
BYTES
0x1B–0x22
1/Reg.
0x23
1
REGISTER FIELDS
0x41–0x48
Interchannel delay registers
Set inter-channel delay
Inter-channel offset
Absolute delay offset for channel 1
(0 – 255)
Minimum absolute default = 0
DCLK periods
RESERVED
4
32/Reg
Bank switching command
register
See Input Mixer Registers
(0x41 – 0x48, Channels 1 – 8),
Section 6.15
0x49–0x88
0x89–0x90
Set up DAP coefficients bank
switching for banks 1, 2, and 3
8X8 input crossbar mixer setup
Manual selection – bank 1
SDIN1−Left to input mixer 1
SDIN1−Right to input mixer 2
SDIN2−Left to input mixer 3
SDIN2−Right to input mixer 4
SDIN3−Left to input mixer 5
SDIN3−Right to input mixer 6
SDIN4−Left to input mixer 7
SDIN4−Right to input mixer 8
RESERVED
8
Bass and Treble Bypass
Ch 1–8
0x91–0xA9
Bypass bass and treble for
channels 1–8
Bass and treble bypassed for all
channels
RESERVED
0xAA
8
sel op1–8 and mix to S
Select 0 to 2 of eight channels to
output mixer S
Select channel 1 to PWM 1
0xAB
8
sel op1–8 and mix to T
Select 0 to 2 of eight channels to
output mixer T
Select channel 2 to PWM 2
0xAC
8
sel op1–8 and mix to U
Select 0 to 2 of eight channels to
output mixer U
Select channel 3 to PWM 3
0xAD
8
sel op1–8 and mix to V
Select 0 to 2 of eight channels to
output mixer V
Select channel 4 to PWM 4
0xAE
8
sel op1–8 and mix to W
Select 0 to 2 of eight channels to
output mixer W
Select channel 5 to PWM 5
0xAF
8
sel op1–8 and mix to X
Select 0 to 2 of eight channels to
output mixer X
Select channel 6 to PWM 6
0xB0
12
sel op1–8 and mix to Y
Select 0 to 3 of eight channels to
output mixer Y
Select channel 7 to PWM 7
0xB1
12
sel op1–8 and mix to Z
Select 0 to 3 of eight channels to
output mixer Z
Select channel 8 to PWM 8
0xD0
4
Vol, T and B slew rates
U (31:24), U (23:16), U (15:12)
VSR(11:8), TBSR(7:0)
0x00, 0x00, 0x01, 0x3F
0xD1
4
Ch1 volume
Channel 1 volume
0 dB
0xD2
4
Ch2 volume
Channel 2 volume
0 dB
0xD3
4
Ch3 volume
Channel 3 volume
0 dB
0xD4
4
Ch4 volume
Channel 4 volume
0 dB
0xB2–0xCF
50
DEFAULT STATE
Channel 1 delay = –23 DCLK
periods
Channel 2 delay = 0 DCLK periods
Channel 3 delay = –16 DCLK
periods
Channel 4 delay = 16 DCLK
periods
Channel 5 delay = –24 DCLK
periods
Channel 6 delay = 8 DCLK periods
Channel 7 delay = –8 DCLK
periods
Channel 8 delay = 24 DCLK
periods
0x24–0x3F
0x40
DESCRIPTION OF CONTENTS
TAS5028A
RESERVED
SLES112 — June 2004
Serial Control I 2C Register Summary
I2C
SUBADDRESS
TOTAL
BYTES
0xD5
4
Ch5 volume
Channel 5 volume
0 dB
0xD6
4
Ch6 volume
Channel 6 volume
0 dB
0xD7
4
Ch7 volume
Channel 7 volume
0 dB
0xD8
4
Ch8 volume
Channel 8 volume
0 dB
0xD9
4
Master volume
Master volume
Mute
OXDA
4
Bass filter set (1–5)
Bass filter set (all channels)
Filter set 3
REGISTER FIELDS
DESCRIPTION OF CONTENTS
DEFAULT STATE
0xDB
4
Bass filter index
Bass filter level (all channels)
0 dB
0xDC
4
Treble filter set (1–5)
Treble filter set (all channels)
Filter set 3
0xDD
4
Treble filter index
Treble filter level (all channels)
0 dB
0xDE
4
AM mode and tuned frequency
register
Set-up AM mode for AM-interference
reduction
AM mode disabled
Select sequence 1
IF frequency = 455 kHz
Use BCD-tuned frequency
4
General control register
0xDF
RESERVED
0xE0
0xE1–0xFD
0xFE
Six or eight channel configuration
Eight channel configuration
RESERVED
4 (min)
0xFF
SLES112 — June 2004
Multiple bit writer append
register
Special register
N/A
RESERVED
TAS5028A
51
Serial Control Interface Register Definitions
6
Serial Control Interface Register Definitions
Unless otherwise noted, the I2C register default values are in bold font.
Note that u indicates unused bits.
6.1
Clock Control Register (0x00)
Bit D1 is Don’t Care.
Table 6−1. Clock Control Register
D7
D6
D5
D4
D3
D2
0
0
0
−
−
−
−
32-kHz data rate
0
0
1
−
−
−
−
38-kHz data rate
0
1
0
−
−
−
−
44.1-kHz data rate
0
1
1
−
−
−
−
48-kHz data rate
1
0
0
−
−
−
−
88.2-kHz data rate
1
0
1
−
−
−
−
96-kHz data rate
1
1
0
−
−
−
−
176.4-kHz data rate
1
1
1
−
−
−
−
192-kHz data rate
−
−
−
0
0
0
MCLK frequency = 64
−
−
−
0
0
1
MCLK frequency = 128
−
−
−
0
1
0
MCLK frequency = 192
−
−
−
0
1
1
MCLK frequency = 256
−
−
−
1
0
0
MCLK frequency = 384
−
−
−
1
0
1
MCLK frequency = 512
−
−
−
1
1
0
MCLK frequency = 768
−
−
−
1
1
1
Reserved
−
−
−
−
−
−
1
Clock register is valid (read only)
−
−
−
−
−
−
0
Clock register is not valid (read only)
6.2
D1
D0
FUNCTION
General Status Register 0 (0x01)
Table 6−2. General Status Register (0x01)
D7
D6
D5
D4
D3
D2
D1
D0
1
−
−
−
−
−
−
−
Clip indicator
−
1
−
−
−
−
−
−
Bank switching busy
−
−
0
0
0
0
0
1
Identification code for TAS5028A
6.3
FUNCTION
Error Status Register (0x02)
Note that the error bits are sticky bits that are not cleared by the hardware. This means that the software must
clear the register (write zeroes) and then read them to determine if there are any persistent errors.
Table 6−3. Error Status Register (0X02)
D7
D6
D5
D4
D3
D2
D1
D0
1
−
−
−
−
−
−
−
PLL phase lock error
−
1
−
−
−
−
−
−
PLL auto lock error
−
−
1
−
−
−
−
−
SCLK error
−
−
−
1
−
−
−
−
LRCLK error
−
−
−
−
1
−
−
−
Frame slip
0
0
0
0
0
0
0
0
No errors
SLES120 − September 2004
FUNCTION
TAS5028A
53
Serial Control Interface Register Definitions
6.4
System Control Register 1 (0x03)
Bit D5, D2, D1, and D0 are Don’t Care.
Table 6−4. System Control Register 1
D7
D6
0
1
D4
D3
−
−
−
PWM high pass disabled
−
−
−
PWM high pass enabled
−
−
0
Soft unmute on recovery from clock error
−
−
1
Hard unmute on recovery from clock error
6.5
D5
D2
D1
D0
FUNCTION
System Control Register 2 (0x04)
Bit D3 and D2 are Don’t Care.
Table 6−5. System Control Register 2
D7
D6
D5
D4
0
−
−
−
0
−
−
1
D3
D2
D1
D0
FUNCTION
−
−
−
Reserved
−
−
−
PWM automute detection enabled
−
−
−
−
PWM automute detection disabled
0
−
−
−
8 Ch device input detection automute enabled
−
−
1
−
−
−
8 Ch device input detection automute disabled
−
−
−
0
−
−
Unmute threshold 6 dB over input threshold
−
−
−
1
−
−
Unmute threshold equal to input threshold
−
−
−
−
0
0
No de-emphasis
−
−
−
−
0
1
De-emphasis for Fs = 32 kHz
−
−
−
−
1
0
De-emphasis for Fs = 44.1 kHz
−
−
−
−
1
1
De-emphasis for Fs = 48 kHz
6.6
Channel Configuration Control Register (0x05−X0C)
Channels 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, and 0x0C.
Bit D0 is Don’t Care.
Table 6−6. Channel Configuration Control Registers
D7
D6
D5
D4
D3
D2
D1
0
−
−
−
−
−
−
Disable backend reset sequence for a channel – BEErrorRecEn
1
−
−
−
−
−
−
Enable backend reset sequence for a channel
−
0
−
−
−
−
−
Valid does not have to be low for this channel to be reset BEValidRst
−
1
−
−
−
−
−
Valid must be low for this channel to be reset
−
−
0
−
−
−
−
Valid does not have to be low for this channel to be muted BEValidMute
−
−
1
−
−
−
−
Valid must be low for this channel to be muted
−
−
−
0
−
−
−
Normal BEPolarity
−
−
−
1
−
−
−
Switches PWM+ and PWM– and invert audio signal
−
−
−
−
0
−
−
Do not remap output to comply with 5182 interface
−
−
−
−
1
−
−
Remap output to comply with 5182 interface
−
−
−
−
−
0
−
Do not go to low low in mute – BELowMute
−
−
−
−
−
1
−
Go to low-low in Mute
−
−
−
−
−
−
0
Do not remap Hi-Z state to low-low state – BE5111BsMute
−
−
−
−
−
−
1
Remap Hi-Z state to low-low state
54
TAS5028A
D0
FUNCTION
SLES120 − September 2004
Serial Control Interface Register Definitions
6.7
Headphone Configuration Control Register (0x0D)
Bit D0 is Don’t Care.
Table 6−7. Headphone Configuration Control Register
D7
D6
D5
D4
D3
D2
D1
0
−
−
−
−
−
−
Disable backend reset sequence for a channel – BEErrorRecEn
1
−
−
−
−
−
−
Enable backend reset sequence for a channel
−
0
−
−
−
−
−
Valid does not have to be low for this channel to be reset BEValidRst
−
1
−
−
−
−
−
Valid must be low for this channel to be reset
−
−
0
−
−
−
−
Valid does not have to be low for this channel to be muted BEValidMute
−
−
1
−
−
−
−
Valid must be low for this channel to be muted
−
−
−
0
−
−
−
Normal BEPolarity
−
−
−
1
−
−
−
Switches PWM+ and PWM– and invert audio signal
−
−
−
−
0
−
−
Do not remap output to comply with 5182 interface
−
−
−
−
1
−
−
Remap output to comply with 5182 interface
−
−
−
−
−
0
−
Do not go to low low in mute – BELowMute
−
−
−
−
−
1
−
Go to low-low in Mute
−
−
−
−
−
−
0
Do not remap Hi-Z state to low-low state – BE5111BsMute
−
−
−
−
−
−
1
Remap Hi-Z state to low-low state
6.8
D0
FUNCTION
Serial Data Interface Control Register (0x0E)
Nine serial modes can be programmed I2C.
Table 6−8. Serial Data Interface Control Register Format
RECEIVE SERIAL DATA
INTERFACE FORMAT
WORD LENGTHS
D7–D4
D3
D2
D1
D0
Right justified
16
0000
0
0
0
0
Right justified
20
0000
0
0
0
1
Right justified
24
0000
0
0
1
0
I2S
16
0000
0
0
1
1
I2S
20
0000
0
1
0
0
I2S
24
0000
0
1
0
1
Left justified
16
0000
0
1
1
0
Left justified
20
0000
0
1
1
1
Left justified
24
0000
1
0
0
0
Illegal
0000
1
0
0
1
Illegal
0000
1
0
1
0
Illegal
0000
1
0
1
1
Illegal
0000
1
1
0
0
Illegal
0000
1
1
0
1
Illegal
0000
1
1
1
0
Illegal
0000
1
1
1
1
SLES120 − September 2004
TAS5028A
55
Serial Control Interface Register Definitions
6.9
Soft Mute Register (0x0F)
Table 6−9. Soft Mute Register
D7
D6
D5
D4
D3
D2
D1
D0
Function
−
−
−
−
−
−
−
1
Soft−mute channel 1
−
−
−
−
−
−
1
−
Soft−mute channel 2
−
−
−
−
−
1
−
−
Soft−mute channel 3
−
−
−
−
1
−
−
−
Soft−mute channel 4
−
−
−
1
−
−
−
−
Soft−mute channel 5
−
−
1
−
−
−
−
−
Soft−mute channel 6
−
1
−
−
−
−
−
−
Soft−mute channel 7
1
−
−
−
−
−
−
−
Soft−mute channel 8
0
0
0
0
0
0
0
0
Unmute all channels
6.10 Automute Control Register(0x14)
Table 6−10. Automute Control Register
D7
D6
D5
D4
D3
D2
D1
D0
−
−
−
−
0
0
0
0
Set input automute and PWM automute delay to 1 ms
−
−
−
−
0
0
0
1
Set input automute and PWM automute delay to 2 ms
−
−
−
−
0
0
1
0
Set input automute and PWM automute delay to 3 ms
−
−
−
−
0
0
1
1
Set input automute and PWM automute delay to 4 ms
−
−
−
−
0
1
0
0
Set input automute and PWM automute delay to 5 ms
−
−
−
−
0
1
0
1
Set input automute and PWM automute delay to 10 ms
−
−
−
−
0
1
1
0
Set input automute and PWM automute delay to 20 ms
−
−
−
−
0
1
1
1
Set input automute and PWM automute delay to 30 ms
−
−
−
−
1
0
0
0
Set input automute and PWM automute delay to 40 ms
−
−
−
−
1
0
0
1
Set input automute and PWM automute delay to 50 ms
−
−
−
−
1
0
1
0
Set input automute and PWM automute delay to 60 ms
−
−
−
−
1
0
1
1
Set input automute and PWM automute delay to 70ms
−
−
−
−
1
1
0
0
Set input automute and PWM automute delay to 80 ms
−
−
−
−
1
1
0
1
Set input automute and PWM automute delay to 90 ms
−
−
−
−
1
1
1
0
Set input automute and PWM automute delay to 100 ms
−
−
−
−
1
1
1
1
Set input automute and PWM automute delay to 110 ms
0
0
0
0
−
−
−
0
0
0
1
−
−
−
−
Set input automute threshold less than bit 1 (zero input signal), lowest automute
threshold.
0
0
1
0
−
−
−
−
Set input automute threshold less than bit 2
0
0
1
1
−
−
−
−
Set input automute threshold less than bit 3
0
1
0
0
−
−
−
−
Set input automute threshold less than bit 4
0
1
0
1
−
−
−
−
Set input automute threshold less than bit 5
0
1
1
0
−
−
−
−
Set input automute threshold less than bit 6
0
1
1
1
−
−
−
−
Set input automute threshold less than bit 7
1
0
0
0
−
−
−
−
Set input automute threshold less than bit 8
1
0
0
1
−
−
−
−
Set input automute threshold less than bit 9
1
0
1
0
−
−
−
−
Set input automute threshold less than bit 10
1
0
1
1
−
−
−
−
Set input automute threshold less than bit 11
1
1
0
0
−
−
−
−
Set input automute threshold less than bit 12
1
1
0
1
−
−
−
−
Set input automute threshold less than bit 13
1
1
1
0
−
−
−
−
Set input automute threshold less than bit 14
1
1
1
1
−
−
−
−
Set input automute threshold less than bit 15
56
TAS5028A
FUNCTION
SLES120 − September 2004
Serial Control Interface Register Definitions
6.11 Automute PWM Threshold and Backend Reset Period (0x15)
Table 6−11. Automute PWM Threshold and Backend Reset Period
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
−
−
−
−
Set PWM automute threshold equals input automute threshold
FUNCTION
0
0
0
1
−
−
−
−
Set PWM automute threshold 1 bit more than input automute threshold
0
0
1
0
−
−
−
−
Set PWM automute threshold 2 bits more than input automute threshold
0
0
1
1
−
−
−
−
Set PWM automute threshold 3 bits more than input automute threshold
0
1
0
0
−
−
−
−
Set PWM automute threshold 4 bits more than input automute threshold
0
1
0
1
−
−
−
−
Set PWM automute threshold 5 bits more than input automute threshold
0
1
1
0
−
−
−
−
Set PWM automute threshold 6 bits more than input automute threshold
0
1
1
1
−
−
−
−
Set PWM automute threshold 7 bits more than input automute threshold
1
0
0
0
−
−
−
−
Set PWM automute threshold equals input automute threshold
1
0
0
1
−
−
−
−
Set PWM automute threshold 1 bit less than input automute threshold
1
0
1
0
−
−
−
−
Set PWM automute threshold 2 bits less than input automute threshold
1
0
1
1
−
−
−
−
Set PWM automute threshold 3 bits less than input automute threshold
1
1
0
0
−
−
−
−
Set PWM automute threshold 4 bits less than input automute threshold
1
1
0
1
Set PWM automute threshold 5 bits less than input automute threshold
1
1
1
0
Set PWM automute threshold 6 bits less than input automute threshold
1
1
1
1
Set PWM automute threshold 7 bits less than input automute threshold
−
−
−
−
0
0
0
0
Set backend reset period < 1 ms
−
−
−
−
0
0
0
1
Set backend reset period 1 ms
−
−
−
−
0
0
1
0
Set backend reset period 2 ms
−
−
−
−
0
0
1
1
Set backend reset period 3 ms
−
−
−
−
0
1
0
0
Set backend reset period 4 ms
−
−
−
−
0
1
0
1
Set backend reset period 5 ms
−
−
−
−
0
1
1
0
Set backend reset period 6 ms
−
−
−
−
0
1
1
1
Set backend reset period 7 ms
−
−
−
−
1
0
0
0
Set backend reset period 8 ms
−
−
−
−
1
0
0
1
Set backend reset period 9 ms
−
−
−
−
1
0
1
0
Set backend reset period 10 ms
−
−
−
−
1
0
1
1
Set backend reset period 10 ms
−
−
−
−
1
1
X
X
Set backend reset period 10 ms
6.12 Modulation Index Limit Register (0x16)
Table 6−12. Modulation Index Limit Register
D7
D6
D5
SLES120 − September 2004
D4
D3
D2
D1
D0
LIMIT
[DCLKS]
MIN WIDTH
[DCLKS]
MODULATION INDEX
0
0
0
1
2
99.2%
0
0
1
2
4
98.4%
0
1
0
3
6
97.7%
0
1
1
4
8
96.9%
1
0
0
5
10
96.1%
1
0
1
6
12
95.3%
1
1
0
7
14
94.5%
1
1
1
8
16
93.8%
TAS5028A
57
Serial Control Interface Register Definitions
6.13 Interchannel Channel Delay Registers (0x1B – 0x22) and Offset Register (0x23)
Channels 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into (0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x20, 0x21, and 0x22).
Bits D1 and D0 are Don’t Care.
Table 6−13. Interchannel Channel Delay Registers
D7
D6
D5
D4
D3
D2
0
0
0
0
0
0
D1
D0
Minimum absolute delay, 0 DCLK cycles, default for channel 1
FUNCTION
0
1
1
1
1
1
Maximum positive delay, 31 × 4 DCLK cycles
1
0
0
0
0
0
Maximum negative delay, –32 × 4 DCLK cycles
1
0
0
0
0
0
Default value for Channel 1: –32
0
0
0
0
0
0
Default value for Channel 2: 0
1
1
0
0
0
0
Default value for Channel 3: –16
0
1
0
0
0
0
Default value for Channel 4: 16
1
0
1
0
0
0
Default value for Channel 5: –24
0
0
1
0
0
0
Default value for Channel 6: 8
1
1
1
0
0
0
Default value for Channel 7: –8
0
1
1
0
0
0
Default value for Channel 8: 24
The offset register is mapped into 0x23.
Table 6−14. Channel Offset Register
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
Minimum absolute offset, 0 DCLK cycles default for channel 1
1
1
1
1
1
1
1
1
Maximum absolute delay, 255 DCLK cycles
58
TAS5028A
FUNCTION
SLES120 − September 2004
Serial Control Interface Register Definitions
6.14 Bank Switching Command (0x40)
Bits D31–D24, D22–D19 are Don’t Care.
Table 6−15. Bank Switching Command
D31
D30
D29
D28
D27
D26
D25
D24
FUNCTION
Unused bits
D23
D18
D17
D16
−
D22
D21
D20
D19
0
0
0
Manual selection bank 1
FUNCTION
−
0
0
1
Manual selection bank 2
−
0
1
0
Manual selection bank 3
−
0
1
1
Automatic bank selection
−
1
0
0
Update the values in bank 1
−
1
0
1
Update the values in bank 2
−
1
1
0
Update the values in bank 3
0
1
1
1
Update only the bank map
0
x
x
x
Update the bank map using values in
D15–D0
1
x
x
x
Do not update the bank map using
values in D15–D0
D15
D14
D13
D12
D11
D10
D9
D8
1
−
−
−
−
−
−
−
32-kHz data rate – use bank 1
−
1
−
−
−
−
−
−
38-kHz data rate – use bank 1
−
−
1
−
−
−
−
−
44.1-kHz data rate – use bank 1
−
−
−
1
−
−
−
−
48-kHz data rate – use bank 1
−
−
−
−
1
−
−
−
88.2-kHz data rate – use bank 1
−
−
−
−
−
1
−
−
96-kHz data rate – use bank 1
−
−
−
−
−
−
1
−
176.4-kHz data rate – use bank 1
−
−
−
−
−
−
−
1
192-kHz data rate – use bank 1
1
1
1
1
1
1
1
1
Default
D7
D6
D5
D4
D3
D2
D1
D0
1
−
−
−
−
−
−
−
32-kHz data rate – use bank 2
−
1
−
−
−
−
−
−
38-kHz data rate – use bank 2
−
−
1
−
−
−
−
−
44.1-kHz data rate – use bank 2
−
−
−
1
−
−
−
−
48-kHz data rate – use bank 2
−
−
−
−
1
−
−
−
88.2-kHz data rate – use bank 2
−
−
−
−
−
1
−
−
96-kHz data rate – use bank 2
−
−
−
−
−
−
1
−
176.4-kHz data rate – use bank 2
−
−
−
−
−
−
−
1
192-kHz data rate – use bank 2
1
1
1
1
1
1
1
1
Default
SLES120 − September 2004
FUNCTION
FUNCTION
TAS5028A
59
Serial Control Interface Register Definitions
6.15 Input Mixer Registers (0x41 – 0x48, Channels 1 – 8)
Input mixers 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into registers 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, and
0x48.
Each gain coefficient is in 28-bit (5.23) format so 0x800000 is a gain of 1. Each gain coefficient is written as
a 32-bit word with the upper 4 bits not used. For 8-gain coefficients, the total is 32 bytes.
Bold indicates the one channel that is passed through the mixer.
Table 6−16. Input Mixer Registers Format (0x41 – 0x48, Channels 1 – 8)
I2C
SUBADDRESS
0x41
0x42
60
TAS5028A
TOTAL
BYTES
REGISTER
FIELDS
DESCRIPTION OF CONTENTS
DEFAULT STATE
A_to_ipmix[1]
SDIN1–Left (Ch 1) A to Input Mixer 1 coefficient (default = 1)
U (31:28), A_1 (27:24), A_1 (23:16), A_1 (15:8), A_1 (7:0)
0x00, 0x80, 0x00, 0x00
B_to_ipmix[1]
SDIN1–Right (Ch 2) B to input mixer 1 coefficient (default = 0)
U (31:28), B_1 (27:24), B_1 (23:16), B_1 (15:8), B_1 (7:0)
0x00, 0x00, 0x00, 0x00
C_to_ipmix[1]
SDIN2–Left (Ch 3) C to input mixer 1 coefficient (default = 0)
U (31:28), C_1 (27:24), C_1 (23:16), C_1 (15:8), C_1 (7:0)
0x00, 0x00, 0x00, 0x00
D_to_ipmix[1]
SDIN2–Right (Ch 4) D to input mixer 1 coefficient (default = 0)
U (31:28), D_1 (27:24), D_1 (23:16), D_1 (15:8), D_1 (7:0)
0x00, 0x00, 0x00, 0x00
E_to_ipmix[1]
SDIN3–Left (Ch 5) E to input mixer 1 coefficient (default = 0)
U (31:28), E_1 (27:24), E_1 (23:16), E_1 (15:8), E_1 (7:0)
0x00, 0x00, 0x00, 0x00
F_to_ipmix[1]
SDIN3–Right (Ch 6) F to input mixer 1 coefficient (default = 0)
U (31:28), F_1 (27:24), F_1 (23:16), F_1 (15:8), F_1 (7:0)
0x00, 0x00, 0x00, 0x00
G_to_ipmix[1]
SDIN4–Left (Ch 7) G to input mixer 1 coefficient (default = 0)
U (31:28), G_1 (27:24), G_1 (23:16), G_1 (15:8), G_1 (7:0)
0x00, 0x00, 0x00, 0x00
H_to_ipmix[1]
SDIN4–Right (Ch 8) H to input mixer 1 coefficient (default = 0)
U (31:28), H_1 (27:24), H_1 (23:16), H_1 (15:8), H_1 (7:0)
0x00, 0x00, 0x00, 0x00
A_to_ipmix[2]
SDIN1–Left (Ch 1) A to input mixer 2 coefficient (default = 0)
U (31:28), A_2 (27:24), A_2 (23:16), A_2 (15:8), A_2 (7:0)
0x00, 0x00, 0x00, 0x00
B_to_ipmix[2]
SDIN1–Right (Ch 2) B to input mixer 2 coefficient (default = 1)
U (31:28), B_2 (27:24), B_2 (23:16), B_2 (15:8), B_2 (7:0)
0x00, 0x80, 0x00, 0x00
C_to_ipmix[2]
SDIN2–Left (Ch 3) C to input mixer 2 coefficient (default = 0)
U (31:28), C_2(27:24), C_2(23:16), C_2(15:8), C_2(7:0)
0x00, 0x00, 0x00, 0x00
D_to_ipmix[2]
SDIN2–Right (Ch 4) D to input mixer 2 coefficient (default = 0)
U (31:28), D_2 (27:24), D_2 (23:16), D_2 (15:8), D_2 (7:0)
0x00, 0x00, 0x00, 0x00
E_to_ipmix[2]
SDIN3–Left (Ch 5) E to input mixer 2 coefficient (default = 0)
U (31:28), E_2 (27:24), E_2 (23:16), E_2 (15:8), E_2 (7:0)
0x00, 0x00, 0x00, 0x00
F_to_ipmix[2]
SDIN3–Right (Ch 6) F to input mixer 2 coefficient (default = 0)
U (31:28), F_2 (27:24), F_2 (23:16), F_2 (15:8), F_2 (7:0)
0x00, 0x00, 0x00, 0x00
G_to_ipmix[2]
SDIN4–Left (Ch 7) G to input mixer 2 coefficient (default = 0)
U (31:28), G_2 (27:24), G_2 (23:16), G_2 (15:8), G_2 (7:0)
0x00, 0x00, 0x00, 0x00
H_to_ipmix[2]
SDIN4–Right (Ch 8) H to input mixer 2 coefficient (default = 0)
U (31:28), H_2 (27:24), H_2 (23:16), H_2 (15:8), H_2 (7:0)
0x00, 0x00, 0x00, 0x00
32
32
SLES120 − September 2004
Serial Control Interface Register Definitions
I2C
SUBADDRESS
0x43
0x44
0x45
TOTAL
BYTES
REGISTER
FIELDS
DEFAULT STATE
A_to_ipmix[3]
SDIN1–Left (Ch 1) A to input mixer 3 coefficient (default = 0)
U (31:28), A_3 (27:24), A_3 (23:16), A_3 (15:8), A_3 (7:0)
0x00, 0x00, 0x00, 0x00
B_to_ipmix[3]
SDIN1–Right (Ch 2) B to input mixer 3 coefficient (default = 0)
U (31:28), B_3 (27:24), B_3 (23:16), B_3 (15:8), B_3 (7:0)
0x00, 0x00, 0x00, 0x00
C_to_ipmix[3]
SDIN2–Left (Ch 3) C to input mixer 3 coefficient (default = 1)
U (31:28), C_3 (27:24), C_3 (23:16), C_3 (15:8), C_3 (7:0)
0x00, 0x80, 0x00, 0x00
D_to_ipmix[3]
SDIN2–Right (Ch 4) D to input mixer 3 coefficient (default = 0)
U (31:28), D_3 (27:24), D_3 (23:16), D_3 (15:8), D_3 (7:0)
0x00, 0x00, 0x00, 0x00
E_to_ipmix[3]
SDIN3–Left (Ch 5) E to input mixer 3 coefficient (default = 0)
U (31:28), E_3 (27:24), E_3 (23:16), E_3 (15:8), E_3 (7:0)
0x00, 0x00, 0x00, 0x00
F_to_ipmix[3]
SDIN3–Right (Ch 6) F to input mixer 3 coefficient (default = 0)
U (31:28), F_3 (27:24), F_3 (23:16), F_3 (15:8), F_3 (7:0)
0x00, 0x00, 0x00, 0x00
G_to_ipmix[3]
SDIN4–Left (Ch 7) G to input mixer 3 coefficient (default = 0)
U (31:28), G_3 (27:24), G_3 (23:16), G_3 (15:8), G_3 (7:0)
0x00, 0x00, 0x00, 0x00
H_to_ipmix[3]
SDIN4–Right (Ch 8) H to input mixer 3 coefficient (default = 0)
U (31:28), H_3 (27:24), H_3 (23:16), H_3 (15:8), H_3 (7:0)
0x00, 0x00, 0x00, 0x00
A_to_ipmix[4]
SDIN1–Left (Ch 1) A to input mixer 4 coefficient (default = 0)
U (31:28), A_4 (27:24), A_4 (23:16), A_4 (15:8), A_4 (7:0)
0x00, 0x00, 0x00, 0x00
B_to_ipmix[4]
SDIN1–Right (Ch 2) B to input mixer 4 coefficient (default = 0)
U (31:28), B_4 (27:24), B_4 (23:16), B_4 (15:8), B_4 (7:0)
0x00, 0x00, 0x00, 0x00
C_to_ipmix[4]
SDIN2–Left (Ch 3) C to input mixer 4 coefficient (default = 0)
U (31:28), C_4 (27:24), C_4 (23:16), C_4 (15:8), C_4 (7:0)
0x00, 0x00, 0x00, 0x00
D_to_ipmix[4]
SDIN2–Right (Ch 4) D to input mixer 4 coefficient (default = 1)
U (31:28), D_4 (27:24), D_4 (23:16), D_4 (15:8), D_4 (7:0)
0x00, 0x80, 0x00, 0x00
E_to_ipmix[4]
SDIN3–Left (Ch 5) E to input mixer 4 coefficient (default = 0)
U (31:28), E_4 (27:24), E_4 (23:16), E_4 (15:8), E_4 (7:0)
0x00, 0x00, 0x00, 0x00
F_to_ipmix[4]
SDIN3–Right (Ch 6) F to input mixer 4 coefficient (default = 0)
U (31:28), F_4 (27:24), F_4 (23:16), F_4 (15:8), F_4 (7:0)
0x00, 0x00, 0x00, 0x00
G_to_ipmix[4]
SDIN4–Left (Ch 7) G to input mixer 4 coefficient (default = 0)
U (31:28), G_4 (27:24), G_4 (23:16), G_4 (15:8), G_4 (7:0)
0x00, 0x00, 0x00, 0x00
H_to_ipmix[4]
SDIN4–Right (Ch 8) H to input mixer 4 coefficient (default = 0)
U (31:28), H_4 (27:24), H_4 (23:16), H_4 (15:8), H_4 (7:0)
0x00, 0x00, 0x00, 0x00
A_to_ipmix[5]
SDIN1–Left (Ch 1) A to input mixer 5 coefficient (default = 0)
U (31:28), A_5 (27:24), A_5 (23:16), A_5 (15:8), A_5 (7:0)
0x00, 0x00, 0x00, 0x00
B_to_ipmix[5]
SDIN1–Right (Ch 2) B to input mixer 5 coefficient (default = 0)
U (31:28), B_5 (27:24), B_5 (23:16), B_5 (15:8), B_5 (7:0)
0x00, 0x00, 0x00, 0x00
C_to_ipmix[5]
SDIN2–Left (Ch 3) C to input mixer 5 coefficient (default = 0)
U (31:28), C_5 (27:24), C_5 (23:16), C_5 (15:8), C_5 (7:0)
0x00, 0x00, 0x00, 0x00
D_to_ipmix[5]
SDIN2–Right (Ch 4) D to input mixer 5 coefficient (default = 0)
U (31:28), D_5 (27:24), D_5 (23:16), D_5 (15:8), D_5 (7:0)
0x00, 0x00, 0x00, 0x00
E_to_ipmix[5]
SDIN3–Left (Ch 5) E to input mixer 5 coefficient (default = 1)
U (31:28), E_5 (27:24), E_5 (23:16), E_5 (15:8), E_5 (7:0)
0x00, 0x80, 0x00, 0x00
F_to_ipmix[5]
SDIN3–Right (Ch 6) F to input mixer 5 coefficient (default = 0)
U (31:28), F_5 (27:24), F_5 (23:16), F_5 (15:8), F_5 (7:0)
0x00, 0x00, 0x00, 0x00
G_to_ipmix[5]
SDIN4–Left (Ch 7) G to input mixer 5 coefficient (default = 0)
U (31:28), G_5 (27:24), G_5 (23:16), G_5 (15:8), G_5 (7:0)
0x00, 0x00, 0x00, 0x00
H_to_ipmix[5]
SDIN4–Right (Ch 8) H to input mixer 5 coefficient (default = 0)
U (31:28), H_5 (27:24), H_5 (23:16), H_5 (15:8), H_5 (7:0)
0x00, 0x00, 0x00, 0x00
32
32
32
SLES120 − September 2004
DESCRIPTION OF CONTENTS
TAS5028A
61
Serial Control Interface Register Definitions
I2C
SUBADDRESS
0x46
0x47
0x48
62
TAS5028A
TOTAL
BYTES
REGISTER
FIELDS
DESCRIPTION OF CONTENTS
DEFAULT STATE
A_to_ipmix[6]
SDIN1–Left (Ch 1) A to input mixer 6 coefficient (default = 0)
U (31:28), A_6 (27:24), A_6 (23:16), A_6 (15:8), A_6 (7:0)
0x00, 0x00, 0x00, 0x00
B_to_ipmix[6]
SDIN1–Right (Ch 2) B to input mixer 6 coefficient (default = 0)
U (31:28), B_6 (27:24), B_6 (23:16), B_6 (15:8), B_6 (7:0)
0x00, 0x00, 0x00, 0x00
C_to_ipmix[6]
SDIN2–Left (Ch 3) C to input mixer 6 coefficient (default = 0)
U (31:28), C_6 (27:24), C_6 (23:16), C_6 (15:8), C_6 (7:0)
0x00, 0x00, 0x00, 0x00
D_to_ipmix[6]
SDIN2–Right (Ch 4) D to input mixer 6 coefficient (default = 0)
U (31:28), D_6 (27:24), D_6 (23:16), D_6 (15:8), D_6 (7:0)
0x00, 0x00, 0x00, 0x00
E_to_ipmix[6]
SDIN3–Left (Ch 5) E to input mixer 6 coefficient (default = 0)
U (31:28), E_6 (27:24), E_6 (23:16), E_6 (15:8), E_6 (7:0)
0x00, 0x00, 0x00, 0x00
F_to_ipmix[6]
SDIN3–Right (Ch 6) F to input mixer 6 coefficient (default = 1)
U (31:28), F_6 (27:24), F_6 (23:16), F_6 (15:8), F_6 (7:0)
0x00, 0x80, 0x00, 0x00
G_to_ipmix[6]
SDIN4–Left (Ch 7) G to input mixer 6 coefficient (default = 0)
U (31:28), G_6 (27:24), G_6 (23:16), G_6 (15:8), G_6 (7:0)
0x00, 0x00, 0x00, 0x00
H_to_ipmix[6]
SDIN4–Right (Ch 8) H to input mixer 6 coefficient (default = 0)
U (31:28), H_6 (27:24), H_6 (23:16), H_6 (15:8), H_6 (7:0)
0x00, 0x00, 0x00, 0x00
A_to_ipmix[7]
SDIN1–Left (Ch 1) A to input mixer 7 coefficient (default = 0)
U (31:28), A_7 (27:24), A_7 (23:16), A_7 (15:8), A_7 (7:0)
0x00, 0x00, 0x00, 0x00
B_to_ipmix[7]
SDIN1–Right (Ch 2) B to input mixer 7 coefficient (default = 0)
U (31:28), B_7 (27:24), B_7 (23:16), B_7 (15:8), B_7 (7:0)
0x00, 0x00, 0x00, 0x00
C_to_ipmix[7]
SDIN2–Left (Ch 3) C to input mixer 7 coefficient (default = 0)
U (31:28), C_7 (27:24), C_7 (23:16), C_7 (15:8), C_7 (7:0)
0x00, 0x00, 0x00, 0x00
D_to_ipmix[7]
SDIN2–Right (Ch 4) D to input mixer 7 coefficient (default = 0)
U (31:28), D_7 (27:24), D_7 (23:16), D_7 (15:8), D_7 (7:0)
0x00, 0x00, 0x00, 0x00
E_to_ipmix[7]
SDIN3–Left (Ch 5) E to input mixer 7 coefficient (default = 0)
U (31:28), E_7 (27:24), E_7 (23:16), E_7 (15:8), E_7 (7:0)
0x00, 0x00, 0x00, 0x00
F_to_ipmix[7]
SDIN3–Right (Ch 6) F to input mixer 7 coefficient (default = 0)
U (31:28), F_7 (27:24), F_7 (23:16), F_7 (15:8), F_7 (7:0)
0x00, 0x00, 0x00, 0x00
G_to_ipmix[7]
SDIN4–Left (Ch 7) G to input mixer 7 coefficient (default = 1)
U (31:28), G_7 (27:24), G_7 (23:16), G_7 (15:8), G_7 (7:0)
0x00, 0x80, 0x00, 0x00
H_to_ipmix[7]
SDIN4–Right (Ch 8) H to input mixer 7 coefficient (default = 0)
U (31:28), H_7 (27:24), H_7 (23:16), H_7 (15:8), H_7 (7:0)
0x00, 0x00, 0x00, 0x00
A_to_ipmix[8]
SDIN1–Left (Ch 1) A to input mixer 8 coefficient (default = 0)
U (31:28), A_8 (27:24), A_8 (23:16), A_8 (15:8), A_8 (7:0)
0x00, 0x00, 0x00, 0x00
B_to_ipmix[8]
SDIN1–Right (Ch 2) B to input mixer 8 coefficient (default = 0)
U (31:28), B_8 (27:24), B_8 (23:16), B_8 (15:8), B_8 (7:0)
0x00, 0x00, 0x00, 0x00
C_to_ipmix[8]
SDIN2–Left (Ch 3) C to input mixer 8 coefficient (default = 0)
U (31:28), C_8 (27:24), C_8 (23:16), C_8 (15:8), C_8 (7:0)
0x00, 0x00, 0x00, 0x00
D_to_ipmix[8]
SDIN2–Right (Ch 4) D to input mixer 8 coefficient (default = 0)
U (31:28), D_8 (27:24), D_8 (23:16), D_8 (15:8), D_8 (7:0)
0x00, 0x00, 0x00, 0x00
E_to_ipmix[8]
SDIN3–Left (Ch 5) E to input mixer 8 coefficient (default = 0)
U (31:28), E_8 (27:24), E_8 (23:16), E_8 (15:8), E_8 (7:0)
0x00, 0x00, 0x00, 0x00
F_to_ipmix[8]
SDIN3–Right (Ch 6) F to input mixer 8 coefficient (default = 0)
U (31:28), F_8 (27:24), F_8 (23:16), F_8 (15:8), F_8 (7:0)
0x00, 0x00, 0x00, 0x00
G_to_ipmix[8]
SDIN4–Left (Ch 7) G to input mixer 8 coefficient (default = 0)
U (31:28), G_8 (27:24), G_8 (23:16), G_8 (15:8), G_8 (7:0)
0x00, 0x00, 0x00, 0x00
H_to_ipmix[8]
SDIN4–Right (Ch 8) H to input mixer 8 coefficient (default = 1)
U (31:28), H_8 (27:24), H_8 (23:16), H_8 (15:8), H_8 (7:0)
0x00, 0x80, 0x00, 0x00
32
32
32
SLES120 − September 2004
Serial Control Interface Register Definitions
6.16 Bass and Treble Bypass Register (0x89 – 0x90, Channels 1 – 8)
Channels 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into registers 0x89, 0x8A, 0x8B, 0x8C,0x8D, 0x8E, 0x8F, and
0x90. Eight bytes are written for each channel. Each gain coefficient is in 28-bit (5.23) format so 0x800000
is a gain of 1. Each gain coefficient is written as a 32-bit word with the upper four bits not used.
Table 6−17. Bass and Treble Bypass Register Format (0x89–0x90)
REGISTER NAME
TOTAL BYTES
Channel bass and
treble bypass
8
Channel bass and
treble inline
CONTENTS
INITIALIZATION VALUE
U 31:28), Bypass (27:24), Bypass (23:16), Bypass (15:8), Bypass (7:0)
0x00, 0x80, 0x00, 0x00
U (31:28), Inline (27:24), Inline (23:16), Inline (15:8), Inline (7:0)
0x00, 0x00, 0x00, 0x00
6.17 8x2 Output Mixer Registers (0xAA – 0xAF)
Output mixers for channels 1–6 map to registers 0xAA – 0xAF.
Total data per register is 8 bytes.
Table 6−18. Output Mixer Control Register Format (Upper 4 Bytes)
D31
D30
D29
D28
0
0
0
0
D27
D26
D25
D24
Select channel 1 to output mixer
0
0
0
1
Select channel 2 to output mixer
0
0
1
0
Select channel 3 to output mixer
0
0
1
1
Select channel 4 to output mixer
0
1
0
0
Select channel 5 to output mixer
0
1
0
1
Select channel 6 to output mixer
0
1
1
0
Select channel 7 to output mixer
0
1
1
1
Select channel 8 to output mixer
G27
G26
G25
G24
D23
D22
D21
D20
D19
D18
D17
D16
G23
G22
G21
G20
G19
G18
G17
G16
D15
D14
D13
D12
D11
D10
D9
D8
G15
G14
G13
G12
G11
G10
G9
G8
D7
D6
D5
D4
D3
D2
D1
D0
G7
G6
G5
G4
G3
G2
G1
G0
SLES120 − September 2004
FUNCTION
Selected channel gain (upper 4 bits)
FUNCTION
Selected channel gain (continued)
FUNCTION
Selected channel gain (continued)
FUNCTION
Selected channel gain (lower 8 bits)
TAS5028A
63
Serial Control Interface Register Definitions
Table 6−19. Output Mixer Control (Lower 4 Bytes)
D31
D30
D29
D28
D27
0
0
0
0
Select channel 1 to output mixer
0
0
0
1
Select channel 2 to output mixer
0
0
1
0
Select channel 3 to output mixer
0
0
1
1
Select channel 4 to output mixer
0
1
0
0
Select channel 5 to output mixer
0
1
0
1
Select channel 6 to output mixer
0
1
1
0
Select channel 7 to output mixer
0
1
1
1
Select channel 8 to output mixer
G27
D26
G26
D25
G25
D24
G24
D23
D22
D21
D20
D19
D18
D17
D16
G23
G22
G21
G20
G19
G18
G17
G16
D15
D14
D13
D12
D11
D10
D9
D8
G15
G14
G13
G12
G11
G10
G9
G8
D7
D6
D5
D4
D3
D2
D1
D0
G7
G6
G5
G4
G3
G2
G1
G0
FUNCTION
Selected channel gain (upper 4 bits)
FUNCTION
Selected channel gain (continued)
FUNCTION
Selected channel gain (continued)
FUNCTION
Selected channel gain (lower 8 bits)
6.18 8x3 Output Mixer Registers (0xB0 – 0xB1)
Output mixers for channels 7 and 8 map to registers 0xB0 and 0xB1.
Total data per register is 12 bytes.
Table 6−20. Output Mixer Control (Upper 4 Bytes)
D31
D30
D29
D28
D27
D26
D25
D24
0
0
0
0
Select channel 1 to output mixer
0
0
0
1
Select channel 2 to output mixer
0
0
1
0
Select channel 3 to output mixer
0
0
1
1
Select channel 4 to output mixer
0
1
0
0
Select channel 5 to output mixer
0
1
0
1
Select channel 6 to output mixer
0
1
1
0
Select channel 7 to output mixer
0
1
1
1
Select channel 8 to output mixer
G27
G26
G25
G24
D23
D22
D21
D20
D19
D18
D17
D16
G23
G22
G21
G20
G19
G18
G17
G16
D15
D14
D13
D12
D11
D10
D9
D8
G15
G14
G13
G12
G11
G10
G9
G8
D7
D6
D5
D4
D3
D2
D1
D0
G7
G6
G5
G4
G3
G2
G1
G0
64
TAS5028A
FUNCTION
Selected channel gain (upper 4 bits)
FUNCTION
Selected channel gain (continued)
FUNCTION
Selected channel gain (continued)
FUNCTION
Selected channel gain (lower 8 bits)
SLES120 − September 2004
Serial Control Interface Register Definitions
Table 6−21. Output Mixer Control (Middle 4 Bytes)
D31
D30
D29
D28
D27
D26
D25
D24
0
0
0
0
Select channel 1 to output mixer
0
0
0
1
Select channel 2 to output mixer
0
0
1
0
Select channel 3 to output mixer
0
0
1
1
Select channel 4 to output mixer
0
1
0
0
Select channel 5 to output mixer
0
1
0
1
Select channel 6 to output mixer
0
1
1
0
Select channel 7 to output mixer
0
1
1
1
Select channel 8 to output mixer
G27
G26
G25
G24
FUNCTION
Selected channel gain (upper 4 bits)
D23
D22
D21
D20
D19
D18
D17
D16
FUNCTION
G23
G22
G21
G20
G19
G18
G17
G16
D15
D14
D13
D12
D11
D10
D9
D8
G15
G14
G13
G12
G11
G10
G9
G8
D7
D6
D5
D4
D3
D2
D1
D0
G7
G6
G5
G4
G3
G2
G1
G0
D31
D30
D29
D28
D27
0
0
0
0
Select channel 1 to output mixer
0
0
0
1
Select channel 2 to output mixer
0
0
1
0
Select channel 3 to output mixer
0
0
1
1
Select channel 4 to output mixer
0
1
0
0
Select channel 5 to output mixer
0
1
0
1
Select channel 6 to output mixer
0
1
1
0
Select channel 7 to output mixer
0
1
1
1
Select channel 8 to output mixer
Selected channel gain (continued)
FUNCTION
Selected channel gain (continued)
FUNCTION
Selected channel gain (lower 8 bits)
Table 6−22. Output Mixer Control (Lower 4 Bytes)
D26
D25
D24
G27
G26
G25
G24
D23
D22
D21
D20
D19
D18
D17
D16
G23
G22
G21
G20
G19
G18
G17
G16
D15
D14
D13
D12
D11
D10
D9
D8
G15
G14
G13
G12
G11
G10
G9
G8
D7
D6
D5
D4
D3
D2
D1
D0
G7
G6
G5
G4
G3
G2
G1
G0
FUNCTION
Selected channel gain (upper 4 bits)
FUNCTION
Selected channel gain (continued)
FUNCTION
Selected channel gain (continued)
FUNCTION
Selected channel gain (lower 8 bits)
6.19 Volume Treble and Bass Slew Rates (0xD0)
Table 6−23. Volume Gain Update Rate (Slew Rate)
D31–D10
D9
D8
0
0
0
512 step update at 4 Fs, 42.6 ms at 48 kHz
0
0
1
1024 step update at 4 Fs, 85.3 ms at 48 kHz
0
1
0
2048 step update at 4 Fs, 170 ms at 48 kHz
0
1
1
2048 step update at 4 Fs, 170 ms at 48 kHz
SLES120 − September 2004
FUNCTION
TAS5028A
65
Serial Control Interface Register Definitions
Table 6−24. Treble and Bass Gain Step Size (Slew Rate)
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
Minimum rate – Updates every 0.083 ms (every LRCLK at 48 kHz)
0
0
1
0
0
0
0
0
Update ever 0.67 ms (32 LRCLKs at 48 kHz)
0
0
1
1
1
1
1
1
Default rate – Updates every 1.31 ms (63 LRCLKs at 48 kHz). This is the
maximum constant time that can be set for all sample rates.
1
1
1
1
1
1
1
1
Minimum rate – Updates every 5.08 ms (every 255 LRCLKs at 48 kHz)
No operation
6.20 Volume Registers (0xD1 – 0xD9)
Channels 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into registers 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, and
0xD8.
Master volume is mapped into register 0xD9.
Bits D31 – D12 are Don’t Care.
Table 6−25. Volume Registers
D31
D30
D29
D28
D27
D26
D25
D24
FUNCTION
Unused bits
D23
D22
D21
D20
D19
D18
D17
D16
FUNCTION
Unused bits
D15
D14
D13
D12
D11
D10
D9
D8
V11
V10
V9
V8
D7
D6
D5
D4
D3
D2
D1
D0
V7
V6
V5
V4
V3
V2
V1
V0
66
TAS5028A
FUNCTION
Volume
FUNCTION
Volume
SLES120 − September 2004
Serial Control Interface Register Definitions
Table 6−26. Master and Individual Volume Controls
VOLUME INDEX (H)
GAIN/INDEX
EXPECTED
ACTUAL
001
17.75
17.81
17.81
002
17.5
17.56
17.56
003
17.25
17.31
17.31
004
17
17.06
17.06
005
16.75
16.81
16.81
006
16.5
16.56
16.56
007
16.25
16.31
16.31
008
16
16.05
16.05
009
15.75
15.8
15.8
00A
15.5
15.55
15.55
00B
15.25
15.3
15.3
00C
15
15.05
15.05
00D
14.75
14.8
14.8
00E
14.5
14.55
14.55
00F
14.25
14.3
14.3
010
14
14.05
14.05
044
1
1
1
045
0.75
0.75
0.75
046
0.5
0.5
0.5
047
0.25
0.25
0.25
048
0
0
0
049
–0.25
–0.25
–0.25
04A
–0.5
–0.5
–0.5
–0.75
04B
–0.75
–0.75
04C
–1
–1
–1
240
–126
–126.43
–126.43
241
–126.25
–126.68
–126.99
242
–126.5
–126.93
–126.99
243
–126.75
–127.19
–127.59
244
–127
–127.44
–127.59
245
Mute
Mute
Mute
3FF
Mute
Mute
Mute
TO
6.21 Bass Filter Set Register (0xDA)
Bits D31–D27, D23–D19, D15–D11, and D7–D3 are Don’t Care.
Table 6−27. Channel 8 Sub Woofer
D31
D30
D29
D28
D27
D26
D25
D24
0
0
0
0
0
0
0
0
No change
0
0
0
0
0
0
0
1
Bass filter set 1
0
0
0
0
0
0
1
0
Bass filter set 2
0
0
0
0
0
1
1
1
Bass filter set 3
0
0
0
0
0
1
0
0
Bass filter set 4
0
0
0
0
0
1
0
1
Bass filter set 5
0
0
0
0
0
1
1
0
Illegal
0
0
0
0
0
1
1
1
Illegal
SLES120 − September 2004
FUNCTION
TAS5028A
67
Serial Control Interface Register Definitions
Table 6−28. Channel 6 and 5 (Right and Left Lineout in Six Channel Configuration Right and
Left Surround in Eight Channel Configuration)
D23
D22
D21
D20
D19
D18
D17
D16
FUNCTION
0
0
0
0
0
0
0
0
No change
0
0
0
0
0
0
0
1
Bass filter set 1
0
0
0
0
0
0
1
0
Bass filter set 2
0
0
0
0
0
1
1
1
Bass filter set 3
0
0
0
0
0
1
0
0
Bass filter set 4
0
0
0
0
0
1
0
1
Bass filter set 5
0
0
0
0
0
1
1
0
Illegal
0
0
0
0
0
1
1
1
Illegal
Table 6−29. Channel 4 and 3 (Right and Left Rear)
D15
D14
D13
D12
D11
D10
D9
D8
0
0
0
0
0
0
0
0
No change
FUNCTION
0
0
0
0
0
0
0
1
Bass filter set 1
0
0
0
0
0
0
1
0
Bass filter set 2
0
0
0
0
0
1
1
1
Bass filter set 3
0
0
0
0
0
1
0
0
Bass filter set 4
0
0
0
0
0
1
0
1
Bass filter set 5
0
0
0
0
0
1
1
0
Illegal
0
0
0
0
0
1
1
1
Illegal
Table 6−30. Channel 7, 2, 1 (Center, Right Front, and Left Front)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
No change
FUNCTION
0
0
0
0
0
0
0
1
Bass filter set 1
0
0
0
0
0
0
1
0
Bass filter set 2
0
0
0
0
0
1
1
1
Bass filter set 3
0
0
0
0
0
1
0
0
Bass filter set 4
0
0
0
0
0
1
0
1
Bass filter set 5
0
0
0
0
0
1
1
0
Illegal
0
0
0
0
0
1
1
1
Illegal
6.22 Bass Filter Index Register (0xDB)
Index values above 0x24 are invalid.
Table 6−31. Bass Filter Index Register
I2C
SUBADDRESS
0xDB
68
TAS5028A
TOTAL BYTES
REGISTER NAME
DESCRIPTION OF CONTENTS
DEFAULT STATE
Bass filter index
(BFI)
4
Ch8_BFI (31:24), Ch65_BFI (23:16), Ch43_BFI
(15:8), Ch721_BFI (7:0)
0x12, 0x12, 0x12, 0x12,
SLES120 − September 2004
Serial Control Interface Register Definitions
Table 6−32. Bass Filter Index Table
TREBLE INDEX
VALUE
ADJUSTMENT
(DB)
TREBLE INDEX
VALUE
ADJUSTMENT
(DB)
0x00
18
0x13
–1
0x01
17
0x14
–2
0x02
16
0x15
–3
0x03
15
0x16
–4
0x04
14
0x17
–5
0x05
13
0x18
–6
0x06
12
0x19
–7
0x07
11
0x1A
–8
0x08
10
0x1B
–9
0x09
9
0x1C
–10
0x0A
8
0x1D
–11
0x0B
7
0x1E
–12
0x0C
6
0x1F
–13
0x0D
5
0x20
–14
0x0E
4
0x21
–15
0x0F
3
0x22
–16
0x10
2
0x23
–17
0x11
1
0x24
–18
0x12
0
6.23 Treble Filter Set Register (0xDC)
Bits D31–D27 are Don’t Care.
Table 6−33. Channel 8 Sub Woofer
D31
D30
D29
D28
D27
D26
D25
D24
0
0
0
0
0
0
0
0
No change
FUNCTION
0
0
0
0
0
0
0
1
Treble filter set 1
0
0
0
0
0
0
1
0
Treble filter set 2
0
0
0
0
0
1
1
1
Treble filter set 3
0
0
0
0
0
1
0
0
Treble filter set 4
0
0
0
0
0
1
0
1
Treble filter set 5
0
0
0
0
0
1
1
0
Illegal
0
0
0
0
0
1
1
1
Illegal
Table 6−34. Channel 6 and 5 (Right and Left Lineout in Six Channel Configuration or Right
and Left Surround in Eight Channel Configuration)
D23
D22
D21
D20
D19
D18
D17
D16
0
0
0
0
0
0
0
0
No change
0
0
0
0
0
0
0
1
Treble filter set 1
0
0
0
0
0
0
1
0
Treble filter set 2
0
0
0
0
0
1
1
1
Treble filter set 3
0
0
0
0
0
1
0
0
Treble filter set 4
0
0
0
0
0
1
0
1
Treble filter set 5
0
0
0
0
0
1
1
0
Illegal
0
0
0
0
0
1
1
1
Illegal
SLES120 − September 2004
FUNCTION
TAS5028A
69
Serial Control Interface Register Definitions
Table 6−35. Channel 4 and 3 (Right and Left Rear)
D15
D14
D13
D12
D11
D10
D9
D8
FUNCTION
0
0
0
0
0
0
0
0
No change
0
0
0
0
0
0
0
1
Treble filter set 1
0
0
0
0
0
0
1
0
Treble filter set 2
0
0
0
0
0
1
1
1
Treble filter set 3
0
0
0
0
0
1
0
0
Treble filter set 4
0
0
0
0
0
1
0
1
Treble filter set 5
0
0
0
0
0
1
1
0
Illegal
0
0
0
0
0
1
1
1
Illegal
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
No change
0
0
0
0
0
0
0
1
Treble filter set 1
0
0
0
0
0
0
1
0
Treble filter set 2
0
0
0
0
0
1
1
1
Treble filter set 3
0
0
0
0
0
1
0
0
Treble filter set 4
0
0
0
0
0
1
0
1
Treble filter set 5
0
0
0
0
0
1
1
0
Illegal
0
0
0
0
0
1
1
1
Illegal
Table 6−36. Channel 7, 2, 1 (Center, Right Front, and Left Front)
FUNCTION
6.24 Treble Filter Index (0xDD)
Index values above 0x24 are invalid.
Table 6−37. Treble Filter Index Register
I2C
SUBADDRESS
TOTAL BYTES
REGISTER
NAME
0xDD
Treble filter index (TFI)
4
DESCRIPTION OF CONTENTS
DEFAULT STATE
Ch8_TFI (31:24), Ch65_TFI (23:16), Ch43_TFI (15:8),
Ch721_TFI (7:0)
0x12,0x12,0x12,0x12
Table 6−38. Treble Filter Index
70
TAS5028A
TREBLE INDEX VALUE
ADJUSTMENT (DB)
TREBLE INDEX VALUE
ADJUSTMENT (DB)
0x00
18
0x13
–1
0x01
17
0x14
–2
0x02
16
0x15
–3
0x03
15
0x16
–4
0x04
14
0x17
–5
0x05
13
0x18
–6
0x\06
12
0x19
–7
0x07
11
0x1A
–8
0x08
10
0x1B
–9
0x09
9
0x1C
–10
0x0A
8
0x1D
–11
0x0B
7
0x1E
–12
0x0C
6
0x1F
–13
0x0D
5
0x20
–14
0x0E
4
0x21
–15
0x0F
3
0x22
–16
0x10
2
0x23
–17
0x11
1
0x24
–18
0x12
0
SLES120 − September 2004
Serial Control Interface Register Definitions
6.25 AM Mode Register (0xDE)
Bits D31–D21 are Don’t Care.
Table 6−39. AM Mode Register
D31
D30
D29
D28
D27
D26
D25
D24
FUNCTION
Unused bits
D23
D22
D21
D20
D19
D18
D17
D16
0
−
−
−
−
AM mode disabled
FUNCTION
1
−
−
−
−
AM mode enabled
−
0
0
−
−
Select sequence 1
−
0
1
−
−
Select sequence 2
−
1
0
−
−
Select sequence 3
−
1
1
−
−
Select sequence 4
−
−
−
0
−
IF frequency 455
−
−
−
1
−
IF frequency 262.5
−
−
−
−
0
Use BCD tuned frequency
−
−
−
−
1
Use binary tuned frequency
Table 6−40. AM Tuned Frequency Register in BCD Mode (Lower 2 Bytes of 0xDE)
D15
D14
D13
D12
D11
D10
D9
D8
0
0
0
B0
−
−
−
−
BCD frequency (1000s kHz)
FUNCTION
−
−
−
−
B3
B2
B1
B0
BCD frequency (100s kHz)
0
0
0
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
B3
B2
B1
B0
−
−
−
−
BCD frequency (10s kHz)
−
−
−
−
B3
B2
B1
B0
BCD frequency (1s kHz)
0
0
0
0
0
0
0
0
Default value
FUNCTION
Default value
Table 6−41. AM Tuned Frequency Register in Binary Mode (Lower 2 Bytes of 0xDE)
D15
D14
D13
D12
D11
D10
D9
D8
0
0
0
0
0
B10
B9
B8
0
0
0
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
B7
B6
B5
B4
B3
B2
B1
B0
0
0
0
0
0
0
0
0
FUNCTION
Binary frequency (upper 3 bits)
Default value
FUNCTION
Binary frequency (lower 8 bits)
Default value
6.26 General Control Register (0xE0)
Bits D31–D4 are zero. Bit D0 is Don’t Care.
Table 6−42. General Control Register
D31 – D4
D2
D1
0
D3
−
0
D0
/8 channel configuration
FUNCTION
0
−
1
6 channel configuration
6.27 Incremental Multiple Write Append Register (0xFE)
This is a special register used to append data to a previously opened register.
SLES120 − September 2004
TAS5028A
71
TAS5028A Example Application Schematic
7
TAS5028A Example Application Schematic
The following page contains an example application schematic for the TAS5028A.
SLES120 − September 2004
TAS5028A
73
5
4
3
2
1
V-HBRIDGE
+3.3V +5.0V
/SD2_TAS5121
Left + Right Line Out
/LINE_OUT_ENABLE
/OTW_TAS5121
/SD1_TAS5121
GVDD
V-HBRIDGE
/TEMP_WARNING
GVDD
+5.0V
PWM_P_R
PWM_P
+3.3V
PWM_M_R
Phono socket
J950
LINE OUTPUT
4
3
2
1
/OE
OUT_R
/VALID
OUT_1
1
OUT_2
2
J600
PWM_M_L
RIGHT BACK
SURROUND
SPEAKER
OUTPUT
CH6 TAS5121 H-Bridge Output Stage
PWM_P_L
Phono socket
J951
D
PWM_M
/VALID_CH5+CH6
4
3
2
1
V-HBRIDGE
OUT_L
/SD2_TAS5121
2 Channel Line Out (TLV272)
/OTW_TAS5121
GND
+5.0V
Left + Right Headphone
/SHUTDOWN_TAS5121
/TEMP_WARNING
GVDD
PWM_P
PWM_M
+5.0V
R20 +3.3V
22.0R
1
2
J900
OUT_R
PWM_HPM_R
OUT_GND
PWM_HPP_R
Mini-Jack (3.5mm)
OUT_L
C25
220nF
OUT_2
2
C26
10uF
2
4
3
2
1
HEADPHONE OUTPUT
1
J500
LEFT BACK
SURROUND
SPEAKER
OUTPUT
V-HBRIDGE
2
PWM_HPP_L
/VALID
OUT_1
CH5 TAS5121 H-Bridge Output Stage
1
1
PWM_HPM_L
/VALID_CH5+CH6
D
GVDD
V-HBRIDGE
/SD2_TAS5121
/OTW_TAS5121
GND
2 Channel Headphone Design (TPA112)
/SHUTDOWN_TAS5121
GVDD
V-HBRIDGE
/TEMP_WARNING
GVDD
PWM_P
/VALID
PWM_M
OUT_1
1
/VALID
OUT_2
2
SUBWOOFER
SPEAKER
OUTPUT
J800
CH8 TAS5121 H-Bridge Output Stage
V-HBRIDGE
/SD1_TAS5121
/OTW_TAS5121
C
MCLK
/RESET_TAS5028A
1
/OTW_TAS5121
47
PWM_P
PLL_FLTM
PWM_M_4
46
PWM_M
OUT_1
1
4
PLL_FLTP
PWM_P_3
45
/VALID
OUT_2
2
5
AVSS
PWM_M_3
44
6
AVSS
PWM_P_2
43
7
VRD_PLL
PWM_M_2
42
8
AVSS_PLL
PWM_P_1
41
/SD2_TAS5121
9
AVDD_PLL
PWM_M_1
40
/OTW_TAS5121
TAS5028A
10
VBGAP
VAILD
39
11
RESET
DVSS
38
BKND_ERR
37
DVDD
36
PDN
MUTE
DVSS
35
15
DVDD
DVSS
34
16
DVSS
VR_DIG
33
/VALID
J400
V-HBRIDGE
+3.3V
/VALID
/TEMP_WARNING
GVDD
PWM_M
OUT_1
1
/VALID
OUT_2
2
J300
1
/BKND_ERR_TAS5028A
LEFT
SURROUND
SPEAKER
OUTPUT
B
CH3 TAS5121 H-Bridge Output Stage
R18
1R
C23
10uF
1
/SD1_TAS5121
C24
100nF
2
C22
100nF
/OTW_TAS5121
/SHUTDOWN_TAS5121
GVDD
V-HBRIDGE
/TEMP_WARNING
GVDD
2
1
2
V-HBRIDGE
2
PSVC
GVDD
V-HBRIDGE
PWM_P
PWM_P
32
SDIN1
31
SDIN2
30
SDIN3
29
SDIN4
28
SCLK
27
LRCLK
26
SCL
25
SDA
24
RESERVED
23
RESERVED
22
RESERVED
21
XTL_IN
20
XTL_OUT
OSC_CAP
19
17
/SHUTDOWN_TAS5121
/VALID
/VALID
GND
1
1
PWM_M
OUT_1
1
/VALID
OUT_2
2
RIGHT
SPEAKER
OUTPUT
J200
C21
100nF
2
CH2 TAS5121 H-Bridge Output Stage
V-HBRIDGE
2
1
RIGHT
SURROUND
SPEAKER
OUTPUT
CH4 TAS5121 H-Bridge Output Stage
1
18
2
VR_DPLL
+3.3V
+5.0V +3.3V
GVDD
GVDD
3
14
2
GVDD
/TEMP_WARNING
48
U10
CENTER
SPEAKER
OUTPUT
V-HBRIDGE
VR_PWM
R14
1R
V-HBRIDGE
/SHUTDOWN_TAS5121
PWM_P_4
13
C20
100nF
2
PLL_FLT_RET
/PDN_TAS5028A
C19
10uF
OUT_2
VRA_PLL
/MUTE_TAS5028A
GND
/VALID
2
HP_SEL
1
R13
3.30R
1
1
1
B
OUT_1
V-HBRIDGE
/SD2_TAS5121
12
/HP_SEL
C
PWM_M
2
50
51
52
53
54
55
56
57
58
59
60
61
62
49
PWM_M_7
PWM_P_7
PWM_M_8
PWM_P_8
DVSS_PWM
DVDD_PWM
PWM_M_5
PWM_P_5
PWM_M_6
PWM_P_6
PWM_HPML
PWM_HPPL
PWM_HPMR
63
PWM_HPPR
MCLK
64
C18
1nF
2
2
2
C17
100nF
GVDD
J700
1
1
1
1
2
C16
10uF
RESERVED
1
2
2
2
2
C12
100nF
/TEMP_WARNING
CH7 TAS5121 H-Bridge Output Stage
C29
100nF
2
2
C14
100nF
R12
2R
1
C15
100nF
C13
10nF
12
12
R11
200R
C11
100nF
+3.3V
1
1
1
1
2
R10
200R
GVDD
V-HBRIDGE
PWM_P
/VALID
C10
10nF
/SHUTDOWN_TAS5121
GND
/SD1_TAS5121
GND
PSVC_TAS5028A
/OTW_TAS5121
/SHUTDOWN_TAS5121
GVDD
V-HBRIDGE
/TEMP_WARNING
GVDD
/RESET_TAS5028A
/RESET
SDIN3
/VALID
13.5MHz
/BKND_ERR_TAS5028A
2
2
/BKND_ERR_TAS5028A
/BKND_ERR
PSVC_TAS5028A
/SD1_TAS5121
PSVC_TAS5028A
/SD1
/SD2_TAS5121
CONF_SEL
/VALID
/VALID_CH5+CH6
/LINE_OUT_ENABLE
CONF_SEL
/SD2
C27
15pF
/SD1_TAS5121
1
A
PSVC_MCPU
/SD1
SDIN4
R21
1M
/LINE_OUT_ENABLE
/OTW_TAS5121
/OTW
OUT_1
1
/VALID
OUT_2
2
J100
SCL
SDA
A
/SD2_TAS5121
/SD2
TAS5028A Example Application Schematic
/OTW_TAS5121
(Circuit is Subject To Change Without Notice)
/OTW
PSU and Interface Logic
5
LEFT
SPEAKER
OUTPUT
LRCLK
C28
15pF
/VALID
/VALID_CH5+CH6
PWM_M
CH1 TAS5121 H-Bridge Output Stage
SCLK
1
2
/BKND_ERR
PSVC_MCPU
PWM_P
SDIN2
X10
/RESET_TAS5028A
1
+3.3V
+5.0V
GVDD
V-HBRIDGE
SDIN1
/RESET
4
3
2
1
PACKAGE OPTION ADDENDUM
www.ti.com
19-Jun-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TAS5028APAG
ACTIVE
TQFP
PAG
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
TAS5028APAGG4
ACTIVE
TQFP
PAG
64
160
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
TAS5028APAGR
ACTIVE
TQFP
PAG
64
1500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
TAS5028APAGRG4
ACTIVE
TQFP
PAG
64
1500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
TAS5028APAGR
Package Pins
PAG
64
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
SITE 60
330
24
13.0
13.0
1.5
16
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
24
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
TAS5028APAGR
PAG
64
SITE 60
367.0
367.0
45.0
Pack Materials-Page 2
MECHANICAL DATA
MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996
PAG (S-PQFP-G64)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
48
0,08 M
33
49
32
64
17
0,13 NOM
1
16
7,50 TYP
Gage Plane
10,20
SQ
9,80
12,20
SQ
11,80
0,25
0,05 MIN
1,05
0,95
0°– 7°
0,75
0,45
Seating Plane
0,08
1,20 MAX
4040282 / C 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265