TI VSP2267GSJ

Data Manual
December 2002
Mixed Signal Products
SBES001
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
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Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright  2002, Texas Instruments Incorporated
Contents
Contents
Section
1
2
Page
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.4
Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.5
Package/Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.6
Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2
Timing Generator (TG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3
Analog Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4
Correlated Double Sampler (CDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.5
Input Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.6
14-Bit A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.7
Digital Programmable Gain Amplifier (DPGA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.8
AFE Operating Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.9
Black-Level Clamp Loop and 10-Bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.10
Preblanking and Data Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.11
Power-Save Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.12
Additional Output Delay Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.13
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.14
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.15
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.16
TG Vertical-Rate Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.16.1
Field Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.16.2
Frame Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.16.3
2 Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.16.4
2 Monitor Mode Operation (2A, 2B CCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.17
Still Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.17.1
Operation Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.17.2
Operation Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.18
Strobe (STO Output) Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.18.1
Operation Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.18.2
Operation Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.19
Electronic Zoom Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.19.1
Operation Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.19.2
Operation Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.20
Readout Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.20.1
Operation Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.20.2
Operation Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.21
Power-Save-1 Function Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.21.1
Operation Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.21.2
Operation Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.22
Power-Save-2 Function Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.22.1
Operation Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.22.2
Operation Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
December 2002
SBES001
iii
Contents
2.23
3
4
iv
TG Pixel-Rate Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.23.1
High-Speed Pulse Adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.23.2
Default Timing Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.24
High-Speed Clock Timing Adjustable Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.24.1
ADCCK Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.24.2
H1, H2, R Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.24.3
SHP, SHD, PBLK, CLPOB, CLPDM Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Interface Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
Serial Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2
PGA Gain Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.3
AFE Standby Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.4
Operation Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.5
Function, ExtTRG, Strobe Duration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.6
Strobe Position Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.7
E-Shutter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.8
E-Shutter, VDHD Polarity Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.9
SUBSW Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.10
Strobe/V-Transfer E-Zoom/SUBSW2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.11
E-Zoom Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.12
H1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.13
H2 I/O Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.14
H2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.15
R I/O Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.16
R Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.17
SHP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.18
SHD Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.19
ADCCK Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.20
Test AFE I/O Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1
HD-MCLK Relation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2
VD-HD Relation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3
High-Speed Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4
Horizontal Timing Chart (for 2A CCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5
Vertical Timing Chart (for 2A CCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6
Vertical High-Speed Transfer Timing Chart (for 2A CCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7
Vertical Rate Timing (for 2A CCD) [field mode—odd field] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8
Vertical Rate Timing (for 2A CCD) [field mode—even field] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9
Vertical Rate Timing (for 2A CCD) [frame mode—odd field] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10
Vertical Rate Timing (for 2A CCD) [frame mode—even field] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.11
Vertical Rate Timing (for 2A CCD) [ 2 mode—odd field] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.12
Vertical Rate Timing (for 2A CCD) [ 2 mode—even field] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.13
Vertical Rate Timing (for 2A CCD) [ 2 monitor mode] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.14
Vertical Rate Timing (for 2A CCD) [frame mode—still function—odd field] . . . . . . . . . . . . . . . . . . . . .
4.15
Vertical Rate Timing (for 2A CCD) [frame mode—still function—even field] . . . . . . . . . . . . . . . . . . . .
4.16
Vertical Rate Timing (for 2A CCD) [frame mode—still function turnoff] . . . . . . . . . . . . . . . . . . . . . . . . .
4.17
Vertical Rate Timing (for 2A CCD) [field mode—e-zoom function—odd field] . . . . . . . . . . . . . . . . . . .
4.18
Vertical Rate Timing (for 2A CCD) [field mode—e-zoom function—even field] . . . . . . . . . . . . . . . . . .
4.19
Vertical Rate Timing (for 2A CCD) [ 2 monitor mode—e-zoom function] . . . . . . . . . . . . . . . . . . . . . .
SBES001
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24
24
25
25
26
27
29
30
31
31
32
32
33
33
34
34
34
35
35
35
36
36
36
36
37
37
38
38
39
39
40
41
42
43
47
48
49
50
51
52
53
54
55
56
57
58
59
60
December 2002
List of Illustrations
5
6
4.20
Horizontal Timing Chart (for 2B CCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.21
Vertical Timing Chart (for 2B CCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.22
Vertical High-Speed Transfer Timing Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.23
Vertical Rate Timing (for 2B CCD) [field mode—odd field] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.24
Vertical Rate Timing (for 2B CCD) [field mode—even field] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.25
Vertical Rate Timing (for 2B CCD) [frame mode—odd field] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.26
Vertical Rate Timing (for 2B CCD) [frame mode—even field] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.27
Vertical Rate Timing (for 2B CCD) [ 2 mode—odd field] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.28
Vertical Rate Timing (for 2B CCD) [ 2 mode—even field] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.29
Vertical Rate Timing (for 2B CCD) [ 2 monitor mode] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.30
Vertical Rate Timing (for 2B CCD) [frame mode—still function—odd field] . . . . . . . . . . . . . . . . . . . . .
4.31
Vertical Rate Timing (for 2B CCD) [frame mode—still function—even field] . . . . . . . . . . . . . . . . . . . .
4.32
Vertical Rate Timing (for 2B CCD) [frame mode—still function turnoff] . . . . . . . . . . . . . . . . . . . . . . . . .
4.33
Vertical Rate Timing (for 2B CCD) [field mode—e-zoom function—odd field] . . . . . . . . . . . . . . . . . . .
4.34
Vertical Rate Timing (for 2B CCD) [field mode—e-zoom function—even field] . . . . . . . . . . . . . . . . . .
4.35
Vertical Rate Timing (for 2B CCD) [ 2 monitor mode—e-zoom function] . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1
Absolute Maximum Ratings Over Operating Free-Air Temperature Range . . . . . . . . . . . . . . . . . . . . .
5.2
Electrical Characteristics, All Specifications at TA = 25°C, All Power Supply Voltages = 3 V,
and Conversion Rate = 20 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
61
63
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
81
81
85
List of Illustrations
Figure
2–1
2–2
2–3
2–4
2–5
2–6
2–7
Title
Page
VSP2267 High-Speed Clock Circuit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
VSP2267 Line and Pixel Counter Circuit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VSP2267 Vertical-Rate Timing Circuit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
VSP2267 AFE Simplified Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CDS and Input Clamp Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PGA Gain Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Digital PGA and Black-Level Clamp Loop Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
List of Tables
Table
Title
Page
2–1 Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
December 2002
SBES001
v
Introduction
1
Introduction
1.1
Description
The VSP2267 is a complete mixed-signal IC for CCD signal processing with a CCD timing generator and A/D
converter. The system synchronizes the master clock, HD, and VD. The VSP2267 supports all signal terminals
that the CCD and the vertical driver require, plus externally triggered mechanical shutter and strobe functions.
The R driver and H driver synchronize the A/D converter clock phase to realize ideal performance. The CCD
channel has correlated double sampling (CDS) to extract image information from the CCD output signal. The
digital control gain curve is linear in dB, ranging from –6 dB to 42 dB. A black-level clamping circuit ensures
an accurate black reference level and quick black-level recovery after a gain change. Input signal clamping
with a CDS offset adjustment function is available.
1.2
Features
The VSP2267 supports the following features:
•
CCD Signal Processing:
–
Correlated Double Sampling (CDS)
–
Programmable Black-Level Clamping
•
Timing Generator With R and H Drivers
•
Programmable Phase Control:
–
Fine Step: 0.6 ns
–
Wide Step: 8 ns
•
Programmable-Gain Amplifier (PGA): –6 dB to 42 dB Gain Range
•
12-Bit Digital Data Output:
–
Up to 25-MHz Conversion Rate
–
No Missing Codes
•
Signal-to-Noise Ratio: 79 dB
•
Portable Operation:
•
–
Low Voltage: 3.0 V to 3.6 V
–
Low Power: 138 mW at 3.0 V and 20 MHz
151 mW at 3.0 V and 25 MHz
–
Standby Plus Power-Save Mode: 34 mW
–
MCLK-Off Mode: 6 mW
Recommended CCD: MN39470, MN39471, MN39472, MN39473, MN39474 (Panasonic)
SBES001—December 2002
VSP2267
1
Introduction
1.3
Block Diagram
SOUT SDATA SLOAD SCLK
HD
VD
SYSRST
TRG
VDD
TP3
TP2
ADCCK
VDD
TP0/1
V-PULSE
Serial Interface
TG
H-Driver
H-PULSE
R-Driver
R
MCLK
CLPDM
CLPOB
ADCCK
PBLK
STO
SHP
SHD
CLKO
SUBSW
Optical Black (OB) Level
Clamping
Input
Clamp
Pre-Blanking
Timing Control
CCDIN
Correlated
Double
Sampling
(CDS)
Programmable
Gain Amp.
(PGA)
–6 dB to 42 dB
CCD
Output
Signal
VSP2267
Analog-to-Didital
Converter
Output
Latch
12-Bit
Digital
Output
B[11:0]
Reference Voltage Generator
COB
2
and
BYPP2
BYP
BYPM
REFN
CM
REFP
VSS
VSS
SBES001—December 2002
Introduction
1.4
1.5
Terminal Assignments
1
2
3
4
5
6
7
8
9
10
A
BYP2
BYP
(NC)
CCDIN
VDD
VSS
VSS
VSS
TRG
SUBSW2
B
BYPM
COB
(NC)
VDD
VSS
VDD
VDD
VDD
VSS
H1
C
CM
VDD
VSS
(NC)
VSS
MCLK
CLKO
SYSRST
VDD
VDD
D
REFP
REFN
(NC)
(NC)
(NC)
(NC)
(NC)
H2
VSS
VSS
E
VDD
VSS
VSS
(NC)
(NC)
R
SUB
VDD
F
TP3
TP2
VSS
(NC)
(NC)
(NC)
SUBSW
STO
G
VDD
(NC)
SLOAD
(NC)
(NC)
(NC)
(NC)
V2
V3
V4
H
SDATA
SCLK
B9
B6
B3
TP1
HD
(NC)
CH4
V1
J
SOUT
ADCCK
B8
B5
B1
B0
VSS
VDD
CH1
CH3
K
B11
B10
B7
B4
B2
TP0
VDD
VD
VSS
CH2
Package/Ordering Information
PRODUCT
PACKAGE
PACKAGE
CODE
OPERATION
TEMPERATURE RANGE
PACKAGE
MARKING
VSP2267GSJ
BGA 96
GSJ
–25°C
25°C to 85°C
VSP2267
SBES001—December 2002
ORDERING
NUMBER
TRANSPORT MEDIA
VSP2267GSJ
168-piece tray
VSP2267GSJR
Tape and reel
VSP2267
3
Introduction
1.6
Terminal Functions
TERMINAL
TYPE†
DESCRIPTIONS
NAME
NO.
ADCCK
J2
DO
Clock for digital output buffer
B0
J6
DO
A/D converter output, bit 0
B1
J5
DO
A/D converter output, bit 1
B2
K5
DO
A/D converter output, bit 2
B3
H5
DO
A/D converter output, bit 3
B4
K4
DO
A/D converter output, bit 4
B5
J4
DO
A/D converter output, bit 5
B6
H4
DO
A/D converter output, bit 6
B7
K3
DO
A/D converter output, bit 7
B8
J3
DO
A/D converter output, bit 8
B9
H3
DO
A/D converter output, bit 9
B10
K2
DO
A/D converter output, bit 10
B11
K1
DO
A/D converter output, bit 11
BYP
A2
AO
BYP2
A1
AO
Internal reference C (bypass to ground)¶
Internal reference P (bypass to ground)§
BYPM
B1
AO
Internal reference N (bypass to ground)‡
CCDIN
A4
AI
CCD signal input
CH1
J9
DO
Readout pulse 1
CH2
K10
DO
Readout pulse 2
CH3
J10
DO
Readout pulse 3
CH4
H9
DO
Readout pulse 4
CLKO
C7
DO
FCK output
CM
C1
AO
A/D converter common-mode voltage (bypass to ground)¶
COB
B2
AO
Optical black clamp loop reference (bypass to ground)‡
H1
B10
DO
CCD horizontal driver 1
H2
D8
DO
CCD horizontal driver 2
HD
H7
DI
HD input
Master clock input
MCLK
C6
DI
A3, B3, C4, D3, D4,
D5, D6, D7, E4, E7,
F4, F7, F8, G2, G4,
G5, G6, G7, H8
—
R
E8
DO
CCD reset driver
REFN
D2
AO
REFP
D1
AO
A/D converter negative voltage (bypass to ground)¶
A/D converter positive voltage (bypass to ground)¶
SCLK
H2
DI
Clock for serial-data shift
SDATA
H1
DI
Serial-data input
SLOAD
G3
DI
Serial-data latch signal
SOUT
J1
DO
Serial-data monitor out
F10
DO
Strobe
NC
STO
† Designators in TYPE column: P–Power supply and ground, DI–Digital input, DO–Digital output, AI–Analog input, AO–Analog output
‡ Should be connected to ground with a bypass capacitor. A value of 0.1 µF to 0.22 µF is recommended; however, it depends on the application
environment. See Black Level Clamp Loop and 10-Bit DAC (Section 2.9) for details.
§ Should be connected to ground with a bypass capacitor. A value of 400 pF to 1000 pF is recommended; however, it depends on the application
environment. See Voltage Reference (Section 2.13) for details.
¶ Should be connected to ground with a bypass capacitor (0.1 µF). See Voltage Reference (Section 2.13) for details.
4
VSP2267
SBES001—December 2002
Introduction
TERMINAL
TYPE†
DESCRIPTIONS
NAME
NO.
SUB
E9
DO
CCD sub pulse
SUBSW
F9
DO
CCD sub bias control
SUBSW2
A10
DO
CCD sub bias control switch 2
SYSRST
C8
DI
System reset
TP0
K6
DI/O
H1
TP1
H6
DI/O
H2, R
TP2
F2
DI/O
SHP, CPOB, PBLK
TP3
F1
DI/O
SHD, CLPD
TRG
A9
DI
External trigger
V1
H10
DO
V1 pulse
V2
G8
DO
V2 pulse
V3
G9
DO
V3 pulse
V4
G10
DO
V4 pulse
VD
K8
DI
VD input
VDD
A5, B4, C2, E1
P
Analog power supply
VDD
B6, B7, B8, C9, C10,
E10, G1, J8, K7
P
Digital power supply
VSS
B5, C3, C5, E2, E3
P
Analog ground
VSS
A6, A7, A8, B9, D9,
D10, F3, J7, K9
P
Digital ground
† Designators in TYPE column: P–Power supply and ground, DI–Digital input, DO–Digital output, AI–Analog input, AO–Analog output
SBES001—December 2002
VSP2267
5
Theory of Operation
2
Theory of Operation
2.1
Introduction
The VSP2267 is a high-resolution mixed-signal IC that contains key features associated with the processing
of the CCD signal in a digital still camera (DSC). The VSP2267 integrates the analog front end (AFE) and CCD
timing generator (TG) with the H and R drivers.
The AFE block includes a correlated double sampler (CDS), 14-bit analog-to-digital converter (ADC), digital
gain amplifier, black-level clamp loop, input clamp, CDS timing generator, and voltage reference. The built-in
TG generates not only horizontal (H-rate) timing, but also vertical (V-rate) timing for several specified CCD
models. Optimized timing is generated by selecting the CCD model and operating mode through the serial
interface.
2.2
Timing Generator (TG)
The TG generates both H-rate timing and V-rate timing.
Figure 2–1 shows a high-speed timing block of the TG. This part generates six high-speed pulses for H-rate
timing such as R, H1/H2, SHP/SHD, and ADCCK. These high-speed pulses are generated from the master
clock, which has a speed of twice the pixel rate. The serial interface sets the amount of phase adjustment for
these high-speed pulses in 16 steps (8 steps for R) with a minimum 0.6-ns pitch (4 steps of 0.6 ns and 4 steps
of 1.2 ns for R). The power mode controls the output driver enable/disable. An on-chip decoder calculates H
clear according to the CCD model and operating mode. H1, H2, and R can drive the CCD directly. The ADCCK,
SHP, SHD, R, H1, and H2 pulses can select either the internal generation mode or the external supply mode.
SBES001—December 2002
VSP2267
7
Theory of Operation
MCLK
1/2
24 MHz
to
50 MHz
12 MHz
to
25 MHz
Phase Adjust
CLKO
I/O
Phase Adjust
64 Steps
AFE Block
ADCCK
I/O
Phase Adjust
16 Steps
SHP
I/O
Phase Adjust
16 Steps
SHD
I/O
Phase Adjust
8 Steps
R
F/F
Power Save
I/O
Phase Adjust
16 Steps
F/F
H Clear
Power Save
H1
I/O
Phase Adjust
16 Steps
F/F
H2
Figure 2–1. VSP2267 High-Speed Clock Circuit Block Diagram
8
VSP2267
SBES001—December 2002
Theory of Operation
An on-chip V-rate timing generator creates all the signals that are required for specific CCD image sensors.
The TG contains the line and pixel counters used to generate V-rate timing. Figure 2–2 is the block diagram
of the line and pixel counter circuit. A maximum of 2047 lines and 4095 pixels per line are supported in time
scale.
F/F
SYSRST
VD
RST
Line Counter
(MAX 2047 lines)
HD
Decoder
11 Bit
H[10:0]
clk
F/F
RST
Pixel Counter
(MAX 4095 Pixels)
MCLK
13 Bit
P[12:0]
clk
Figure 2–2. VSP2267 Line and Pixel Counter Circuit Block Diagram
Figure 2–3 shows a V-rate timing generator block diagram. By one H (horizontal line) before CCD readout,
serial data transfer must be completed by the user, and data must be loaded in the registers containing CCD
model, operation mode, integration time, and electronic zoom area information. Just before CCD readout,
information in the registers is supplied automatically to the decoder, which generates the V-rate signal using
line counter and pixel counter data. Not only the signals used for the CCD, but also the strobe light control
signal is supported. CPOB, CLPD, and PBLK can select either the internal generation mode or the external
supply mode.
SBES001—December 2002
VSP2267
9
Theory of Operation
H[10:0]
P[12:0]
Serial Data Register
F/F
11 Bits
13 Bits
Decoder
V1
Q
J
Variables
11 Bits
13 Bits
Decoder
V2
K
V3
Variables
V4
F/F
11 Bits
13 Bits
Decoder
Q
J
CH2
Variables
11 Bits
13 Bits
Decoder
CH1
K
CH3
Variables
CH4
F/F
11 Bits
13 Bits
Decoder
J
Variables
11 Bits
Decoder
Q
CLPDM
CLPOB
K
13 Bits
PBLK
Variables
SWSUB
SUB
Figure 2–3. VSP2267 Vertical-Rate Timing Circuit Block Diagram
10
VSP2267
SBES001—December 2002
Theory of Operation
2.3
Analog Front End
Figure 2–4 shows a simplified AFE block diagram of the VSP2267. The AFE circuit includes the correlated
double sampler (CDS), a 14-bit analog-to-digital converter (ADC), digital gain amplifier, black-level clamp
loop, input clamp, CDS timing generator, and voltage reference. An off-chip emitter-follower buffer or
preamplifier is needed between the CCD output and the VSP2267 CCDIN input.
CPOB
ADCCK
CLPOB SYSRST
Off Chip On Chip
10-Bit
DAC
CCD
Input
CDS
Decoder
14-Bit
ADC
12-Bit
Output
Output
Register
CLPD
Input Clamp
ADCCK
PBLK
SYSRST
Figure 2–4. VSP2267 AFE Simplified Block Diagram
2.4
Correlated Double Sampler (CDS)
The output signal of a CCD image sensor is sampled twice during one pixel period: once during the reference
interval and again during the data interval. Subtracting these two samples extracts the video information of
the pixel and removes noise which is low frequency—the kTC and CCD reset noise. Figure 2–5 is a block
diagram of the CDS.
The CDS is driven through an off-chip coupling capacitor CIN. (A 0.1-µF capacitor is recommended for CIN).
AC coupling is highly recommended because the dc level of the CCD output signal is usually too high (several
volts) for the CDS to work properly. The appropriate common-mode voltage for the CDS is around 0.5 V–1.5 V.
The reference-level sampling is performed while SHP is active, and the voltage level is held on sampling
capacitor C1 at the trailing edge of SHP. The data-level sampling is performed while SHD is active, and the
voltage level is held on sampling capacitor C2 at the trailing edge of SHD. Then the subtraction of the two levels
is performed by the switched-capacitor amplifier. The off-chip emitter follower or equivalent buffer must be able
to drive more than 10 pF because the 10-pF sampling capacitor is seen at the input terminal. (Usually
additional stray capacitance of a few pF is present.) The analog input signal range of the VSP2267 is about
1 Vp-p.
SBES001—December 2002
VSP2267
11
Theory of Operation
Off Chip On Chip
SHP
C1
CCD
Input
CIN
+
OPA
_
C2
CLPD
SHD
SHP
CM
Figure 2–5. CDS and Input Clamp Block Diagram
2.5
Input Clamp
The buffered CCD output is capacitively coupled to the VSP2267. The input clamp restores the dc component
of the input signal which was lost with the ac coupling and establishes the desired dc bias point for the CDS.
Figure 2–5 also shows the block diagram of the input clamp. The input level is clamped to the internal
reference voltage CM (1.5 V) during the dummy pixel interval. More specifically, the clamping function
becomes active when both CLPD and SHP are active.
2.6
14-Bit A/D Converter
The ADC uses a fully differential pipelined architecture of 1.5 bits per stage, which is well-suited for low-power,
low-voltage, and high-speed applications. The ADC provides 14-bit resolution for the entire scale. The
1.5-bit-per-stage structure of the ADC is advantageous in realizing better linearity for a smaller signal level.
Improved linearity occurs because large linearity errors tend to occur at specific points in the full scale and
the linearity improves for a signal level below any such specific point.
2.7
Digital Programmable Gain Amplifier (DPGA)
Figure 2–6 shows the characteristics of the DPGA gain. The DPGA provides a gain range of –6 dB to 42 dB,
which is linear in dB. The gain, controlled by a digital code with 10-bit resolution, can be set through the serial
interface; see the Serial Interface Timing Specification (Section 3) for details. The default value of the gain
control code is 128 (PGA gain = 0 dB).
After powering on, the gain control value is undetermined. For this reason, it must be set to an appropriate
value by using the serial interface or reset to the default value by strobing the SYSRST terminal.
12
VSP2267
SBES001—December 2002
Theory of Operation
INPUT CODE FOR GAIN CONTROL
vs
GAIN
50
40
Gain – dB
30
20
10
0
–10
0
100 200 300 400 500 600 700 800 900 1000
Input Code for Gain Control (0 to 1023)
Figure 2–6. PGA Gain Characteristics
PBLK
ADCCK PWSV
14-Bit ADC
CCDIN
CDS
Digital
PGA
Output
Register
10-Bit
Current DAC
Decoder
ADC
To Output
Buffer
BYPP
CLPOB
COB
Off Chip
On Chip
ADCCK PWSV
CPOB
Figure 2–7. Digital PGA and Black-Level Clamp Loop Block Diagram
2.8
AFE Operating Timing
The CDS and the ADC are operated by SHP, SHD, and their derivative timing clocks generated by the internal
on-chip timing generator. The DPGA output register and decoder are operated by ADCCK. The digital output
data is synchronized with ADCCK. The timing relationship between the CCD signal, SHP, SHD, ADCCK, and
the output data is shown in the VSP2267 timing specification. CPOB activates the black-level clamp loop
during the OB pixel interval and CLPD activates input clamping during the dummy pixel interval.
SBES001—December 2002
VSP2267
13
Theory of Operation
2.9
Black-Level Clamp Loop and 10-Bit DAC
To extract the video information correctly, the CCD signal must be referenced to a well-established black level.
The VSP2267 has an auto-zero loop (calibration loop) to establish the black level using the CCD optical black
(OB) pixels. Figure 2–7 shows the block diagram of this loop. The input signal level from the OB pixels is
identified as the real black level, and the loop is closed during this period (actually during the period while
CPOB = ACTIVE). While the auto-zero loop is closed, the difference between the ADC output code is
evaluated and applied to the decoder, which then controls the 10-bit current DAC. The current DAC can charge
or discharge the external capacitor at COB, depending on the sign of the code difference. The loop adjusts
the voltage at COB, which sets the offset of the CDS to make the code difference zero. Thus the ADC output
code converges to black level during CPOB = ACTIVE and maintains the black level derived from the OB pixels
after the loop has converged. CPOB performs the OB clamping of both channels simultaneously.
To determine the loop time constant, an off-chip capacitor is required and should be connected to the COB
terminal. The time constant T is calculated using the following equation:
T+
C
(16384
I MIN)
(1)
where C is the capacitor value connected to COB, IMIN is the minimum current (0.15 µA) of the control DAC
in the OB level clamp loop, and 0.15 µA is equivalent to 1 LSB of the DAC output current. When C is 0.1 µF,
then the time constant T is 40.7 µs for the ADC output code from 0 LSB to 1543 LSB (The convergence curve
becomes exponential).
For the output code above 1543 LSB, the current DAC injects constant (maximum) current into the capacitor
and the convergence curve becomes linear. The slew rate SR is calculated using the following equation.
SR +
I MAX
C
(2)
where C is the capacitor value connected to COB. IMAX is the maximum current (153 µA) of the control DAC
in the OB level clamp loop, and 153 µA is equivalent to 1023 LSB of the DAC output current.
Generally, OB level clamping at high speed causes clamping noise. However, the noise can be reduced by
making C large. On the other hand, a large C requires a much longer time to restore from the power-save mode
or right after the power goes ON. Therefore, 0.1 µF to 0.22 µF is considered a reasonable value for C. If the
application environment requires a value outside this range, making careful adjustments by the trial-and-error
method is recommended.
The OB clamp level (the pedestal level) is programmable through the serial interface; see the Serial Interface
Timing Specification (Section 3) for details. Also see the Serial Interface Timing Specification section for the
relationship between input code and the OB clamp level.
The black-level clamp loop not only eliminates the CCD black-level offset, but also eliminates the offsets of
the VSP2267 CDS and ADC themselves.
2.10 Preblanking and Data Latency
The VSP2267 has a preblanking function. When PBLK = LOW, the digital outputs all become zero at the ninth
rising edge of ADCCK, counting from the time when PBLK becomes LOW, to accommodate the clock latency
of the VSP2267.
Data latency of this device is seven clock cycles. The digital output data come out on the rising edge of ADCCK
with a delay of seven clock cycles.
Some CCDs have a large transient output signal during blanking intervals. If the input voltage is higher than
the supply rail or lower than the ground rail by 0.3 V, then protection diodes are turned on, limiting the input
voltage. Such a high-swing signal can cause device damage to the VSP2267 and should be avoided.
14
VSP2267
SBES001—December 2002
Theory of Operation
2.11 Power-Save Mode
For the purpose of power savings, the VSP2267 can be put into the standby plus power-save mode by serial
interface command. In this mode, all the function blocks are disabled, the A/D outputs all go to zero and the
TG output goes to high or low status by configuration of the serial interface command. The current
consumption drops to 34 mA. Because all the bypass capacitors discharge during this mode, a substantial
time (usually of the order of 200–300 ms) is required to restore from the standby plus power-save mode.
2.12 Additional Output Delay Control
The VSP2267 can control the delay time of output data by setting registers through the serial interface. In some
cases, the transition of output data affects analog performance. Generally, this is avoided by adjusting the
timing of ADCCK. In case the ADCCK timing cannot be adjusted, the additional output delay control is effective
for reducing the influence of transient noise. Refer to the Serial Interface Timing Specification (Section 3) for
details.
2.13 Voltage Reference
All the reference voltages and bias currents used on the device are created from internal band-gap circuitry.
The CDS and the ADC mainly use three reference voltages, REFP (1.75 V), REFN (1.25 V) and CM (1.5 V).
REFP and REFN are buffered on-chip. CM is derived as the midvoltage of the resistor chain connecting REFP
and REFN internally. The ADC full-scale range is determined by twice the voltage difference between REFP
and REFN.
REFP, REFN, and CM should be heavily decoupled with appropriate capacitors.
Table 2–1. Function Table
OPERATION MODE
2A CCD†
FUNCTION
2B CCD‡
FIELD
FRAME
×2 SPEED
×2 MONITOR
FIELD
FRAME
×2 SPEED
×2 MONITOR
LONG INTEGRATION (CHDEL)
√
√
√
√
√
√
√
√
POWER SAVE (PWSV)
√
√
√
√
√
√
√
√
STROBE (STRB)
√
√
√
√
√
√
√
√
STILL (STIL)
√
√
√
√
√
√
√
√
E-ZOOM (EZOOM)
√
√
√
√
√
√
√
√
E-SHUTTER
√
√
√
√
√
√
√
√
SUB STOP 1/4-STEP
√
√
√
† Recommended CCD MN39470, MN39472, MN39473 (Panasonic)
‡ Recommended CCD MN39471, MN39474 (Panasonic)
√
√
√
√
√
2.14 Operating Modes
•
Field mode enables the summation of vertically neighboring pixels.
•
Frame mode enables each pixel output.
•
×2 speed mode enables output interval lines.
•
×2 monitor mode enables output of two by eight lines or two by ten lines for CCDs 2A or 2B, respectively.
The field mode, frame mode, and ×2 speed mode operate with interlace between even/odd frames.
SBES001—December 2002
VSP2267
15
Theory of Operation
2.15 Functions
•
The long integration function stops CCD readout (CH1, CH2, CH3, CH4 pulse) at the end of one frame,
as defined by the serial data instruction.
•
The power save function stops all clocks and preserves high or low levels by the serial data instruction.
•
The strobe function enables external strobe light operation to synchronize electronic shutter timing by the
serial data instruction.
•
The e-zoom function enables electronic zoom, by which successive lines are selected according to the
serial data instruction.
•
The e-shutter function enables electronic shutter operation by the serial data instruction.
•
The SUB-stop 1/4-step function enables selection by the serial data instruction of the SUB pulse position
from among four points on a line.
2.16 TG Vertical-Rate Operation
2.16.1
Field Mode Operation
2.16.1.1 Operation Outline
Horizontal output of the CCD is generated by summing pixels that are vertically adjacent to each other, and
successively repeating the summation for each CCD pixel column. Either the odd field or the even field is
selectable.
2.16.1.2 Operation Sequence
1. Set serial data address 000100 bits 6–5 = 00.
2. Define odd/even by the relation of VD and HD or by serial address 000100 bits 8–7.
2A CCD, 2B CCD
PIX
Odd
Field
PIX
Even
Field
PIX
PIX
PIX
PIX
PIX
PIX
Signal Transfer Direction
16
VSP2267
SBES001—December 2002
Theory of Operation
2.16.2
Frame Mode Operation
2.16.2.1 Operation Outline
Horizontal output of the CCD is generated by reading out individual pixels vertically at 2-pixel intervals, and
successively repeating the readout for each pixel column. Either the odd field or the even field is selectable.
2.16.2.2 Operation Sequence
1. Set serial data address 000100 bits 6–5 = 01.
2. Define odd/even by the relation of VD and HD or by serial address 000100 bits 8–7.
2A CCD, 2B CCD
PIX
Even
Field
Odd
Field
PIX
PIX
PIX
PIX
PIX
PIX
PIX
Signal Transfer Direction
SBES001—December 2002
VSP2267
17
Theory of Operation
2.16.3
2 Mode Operation
2.16.3.1 Operation Outline
Horizontal output of the CCD is generated by summing pixels vertically in groups of two at 4-pixel intervals,
and successively repeating the readout for each pixel column. Either the odd field or the even field is
selectable.
2.16.3.2 Operation Sequence
1. Set serial data address 000100 bits 6–5 = 10.
2. Define odd/even by the relation of VD and HD or by serial address 000100 bits 8–7.
2A CCD, 2B CCD
PIX
PIX
Even
Field
Odd
Field
PIX
PIX
PIX
PIX
PIX
PIX
Signal Transfer Direction
18
VSP2267
SBES001—December 2002
Theory of Operation
2.16.4
2 Monitor Mode Operation (2A, 2B CCD)
2.16.4.1 Operation Outline
(2A CCD) Horizontal output of the CCD is generated by summing pixels vertically in groups of two, and
successively repeating the readout for each pixel column.The third and eighth of every eight consecutive
vertical pixels are selected for summing.
(2B CCD) Horizontal output of the CCD is generated by summing pixels vertically in groups of two, and
successively repeating the readout for each pixel column. The fifth and tenth of every ten consecutive vertical
pixels are selected for summing.
2.16.4.2 Operation Sequence
1. Set serial data address 000100 bits 6–5 = 11.
2. Operation proceeds without regard for odd-/even-field considerations.
2B CCD
PIX
2A CCD
PIX
PIX
PIX
PIX
PIX
PIX
PIX
PIX
PIX
PIX
PIX
PIX
PIX
PIX
PIX
PIX
PIX
Signal Transfer Direction
SBES001—December 2002
Signal Transfer Direction
VSP2267
19
Theory of Operation
2.17 Still Function
2.17.1
Operation Outline
Readout timing is selected by the TRG input. Smear dump operation, which is synchronized to the mechanical
shutter, is available.
SUB output is controlled by using both the serial data instruction and the external TRG signal.
The SUBSW level follows the still mode condition. SUBSW can be used for the SUB bias control circuit when
using a mechanical shutter. It is recommended to set the toggling position of SUBSW after the mechanical
shutter has closed.
2.17.2
Operation Sequence
1. Set the serial data address 000101.
Input bit 2 = H, and set to the still mode.
Select the trigger signal EDGSL bit 3 = L for VD or bit 3 = H for TRG.
Select the SUB output STLSUB bit 4 = L for TRG input or bit 4 = H for serial data input.
(In this case, the SUB output is defined by the TRG input. To use the serial data instruction, the integration
time is defined by ES 000111, which can be done after Step 2, following.)
2. Input a pulse to SLOAD and send the serial data.
3. Set the serial data address 001010. Input the STVV data in bits 0–5 for SUBSW rise time definition. Data
is stored in the register 1 H before a readout operation. Upon going to still mode, during the horizontal scan
time preceding a readout operation, a SUB output is made for every H and charge is drained.
4. Input a TRG falling edge signal if necessary. The TRG falling edge is latched by the internal HD_flg. The
SUB output goes high after the next horizontal blank, and charge integration starts. See Note 1.
5. Input a TRG rising edge or VD signal. SUBSW goes high at the position defined by the serial data. The
SUBSW toggling position is determined by counting the number of HD pulses after the rising edge of TRG
or VD. A vertical high-speed pulse, which is more than the the line number of one field, is applied.
6. Input serial data to set bit 3 = L at address 000101 and release the the trigger-select function during the
vertical high-speed pulse operation that was initiated in Step 5.
7. Input a VD pulse after one field of CCD output signal has completed, keeping SUBSW high.
8. Input serial data for address 000101 and bit 2 = L to exit from the still mode.
9. Input a VD pulse after one field of CCD output signal has completed. SUBSW goes low at the next HD
rising edge.
NOTES:
1. In this mode, the mechanical shutter was open while the TRG input was low.
2. Do not use the electronic shutter in the still mode, when SUBSW is high.
3. For the VD-to-VD interval, more than 90 counts of the HD-to-HD interval are required.
20
VSP2267
SBES001—December 2002
Theory of Operation
2.18 Strobe (STO Output) Function
2.18.1
Operation Outline
STO output is initiated by the serial data instruction, which includes the STO signal position and duration.
2.18.2
Operation Sequence
1. Set data bit 6 = H at address 001010 for the STO (strobe) rising point instruction. See Note 1.
2. Input a pulse to SLOAD and transfer the serial data.
3. Set data bits 0–9 at address 000110 for the STO (strobe) rising point instruction. In this case, use the binary
code for data ST[9:0] starting from the HD rising edge (10 T), which is 2 H after the readout pulse. The
data range of ST is 0 ≤ n1 ≤ A–2, where A is the number of HD between VD–VD. See Note 3.
4. Input a pulse to SLOAD and transfer the serial data.
5. Set data bits 5–9 at address 000101 for the SWT duration instruction. In this case, use the binary code
for data SWT[9:5], starting from the STO rising edge (10 T). See Note 3.
6. Input a pulse to SLOAD and transfer the serial data. Data is stored into the resistor at 1 H before the
readout operation. STO goes high at the point determined by the serial data instruction. STO goes low
when the duration of the STO high level extends beyond SWT in the interval between two HD pulses. See
Note 2.
NOTE:
1. The strobe function can be used in the normal mode as well as in the still mode. Then strobe
operation is useful for red-eye prevention.
2. Rise time and fall time of STO are 10 T.
3. Adjust the STO position and width so that STO goes low 2 HD before the readout operation.
SBES001—December 2002
VSP2267
21
Theory of Operation
2.19 Electronic Zoom Function
2.19.1
Operation Outline
•
Vertical CCD transfer enables vertical image extraction.
•
Horizontal image extraction and the zooming process require signal processing outside this device.
•
This mode enables high-speed image output of a limited area.
2.19.2
Operation Sequence
1. Set serial data address 000101. At the same time, input data bit 1 = H, and set the electronic zoom mode.
Set the number of transfer stage using binary address 001011 and code in data bits 0–9. See Note 4 for
the data range. See Notes 1–5.
2. Input a pulse to SLOAD and transfer the serial data. According to serial data stage instruction, a
high-speed vertical transfer of V1 to V4 output is made. After the high-speed transfer, a standard vertical
transfer of V1 to V4 is made for each H. At the next VD, high speed vertical transfer of V1 to V4 is output
for approximately one field. See Note 2.
NOTE:
1. This mode can not be combined with still mode.
2. In the electronic zoom function, the user instruction pertains only to a vertical high-speed transfer
following a readout operation. The number of vertical high-speed transfers preceding a readout
operation is fixed for each CCD model.
3. Signal performance is not assured during 1 field after a change to this mode and release from this
mode.
4. Transfer stage setting is as follows:
[2A CCD]
0 ≤ n ≤ 640 stages (0.5 stage pitch is available by odd/even select)
Note that n must be divided by 2.
[2B CCD]
0 ≤ n ≤ 610 stages (0.5 stage pitch is available by odd/even select)
Note that n must be divided by 5.
5. The interval between VD to VD must be more than 90 HD.
22
VSP2267
SBES001—December 2002
Theory of Operation
2.20 Readout Function
2.20.1
Operation Outline
This mode can control a pair of pixels, which are mixed in the vertical transfer CCD. Control is not
accomplished by the HD–VD phase, but by the serial data instruction.
2.20.2
Operation Sequence
1. Set serial data address 000100. At the same time, input data bit 7 = H and set the serial data control mode.
In this case, readout timing is defined by bit-8 data. When bit 8 = L, the odd field is read out; when bit 8 = H,
the even field is read out.
2. Input a pulse to SLOAD and send the serial data.
NOTE:
If bit 7 = L, odd/even readout recognition is made by the HD–VD phase difference.
2.21 Power-Save-1 Function Explanation
2.21.1
Operation Outline
Power save by stopping
2.21.2
H1, R, V3, V4, CH1, CH2, CH3, CH4, SUB, SHP, SHD, CPOB, CLPDM,
PBLK = Fixed high
H1, ADCCK, V1, V2 = Fixed low
Operation Sequence
1. Set serial data 000100. Set data bit PWSV1 = H to enter the power-save mode.
2. Input a pulse for SLOAD and transfer the serial data.
NOTES:
1. After release from this mode, signal performance is not assured during 1 V.
2. Do not use both power-save modes 1 and 2 at the same time.
2.22 Power-Save-2 Function Explanation
2.22.1
Operation Outline
Power save by stopping H1, H2, R, SHP, SHD, ADCCK, V1–V4, CH1–CH4, SUB, CPOB, CLPDM, PBLK.
2.22.2
Operation Sequence
(same as power-save-1 function)
NOTES:
(same as power-save-1 function)
SBES001—December 2002
VSP2267
23
Theory of Operation
2.23 TG Pixel-Rate Operation
2.23.1
High-Speed Pulse Adjustment
For a high-speed pulse, the CCD signal sampling time is adjustable (see serial data addresses from 001100
to 010110). The default value is set as follows.
(25-MHz Operation)
0 ns
8.2~14.8 ns
R
CCD
SHP (Default)
SHP (Adjustment)
1.2~10.2 ns
15.2~24.2 ns
SHD (Default)
SHD (Adjustment)
24.2~33.2 ns 35.2~44.2 ns
2.23.2
24
Default Timing Value
•
R: Standard reset duration is 25% of cycle.
•
SHP: Standard rise point is 50% of cycle, based on a 3-ns CCD signal delay. Actual delay depends on
the system.
•
SHD: Standard rise point is 100% of cycle, based on a 3-ns CCD signal delay. Actual delay depends on
the system.
•
H1: Standard duration is 50% of cycle.
•
H1 and H2 are complementary. The crossover point of the H1 rising edge and H2 falling edge should be
higher than VDD/2.
•
H2: Standard duration is 50% of cycle.
•
ADCCK: Standard rise and fall points are 25% and 75% of cycle respectively, based on a 3-ns CCD signal
delay.
VSP2267
SBES001—December 2002
Theory of Operation
2.24 High-Speed Clock Timing Adjustable Range
The timing reference for the values in the following table is the R pulse rising edge.
25-MHz OPERATION
TERMINAL
R
SHP
SHD
H1
H2
ADCCK
(phase 00)
2.24.1
EDGE
MIN
STD
20-MHz OPERATION
MAX
MIN
STD
12-MHz OPERATION
MAX
MIN
STD
MAX
NOTE
Rising
0
0
0
0
0
0
0
0
0
0%
Falling
8.2
10
14.8
10.7
12.5
17.3
19.0
20.8
25.6
25%
Rising
15.2
20
24.2
20.2
25
29.2
36.9
41.7
45.9
50%
Falling
1.2
6
10.2
6.2
11
15.2
22.9
27.7
31.9
14 ns
Rising
35.2
40
44.2
45.2
50
54.2
78.5
83.3
87.5
100%
Falling
24.2
29
33.2
34.2
39
43.2
67.5
72.3
76.5
11 ns
Rising
–4.2
0
4.8
–4.2
0
4.8
–4.2
0
4.8
0%
Falling
15.8
20
24.8
20.8
25
29.8
37.5
41.7
46.5
50%
50%
Rising
15.8
20
24.8
20.8
25
29.8
37.5
41.7
46.5
Falling
–4.2
0
4.8
–4.2
0
4.8
–4.2
0
4.8
0%
Rising
3.6
6
12.6
7.1
9.5
16.1
15.1
17.5
24.1
25%
Falling
23.6
26
32.6
32.1
34.5
41.1
56.7
59.1
65.7
75%
ADCCK Clock
Signal monitoring is available using the ADCCK I/O terminal. External input is available via the serial data
instruction.
0
TG Circuit
AFE Circuit
1
ADCCK_EXT
ADCCK_MON
ADCCK
(PAD)
SBES001—December 2002
VSP2267
25
Theory of Operation
2.24.2
H1, H2, R Clocks
Signal monitoring and signal input (H1, H2, R) are available using the corresponding I/O terminal.
H_DR_ENABLE
(H1 Signal)
H1
(PAD)
TG Circuit
0
H1_EXT
H1_MON
1
TP0
(PAD)
(R Signal)
R
(PAD)
TG Circuit
0
R_EXT
H_DR_ENABLE
1
(H2 Signal)
H2
(PAD)
TG Circuit
0
H2_EXT
PASS_SW
RMONTP1_SW
1
MUXTP1_SW = 0
MUXTP1_SW = 1
TP1
(PAD)
MUXTP1_SW = 0
MUXTP1_SW = 1
26
VSP2267
SBES001—December 2002
Theory of Operation
2.24.3
SHP, SHD, PBLK, CLPOB, CLPDM Clocks
Signal monitoring and signal input for SHP, SHD, PBLK, CLPOB, and CLPDM are available using the
corresponding I/O terminal.
0
(SHP Signal)
AFE Circuit
TG Circuit
SHP_EXT
1
TG Circuit
(CLPOB Signal) 0
AFE Circuit
CLPOB_EXT
TG Circuit
(PBLK Signal)
1
0
AFE Circuit
PBLK_EXT
1
SHP_MON
TP023A = 1, TP23B = 0
TP023A = 0, TP23B = 1
TP023A = 1, TP23B = 1
TP2
(PAD)
TP023A = 1, TP23B = 0
TP023A = 0, TP23B = 1
TP023A = 1, TP23B = 1
TG Circuit
0
(SHD Signal)
AFE Circuit
SHD_EXT
TG Circuit
(CLPDM Signal)
1
0
AFE Circuit
SHD_MON
CLPDM_EXT
1
TP23C = 0
TP23C = 1
TP3
(PAD)
TP23C = 0
TP23C = 1
SBES001—December 2002
VSP2267
27
Serial Interface Timing Specification
3
Serial Interface Timing Specification
tXH
tXS
SLOAD
tCKH
tCKL
tCKP
SCLK
tDH
tDS
MSB
SDATA
LSB
2 Bytes
PARAMETER
MIN
TYP
MAX
UNIT
tCKP
tCKH
Clock period
100
ns
Clock high-pulse duration
40
ns
tCKL
tDS
Clock low-pulse duration
40
ns
Data setup time
30
ns
tDH
tXS
Data hold time
30
ns
SLOAD to SCLK setup time
30
ns
tXH
SCLK to SLOAD hold time
30
ns
A data shift operation should occur at the rising edge of SCLK while SLOAD is LOW. At the rising edge of
SLOAD, 2 bytes of input data are loaded into the parallel latch in the VSP2267.
When the input serial data is longer than 2 bytes (16 bits), the last 2 bytes become effective and the previous
bits are lost.
SD15
MSB
SD14
SD13
SD12
SD11
SD10
LSB
SD9
MSB
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
LSB
A5
A4
A3
A2
A1
A0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Register address (default)
Register data (default value)
Serial data for the AFE is supplied to the operation at every ADCCK edge (address 000000 to 000011).
Serial data input for the TG should be made when the CCD operation is changed.
Serial data for the TG is applied to the operation 1 H before every readout. (CCD) starting point (address
000100 to 011000).
CCD
READOUT
Horizontal Transfer
CCD
READOUT
Horizontal Transfer
HD
SERIAL DATA is
Applied to Operation
SERIAL DATA is
Applied to Operation
SOUT
Serial data output, starting from address 000000, occurs during CCD readout.
SBES001—December 2002
VSP2267
29
Serial Interface Timing Specification
3.1
Serial Data Format
Register
Name
A5
A4
A3
A2
A1
A0
D9
MSB
D8
D7
D6
D5
D4
D3
D2
D1
D0
LSB
Configuration
0
0
0
0
0
0
0
O3
O2
O1
O0
P2
P1
P0
J1
J0
PGA gain
0
0
0
0
0
1
G9
G8
G7
G6
G5
G4
G3
G2
G1
G0
Reserved
0
0
0
0
1
0
—
—
—
—
—
—
—
—
—
—
AFE
standby
0
0
0
0
1
1
0
0
0
0
0
C0
0
0
0
0
Operation
mode
0
0
0
1
0
0
0
CHMOD2
CHMOD1
DRV2
DRV1
CCD
MSB
CCD
CCD
LSB
PWSV2
PWSV1
Function,
ExtTRG
strobe
duration
0
0
0
1
0
1
SWT4
MSB
SWT3
SWT2
SWT1
SWT0
LSB
STLSUB
EDGSL
STILL
ZOOM
CHDEL
Strobe
position
0
0
0
1
1
0
ST9
MSB
ST8
ST7
ST6
ST5
ST4
ST3
ST2
ST1
ST0
LSB
E-shutter
0
0
0
1
1
1
ES9
MSB
ES8
ES7
ES6
ES5
ES4
ES3
ES2
ES1
ES0
LSB
E-shutter
VDHD
Polarity
0
0
1
0
0
0
0
0
POLHV
0
0
0
1
0
DD1
MSB
DD2
LSB
SUBSW
0
0
1
0
0
1
SUBSW9
MSB
SUBSW8
SUBSW7
SUBSW6
SUBSW5
SUBSW4
SUBSW3
SUBSW2
SUBSW1
SUBSW0
LSB
Strobe/
V-transfer
E-zoom/
SUBSW2
0
0
1
0
1
0
SUB2
MSB
SUB2
LSB
0
STROBE
STVV5
MSB
STVV4
STVV3
STVV2
STVV1
STVV0
LSB
E-zoom
0
0
1
0
1
1
EZ9
MSB
EZ8
EZ7
EZ6
EZ5
EZ4
EZ3
EZ2
EZ1
EZ0
LSB
H1
0
0
1
1
0
0
H1
ext
H1
mon
0
0
0
0
H1fa3
MSB
H1fa2
H1fa1
H1fa0
LSB
Reserved
0
0
1
1
0
1
—
—
—
—
—
—
—
—
—
—
H2 I/O
0
0
1
1
1
0
H2
ext
0
0
0
0
0
0
0
0
0
H2
0
0
1
1
1
1
0
0
0
0
0
0
H2ri3
MSB
H2ri2
H2ri1
H2ri0
LSB
R I/O
0
1
0
0
0
0
R
ext
R
mon
0
0
0
0
0
0
0
0
R
0
1
0
0
0
1
0
0
0
0
0
Rfa4
MSB
Rfa3
Rfa2
Rfa1
Rfa0
LSB
SHP
0
1
0
0
1
0
SHP
ext
SHP
mon
0
0
0
0
SHPfa3
MSB
SHPfa2
SHPfa1
SHPfa0
LSB
Reserved
0
1
0
0
1
1
—
—
—
—
—
—
—
—
—
—
SHD
0
1
0
1
0
0
SHD
ext
SHD
mon
0
0
0
0
SHDfa3
MSB
SHDfa2
SHDfa1
SHPfa0
LSB
Reserved
0
1
0
1
0
1
—
—
—
—
—
—
—
—
—
—
ADCCK
0
1
0
1
1
0
ADCCK
ext
ADCCK
mon
0
0
ADCCKri5
ADCCKri4
ADCCKri3
ADCCKri2
ADCCKri1
ADCCKri0
Reserved
0
1
0
1
1
1
—
—
—
—
—
—
—
—
—
—
TEST AFE
0
1
1
0
0
0
TP23
MSB
TP23
TP23
MSB
TP01
CLPDM
ext
0
PBLK
ext
0
CLPOB
ext
0
MSB
LSB
Do not input values into reserved registers.
A 0 input is required for data bits marked with a dash (—), except in reserved registers.
30
VSP2267
SBES001—December 2002
Serial Interface Timing Specification
3.1.1 Configuration Register
SD15
SD14
SD13
SD12
SD11
SD10
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
0
0
0
0
0
0
0
O3
O2
O1
O0
P2
P1
P0
J1
J0
0
1
0
0
0
0
0
0
0
0
default
BIT
NAME
DEFAULT VALUE
SD8–SD5
O[3:0]
1000
DESCRIPTION
SD4
P2
0
SHP/SHD clock polarity
0 = Polarity of SHP/SHD is active low.
1 = Polarity of SHP/SHD is active high.
SD3
P1
0
CLPOB clock polarity
0 = Polarity of CLPOB is active low
1 = Polarity of CLPOB is active high
SD2
P0
0
CLPDM clock polarity
0 = Polarity of CLPDM is active low
1 = Polarity of CLPDM is active high
SD1–SD0
J[1:0]
00
Additional output delay
00 = Additional delay is 0 ns
01 = Additional delay is 5 ns (typical)
10 = Additional delay is 10 ns (typical)
11 = Additional delay is 13 ns (typical)
Programmable OB clamp level
0000 = 2 LSB
0001 = 18 LSB
0010 = 34 LSB
0011 = 50 LSB
0100 = 66 LSB
0101 = 82 LSB
0110 = 98 LSB
0111 = 114 LSB
1000 = 130 LSB (default)
1001 = 146 LSB
1010 = 162 LSB
1011 = 178 LSB
1100 = 194 LSB
1101 = 210 LSB
1110 = 226 LSB
1111 = 242 LSB
3.1.2 PGA Gain Register
SD15
SD14
SD13
SD12
SD11
SD10
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
0
0
0
0
0
1
G9
G8
G7
G6
G5
G4
F3
G2
G1
G0
0
0
1
0
0
0
0
0
0
0
default
BIT
NAME
DEFAULT VALUE
SD9–SD0
G[9:0]
0010000000
SBES001—December 2002
DESCRIPTION
PGA gain characteristics
0000000000 = –6 dB
0000110101 = –3 dB
0010000000 = 0 dB
0010110101 = 3 dB
0011111111 = 6 dB
0101111111 = 12 dB
1000100000 = 20 dB
1101001000 = 34 dB
1111111111 = 42 dB
VSP2267
31
Serial Interface Timing Specification
3.1.3 AFE Standby Register
SD15
SD14
SD13
SD12
SD11
SD10
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
0
0
0
0
1
1
0
0
0
0
0
C0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
default
BIT
NAME
DEFAULT VALUE
SD4
C0
0
DESCRIPTION
AFE operation mode (normal/standby)
0 = AFE normal operation mode
1 = AFE standby mode
3.1.4 Operation Mode Register
SD15 SD14 SD13 SD12
0
0
0
1
SD11
SD10
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
0
0
0
CHMOD2
CHMOD1
DRV2
DRV1
CCD
MSB
CCD
CCD
LSB
PWSV2
PWSV1
0
0
0
0
1
0
0
1
0
0
default
BIT
NAME
DEFAULT
VALUE
SD8–SD7
CHMOD[2:1]
00
Operation mode:
X0 = HD-VD phase (default)
01 = Odd field
11 = Even field
SD6–SD5
DRV [2:1]
01
Operation mode:
00 = Field mode
01 = Frame mode (default)
10 = ×2 mode
11 = ×2 monitor
SD4–SD2
CCD[2:0]
001
CCD model:
001 = 2A CCD (default)
010 = 2B CCD
SD1
PWSV2
0
Output pin state:
0 = normal operation
1 = (H1, R, V3, V4, CH1, CH2, CH3, CH4, SUB , SHP, SHD, CPOB, CLPDM, PBLK = Fixed
low)
(H2, ADCLK, V1, V2 = Fixed low)
SD0
PWSV1†
0
Output pin state:
0 = normal operation‡
(H2, ADCLK, V1, V2 = Fixed low)‡
1 = (H1, R, V3, V4, CH1, CH2, CH3, CH4, SUB, SHP, SHD, CPOB, CLPDM, PBLK = Fixed
high)
DESCRIPTION
† When PWSV1 = PWSV2=1, automatically set as PWSV1 = 1, PWSV2 = 0.
‡ When PWSV1 = 1, the H1 and H2 pins become high impedance. PWSV1 = 1 during H-blanking makes H1 = high, H2 = low.
32
VSP2267
SBES001—December 2002
Serial Interface Timing Specification
3.1.5 Function, ExtTRG, Strobe Duration Register
SD15 SD14 SD13 SD12
0
0
0
1
SD11
SD10
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
0
1
SWT4
MSB
SWT3
SWT2
SWT1
SWT0
LSB
STLSUB
EDGSL
STILL
ZOOM
CHDEL
0
0
0
0
0
1
0
0
0
0
default
BIT
NAME
DEFAULT
VALUE
SD9–SD5
SWT[4:0]
00000
SD4
STLSUB
1
SUB pulse stop point:
0 = Define SUB (SUB pin) pulse stop point by external trigger.
1 = Define SUB (SUB pin) pulse stop point by serial data.
SD3
EDGSL
0
Trigger select for the still function:
0 = Use VD (VD pin) rising edge as count start for SUBSW high.
1 = Use external trigger (TRG pin) rising edge as count start for SUBSW high.
SD2
STILL†
0
Function:
0 = normal operation
1 = Still function (see Still Function, Section 2.17)
SD1
ZOOM†
0
Function:
0 = normal operation
1 = Electronic zoom function (see E-Zoom Register, Section 3.1.11)
SD0
CHDEL
0
Output pin:
0 = normal operation
1 = (CH1, CH2, CH3, CH4 pins = Fixed high) for longer integration
DESCRIPTION
Strobe output width definition:
Strobe (STO pin) signal duration instruction.
Effective only when the strobe function is ON (address 001010 bit 6 = high)
The strobe pulse duration is defined by 1H step.
Use binary code from 0 ≤ n2 ≤ 31
When n2 = 0, the STO output remains low.
† Electronic zoom and still modes are alternatives.
3.1.6 Strobe Position Register
SD15 SD14 SD13 SD12
0
0
0
1
SD11
SD10
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
1
0
ST9
MSB
ST8
ST7
ST6
ST5
ST4
ST3
ST2
ST1
ST0
LSB
0
0
0
0
0
0
0
0
0
0
default
BIT
NAME
DEFAULT
VALUE
SD9–SD0
ST[9:0]
0000000000
SBES001—December 2002
DESCRIPTION
Strobe (STO pin) signal start position instruction.
Effective only when the strobe function is ON (address 001010 bit 6 = high)
Strobe pulse start position is defined by 1H step.
Use binary code from 0 ≤ n1 ≤ A–2. Note that A is an HD number between two
successive VD pulses.
Count n1 = 0 at 2 H after readout pulse (CH1 to CH4).
VSP2267
33
Serial Interface Timing Specification
3.1.7 E-Shutter Register
SD15 SD14 SD13 SD12
0
0
0
SD11
SD10
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
1
1
ES9
MSB
ES8
ES7
ES6
ES5
ES4
ES3
ES2
ES1
ES0
LSB
0
1
1
1
0
1
1
0
0
1
1
default
BIT
NAME
DEFAULT VALUE
SD9–SD0
ES[9:0]
0111011001
DESCRIPTION
SUB (SUB pin) pulse number instruction
SUB pulse number is definied using binary code from 0 ≤ n ≤ A–3.
Note that A is an HD number between two successive VD pulses.
When n = 0, SUB pulse is zero.
SUB pulse starts 2H after readout (CH1 to CH4).
Integration time is defined by (A – n – 1) H.
Initial: 16.6 ms integration at 36-MHz (MCLK) frame mode
3.1.8 E-Shutter, VDHD Polarity Register
SD15 SD14 SD13 SD12
0
0
1
SD11
SD10
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
0
0
0
0
POLHV
0
0
0
1
0
DD1
MSB
DD2
LSB
0
0
0
0
0
0
1
0
0
0
0
default
BIT
NAME
DEFAULT VALUE
SD7
POLHV
0
VD, HD polarity selection:
0 = positive
1 = negative
SD5
0
(Input required)
0
SD4
0
(Input required)
0
SD3
1
(Input required)
1
00
Electronic shutter SUB pulse position:
00 = Position A (during horizontal blanking)
01 = Position B (during horizontal transfer)
10 = Position C (during horizontal transfer)
11 = Position D (during horizontal transfer)
SD1–SD0
DD[1:0]
DESCRIPTION
3.1.9 SUBSW Register
SD15
SD14
SD13
SD12
SD11
SD10
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
0
0
1
0
0
1
SUBSW9
MSB
SUBSW8
SUBSW7
SUBSW6
SUBSW5
SUBSW4
SUBSW3
SUBSW2
SUBSW1
SUBSW0
LSB
0
0
0
0
0
0
0
0
0
0
default
BIT
NAME
DEFAULT VALUE
DESCRIPTION
SD9–SD0
SUBSW[9:0]
0000000000
SUBSW signal output position when in the still function.
SUBSW signal output position is defined by 1H step using a binary code from 0 ≤ n0 ≤ A–2.
Note that A is an HD number between two successive VD pulses.
When n0 = 0, SUBSW must be kept 0.
Count as 1 the first HD after VD or a trigger pulse.
34
VSP2267
SBES001—December 2002
Serial Interface Timing Specification
3.1.10
Strobe/V-Transfer E-Zoom/SUBSW2 Register
SD15
SD14
SD13
SD12
SD11
SD10
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
0
0
1
0
1
0
SUB2
MSB
SUB2
LSB
0
STROBE
STVV5
MSB
STVV4
STVV3
STVV2
STVV1
STVV0
LSB
0
0
0
0
0
0
0
0
0
0
default
BIT
NAME
DEFAULT VALUE
SD9–SD8
SUB2[1:0]
00
SUBSW2 function:
0X = SUBSW2 low during
10 = SUBSW2 low
11 = SUBSW2 high
SD6
STROBE
0
SD5–SD0
STVV[5:0]
000000
3.1.11
DESCRIPTION
2,
2 monitor modes
Strobe function flag:
0 = Strobe off
1 = Strobe function (Position defined by ST[9:0]. Duration defined by STW[4:0])
Vertical high speed transfer position control when in the still function.
Position is controlled by 1H step counting binary code from 0 ≤ n3 ≤ 63.
When n0 = 0, Vertical high speed transfer synchronizes to the SUBSW rising edge.
E-Zoom Register
SD15
SD14
SD13
SD12
SD11
SD10
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
0
0
1
0
1
1
EZ9
MSB
EZ8
EZ7
EZ6
EZ5
EZ4
EZ3
EZ2
EZ1
EZ0
LSB
0
0
0
0
0
0
0
0
0
0
default
BIT
NAME
DEFAULT VALUE
DESCRIPTION
SD9–SD0
EZ[1:0]
0000000000
Electronic zoom vertical transfer line definition, when in the electronic zoom function.
Vertical transfer line number, after readout, is defined using a binary code from 0 to H-Max
(H-Max varies depending on the CCD model). When EZ = 0, no vertical transfer is made after
readout.
3.1.12
H1 Register
SD15
SD14
SD13
SD12
SD11
SD10
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
0
0
1
1
0
0
H1
ext
H1
mon
0
0
0
0
H1fa3
MSB
H1fa2
H1fa1
H1fa0
LSB
0
1
0
0
0
0
0
1
1
1
default
BIT
NAME
DEFAULT VALUE
SD9
H1 ext
0
External selection:
0 = Without use of external H1 clock
1 = Use external H1 clock
SD8
H1 mon
1
Monitor selection:
0 = H1 clock monitor
1 = H1 clock without monitor
SD3–SD0
H1fa[3:0]
0111
SBES001—December 2002
DESCRIPTION
H1 delay definition using 4 bits:
1111 = H1 delay, maximum
:
0111 = H1 delay, typical
:
0000 = H1 delay, minimum
VSP2267
35
Serial Interface Timing Specification
3.1.13
H2 I/O Register
SD15
SD14
SD13
SD12
SD11
SD10
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
0
0
1
1
1
0
H2
ext
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
default
BIT
NAME
DEFAULT VALUE
SD9
H2 ext
0
3.1.14
DESCRIPTION
External selection:
0 = Without use of external H2 clock
1 = Use external H2 clock
H2 Register
SD15
SD14
SD13
SD12
SD11
SD10
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
0
0
1
1
1
1
0
0
0
0
0
0
H2ri3
MSB
H2ri2
H2ri1
H2ri0
LSB
0
0
0
0
0
0
0
1
1
1
default
BIT
NAME
DEFAULT VALUE
SD3–SD0
H2ri[3:0]
0111
3.1.15
DESCRIPTION
H2 delay edge definition using 4 bits
1111 = H2 delay, maximum
:
0111 = H2 delay, typical
:
0000 = H2 delay, minimum
R I/O Register
SD15
SD14
SD13
SD12
SD11
SD10
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
0
1
0
0
0
0
R
ext
R
mon
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
default
BIT
NAME
DEFAULT VALUE
SD9
R ext
0
External selection:
0 = Without use of external R clock
1 = Use external R clock
SD8
R mon
1
Monitor selection:
0 = R clock without monitor
1 = R clock monitor
3.1.16
DESCRIPTION
R Register
SD15
SD14
SD13
SD12
SD11
SD10
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
0
1
0
0
0
1
0
0
0
0
0
Rfa4
MSB
Rfa3
Rfa2
Rfa1
Rfa0
LSB
0
0
0
0
0
0
0
0
0
0
default
BIT
NAME
DEFAULT VALUE
SD4–SD0
Rfa[4:0]
00000
36
VSP2267
DESCRIPTION
R falling edge definition using 5 bits
R duration MAX = 111XX
110XX
101XX
100XX
R duration TYP = 0XX00
0XX01
0XX10
R duration MIN = 0XX11
SBES001—December 2002
Serial Interface Timing Specification
3.1.17
SHP Register
SD15
SD14
SD13
SD12
SD11
SD10
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
0
1
0
0
1
0
SHP
ext
SHP
mon
0
0
0
0
SHPfa3
MSB
SHPfa2
SHPfa1
SHPfa0
LSB
0
1
0
0
0
0
1
0
0
0
default
BIT
NAME
DEFAULT VALUE
SD9
SHP ext
0
External selection:
0 = Without use of external SHP clock
1 = Use external SHP clock
SD8
SHP mon
1
Monitor selection:
0 = SHP clock monitor
1 = SHP clock without monitor
SD3–SD0
SHPfa[3:0]
1000
3.1.18
DESCRIPTION
SHP delay edge definition using 4 bits
1111 = SHP delay maximum
:
1000 = SHP delay typical
:
0000 = SHP delay minimum
SHD Register
SD15
SD14
SD13
SD12
SD11
SD10
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
0
1
0
1
0
0
SHD
ext
SHD
mon
0
0
0
0
SHDfa3
MSB
SHDfa2
SHDfa1
SHDfa0
LSB
0
1
0
0
0
0
1
0
0
0
default
BIT
NAME
DEFAULT VALUE
SD9
SHD ext
0
External selection:
0 = Without use of external SHD clock
1 = Use external SHD clock
SD8
SHD mon
1
Monitor selection:
0 = SHD clock monitor
1 = SHD clock without monitor
SD3–SD0
SHDfa[3:0]
1000
SBES001—December 2002
DESCRIPTION
SHD delay edge definition using 4 bits
1111 = SHD delay maximum
:
1000 = SHD delay typical
:
0000 = SHD delay minimum
VSP2267
37
Serial Interface Timing Specification
3.1.19
ADCCK Register
SD15
SD14
SD13
SD12
SD1
1
SD1
0
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
0
1
0
1
1
0
ADCCK
ext
ADCCK
mon
0
0
ADCCK90
MSB
ADCCK90
LSB
ADCCKri3
MSB
ADCCKri2
ADCCKri1
ADCCKri0
LSB
0
1
0
0
0
1
0
1
0
0
default
BIT
NAME
DEFAULT VALUE
SD9
ADCCK ext
0
External selection:
0 = Without use of external ADCCK-clock
1 = Use external ADCCK-clock
SD8
ADCCK mon
1
Monitor selection:
0 = ADCCK-clock monitor
1 = ADCCK-clock without monitor
SD5–SD4
ADCCK90[1:0]
01
ADCLK 90° adjustment:
00 = ADCCK phase is lagging 0° with respect to CLKO
01 = ADCCK phase is lagging 90° with respect to CLKO
10 = ADCCK phase is lagging 180° with respect to CLKO
11 = ADCCK phase is lagging 270° with respect to CLKO
SD3–SD0
ADCCKri[3:0]
0100
3.1.20
DESCRIPTION
ADCLK delay edge definition using 4 bits
Test AFE I/O Register
SD15
SD14
SD13
SD12
SD11
SD10
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
0
1
1
0
0
0
TP23
MSB
TP23
TP23
LSB
TP01
CLPDM
ext
0
PBLK
ext
0
CLPOB
ext
0
0
0
0
0
0
0
0
0
0
0
default
38
BIT
NAME
DEFAULT VALUE
SD9–SD7
TP23[2:0]
000
SD6
TP01
0
TP01 source selection:
0 = H1 and R
1 = H1 and H2
SD5
CLPDM
ext
0
CLPDM input source selection:
0 = Use internally generated CLPDM clock, with or without monitor
1 = Use external CLPDM clock
SD3
PBLK
ext
0
PBLK input source selection:
0 = Use internally generated PBLK clock, with or without monitor
1 = Use external PBLK clock
SD1
CLPOB
ext
0
CLPOB input source selection:
0 = Use internally generated CLPOB clock, with or without monitor
1 = Use external CLPOB clock
VSP2267
DESCRIPTION
TP23 input source selection:
000 = open
001 = SHP and SHD
110 = CLPOB and CLPDM
111 = PBLK and CLPDM
SBES001—December 2002
Timing Specification
4
Timing Specification
4.1
HD-MCLK Relation
HD
tMCK
MCLK
tCH3
tCH2
tPCLK(latency)
CLKO
tCH1
P[12:0]
N-1 (Pix)
H[10:0]
N (Pix)
0 (Pix)
N (H)
PARAMETER
0 (H)
MIN
TYP
MAX
UNIT
tCH1
tCH2
CLKO rising edge to HD rising edge
–9
9
ns
MCLK rising edge to HD rising edge
4
12
ns
tCH3
tMCK
HD rising edge to MCLK falling edge
0
Master clock period
tPCLK(latency) Clock start latency
† Unit T is the master clock cycle duration.
SBES001—December 2002
ns
20
41.7
10
VSP2267
ns
T†
39
Timing Specification
4.2
VD-HD Relation
(1) Odd Field
VD
HD
tH
tVHA
H[10:0]
0 (H)
1 (H)
tHCLK(latency)
(2) Even Field
VD
HD
tHVB
tVHB
tH
N (H)
H[10:0]
PARAMETER
0 (H)
MIN
tVHA
tHVB
HD rising edge to VD rising edge (odd field)
>0
HD rising edge to VD rising edge (even field)
> 30
tVHB
tH
VD rising edge to HD rising edge (even field)
> 30
HD duration
tHCLK(latency) H clock start latency
† Unit T is the master clock cycle duration.
TYP
MAX
<200
UNIT
ns
µs
µs
1
10
10
11
µs
T†
VD
tVD
PARAMETER
tVD
40
VD duration
VSP2267
MIN
> 1 HD
TYP
MAX
UNIT
HD–HD
SBES001—December 2002
Timing Specification
4.3
High-Speed Timing Specifications
MCLK
tCKP
(See Note 1)
CLKO
H1
tH12
(See Note 2)
H2
R
tRCCD
(See Note 3)
CCD
tPF
tPR
tWP
SHP
tDR
tPD
tDP
SHD
tINHIBIT
tWD
tADC
tCKP
ADCCK
tHOLD
B[11:0]
N-8
tOD
N-7
PARAMETER
tADC
N-6
N-5
MIN
TYP
MAX
UNIT
83.3
ns
tCKP(1)
tH12(2)
Clock period
Horizontal transfer pulse delay
3
tRCCD(3)
Reset-to-CCD reset delay (varies with CCD model and wiring)
3
tPF
tPR
CCD CDS rising edge to SHP falling edge delay
SHP rising edge to CCD CDS falling edge delay
5
ns
tDR
tWP
SHD rising edge to CCD signal out rising edge delay
5
ns
SHP pulse duration
14
ns
tWD
tPD
SHD pulse duration
11
ns
SHP trailing edge to SHD leading edge
8
ns
tDP
tINHIBIT
SHD trailing edge to SHP leading edge
12
tADC
tHOLD
ADCCK high/low pulse duration
tOD
DL
Output delay (no load)
40
Data latency, normal operation mode
ns
5
Inhibited clock period
Output hold time
ns
ns
ns
20
20
ns
41.7
2
ns
ns
27
9 (fixed)
ns
ADCCK cycles
NOTES: 1. Clock period varies by CCD model.
2. Horizontal transfer pulse delay varies by CCD model.
3. Reset-to-CDS delay depends on CCD signal response delay. Default setting is 3 ns.
SBES001—December 2002
VSP2267
41
Timing Specification
4.4
Horizontal Timing Chart (for 2A CCD)
0t = 3808t
HD†(+10t)
483t 509t 513t
102t
OB:50
Pix
CCD_OUT{
Dummy 1 Pix
PD: 1648 Pix
102t
Dummy: 13 Pix
483t
102t
483t
(Effective Pixels)
OB:2 Pix
H1
H2
20t 80t
CPOB
102t
512t
PBLK
486t 504t
CLPD
1) Still Mode / Frame Mode: Enlarged Section
200t
128t
ΦV1
176t
248t
ΦV2
104t
ΦV3
224t
152t
ΦV4
272t
140t
ΦSUB
356t
2) ×2 Mode: Enlarged Section
128t 200t 320t 392t
ΦV1
176t 248t 368t 440t
ΦV2
104t 224t 296t 416t
ΦV3
152t 272t 344t 464t
ΦV4
140t
ΦSUB
356t
† External Input
42
VSP2267
SBES001—December 2002
Timing Specification
4.5
Vertical Timing Chart (for 2A CCD)
1) V-Rate Readout Detailed Timing Chart: (Field Mode, Odd Field)
0t
HD{(+10t)
176t
ΦV2
200t
128t
128t 200t
ΦV1
392t
176t
248t
224t
104t
ΦV3
272t
152t
ΦV4
58t
176t
ΦCH1, 3
248t
ΦCH2, 4
356t
2) V-Rate Readout Detailed Timing Chart: (Field Mode, Even Field)
0t
HD{(+10t)
128t 200t
ΦV1
ΦV2
176t
248t
224t
104t
ΦV3
392t
ΦV4
58t
272t
176t
ΦCH1, 3
248t
ΦCH2, 4
356t
† External Input
SBES001—December 2002
VSP2267
43
Timing Specification
4.5
Vertical Timing Chart (for 2A CCD) (continued)
1) V-Rate Readout Detailed Timing Chart: (Frame Mode, Odd Field)
0t
HD{(+10t)
ΦV1
128t
200t
72t
ΦV2
104t
248t
224t
ΦV3
152t
272t
ΦV4
ΦCH1, 3
58t
176t
ΦCH2, 4
2) V-Rate Readout Detailed Timing Chart: (Frame Mode, Even Field)
0t
HD{(+10t)
ΦV1
ΦV2
ΦV3
152t
276t
ΦV4
272t 380t
ΦCH1, 3
ΦCH2, 4
† External Input
44
VSP2267
SBES001—December 2002
Timing Specification
4.5
Vertical Timing Chart (for 2A CCD) (continued)
1) V-Rate Readout Detailed Timing Chart: (×2 Mode, Odd Field)
0t
HD{(+10t)
128t
ΦV1
200t
72t
ΦV2
104t
128t
200t
176t
248t
224t
248t
104t
224t
ΦV3
272t
152t
152t
272t
ΦV4
ΦCH1, 3
68t 176t
ΦCH2, 4
2) V-Rate Readout Detailed Timing Chart: (×2 Mode, Even Field)
0t
HD{(+10t)
128t 200t
320t
ΦV1
176t
248t
392t
368t
440t
ΦV2
104t
224t
296t
416t
ΦV3
152t
276t
152t
272t
344t
464t
ΦV4
272t 380t
ΦCH1, 3
ΦCH2, 4
† External Input
SBES001—December 2002
VSP2267
45
Timing Specification
4.5
Vertical Timing Chart (for 2A CCD) (continued)
1) V-Rate Readout Detailed Timing Chart: (×2 Monitor Mode)
0t
HD{(+10t)
200t
ΦV1
276t
404t
452t
128t
200t
176t
248t
ΦV2
176t
428t
104t
224t
ΦV3
152t
48t
224t
476t
152t
272t
ΦV4
ΦCH1
ΦCH2
44t 152t
ΦCH3
272t 380t
ΦCH4
† External Input
46
VSP2267
SBES001—December 2002
Timing Specification
4.6
Vertical High-Speed Transfer Timing Chart (for 2A CCD)
High-Speed Transfer Start Point
508t
580t
ΦV1
556t
628t
ΦV2
484t
604t
ΦV3
532t
652t
ΦV4
(0)
(1)
(2)
(3)
(4)
(5)
High-Speed Transfer End Point
1412t
ΦV1
1460t
ΦV2
1444t
ΦV3
1484t
ΦV4
(640 or E-ZOOM Variable)
SBES001—December 2002
VSP2267
47
CCD_OUT}
48
VSP2267
OB
D
42
43
1
3
5
7
9
11
13
15
2
4
6
8
10
12
14
16
45
44
41
40
39
38
37
36
OB
OB
35
D
D
34
33
32
31
30
29
28
27
3
2
1
0
1259
1258
1257
1256
1255
1254
D
(629)
(628)
(627)
(626)
(625)
1253
D
D
1236
OB
1191 1190
1189 1188
1187 1186
1185 1184
1183 1182
1181 1180
1179 1178
1177 1176
1175 1174
(624)
VD}
1173 1172
HD}
(623)
4.7
1171 1170
Timing Specification
Vertical Rate Timing (for 2A CCD) [field mode—odd field]
ΦV1
ΦV2
ΦV3
ΦV4
CH1, 3
CH2, 4
SUB
H1
H2
PBLK{
CPOB{
CLPD{
Data Latch{
STO
† Internal Use
‡ External Input
SBES001—December 2002
CCD_OUT}
SBES001—December 2002
669
670
671
(38)
(39)
(40)
(41)
OB
2
4
6
1
3
5
7
(44)
(45)
12
14
13
15
VSP2267
675
674
673
(43)
10
11
672
8
9
(42)
668
667
666
(37)
D
OB
665
(36)
664
(35)
663
(34)
D
662
(33)
D
661
(32)
660
659
658
657
656
655
654
630
629
628
627
626
625
624
623
(31)
(30)
(29)
(28)
(27)
HD}
D
D
D
(26)
(25)
1236 1235
OB
(24)
1234 1233
OB
(0)
VD}
1186 1185
1184 1183
1182 1181
1180 1179
1178 1177
1176 1175
1174 1173
4.8
1172 1171
Timing Specification
Vertical Rate Timing (for 2A CCD) [field mode—even field]
ΦV1
ΦV2
ΦV3
ΦV4
CH1, 3
CH2, 4
SUB
H1
H2
PBLK{
CPOB{
CLPD{
Data Latch{
STO
† Internal Use
‡ External Input
49
Timing Specification
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
2
1
0
1259
15
13
11
9
7
5
3
1
OB
D
D
D
OB
1236
1258
3
1190
1188
1186
1184
(629)
1182
(628)
1180
1257
(627)
1178
1255
1256
(626)
1176
(624)
1172
(625)
(623)
CCD_OUT}
1174
VD}
1170
HD}
1254
Vertical Rate Timing (for 2A CCD) [frame mode—odd field]
1253
4.9
ΦV1
ΦV2
ΦV3
ΦV4
CH1, 3
CH2, 4
SUB
H1
H2
PBLK{
CPOB{
CLPD{
STO
Data Latch{
† Internal Use
‡ External Input
50
VSP2267
SBES001—December 2002
CCD_OUT}
SBES001—December 2002
(24)
(25)
(26)
(27)
1233
1235
OB
D
663
664
(34)
670
671
672
673
(39)
(40)
(41)
(42)
(43)
(44)
(45)
2
4
8
10
12
14
6
669
(38)
OB
VSP2267
675
674
668
667
(37)
D
666
(36)
D
665
662
(33)
(35)
661
660
659
658
657
656
655
654
630
629
628
627
626
625
624
623
(32)
HD}
(31)
(30)
(29)
(28)
(0)
VD}
1185
1183
1181
1179
1177
1175
1173
1171
Timing Specification
4.10 Vertical Rate Timing (for 2A CCD) [frame mode—even field]
ΦV1
ΦV2
ΦV3
CH1, 3
ΦV4
CH2, 4
SUB
H1
H2
PBLK{
CPOB{
CLPD{
STO
Data Latch{
† Internal Use
‡ External Input
51
52
VSP2267
(313)
1108
1112
1116
1110
1114
1118
31
D
19
23
27
31
35
21
25
29
33
37
39
11
13
15
7
9
17
38
3
5
45
44
43
42
41
40
37
36
OB
1
35
D
34
33
32
30
29
28
1236
HD}
D
OB
1234 1232
4
3
2
1
0
629
628
627
626
625
624
623
4.11 Vertical Rate Timing (for 2A CCD) [
1230 1228
1134 1132
1130 1128
1126 1124
1122 1120
(312)
1106 1104
(314)
(311)
(310)
1102 1100
1098 1096
(309)
1094 1092
CCD_OUT}
(308)
VD}
1090 1088
Timing Specification
2 mode—odd field]
ΦV1
ΦV2
ΦV3
CH1, 3
ΦV4
CH2, 4
SUB
H1
H2
PBLK{
CPOB{
CLPD{
STO
Data Latch{
† Internal Use
‡ External Input
SBES001—December 2002
CCD_OUT}
SBES001—December 2002
(0)
359
360
(44)
(45)
32
358
(43)
36
357
(42)
356
(41)
38
20
22
355
(40)
354
353
34
16
18
(39)
352
28
12
14
(38)
351
30
8
10
(37)
350
24
4
6
(36)
26
OB
349
(34)
2
348
(33)
(35)
347
(32)
D
346
(31)
D
345
344
343
318
317
316
315
(30)
(29)
(28)
(3)
(2)
(1)
314
1235
D
OB
1233 1231
1229 1227
1129 1127
1125 1123
1121 1119
1115
1117
313
1111
312
1109 1107
1113
311
310
309
308
1105 1103
VD}
1101 1099
1097 1095
1093 1091
307
HD}
1089 1087
1085 1083
Timing Specification
4.12 Vertical Rate Timing (for 2A CCD) [×2 mode—even field]
ΦV1
ΦV2
ΦV3
CH1, 3
ΦV4
CH2, 4
SUB
H1
H2
PBLK{
CPOB{
CLPD{
STO
Data Latch{
† Internal Use
‡ External Input
VSP2267
53
Timing Specification
45
44
43
42
41
39
40
38
11
37
8
36
35
34
33
32
31
30
29
2 monitor mode]
28
3
4
2
1
314
0
313
312
311
310
HD}
309
308
4.13 Vertical Rate Timing (for 2A CCD) [
35
32
27
24
19
16
3
OB
D
D
1235
1232
1227
1131
1128
1123
1120
1115
1112
1107
1104
1099
1096
1091
CCD_OUT}
1088
VD}
ΦV1
ΦV2
ΦV3
ΦV4
CH1, 2
CH3, 4
SUB
H1
H2
PBLK{
CPOB{
CLPD{
STO
Data Latch{
† Internal Use
‡ External Input
54
VSP2267
SBES001—December 2002
Timing Specification
83
82
81
80
79
78
77
76
75
74
73
72
71
70
39
38
37
21
20
19
HD}
0
4.14 Vertical Rate Timing (for 2A CCD) [frame mode—still function—odd field]
15
13
11
9
7
5
3
1
OB
D
CCD_OUT}
D
VD}
TRG
High-Speed Transfer 640 Lines, 187 kHz
ΦV1
ΦV2
ΦV3
ΦV4
CH1, 3
CH2, 4
SUB
H1
H2
PBLK{
CPOB{
CLPD{
STO
When SUBSW [9:0]=21
SUBSW
Data Latch{
When STVV [5:0]=17
† Internal Use
‡ External Input
SBES001—December 2002
VSP2267
55
Timing Specification
78
79
80
81
82
83
6
8
10
12
14
77
4
76
2
75
OB
74
73
72
71
70
39
38
HD}
37
0
4.15 Vertical Rate Timing (for 2A CCD) [frame mode—still function—even field]
D
D
D
OB
1235
1233
1231
1229
CCD_OUT}
1227
VD}
TRG
High-Speed Transfer 640 Lines, 187 kHz
ΦV1
ΦV2
ΦV3
ΦV4
CH1, 3
CH2, 4
SUB
H1
H2
PBLK{
CPOB{
CLPD{
STO
SUBSW
Data Latch{
When SUBSW [9:0]=21 STVV [5:0]=17
† Internal Use
‡ External Input
56
VSP2267
SBES001—December 2002
Timing Specification
45
44
43
42
41
40
39
38
37
36
35
34
33
32
6
5
4
3
2
1
0
696
695
694
693
HD}
692
691
4.16 Vertical Rate Timing (for 2A CCD) [frame mode—still function turnoff]
15
13
11
9
7
5
3
1
OB
D
D
D
OB
1236
1234
1232
CCD_OUT}
1230
VD}
TRG}
ΦV1
ΦV2
ΦV3
ΦV4
CH1, 3
CH2, 4
SUB
H1
H2
PBLK{
CPOB{
CLPD{
STO
SUBSW
Data Latch{
† Internal Use
‡ External Input
SBES001—December 2002
VSP2267
57
Timing Specification
69
68
67
66
65
39
38
37
36
35
34
33
32
31
30
29
28
4
3
2
1
0
1259
1258
1257
1256
1255
1254
HD}
1253
4.17 Vertical Rate Timing (for 2A CCD) [field mode—e-zoom function—odd field]
VD}
High-Speed Transfer 640 Lines, 187 kHz
Z
Z+2
Z+1
Z+3
CCD_OUT}
High-Speed Transfer Z≥640 Lines, 187 kHz
ΦV1
ΦV2
ΦV3
ΦV4
CH1, 3
CH2, 4
SUB
H1
H2
PBLK{
CPOB{
CLPD{
STO
Data Latch{
NOTE: After readout, number (EZ) of lines high-speed transfer and CCD output line address, Z = (EZ – 3) ×2.
† Internal Use
‡ External Input
58
VSP2267
SBES001—December 2002
Timing Specification
698
699
(69)
697
(68)
696
695
(65)
(67)
669
(66)
668
664
(34)
(39)
663
(33)
667
662
(32)
(38)
661
(31)
666
660
(30)
(37)
659
(29)
665
658
(28)
(36)
634
(4)
(35)
633
632
631
630
(3)
(2)
(1)
629
(0)
628
627
626
625
624
HD}
623
4.18 Vertical Rate Timing (for 2A CCD) [field mode—e-zoom function—even field]
High-Speed Transfer 640 Lines, 187 kHz
Z
Z+2
High-Speed Transfer Z≤640 Lines, 187 kHz
Z+3
CCD_OUT}
Z+1
VD}
ΦV1
ΦV2
ΦV3
ΦV4
CH1, 3
CH2, 4
SUB
H1
H2
PBLK{
CPOB{
CLPD{
STO
Data Latch{
NOTE: After readout, number (EZ) of lines high-speed transfer and CCD output line address, Z = (EZ – 3) ×2.
† Internal Use
‡ External Input
SBES001—December 2002
VSP2267
59
Timing Specification
69
68
67
66
65
39
38
37
36
35
34
33
32
31
30
29
28
4
3
2
1
0
314
313
312
311
310
309
HD}
308
4.19 Vertical Rate Timing (for 2A CCD) [×2 monitor mode—e-zoom function]
VD}
Z
CCD_OUT}
High-Speed Transfer 640 Lines, 187 kHz
High-Speed Transfer EZ≤640 Lines, 187 kHz
ΦV1
ΦV2
ΦV3
ΦV4
CH1, 3
CH2, 4
SUB
H1
H2
PBLK{
CPOB{
CLPD{
STO
Data Latch{
NOTE: After readout, number (EZ) of lines high-speed transfer and CCD output line address, (If EZ/2 = even, Z = EZ/4–1)×8+3.
If EZ/2=odd, Z = (EZ–2)2)
† Internal Use
‡ External Input
60
VSP2267
SBES001—December 2002
Timing Specification
4.20 Horizontal Timing Chart (for 2B CCD)
0t = 4788t
HD}(+10t)
CCD_OUT}
1127t
167t
OB:83
Dummy 1 Pix
Pix
1157t
PD: 1816 Pix
Dummy: 13 Pix
168t
1127t
102t
1127t
(Effective Pixels)
OB:2 Pix
H1
H2
CPOB{
PBLK{
40t 120t
168t
1158t
1130t 1146t
CPLD{
1) Still Mode / Frame Mode: Enlarged Section
208t
328t
ΦV1
288t
408t
ΦV2
ΦV3
ΦV4
ΦSUB
168t
248t
368t
448t
668t
868t
† Internal Use
‡ External Input
SBES001—December 2002
VSP2267
61
Timing Specification
4.20 Horizontal Timing Chart (for 2B CCD) (continued)
0t = 4788t
HD}(+10t)
167t
CCD_OUT}
OB:83
Pix
1127t
Dummy 1 Pix
1157t
PD: 1648 Pix
Dummy: 13 Pix
168t
1127t
102t
1127t
(Effective Pixels)
OB:2 Pix
H1
H2
CPOB{
PBLK{
40t 120t
1158t
168t
CLPD{
1130t 1146t
2) ×2 Monitor Mode (3 Stages of Transfer): Enlarged Section
208t 328t 528t 648t 848t 968t
ΦV1
288t 408t 608t 728t 928t 1048t
ΦV2
ΦV3
ΦV4
168t 368t 488t 688t 808t 1008t
248t 448t 568t 768t 888t 1088t
668t
ΦSUB
868t
3) ×2 mode: Enlarged Section
×2 Monitor Mode (3 Stages of Transfer)
208t 328t 528t 648t
ΦV1
288t 408t 608t 728t
ΦV2
168t 368t 488t 688t
ΦV3
248t 448t 568t 768t
ΦV4
ΦSUB
668t
868t
† Internal Use
‡ External Input
62
VSP2267
SBES001—December 2002
Timing Specification
4.21 Vertical Timing Chart (for 2B CCD)
1) V-Rate Readout Detailed Timing Chart: (Field Mode, Odd Field)
HD{(+10t)
ΦV1
ΦV2
0t
208t 328t
208t
608t
288t
328t
288t 408t
368t
168t
ΦV3
248t
ΦV4
448t
408t 548t
ΦCH1, 3
148t 288t
ΦCH2, 4
2) V-Rate Readout Detailed Timing Chart: (Field Mode, Even Field)
0t
HD{(+10t)
208t 328t
ΦV1
ΦV2
288t
408t
368t
168t
ΦV3
608t
448t
ΦV4
408t 548t
ΦCH1, 3
ΦCH2, 4
148t 288t
† External Input
SBES001—December 2002
VSP2267
63
Timing Specification
4.21 Vertical Timing Chart (for 2B CCD) (continued)
1) V-Rate Readout Detailed Timing Chart: (Frame Mode, Odd Field)
0t
HD{
ΦV1
328t
208t
152t
ΦV2
408t
168t
368t
ΦV3
248t
448t
ΦV4
ΦCH1, 3
148t
288t
ΦCH2, 4
2) V-Rate Readout Detailed Timing Chart: (Frame Mode, Even Field)
0t
{
HD
ΦV1
ΦV2
ΦV3
248t
412t
ΦV4
408t 548t
ΦCH1, 3
ΦCH2, 4
† External Input
64
VSP2267
SBES001—December 2002
Timing Specification
4.21 Vertical Timing Chart (for 2B CCD) (continued)
1) V-Rate Readout Detailed Timing Chart: (×2 Mode, Odd Field)
0t
HD{
208t
328t
ΦV1
152t 408t
ΦV2
168t
368t
ΦV3
448t
248t
ΦV4
ΦCH1, 3
148t 288t
ΦCH2, 4
2) V-Rate Readout Detailed Timing Chart: (×2 Mode, Even Field)
0t
HD{
208t 328t
ΦV1
288t 408t
ΦV2
168t
368t
ΦV3
248t
412t
248t
448t
ΦV4
408t 548t
ΦCH1, 3
ΦCH2, 4
† External Input
SBES001—December 2002
VSP2267
65
Timing Specification
4.21 Vertical Timing Chart (for 2B CCD) (continued)
1) V-Rate Readout Detailed Timing Chart: (×2 Monitor Mode)
0t
HD{
ΦV1
328t
208t
152t
208t
408t
328t
288t
408t
ΦV2
168t
168t
368t
368t
ΦV3
248t
472t
248t
448t
ΦV4
ΦCH1
ΦCH2
468t 608t
ΦCH3
148t
288t
ΦCH4
† External Input
66
VSP2267
SBES001—December 2002
Timing Specification
4.22 Vertical High-Speed Transfer Timing Chart (for 2B CCD)
High-Speed Transfer Start Point
1168t 1288t
ΦV1
1248t 1368t
ΦV2
1128t
1328t
ΦV3
1208t
1408t
ΦV4
(0)
(1)
(2)
(3)
(4)
(5)
High-Speed Transfer End Point
4672t
ΦV1
4752t
ΦV2
4712t
ΦV3
4792t
ΦV4
(640 or E-ZOOM Variable)
SBES001—December 2002
VSP2267
67
Timing Specification
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
3
2
1
0
5
7
9
11
13
15
8
10
12
14
16
1
2
6
OB
OB
3
D
D
4
D
D
1310
1309
1308
1307
1306
1311
(655)
(654)
D
(653)
OB
D
(652)
1208
OB
(651)
1207 1206
(650)
ΦV1
(649)
CCD_OUT}
1205 1204
VD}
1203 1202
HD}
1305
4.23 Vertical Rate Timing (for 2B CCD) [field mode—odd field]
ΦV2
ΦV3
ΦV4
CH1, 3
CH2, 4
SUB
H1
H2
PBLK{
CPOB{
CLPD{
STO
Data Latch{
† Internal Use
‡ External Input
68
VSP2267
SBES001—December 2002
CCD_OUT}
ΦV1
SBES001—December 2002
705
706
707
(48)
(49)
(50)
(51)
OB
2
4
6
1
3
5
7
709
(53)
(54)
(55)
10
12
14
11
13
15
VSP2267
711
710
708
(52)
8
9
704
703
702
(47)
D
OB
701
700
(44)
(46)
699
D
698
(43)
D
697
(42)
696
695
694
693
692
691
690
656
655
(41)
(40)
(39)
(38)
(37)
(36)
(35)
(34)
(0)
654
653
652
651
650
649
(45)
D
D
VD}
D
OB
OB
1208 1207
1206 1205
HD}
1204 1203
Timing Specification
4.24 Vertical Rate Timing (for 2B CCD) [field mode—even field]
ΦV2
ΦV3
CH1, 3
ΦV4
CH2, 4
SUB
H1
H2
PBLK{
CPOB{
CLPD{
STO
Data Latch{
† Internal Use
‡ External Input
69
Timing Specification
47
48
49
50
51
52
53
54
55
1
3
5
7
9
11
13
15
46
OB
45
44
43
42
41
40
39
38
37
3
2
1
0
D
D
1310
1309
1311
(654)
D
(653)
OB
(652)
1208
1308
(651)
1206
1306
1307
(650)
(649)
1204
(648)
CCD_OUT}
1202
VD}
1200
HD}
1305
4.25 Vertical Rate Timing (for 2B CCD) [frame mode—odd field]
ΦV1
ΦV2
ΦV3
ΦV4
CH1, 3
CH2, 4
SUB
H1
H2
PBLK{
CPOB{
CLPD{
STO
Data Latch{
† Internal Use
‡ External Input
70
VSP2267
SBES001—December 2002
Timing Specification
708
(52)
(53)
(54)
(55)
8
10
12
14
711
707
(51)
6
710
706
709
705
(50)
4
704
(49)
2
703
(48)
OB
702
(47)
D
701
(46)
D
700
699
698
697
696
695
694
693
692
691
690
656
655
654
653
652
651
650
649
4.26 Vertical Rate Timing (for 2B CCD) [frame mode—even field]
D
OB
1207
1205
CCD_OUT}
1203
(45)
(44)
(43)
(42)
(41)
(40)
(39)
(38)
(37)
(36)
(35)
VD}
(34)
(0)
HD}
ΦV1
ΦV2
ΦV3
ΦV4
CH1, 3
CH2, 4
SUB
H1
H2
PBLK{
CPOB{
CLPD{
STO
Data Latch{
† Internal Use
‡ External Input
SBES001—December 2002
VSP2267
71
Timing Specification
29
28
27
26
25
23
24
22
9
11
21
5
7
20
1
3
19
D
OB
18
17
16
15
14
13
12
4
3
2
1
0
13
17
21
25
29
33
15
19
23
27
31
35
D
654
653
652
651
655
(326)
(325)
(324)
(323)
650
(322)
D
OB
(321)
1208 1206
CCD_OUT}
(320)
VD}
1204 1202
HD}
649
4.27 Vertical Rate Timing (for 2B CCD) [×2 mode—odd field]
ΦV1
ΦV2
ΦV3
ΦV4
CH1, 3
CH2, 4
SUB
H1
H2
PBLK{
CPOB{
CLPD{
STO
Data Latch{
† Internal Use
‡ External Input
72
VSP2267
SBES001—December 2002
CCD_OUT}
D
SBES001—December 2002
VSP2267
36
34
30
26
32
22
28
18
22
20
14
10
12
16
6
(29)
(28)
(27)
(26)
(25)
(24)
(23)
(22)
2
8
346
(18)
(21)
345
(17)
4
344
(16)
357
356
355
354
353
352
351
350
349
348
347
343
(20)
342
(15)
OB D
341
(14)
(19)
340
(13)
331
330
329
328
327
326
325
324
323
322
321
320
(12)
(3)
(2)
(1)
(0)
VD}
D
OB
1207 1205
HD}
1203 1201
Timing Specification
4.28 Vertical Rate Timing (for 2B CCD) [×2 mode—even field]
ΦV1
ΦV2
ΦV3
CH1, 3
ΦV4
CH2, 4
SUB
H1
H2
PBLK{
CPOB{
CLPD{
STO
† Internal Use
‡ External Input
Data Latch{
73
Timing Specification
22
23
24
25
26
27
28
29
15
20
25
30
35
40
45
21
10
20
19
18
17
16
15
14
13
12
3
4
2
1
0
261
260
259
258
257
256
255
4.29 Vertical Rate Timing (for 2B CCD) [×2 monitor mode]
HD}
5
OB
D
OB
1205
1200
1195
1190
1185
1180
CCD_OUT}
1175
VD}
ΦV1
ΦV2
ΦV3
ΦV4
CH1, 2
CH3, 4
SUB
H1
H2
PBLK{
CPOB{
CLPD{
STO
Data Latch{
† Internal Use
‡ External Input
74
VSP2267
SBES001—December 2002
Timing Specification
89
90
91
92
93
7
9
11
13
15
88
87
86
85
84
83
82
81
80
39
38
37
21
20
19
HD}
0
4.30 Vertical Rate Timing (for 2B CCD) [frame mode—still function—odd field]
5
3
1
OB
D
CCD_OUT}
D
VD}
TRG
High-Speed Transfer 640 Lines, 147 kHz
ΦV1
ΦV2
ΦV3
ΦV4
CH1, 3
CH2, 4
SUB
H1
H2
PBLK{
CPOB{
CLPD{
STO
When SUBSW [9:0]=21
SUBSW
When STVV [5:0]=17
Data Latch{
† Internal Use
‡ External Input
SBES001—December 2002
VSP2267
75
Timing Specification
88
89
90
91
92
93
6
8
10
12
14
87
4
86
85
84
83
82
81
80
39
38
37
0
691
690
689
688
687
686
HD}
685
4.31 Vertical Rate Timing (for 2B CCD) [frame mode—still function—even field]
2
OB
D
D
D
OB
1207
1205
1203
1201
CCD_OUT}
1199
VD}
TRG
High Speed Transfer 640 Lines, 147 kHz
ΦV1
ΦV2
ΦV3
ΦV4
CH1, 3
CH2, 4
SUB
H1
H2
PBLK{
CPOB{
CLPD{
STO
SUBSW
When SUBSW [9:0]=21 STVV [5:0]=17
Data Latch{
† Internal Use
‡ External Input
76
VSP2267
SBES001—December 2002
Timing Specification
51
52
53
54
9
11
13
55
50
7
49
5
48
47
46
45
44
43
42
6
5
4
3
2
1
0
692
691
690
689
688
687
4.32 Vertical Rate Timing (for 2B CCD) [frame mode—still function turnoff]
HD}
15
3
1
OB
D
D
D
OB
1208
1206
1204
CCD_OUT}
1202
VD}
TRG}
ΦV1
ΦV2
ΦV3
ΦV4
CH1, 3
CH2, 4
SUB
H1
H2
PBLK{
CPOB{
CLPD{
STO
SUBSW
Data Latch{
† Internal Use
‡ External Input
SBES001—December 2002
VSP2267
77
Timing Specification
88
87
86
85
84
49
48
47
46
45
44
43
42
41
40
39
38
4
3
2
1
0
1311
1310
1309
1308
1307
1306
1305
4.33 Vertical Rate Timing (for 2B CCD) [field mode—e-zoom function—odd field]
HD}
High-Speed Transfer 640 Lines, 147 kHz
Z
Z+2
Z+1
CCD_OUT}
Z+3
VD}
High-Speed Transfer Z≤640 Lines, 147 kHz
ΦV1
ΦV2
ΦV3
ΦV4
CH1, 3
CH2, 4
SUB
H1
H2
PBLK{
CPOB{
CLPD{
STO
Data Latch{
NOTE: After readout, number (EZ) of lines high-speed transfer and CCD output line address, Z = (EZ – 3) ×2.
† Internal Use
‡ External Input
78
VSP2267
SBES001—December 2002
Timing Specification
744
743
742
(86)
(88)
741
(85)
Z+3 Z+2
740
(84)
(87)
705
Z+1 Z
704
700
(44)
(49)
699
(43)
703
698
(42)
(48)
697
(41)
702
696
(40)
(47)
695
(39)
701
694
(38)
(46)
660
(4)
(45)
659
658
657
656
(3)
(2)
(1)
655
(0)
654
653
652
651
650
HD}
649
4.34 Vertical Rate Timing (for 2B CCD) [field mode—e-zoom function—even field]
VD}
CCD_OUT}
High-Speed Transfer 640 Lines, 147 kHz
High-Speed Transfer Z≤640 Lines, 147 kHz
ΦV1
ΦV2
ΦV3
ΦV4
CH1, 3
CH2, 4
SUB
H1
H2
PBLK{
CPOB{
CLPD{
STO
Data Latch{
NOTE: After readout, number (EZ) of lines high-speed transfer and CCD output line address, Z = (EZ – 4) ×2 + 1.
† Internal Use
‡ External Input
SBES001—December 2002
VSP2267
79
Timing Specification
88
87
86
85
84
49
48
47
46
45
44
43
42
41
40
39
38
4
3
2
1
HD}
0
4.35 Vertical Rate Timing (for 2B CCD) [×2 monitor mode—e-zoom function]
VD}
Z
CCD_OUT}
High-Speed Transfer 640 Lines, 147 kHz
High-Speed Transfer EZ≤640 Lines, 147 kHz
ΦV1
ΦV2
ΦV3
ΦV4
CH1, 2
CH3, 4
SUB
H1
H2
PBLK{
CPOB{
CLPD{
STO
Data Latch{
NOTE: After readout, number (EZ) of lines high speed transfer and CCD output line address, (If EZ/2=even, Z=(EZ/4-1)×8+3.
If EZ/2=odd, Z = (EZ-2)2).
† Internal Use
‡ External Input
80
VSP2267
SBES001—December 2002
Electrical Characteristics
5
Electrical Characteristics
5.1
Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless
otherwise noted)†
Supply voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V
Supply voltage differences, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.1 V
Ground voltage differences, VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.1 V
Digital input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (VDD + 0.3 V)
Analog input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (VCC + 0.3 V)
Input current (any pins except supplies) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
Ambient temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25°C to 85°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C
Junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Package temperature (IR reflow, peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
5.2
Electrical Characteristics, All Specifications at TA = 25°C, All Power Supply
Voltages = 3 V, and Conversion Rate = 20 MHz (unless otherwise noted)
VSP2267GSJ
PARAMETER
TEST CONDITIONS
MIN
TYP
Resolution
MAX
12
UNIT
Bits
Conversion rate
12
25
MHz
Clock rate
24
50
MHz
DIGITAL INPUTS
Logic family
VT+
VT–
Input voltage
IIH
IIL
Input current
CMOS
LOW to HIGH threshold voltage
1.7
HIGH to LOW threshold voltage
1.0
V
Logic HIGH,
VIN = 3 V
±20
Logic LOW,
VIN = 0 V
±20
Input capacitance
5
Maximum input voltage
µA
A
pF
–0.3
5.3
V
DIGITAL OUTPUTS (DATA)
Logic family
CMOS
Logic coding
VOH
VOL
Output voltage
Straight binary
Logic HIGH,
IOH = –2 mA
Logic LOW,
IOL = 2 mA
J[1:0] = 00
Additional output data delay
SBES001—December 2002
2.4
0.4
V
0
J[1:0] = 01
5
J[1:0] = 10
10
J[1:0] = 11
13
ns
VSP2267
81
Electrical Characteristics
5.2
Electrical Characteristics, All Specifications at TA = 25°C, All Power Supply
Voltages = 3 V, and Conversion Rate = 20 MHz (unless otherwise noted)
(continued)
VSP2267GSJ
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
H-DRIVER OUTPUTS
Output voltage (SUB)
Output
Out
ut voltage (V1...V4, CH1...CH4, STO,
CLKO, SUBSW)
Logic HIGH (VOH) IOH = –0.85 mA
Logic HIGH (VOH) IOH = –1.7 mA
0.4
VDD–0.6
Logic LOW (VOL) IOL = 1.7 mA
Logic HIGH (VOH) IOH = –0 mA
Output voltage
g ((R))
VDD–0.6
Logic LOW (VOL) IOL = 0.85 mA
Logic HIGH (VOH) IOH = –6.8 mA
0.4
Output voltage
g ((H1,, H2))
Logic HIGH (VOH) IOH = –13.6 mA
VDD–0.6
V
0.4
VDD–0.05
VDD–0.6
V
Logic LOW (VOL) IOL = 13.6 mA
TP output
out ut voltage
(SHP, SHD, ADCCK, CLPD, CPOB, PBLK)
Logic HIGH (VOH) IOH = –1.7 mA
V
VDD–0.05
Logic LOW (VOL) IOL = 6.8 mA
Logic HIGH (VOH) IOH = –0 mA
V
0.4
VDD–0.6
0.4
Logic LOW (VOL) IOL = 1.7 mA
V
REFERENCE
Positive reference voltage
1.75
V
Negative reference voltage
1.25
V
ANALOG INPUT (CCDIN)
Input signal level for full-scale out
PGA gain = 0 dB
900
Input capacitance
mV
15
Input limit
–0.3
pF
3.3
V
TRANSFER CHARACTERISTICS
Differential nonlinearity (DNL)
PGA gain = 0 dB
Integral nonlinearity (INL)
PGA gain = 0 dB
No missing codes
±0.5
LSB
±1
LSB
Specified
Step response settling time
Full-scale step input
1
pixel
Overload recovery time
Step input from 1.8 V to 0 V
2
pixels
9
(fixed)
Clock
cycles
Data latency
Signal to noise ratio (see Note 1)
Signal-to-noise
Grounded input cap, PGA gain = 0 dB
79
Grounded input cap, Gain = 12 dB
67
CCD offset correction range
–180
dB
200
mV
INPUT CLAMP
Clamp-on resistance
400
Ω
Clamp level
1.5
V
PROGRAMMABLE GAIN AMP (PGA)
Gain control resolution
10
Bits
Maximum gain
Gain code = 11 1111 1111
42
dB
High gain
Gain code = 11 0100 1000
34
dB
Medium gain
Gain code = 10 0010 0000
20
dB
Low gain
Gain code = 00 1000 0000
0
dB
Minimum gain
Gain code = 00 0000 0000
–6
dB
±0.5
dB
Gain control error
NOTE 1: SNR = 20 log (full-scale voltage/rms noise)
82
VSP2267
SBES001—December 2002
Electrical Characteristics
5.2
Electrical Characteristics, All Specifications at TA = 25°C, All Power Supply
Voltages = 3 V, and Conversion Rate = 20 MHz (unless otherwise noted)
(continued)
VSP2267GSJ
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPTICAL BLACK CLAMP LOOP
Control DAC resolution
10
Programmable range of clamp level
Optical black clamp level
0
OBCLP level at CODE = 1000
Bits
240
LSB
130
Minimum output current for control DAC
COB terminal
±0.15
µA
Maximum output current for control DAC
COB terminal
±153
µA
Loop time constant
CCOB = 0.1 µF
40.7
µs
Slew rate
CCOB = 0.1 µF, Saturated output current
of control DAC
1530
V/s
POWER SUPPLY
VCC
Supply voltage
3.0
Power dissipation (AFE)
Power dissipation (TG+H, R driver)
3.6
V
80
Normall operation
N
ti mode:
d no CCD lload
d ((att
3 V and 20 MHz)
58
Power dissipation (total) without CCD load
Power dissi
ation (total)
dissipation
3.3
mW
138
Standby plus power-save mode:(at 3 V
and 20 MHz)
Master clock-off mode: (at 3 V)
34
mW
6
mW
TEMPERATURE RANGE
Operation temperature
θJA
Thermal resistance
SBES001—December 2002
–25
85
°C
°C/W
37
VSP2267
83
Mechanical Data
6
Mechanical Data
GSJ (S-PBGA-N96)
9,10
8,90
PLASTIC BALL GRID ARRAY
7,20 TYP
SQ
0,80
K
J
H
G
F
E
0,40
D
A1 Corner
C
B
A
1
2
3
4
5
6
7
8
9 10
Bottom View
0,35
0,25
1,20 MAX
Seating Plane
0,50
0,40
0,08
0,45 MAX
0,08
4204222/A 02/02
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
MicroStar Junior package configuration.
Fall within JEDEC MO-225.
MicroStar Junior is a trademark of Texas Instruments.
SBES001—December 2002
VSP2267
85
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
VSP2267GSJ
ACTIVE
BGA
GSJ
96
168
Pb-Free
(RoHS)
SNAGCU
Level-1-260C-UNLIM
VSP2267GSJR
ACTIVE
BGA
GSJ
96
1000
Pb-Free
(RoHS)
SNAGCU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1