VSP2590 www.ti.com.............................................................................................................................................................................................. SBES012 – OCTOBER 2008 DUAL-CHANNEL IMAGE SENSOR ANALOG FRONT-END FEATURES 1 • Dual-Channel Image Signal Processing: 41.5-MHz Correlated Double Sampling (CDS) Provided Sample/Hold (S/H) Mode • Output Resolution: 16 Bits • 16-Bit Analog-to-Digital Conversion: 41.5-MHz Conversion Rate (per Channel) No Missing Codes Ensured • 75-dB Input-Referred SNR (at 0-dB Gain) • Programmable Black Level Clamping • Programmable Gain Amplifier (PGA): –3 dB to +18 dB (through Analog Front Gain) • Portable Operation: Low Voltage: 2.7 V to 3.3 V Low Power: 290 mW at 3.0 V, 36 MHz 2 DESCRIPTION The VSP2590 is a dual-channel analog front-end for processing imager output signals. The device includes a correlated double sampler (CDS), programmable gain amplifier (PGA), analog-to-digital converter (ADC), input clamp, optical black (OB) level clamp loop, serial interface, adjustable sampling timing control, and reference voltage generator. The VSP2590 also provides a sample/hold (S/H) input mode. The VSP2590 is offered in a BGA-159 package and operates on a single +3 V supply. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated VSP2590 SBES012 – OCTOBER 2008.............................................................................................................................................................................................. www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) (1) PRODUCT PACKAGELEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING VSP2590 BGA-159 ZWV –25°C to +85°C VSP2590 ORDERING NUMBER TRANSPORT MEDIA, QUANTITY VSP2590ZWV Tray, 348 VSP2590ZWVR Tape and Reel, 1000 For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. VSP2590 UNIT +4 V Supply voltage differences (among VCC pins) ±0.1 V Ground voltage differences (AVSS, DLLVSS, DVSS, DRVSS, DIVSS, DIVSS2, CVSS) ±0.1 V Digital input voltage –0.3 to (VDD + 0.3) V Analog input voltage –0.3 to (VCC + 0.3) V Supply voltage (AVDD, DLLVDD, DVDD, DRVDD, DIVDD, DIVDD2, CVDD) Input current (all pins except supplies) ±10 mA Ambient temperature under bias –40 to +125 °C Storage temperature –55 to +150 °C Junction temperature +150 °C Package temperature (IR reflow, peak) +260 °C (1) 2 Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): VSP2590 VSP2590 www.ti.com.............................................................................................................................................................................................. SBES012 – OCTOBER 2008 ELECTRICAL CHARACTERISTICS All specifications at TA = +25°C, all power-supply voltages = +3.0 V, and conversion rate = 36 MHz, unless otherwise noted. VSP2560ZWV PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RESOLUTION Resolution 16 Bits 2 Channels CHANNEL Channel CONVERSION RATE Maximum conversion/clock rate VCC = 3.0 V 36 Maximum input signal level for full-scale out Gain = –3 dB 1.5 Maximum input signal for full-scale out Gain = 0 dB 1.0 41.5 MHz ANALOG INPUT (Channels A, B) Allowable input range Input capacitance VPP VPP 2.5 Without package, stray, or ESD capacitance Input limit 15 GND – 0.3 VPP pF VCC + 3.3 V TRANSFER CHARACTERISTICS (Channels A, B) (DNL) (INL) Differential nonlinearity Integral nonlinearity Data range process = 0 mV to 100 mV No missing codes ±0.8 LSB ±32 LSB ±10 LSB Ensured Signal-to-noise ratio (1) Gain = 0 dB CCD offset correction range 75 –200 dB 200 mV +18 dB PROGRAMMABLE GAIN Analog gain programmable range –3 Analog gain programmable step Analog gain accuracy Analog gain channel mismatch 3 dB ±0.3 dB 5 Digital gain programmable range 0 Digital gain programmable step % 32 dB 0.032 dB 400 Ω 1.8 V 12 Bits INPUT CLAMP (Channels A, B) Clamp on-resistance Clamp level Use internal reference OPTICAL BLACK CLAMP (OBCLP) LOOP Control DAC resolution Loop time constant Programmable range of clamp level Optical black clamp level OBCLP level at code = 1000 0000 0000b (center) OB level program step (1) µs 40.7 1536 3072 LSB 2048 LSB 1 LSB SNR = 20 log (full-scale voltage/rms noise). Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): VSP2590 3 VSP2590 SBES012 – OCTOBER 2008.............................................................................................................................................................................................. www.ti.com ELECTRICAL CHARACTERISTICS (continued) All specifications at TA = +25°C, all power-supply voltages = +3.0 V, and conversion rate = 36 MHz, unless otherwise noted. VSP2560ZWV PARAMETER TEST CONDITIONS MIN TYP MAX UNIT GENERAL-PURPOSE 8-BIT DAC (Channels A, B) Minimum output voltage 0.1 Maximum output voltage 2.9 Differential nonlinearity Integral nonlinearity Offset error Gain error Monotonicity V V ±0.25 LSB ±1 LSB ±100 mV ±5 % Ensured Minimum load resistance 10 kΩ Maximum load capacitance 1000 pF DIGITAL INPUTS Logic family VT+ VT– IIH IIL Input voltage Input current CMOS Low-to-high threshold 1.7 V High-to-low threshold 1.0 V Logic high, VIN = +3 V ±20 µA Logic low, VIN = 0 V ±20 µA MCLK clock duty cycle Input capacitance 50 % 5 pF DIGITAL OUTPUT (Channels A, B) Logic family CMOS Logic coding VOH VOL VCC, VDD Output voltage Straight binary DRVDD = 3.0 V, logic high, IOH = –2 mA 2.8 V DRVDD = 3.0 V, logic low, IOL = 2 mA 0.2 V Supply voltage Power dissipation 2.7 3.0 3.3 V Not using DLL, gain = 0 dB 290 mW Not using DLL, gain = +18 dB 310 mW Using DLL, gain = 0 dB 320 mW Using DLL, gain = +18 dB 340 mW Standby mode 4.5 mW TEMPERATURE RANGE (TOPR) Operating temperature θJA 4 –25 Thermal resistance +85 +40 Submit Documentation Feedback °C °C/W Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): VSP2590 VSP2590 www.ti.com.............................................................................................................................................................................................. SBES012 – OCTOBER 2008 TIMING CHARACTERISTICS POWER-ON/POWER-OFF SEQUENCE All VCC ³ 2.7 V VCC Power-On Reset (1.5 V, Typ) Power-Off Reset (1.2 V, Typ) GND Register Status Clear En_TG Clear AFE Status Not Active TG Clock Out Status Not Active Active Clear En_TG = 0 En_TG = 1 Active Clear Not Active RG, H2 = Low H1, LH = High Active Not Active Figure 1. Power-On/Power-Off Reset Sequence Reset Standby Function (1) MODE REGISTER CDS ADC RG CONTROL BUFFER H1 CONTROL BUFFER H2 CONTROL BUFFER LH CONTROL BUFFER Reset Clear Not active Not active Low High Low High Active (1) DLL Standby Active Not active Not active Low High Low High Active DLL is stopped by a DLL reset of a register. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): VSP2590 5 VSP2590 SBES012 – OCTOBER 2008.............................................................................................................................................................................................. www.ti.com DLL CLOCK (PER CHANNEL) tMCKP MCLK (Input) RG (Channel A, B) (Output) tWM tWR tPMR tFH1 tRH1 H1 (Channel A, B) (Output) tRH2 tFH2 H2 (Channel A, B) (Output) N N+1 CCD Signal (Channel A, B) (Input) tRP tFP SHP (Channel A, B) (Internal) tRD tFD SHD (Channel A, B) (Internal) ADINTCK (Channel A, B) (Internal) LogicCK (Channel A, B) (Output) tH Data (Channel A, B) (Output) tOD N - 16 N - 17 tRMCKx2 MCLKx2 (Internal) tHMCKx2 tODMCKx2 Data MUX Channel A First (Output) B(N - 18) A(N - 17) B(N - 17) A(N - 16) Data MUX Channel B First (Output) A(N - 18) B(N - 17) A(N - 17) B(N - 16) Figure 2. CDS Mode Timing Diagram for DLL Clock 6 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): VSP2590 VSP2590 www.ti.com.............................................................................................................................................................................................. SBES012 – OCTOBER 2008 CDS Mode Timing Characteristics for Figure 2 (1) (2) PARAMETER MIN tMCKP Master clock period — 27 ns tWMCK Master clock width — 13.5 ns tPMR Delay master clock↑ to RG↑ tWR RG pulse width tRH1 Delay RG clock↑ to H1↑ tFH1 Delay RG clock↑ to H1↓ tRH2 MAX 2.0 tMCKP4/64 UNIT ns tMCKP20/64 tMCKP35/64 ns –tMCKP16/64 0 tMCKP15/64 ns tMCKP16/64 tMCKP32/64 tMCKP47/64 ns Delay RG clock↑ to H2↑ tMCKP16/64 tMCKP32/64 tMCKP47/64 ns tFH2 Delay RG clock↑ to H2↓ –tMCKP16/64 0 tMCKP15/64 ns tRLH Delay RG clock↑ to LH↑ –tMCKP16/64 0 tMCKP15/64 ns tFLH Delay RG clock↑ to LH↓ tMCKP16/64 tMCKP32/64 tMCKP47/64 ns tRP Delay RG clock↑ to SHP↑ tMCKP10/64 tMCKP26/64 tMCKP41/64 ns tFP Delay RG clock↑ to SHP↓ –tMCKP3/64 tMCKP13/64 tMCKP28/64 ns tRD Delay RG clock↑ to SHD↑ tMCKP42/64 tMCKP58/64 tMCKP73/64 ns tFD Delay RG clock↑ to SHD↓ tMCKP11/64 tMCKP27/64 tMCKP42/64 ns Delay RG clock↑ to 2MCLK↑ tMCKP5/64 tMCKP21/64 tMCKP36/64 ns tRMCKx2 SDLL DLL step tMCKP/64 ns tH Data hold time 1.3 1.7 2.5 ns tOD Data output delay 2.6 3.7 6.1 ns tHMCLKx2 MUX data hold time 1.7 2.3 3.7 ns tODMCLKx2 MUX data output delay 3.4 2.6 7.2 ns Master clock latency — 17 — Clocks CDL (1) (2) TYP TFP < TRP. When a master clock stops, the DLL stops and returns to a standby condition. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): VSP2590 7 VSP2590 SBES012 – OCTOBER 2008.............................................................................................................................................................................................. www.ti.com tMCKP MCLK (Input) RG (Channel A, B) (Output) tWM tWR tPMR tFH1 tRH1 H1 (Channel A, B) (Output) tRH2 tFH2 H2 (Channel A, B) (Output) N N+1 CMOS Signal (Channel A, B) (Input) tRD SHD (Channel A, B) (Internal) ADINTCK (Channel A, B) (Internal) LogicCK (Channel A, B) (Output) tH tOD Data (Channel A, B) (Output) N - 16 N - 17 tRMCKx2 MCLKx2 (Internal) tHMCKx2 tODMCKx2 Data MUX Channel A First (Output) B(N - 18) A(N - 17) B(N - 17) A(N - 16) Data MUX Channel B First (Output) A(N - 18) B(N - 17) A(N - 17) B(N - 16) Figure 3. S/H Mode Timing Diagram for DLL Clock 8 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): VSP2590 VSP2590 www.ti.com.............................................................................................................................................................................................. SBES012 – OCTOBER 2008 S/H Mode Timing Characteristics for Figure 3 (1) (2) PARAMETER MIN tMCKP Master clock period — 27 ns tWMCK Master clock width — 13.5 ns tPMR Delay master clock↑ to RG↑ tWR RG pulse width tRH1 Delay RG clock↑ to H1↑ tFH1 Delay RG clock↑ to H1↓ tRH2 MAX 2.0 tMCKP4/64 UNIT ns tMCKP20/64 tMCKP35/64 ns –tMCKP16/64 0 tMCKP15/64 ns tMCKP16/64 tMCKP32/64 tMCKP47/64 ns Delay RG clock↑ to H2↑ tMCKP16/64 tMCKP32/64 tMCKP47/64 ns tFH2 Delay RG clock↑ to H2↓ –tMCKP16/64 0 tMCKP15/64 ns tRLH Delay RG clock↑ to LH↑ –tMCKP16/64 0 tMCKP15/64 ns tFLH Delay RG clock↑ to LH↓ tMCKP16/64 tMCKP32/64 tMCKP47/64 ns tRD Delay RG clock↑ to SHD↑ tMCKP42/64 tMCKP58/64 tMCKP73/64 ns tFD Delay RG clock↑ to SHD↓ tRMCLKx2 SDLL Delay RG clock↑ to 2MCLK↑ tMCKP27/64 tMCKP5/64 tMCKP21/64 DLL step ns tMCKP36/64 tMCKP/64 ns ns tH Data hold time 1.3 1.7 2.5 ns tOD Data output delay 2.6 3.7 6.1 ns tHMCLKx2 MUX data hold time 1.7 2.3 3.7 ns tODMCLKx2 MUX data output delay 3.4 2.6 7.2 ns Master clock latency — 17 — Clocks CDL (1) (2) TYP TFP < TRP. When a master clock stops, the DLL stops and returns to a standby condition. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): VSP2590 9 VSP2590 SBES012 – OCTOBER 2008.............................................................................................................................................................................................. www.ti.com EXTERNAL CLOCK (PER CHANNEL) N CCD N+1 N+2 tWP N+3 tMCKP SHP tPD tS tWD tDP tMCKP SHD tS tADC tADC tDAD tMCKP ADINTCK tINHIBIT LogicCK (Output) tOD tH B[15:0] N - 16 N - 17 N - 15 N - 14 tINHIBIT2MCK 2MCLK tH2MCK tOD2MCK B[15:0] MUX Channel A First B(N - 18) A(N - 17) B(N - 17) A(N - 16) B(N - 16) A(N - 15) B(N - 15) A(N - 14) B[15:0] MUX Channel B First A(N - 18) B(N - 17) A(N - 17) B(N - 16) A(N - 16) B(N - 15) A(N - 15) B(N - 14) Figure 4. CDS Mode Timing Diagram for External Clock CDS Mode Timing Characteristics for Figure 4 (1) PARAMETER tMCKP Clock period tADC ADINTCK high or low level tWP MAX UNIT 27 ns ns SHP pulse width 6 ns tWD SHD pulse width 13.5 ns tPD SHP↑ to SHD↓ 0 ns tDP SHD↑ to SHP↓ 9 ns tS Sampling delay 3 ns SHD↓ to ADINTCK↑ 0 ns tINHIBIT Inhibit clock period from ADINTCK↑ to LogicCK↑ 4 7 10 ns tH Data hold time 1.3 1.7 2.5 ns tOD Data output delay 2.6 3.7 6.1 ns tHMCLKx2 MUX data hold time 1.7 2.3 3.7 ns tODMCLKx2 MUX data output delay 3.4 2.6 7.2 ns Inhibit clock period from LogicCK↑ to 2MCLK↑ 1.3 3.7 6.1 ns tINHIBIT2MCK DL 10 TYP 13.5 tDAD (1) MIN Data latency 17 Clocks tWP + tPD should be nearly equal to tWD + tDP. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): VSP2590 VSP2590 www.ti.com.............................................................................................................................................................................................. SBES012 – OCTOBER 2008 N+1 N N+2 N+3 SIGIN tMCKP tWD SHD tS tADC tDAD tADC tMCKP ADINTCK tINHIBIT LogicCK (Output) tH B[15:0] tOD N - 16 N - 17 N - 15 N - 14 tINHIBIT2MCK 2MCLK tOD2MCK tH2MCK B[15:0] MUX Channel A First B(N - 18) A(N - 17) B(N - 17) A(N - 16) B(N - 16) A(N - 15) B(N - 15) A(N - 14) B[15:0] MUX Channel B First A(N - 18) B(N - 17) A(N - 17) B(N - 16) A(N - 16) B(N - 15) A(N - 15) B(N - 14) Figure 5. S/H Mode Timing Diagram for External Clock S/H Mode Timing Characteristics for Figure 5 (1) PARAMETER tMCKP Clock period tADC ADINTCK high or low level tWD SHD pulse width tS tDAD tINHIBIT TYP MAX UNIT 27 ns 13.5 ns 6 ns Sampling delay 3 ns SHD↓ to ADINTCK↑ 0 ns Inhibit clock period from ADINTCK↑ to LogicCK↑ 4 7 10 ns tH Data hold time 1.3 1.7 2.5 ns tOD Data output delay 2.6 3.7 6.1 ns tHMCLKx2 MUX data hold time 1.7 2.3 3.7 ns tODMCLKx2 MUX data output delay 3.4 2.6 7.2 ns Inhibit clock period from LogicCK↑ to 2MCLK↑ 1.3 3.7 tINHIBIT2MCK DL (1) MIN Data latency 17 6.1 ns Clocks tWP + tPD should be nearly equal to tWD + tDP. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): VSP2590 11 VSP2590 SBES012 – OCTOBER 2008.............................................................................................................................................................................................. www.ti.com H1, H2, HSEL1, HSEL2, AND PBLK H1 and H2 Timing While PBLK is Low (per channel) When PBLK is low, H1 is fixed high and H2 is fixed low. For the duration that PBLK is low, H1 and H2 can be toggled only by the HSEL1 and HSEL2 input. H1 From DLL H2 From DLL PBLK (External) HSEL1 (External) H1 (Output) HSEL2 (External) H2 (Output) Figure 6. H1 and H2 Timing Diagram HSEL1, HSEL2, and PBLK Timing H1 From DLL H2 From DLL tsDLLH tsDLLH PBLK (External) HSEL1, HSEL2 (External) tsDLLH tsDLLH tINHIBIT_HSEL tINHIBIT_HSEL tWHSEL tWHSEL Figure 7. HSEL1, HSEL2, and PBLK Timing Diagram Timing Characteristics for Figure 7 PARAMETER TYP MAX UNIT +tMCKP ns –tMCKP tWHSEL HSEL high/low period tMCKP ns tsDLLH Setup time H1/H2 (from DLL) to PBLK/HSEL1/HSEL2 800 ps tINHIBIT_HSEL 12 MIN HSEL high period inhibit timing (from PBLK) Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): VSP2590 VSP2590 www.ti.com.............................................................................................................................................................................................. SBES012 – OCTOBER 2008 SERIAL INTERFACE Standard Write Mode tXH tXS tXS SCS tCKH tCKL SCLK tCKP tXHS tDH tDS Address LSB SDI Data LSB Address MSB 8 Bits Data MSB 16 Bits Continuous Write Mode Reflection Timing SCS SCLK Address LSB SDI Address MSB Data MSB Data LSB Data MSB Data LSB 16 Bits 16 Bits Figure 8. Serial Interface Timing Diagram Update Timing Immediate Update: The data shift operation should decode at the rising edge of SCLK while SLOAD is low. 16 bits of input data are loaded to the parallel latch in the VSP2590 at the rising edge of SCS. External Sync Update: Register update timing is synchronized with the falling edge of UPDATE_REG. Continuous Writing Continuous write mode is used when transmitting a large set of data. Receiving data initiates at the falling edge of SLOAD and continues while SLOAD is low. It is only necessary to transmit the starting address data; after that transmission, the address increments by one automatically. The data stream then consists of the starting address followed by the data for that register, then the data for the next register, and so on. The device accepts data for sequential registers as long as SLOAD is low. When SLOAD goes high, no more registers are written to. Over or Shortage Data Input 16-bit data are counted by SCLK. Any over or shortage data are ignored. Timing Characteristics for Figure 8 PARAMETER MIN TYP MAX UNIT tCKP Clock period 50 ns tCKH Clock high pulse width 25 ns tCKL Clock low pulse width 25 ns tDS Data setup time 15 ns tDH Data hold time 15 ns tXS SLOAD to SCLK setup time 20 ns tXH SCLK to CS hold time 50 ns tXHS CS width 50 ns Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): VSP2590 13 VSP2590 SBES012 – OCTOBER 2008.............................................................................................................................................................................................. www.ti.com REGISTER UPDATE UPDATE_REG ¼ LogicCK Register Update Time (At the next rising edge after the second clock) Figure 9. Register Update Timing Diagram PIXEL COUNT-UP START TIMING HD ¼ LogicCK n 0 1 2 ¼ 3 Pixel Couter Reset Time (At the next rising edge after the second clock) Figure 10. Pixel Count-Up Timing Diagram UPDATE_REG HD tHLogicCK LogicCK tsLogicCK Figure 11. LogicCK Timing Diagram Timing Characteristics for Figure 11 PARAMETER 14 MIN TYP MAX UNIT tSLogicCK Setup time LogicCK to UPDATE_REG/UPDATE_INL/HD 800 ps tHLogicCK Hold time LogicCK to UPDATE_REG/UPDATE_INL/HD 2.0 ns Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): VSP2590 VSP2590 www.ti.com.............................................................................................................................................................................................. SBES012 – OCTOBER 2008 PIN CONFIGURATION ZWV PACKAGE BGA-159 (TOP VIEW) A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 AVSSA COBA TEST_ref CMA REFNA REFPA CVDDA LogicCKAD MnSHPA MnLogicCKA CVDDA BYPDA DLLVSSA MCLKA BYPCMA REFVSSA REFVDDA GNDG CVSSA MCLKx2in MnSHDA PBLK CVSSA DLLVSSA DLLVDDA DLLVDDA DOUT21 DOUT17 DOUT13 DVSS DOUT9 DOUT5 DOUT1 DVSS DVDD DVSS DVDD DOUT19 DOUT15 DVDD DOUT11 DOUT7 DOUT3 B AVDDA AVSSA C CCDINA AVSSA D CCDGNDA AVSSA DVDD DOUT23 E AVDDA AVDDA UDACOUT1 DOUT25 RGA H2A H1A LHA DRVDD DRVDD DRVSS DRVSS TEST_UPDATE F CLPDMA DIVSSA DIVDDA DOUT27 HSEL1 HSEL2 G CLPOBA DIVSSA DOUT31 DOUT29 TEST_IN UPDATE_REG H CLPOBB DIVSSB DOUT30 DOUT28 TEST_OUT SCLK SLOAD DIVSS2 SDI RESET (XCLR) DIVSS2 J CLPDMB DIVSSB DIVDDB DOUT26 TEST_IN DIVDD2 DIVSS2 DIVSS2 K AVDDB AVDDB UDACOUT2 DOUT24 DRVDD DRVDD DRVSS DRVSS K CCGNDB AVSSB DVDD DOUT22 DOUT18 DOUT14 DVDD DOUT10 DOUT6 DOUT2 RGB H2B H1B LHB K CCDINB AVSSB DVSS DOUT20 DOUT16 DOUT12 DVSS DOUT8 DOUT4 DOUT0 DVSS DVDD DVSS DVDD K AVDDB AVSSB BYPCMB REFVSSB REFVDDB GNDG CVSSB TEST_IN MnSHDB HD CVSSB DLLVSSB DLLVDDB DLLVDDB K AVSSB COBB TEST_ref CMB REFNB REFPB CVDDB LogicCKBD MnSHPB MnLogicCKB CVDDB BYPDB DLLVSSB MCLKB TERMINAL FUNCTIONS TERMINAL NAME NO. I/O A1 AVSSA P DESCRIPTION A2 COBA AO OB loop output voltage connected to a 0.1-µF capacitor (channel A) A3 Test_ref AO Test setting pin (Hi-Z) A4 CMA AO Analog common dc reference connected to a 0.1-µF capacitor (channel A) A5 REFNA AO ADC negative reference connected to a 0.1-µF capacitor (channel A) A6 REFPA AO ADC positive reference connected to a 0.1-µF capacitor (channel A) A7 CVDDA P A8 LogicCKAD DO Logic clock output (channel A) for digital chip and total output A9 MnSHPA DIO SHP monitor out/external SHP input (channel A) A10 MnLogicCKA DIO MCLKx2 monitor out/external logicCK input (channel A) A11 CVDDA P A12 BYPDA AO A13 DLLVSSA P DLL GND (channel A) A14 MCLKA DI Masker clock (channel A) input B1 AVDDA P Analog power supply (channel A) B2 AVSSA P Analog GND (channel A) B3 BYPCMA AO B4 REFVSSA P Reference block GND (channel A) B5 REFVDDA P Reference block power supply (channel A) B6 GNDG P SUB GND B7 CVSSA P Mask block GND (channel A) B8 MCLKx2in DI External CLKx2 input Analog GND (channel A) Mask block power supply (channel A) HTG block power supply (channel A) DLL bypass connected to DLLVDD 1000-pF capacitor (channel A) Analog positive reference connected to a 0.1-µF capacitor (channel A) B9 MnSHDA DIO B10 PBLK DI SHD monitor out/external SHD input (channel A) Pre-blanking signal input; connect to DVDD when PBLK is not used B11 CVSSA P HTG block GND (channel A) B12 DLLVSSA P DLL GND (channel A) B13 DLLVDDA P DLL power supply (channel A) B14 DLLVDDA P DLL power supply (channel A) C1 CCDINA AI CCD/CMOS sensor signal input (channel A) Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): VSP2590 15 VSP2590 SBES012 – OCTOBER 2008.............................................................................................................................................................................................. www.ti.com TERMINAL FUNCTIONS (continued) TERMINAL 16 NAME NO. I/O C2 AVSSA P Analog GND (channel A) DESCRIPTION C4 DOUT21 DO Data output (channel A) C5 DOUT17 DO Data output (channel A) C6 DOUT13 DO Data output (channel B/MUX) C7 DVSS P C8 DOUT9 DO Digital GND Data output (channel B/MUX) C9 DOUT5 DO Data output (channel B/MUX) C10 DOUT1 DO Data output (channel B/MUX) C11 DVSS P Digital GND C12 DVDD P Digital power supply C13 DVSS P Digital GND C14 DVDD P Digital power supply D1 CCDGNDA AI CCD GND connection/CMOS sensor signal input (channel A) D2 AVSSA P Analog GND (channel A) D3 DVDD P Digital power supply D4 DOUT23 DO Data output (channel A) D5 DOUT19 DO Data output (channel A) D6 DOUT15 DO Data output, MSB (channel B/MUX) D7 DVDD P D8 DOUT11 DO Data output (channel B/MUX) D9 DOUT7 DO Data output (channel B/MUX) D10 DOUT3 DO Data output (channel B/MUX) D11 RGA DO RG pulse output (channel A) D12 H2A DO H2 pulse output (channel A) D13 H1A DO H1 pulse output (channel A) D14 LHA DO LH pulse output (channel A) E1 AVDDA P Analog power supply (channel A) E2 AVDDA P Analog power supply (channel A) E3 UDACOUT1 AO Universal DAC1 output E4 DOUT25 DO Data output (channel A) E11 DRVDD P Digital out power supply E12 DRVDD P Digital out power supply E13 DRVSS P Digital out GND E14 DRVSS P Digital out GND F1 CLPDMA DI CLPDM pulse input (channel A); connect to DVDD when CLPDM is not used F2 DIVSSA P CLKGEN GND supply (channel A) F3 DIVDDA P CLKGEN power supply (channel A) F4 DOUT27 DO Data output (channel A) F11 HSEL1 DI Horizontal mask timing 1; connect to GND when HSEL1 is not used F12 HSEL2 DI Horizontal mask timing 2; connect to GND when HSEL2 is not used F13 TEST_Update DI Test setting pin; connect to DVDD F14 SCLK DI Serial interface clock G1 CLPOBA DI CLPOB pulse input (channel A); connect to DVDD when CLPOB is not used G2 DIVSSA P CLKGEN GND supply (channel A) G3 DOUT31 DO Data output, MSB (channel A) G4 DOUT29 DO Data output (channel A) G11 TEST_IN DI Test setting pin; connect to GND G12 UPDATE_REG DI Serial interface signal G13 SLOAD DI SPI signal G14 DIVSS2 P Serial interface GND Digital power supply Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): VSP2590 VSP2590 www.ti.com.............................................................................................................................................................................................. SBES012 – OCTOBER 2008 TERMINAL FUNCTIONS (continued) TERMINAL NAME NO. I/O H1 CLPOBB DI CLPOB pulse input (channel B); Connect to DVDD when CLPOB is not used DESCRIPTION CLKGEN GND supply (channel B) H2 DIVSSB P H3 DOUT30 DO Data output (channel A) H4 DOUT28 DO Data output (channel A) H11 TEST_OUT DO Test setting pin (normal operation = Hi-Z) H12 SDI DI SRI signal H13 RESET DI System reset; connect to DVDD when RESET is not used H14 DIVSS2 P Serial interface GND J1 CLPDMB DI CLPDM pulse input (channel B); connect to DVDD when CLPDM is not used J2 DIVSSB P CLKGEN GND supply (channel B) J3 DIVDDB P CLKGEN power supply (channel B) J4 DOUT26 DO Data output (channel A) J11 TEST_IN DI Test setting pin; connect to GND J12 DIVDD2 P Serial interface power supply J13 DIVSS2 P Serial interface GND J14 DIVSS2 P Serial interface GND K1 AVDDB P Analog power supply (channel B) K2 AVDDB P Analog power supply (channel B) K3 UDACOUT2 AO Universal DAC2 output K4 DOUT24 DO Data output (channel A) K11 DRVDD P Digital out power supply K12 DRVDD P Digital out power supply K13 DRVSS P Digital out GND K14 DRVSS P Digital out GND L1 CCDGNDB AI CCD GND connection/CMOS sensor signal input (channel B) L2 AVSSB P Analog GND (channel B) L3 DVDD P Digital power supply L4 DOUT22 DO Data output (channel A) L5 DOUT18 DO Data output (channel A) L6 DOUT14 DO Data output (channel B/MUX) L7 DVDD P L8 DOUT10 DO Data output (channel B/MUX) L9 DOUT6 DO Data output (channel B/MUX) L10 DOUT2 DO Data output (channel B/MUX) L11 RGB DO RG pulse output (channel B) L12 H2B DO H2 pulse output (channel B) L13 H1B DO H1 pulse output (channel B) L14 LHB DO LH pulse output (channel B) M1 CCDINB AI CCD/CMOS sensor signal input (channel B) M2 AVSSB P Analog GND (channel B) M3 DVSS P Digital GND M4 DOUT20 DO Data output (channel A) M5 DOUT16 DO Data output, LSB (channel A) M6 DOUT12 DO Data output (channel B/MUX) Digital power supply M7 DVSS P M8 DOUT8 DO Digital GND Data output (channel B/MUX) M9 DOUT4 DO Data output (channel B/MUX) M10 DOUT0 DO Data output, LSB (channel B/MUX) M11 DVSS P Digital GND M12 DVDD P Digital power supply Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): VSP2590 17 VSP2590 SBES012 – OCTOBER 2008.............................................................................................................................................................................................. www.ti.com TERMINAL FUNCTIONS (continued) TERMINAL 18 NAME NO. I/O M13 DVSS P Digital GND DESCRIPTION M14 DVDD P Digital power supply N1 AVDDB P Analog power supply (channel B) N2 AVSSB P Analog GND (channel B) N3 BYPCMB AO N4 REFVSSB P Reference block GND (channel B) N5 REFVDDB P Reference block power supply (channel B) N6 GNDG P SUB GND N7 CVSSB P Mask block GND (channel B) N8 TEST_IN DI Test setting pin; connect to GND N9 MnSHDB DIO N10 HD DI HD timing pulse input; connect to DVDD when HD is not used N11 CVSSB P HTG block GND (channel B) N12 DLLVSSB P DLL GND (channel B) N13 DLLVDDB P DLL power supply (channel B) N14 DLLVDDB P DLL power supply (channel B) P1 AVSSB P Analog GND (channel B) P2 COBB AO OB loop output voltage connected to a 0.1 µF-capacitor (channel B) P3 Test_ref AO Test setting pin (Hi-Z) P4 CMB AO Analog common dc reference connected to a 0.1-µF capacitor (channel A) P5 REFNB AO ADC negative reference connected to a 0.1-µF capacitor (channel B) P6 REFPB AO ADC positive reference connected to a 0.1-µF capacitor (channel B) P7 CVDDB P P8 LogicCKBD DO Logic clock output (channel B) for digital chip and total output Analog positive reference connected to a 0.1-µF capacitor (channel B) SHD monitor out/external SHD input (channel B) Mask block power supply P9 MnSHPB DIO SHP monitor out/external SHP input (channel B) P10 MnLogicCKB DIO External logicCK input (channel B) P11 CVDDB P P12 BYPDB AO P13 DLLVSSB P DLL GND (channel B) P14 MCLKB DI Masker clock input (channel B) HTG block power supply (channel B) DLL bypass connected to DLLVDD 1000-pF capacitor (channel B) Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): VSP2590 VSP2590 www.ti.com.............................................................................................................................................................................................. SBES012 – OCTOBER 2008 FUNCTIONAL BLOCK DIAGRAM BYPDA COBA BYPCMA REFPA CMA REFNA Internal Reference Buffer Current DAC Digital Gain VDEFECT Correction Decoder CCDGNDA CDS/SH -3 dB to 18 dB 16-Bit ADC CCDINA CDS Gain Setting Clamp SHP/SHD A ADINTCK A CLPDM A LogicCK A MnSHP A LogicCK AD SHP A MnSHD A MnLogicCK A SHD A ADINTCK A CLK Select CLKOB A RG A H1 A LogicCK A CLKDM A H2 A Internal Timing Circuit (DLL) MCLKx2 CLKDM A LH A MCLKx2 8-Bit DAC 1 PBLK HSEL1 UDACOUT 1 HSEL2 Digital Output Channel A (16-Bit) HD UPDATE_REG Serial Interface and Function Controller/Register RESET SDATA MCLKx2 MUX SCLK Digital Output MUX (16-Bit) SLOAD Digital Output Channel B (16-Bit) MCLK B CLPDM B CLPOB B LogicCK B ADINTCK B CLK Select MnLogicCK B MnSHD B 8-Bit DAC 2 Internal Timing Circuit (DLL) UDACOUT 2 LH B SHD B H2 B SHP D H1 B MnSHP B RG B Clamp CLPDM B SHP/SHD B LogicCK B ADINTCK B LogicCK BD CDS Gain Setting CCDINB CDS/SH -3 dB to 18 dB 16-Bit ADC CCDGNDB Buffer Current DAC Digital Gain VDEFECT Correction Decoder Internal Reference COBB BYPCMB REFPB CMB REFNB BYPDB Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): VSP2590 19 VSP2590 SBES012 – OCTOBER 2008.............................................................................................................................................................................................. www.ti.com SYSTEM DESCRIPTION OVERVIEW The VSP2590 is a dual-channel analog front-end device for processing imager output signals. A simplified block diagram is shown in Figure 12. The VSP2590 includes a sample/hold mode (S/H), programmable gain amplifier (PGA), analog-to-digital converter (ADC), input clamp, optical black (OB) level clamp loop, serial interface, timing control, and reference voltage generator. The device also provides a correlated double sampler (CDS) input mode. This CDS input mode consists of reconfiguration from the S/H circuit. The input mode is selected through the serial interface. Both the S/H and CDS modes provide analog gain for the input circuit. All functions and parameters (such as PGA gain control, operation mode, and other settings) can be changed via the serial interface. All parameters are reset to default values when the serial interface activates a software reset. The PGA of the VSP2590 provides both analog and digital gain. Digital PGA is a multi-gain function. This function can set different gain coefficients for each set of two pixels. The OB offset code can also set different offsets for every two pixels. COB Buffer Current DAC Decoder From Serial Interface Gain Control CCD Out Signal CDS 16-Bit ADC DPGA Digital Output 16-Bit CCDIN Clamp Internal Clocks (SHP/SHD, ADINTCK, LogicCK, CLPOB, CLPDM) From Internal Timing Circuit (Provided by the DLL or an External CLK) Figure 12. Simplified Block Diagram (Single Channel) SAMPLE-AND-HOLD (S/H) MODE In S/H mode, the input circuit of the VSP2590 is configured as a sample-and-hold mode by the serial interface setting. Figure 13 shows a simplified input circuit of the S/H mode. In this mode, the input signal is sampled by the SHD signal. SHD C1 INP CCDIN INN CCDGND SHD C2 Figure 13. S/H Input Mode Block Diagram 20 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): VSP2590 VSP2590 www.ti.com.............................................................................................................................................................................................. SBES012 – OCTOBER 2008 CORRELATED DOUBLE SAMPLER (CDS) MODE In CDS mode, the input circuit of the VSP2590 is reconfigured as correlated double sampler (CDS) by the serial interface setting. Figure 14 shows a simplified input circuit of the CDS mode. SHP/SHD CCD Input CINP C1 CCDIN CCDGND SHP C2 CLPDM CLPDM SHP SHP REF REF Figure 14. CDS Input Mode Block Diagram INPUT CLAMP In the CCD input mode, CCDIN of the VSP2590 is connected to the buffered CCD output through capacitive coupling; therefore, an input clamp is necessary. The purpose of the input clamp is to restore the dc component of the input signal that was lost during ac coupling and establish the desired dc bias point for CDS. The block diagram of Figure 14 also illustrates the input clamp. The input level is clamped to the internal reference voltage during the dummy pixel interval. More specifically, the clamping function becomes active when both CLPDM and SHP are active. Immediately after device power on, the clamp voltage of the input capacitor is not charged. For a fast charge-up of the clamp voltage, the VSP2590 provides a boost-up circuit. 16-BIT ADC The VSP2590 also provides a high-speed, 16-bit ADC. This ADC uses a fully differential, pipelined architecture with correction. This architecture is very advantageous for realizing better linearity at a lower signal level because large linearity errors tend to occur at specific points in the full-scale range, and the linearity improves for a level of signal below that specific point. The ADC ensures 16-bit resolution for the entire full-scale range. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): VSP2590 21 VSP2590 SBES012 – OCTOBER 2008.............................................................................................................................................................................................. www.ti.com OPTICAL BLACK (OB) LEVEL LOOP AND OB CLAMP LEVEL The VSP2590 has a built-in optical black (OB) offset self-calibration circuit (OB loop) that compensates the OB level by using OB pixels that are output from the CCD image sensor. A block diagram of the OB loop and OB clamp circuit is shown in Figure 15. CCD offset is compensated by converging this calibration circuit while activating CLPOB during a period when OB pixels are output from the CCD. OB Clamp Level - 2 CCDIN CDS S/H 16-Bit ADC Digital Block 1 Digital Block 2 12 Bits Current DAC COB 12 Bits Decoder OB Clamp Level - 1 14 Bits CLPOB Figure 15. OB Loop and OB Level Clamp Because the DPGA (which is a gain stage) is outside the OB loop, OB levels are not affected even when the gain changes. The converging time of the OB loop is determined based on the capacitor value connected to the COB terminal and the output from the current output digital-to-analog converter (DAC) of the loop. The time constant, TJ, can be obtained from Equation 1: C T= 16384 ´ IMIN (1) Where: • C is the capacitor value connected to COB • IMIN is the minimum current (0.15 µA) of the current DAC, which is the current equivalent to 1 LSB of the DAC output. When C = 0.1 µF, T is 40.7 µs. Slew rate (SR) can be obtained from Equation 2: IMAX SR = C (2) Where: • C is the capacitor value connected to COB • IMAX is maximum current (153 µA) of the current DAC, which is the current equivalent to 1023 LSB of the DAC output. DAC output current multiplication is provided. This function increases the DAC output current through serial interface as multiples of x2, x4, and x8. Increased DAC current shortens the time constant of the OB loop. In the case where the OB level drastically changes and must quickly settle the loop, this function is effective. Immediately after power on, the COB capacitor voltage is not charged. For fast start-up, a COB voltage boost-up circuit is provided. 22 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): VSP2590 VSP2590 www.ti.com.............................................................................................................................................................................................. SBES012 – OCTOBER 2008 The OB clamp level can be set from 1536 to 3072 in 1-LSB steps, and provide a multi-OB level function that can be set to different offset values for each two-pixel pair. Table 1 lists the input code and OB clamp level. Table 1. Input Code and OB Clamp Level CODE 16-BIT CLAMP LEVEL (LSB) 0110 0000 0000b 1536 0110 0000 0001b 1537 — — 0111 1111 1110b 2046 0111 1111 1111b 2047 1000 0000 0000b (default) 2048 — — 1011 1111 1111b 3071 1100 0000 0000b 3072 PROGRAMMABLE GAIN The VSP2590 gain ranges from –3 dB to 50 dB. The desired gain is set through a combination of analog gain and the digital programmable gain amplifier (DPGA). Both gain controls through the serial interface. Analog gain can be programmed from –3 dB to 18 dB in 3-dB steps. The –3-dB gain is provided for large input signals (such as over 1.0 V). Digital gain can be programmed from 0 dB to 32 dB in 0.032-dB steps. The digital gain changes linearly in proportion to the setting code. The relationship between the input code and digital gain is shown in Figure 16. 30 25 Gain (dB) 20 15 10 5 0 0 100 200 300 400 500 600 700 800 900 1000 Input Code for Gain Control (10-Bit) Figure 16. Setting Code versus Gain CLOCKING AND DLL The VSP2590 requires the following clocks for proper operation: MCLK is the system clock, SHP is the sampling pedestal level of the sensor signal, SHD is the sampling data level of the sensor signal, ADINTCK outputs the ADC data, CLPOB is the optical black level clamp, and CLPDM is the input clamp. The VSP2590 has built-in DLL circuits that enable the required sampling clocks (SHP, SHD, and ADINTCK) and the horizontal timing pulse of RG, H1, H2, and LH to be generated. The PBLK timing signal (input from the pin) transmits the blanking period timing. In this period, high-speed horizontal timing pulses (RG, H1, H2, and LH) are masked and the trigger timing of H1 and H2 is transmitted as the external timing pulse of HSEL1 and HSEL2, respectively. OUTPUT MULTIPLEXING The VSP2590 allows selection of the output mode by the serial interface, dual channel mode, and multiplexing output mode. Output order in the multiplexing mode is selectable as channel A first or channel B first. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): VSP2590 23 VSP2590 SBES012 – OCTOBER 2008.............................................................................................................................................................................................. www.ti.com VOLTAGE REFERENCE All reference voltages and bias currents used on the device are created from internal bandgap circuitry. The VSP2590 has a symmetrically independent voltage reference for each channel. Both channels of the SH/CDS and the ADC use three primary reference voltages: REFP (1.5 V), REFN (1.0 V), and CM (1.275 V) of individual references. REFP and REFN are buffered on-chip. CM is derived as the midrange voltage of the resistor chain internally connecting REFP and REFN. The ADC full-scale range is determined by twice the difference voltage between REFP and REFN. REFP, REFN, and CM should be heavily decoupled with appropriately-sized capacitors. HOT PIXEL REJECTION Sometimes, OB pixel output signals from the CCD include unusual level signals that are caused by pixel defection. If this level reaches a full-scale level, it may affect OB level stability. The VSP2590 has a function that rejects the unusually large pixel levels (hot pixels) in the OB pixel. This function may contribute to CCD yield improvement that is caused by OB pixel failure. Rejection level for hot pixels is programmable through the serial interface. When hot pixels come from the CCD, the VSP2590 omits it and replaces the previous pixel level with the OB level calculation. VCCD DEFECT COMPENSATION The VSP2590 provides a VCCD defect compensation function. This function can compensate VCCD defects by 32 points. 24 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): VSP2590 VSP2590 www.ti.com.............................................................................................................................................................................................. SBES012 – OCTOBER 2008 REGISTER DEFINITIONS Table 2. Register Definitions ADDRESS REGISTER BIT NAME DESCRIPTION CIRCUIT OPERATION CONDITION 0 STB STB mode 0 = Normal (circuit operates) 1 = STB mode Default = 0 1 REG_RST Register reset 0 = Normal (circuit operates) 1 = clear all registers Default = 0 2 DLL_STB DLL standby 0 = DLL operates 1 = DLL reset (CLK stop) Default = 0 3 DLL_RST DLL reset 5:4 PT CLPOB loop current control UPDATE TIMING 0 = DLL reset 1 = DLL operates Default = 1 00b = 6.2 µA 01b = 12.4 µA 10b = 24.8 µA 11b = 49.6 µA Default = 00b 0 1 2 3 Config 7:6 — Reserved 8 INPPOL S/H mode data level polarity 9 INPMOD Input mode select 10 CLKPOL Sampling clock polarity change for S/H mode 11 — Reserved 12 ExtEn Clock selection (DLL or external) 13 MonMode Monitor out enable or disable 15:14 — Reserved 2:0 HdrvAB RG/H1/H2 pin drive ability select 3 — Reserved 6:4 OutEn_ana Output buffer drive ability (analog output) I/O config 7 — — 10:8 OutEn_dig Output buffer drive ability (digital output) 15:11 — Reserved 11:0 OB level 0-A — 15:12 — Reserved 11:0 OB level 0-B — 15:12 — Reserved OB_level0_A OB level0_B Fixed at 0 Default = 00b 0 = positive data level (S/H mode) 1 = Negative data level (S/H mode) Default = 0 Immediate 0 = CDS mode 1 = S/H mode Default = 0 0 = SHP/SHD negative sampling 1 = SHP/SHD positive sampling Default = 0 Fixed at 0 Default = 0 0 = DLL CLK provided to system 1 = External CLK provided to system Default = 0 0 = No signal appears at the monitor pin 1 = Signal appears at the monitor pin Default = 0 Fixed at 0 Default = 00b 000b = 3 mA 001b = 2 mA 011b = 1 mA 111b = Hi-Z Default = 001b Fixed at 0 Default = 0 000b = 3 mA 001b = 2 mA 011b = 1 mA 111b = Hi-Z Default = 001b Immediate Fixed at 0 Default = 0 000b = 3 mA 001b = 2 mA 011b = 1 mA 111b = Hi-Z Default = 001b Fixed at 0 Default = 00000b OB level is limited as 1536 to 3072 (LSB) Default = 1000 0000 0000b Fixed at 0 Default = 0000b OB level is limited as 1536 to 3072 (LSB) Default = 1000 0000 0000b Fixed at 0 Default = 0000b Immediate Immediate Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): VSP2590 25 VSP2590 SBES012 – OCTOBER 2008.............................................................................................................................................................................................. www.ti.com Table 2. Register Definitions (continued) ADDRESS REGISTER BIT NAME DESCRIPTION 4–7 — — — Reserved 8 9 10 DAC1 DAC2 — Fixed at 0 7:0 — Universal DAC 1 level 8 — Universal DAC 1 on/off 0 = On 1 = Off Default = 0 15:9 — Reserved 7:0 — Universal DAC 2 level Universal DAC 2 level = 256 steps Default = 0000 0000b 8 — Universal DAC 2 on/off 0 = On 1 = Off Default = 0 15:9 — Reserved Fixed at 0 Default = 000 0000b — — Reserved Fixed at 0 Gain Analog gain selection Analog Gain UPDATE TIMING Immediate Universal DAC 1 level = 256 steps Default = 0000 0000b 2:0 11 CIRCUIT OPERATION CONDITION Immediate Fixed at 0 Default = 000 0000b 000b 001b 010b 011b =0 =3 =6 =9 Immediate Register update dB dB dB dB 100b 101b 110b 111b = 12 dB = 15 dB = 18 dB = –3 dB Immediate Default = 000b 12 26 Fixed at 0 Default = 0 0000 0000 0000b 15:3 — Reserved 1:0 OBFIL — 2 — Reserved 3 Shrink_OB — 7:4 — Reserved 12:8 HPIX level — Rejection level (LSB) = (hpix level + 1) × 128 Default = 11111b 13 HPIX enable — 0 = Disabled 1 = Enable hot pixel rejection Default = 0 15:14 — Reserved OB_loop 00 = No filter 01 = 1st-order 10 = 2nd-order Default = 00b Fixed at 0 Default = 0 0 = Shrink OB period 1 = OB period not shrunk Default = 0 Immediate Fixed at 0 Default = 0000b Fixed at 0 Default = 00b Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): VSP2590 VSP2590 www.ti.com.............................................................................................................................................................................................. SBES012 – OCTOBER 2008 Table 2. Register Definitions (continued) ADDRESS REGISTER BIT NAME DESCRIPTION CIRCUIT OPERATION CONDITION 1:0 SKIP_MODE Skip SHP/SHD/RG 0 = No skips 1 = 2 skips 2 = 4 skips Default = 00b 3:2 — Reserved Fixed at 0 Default = 00b 5:4 SKIP_DELAY — 00 = 1 clock delay 01 = 2 clock delay UPDATE TIMING 11 = 3 clock delay 10 = 4 clock delay Default = 00b 13 14 15 16 (1) H-TG skip SHPD — Reserved 8 SKIP_STOP [OB] Inactive skip mode during CLPOB 0 = Skip during OB period 1 = Do not skip during OB period Default = 1 9 SKIP_STOP [DM] Inactive skip mode during CLPDM 0 = Skip during DM period 1 = Do not skip during DM period Default = 1 11:10 — Reserved 12 En_TG H-TG enable 15:13 — Reserved 4:0 SHPA fall DLL tap select (1) 7:5 — Reserved SHP_A 12:8 SHPA rise DLL tap select 15:13 — Reserved 4:0 SHDA fall DLL tap select 7:5 — Reserved SHD_A H1_A Fixed at 0 Default = 00b 7:6 12:8 SHDA rise DLL tap select 15:13 — Reserved 4:0 H1A fall DLL tap select 7:5 — Reserved 12:8 H1A rise DLL tap select 15:13 — Reserved Immediate Fixed at 0 Default = 00b 0 = stop (mask) H1/H2/RG 1 = TG (mask circuit) active Default = 0 Fixed at 0 Default = 000b D4 = 0, TFP = tMCKP13/64 + D[3:0] × tMCKP/64 D4 = 1, TFP = tMCKP13/64 + (16 – D[3:0]) × tMCKP/64 Default = 00000b Fixed at 0 Default = 000b D12 = 0, TRP = tMCKP26/64 + D[11:8] × tMCKP/64 D12 = 1, TRP = tMCKP26/64 + (16 – D[11:8]) × tMCKP/64 Default = 00000b Register update Fixed at 0 Default = 000b D4 = 0, TFD = tMCKP27/64 + D[3:0] × tMCKP/64 D4 = 1, TFD = tMCKP27/64 + (16 – D[3:0]) × tMCKP/64 Default = 00000b Fixed at 0 Default = 000b D12 = 0, TRD = tMCKP58/64 + D[11:8] × tMCKP/64 D12 = 1, TRD = tMCKP58/64 + (16 – D[11:8]) × tMCKP/64 Default = 00000b Register update Fixed at 0 Default = 000b D4 = 0, TFH1 = tMCKP32/64 + D[3:0] × tMCKP/64 D4 = 1, TFH1 = tMCKP32/64 + (16 – D[3:0]) × tMCKP/64 Default = 00000b Fixed at 0 Default = 000b D12 = 0, TRH1 = 0 + D[11:8] × tMCKP/64 D12 = 1, TRH1 = 0 + (16 – D[11:8]) × tMCKP/64 Default = 00000b Register update Fixed at 0 Default = 000b DLL tap selection uses a binary twos complement number. Typ = 00000b, min = 10000b, and max = 01111b. Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): VSP2590 27 VSP2590 SBES012 – OCTOBER 2008.............................................................................................................................................................................................. www.ti.com Table 2. Register Definitions (continued) ADDRESS 17 18 19 20 21 22 28 REGISTER BIT NAME DESCRIPTION CIRCUIT OPERATION CONDITION 4:0 H2A fall DLL tap select D4 = 0, TFH2 = 0 + D[3:0] × tMCKP/64 D4 = 1, TFH2 = 0 + (16 – D[3:0]) × tMCKP/64 Default = 00000b 7:5 — Reserved H2_A LH_A 12:8 H2A rise DLL tap select 15:13 — Reserved 4:0 LH A fall DLL tap select 7:5 — Reserved 12:8 LH A rise DLL tap select 15:13 — Reserved 4:0 RGA fall DLL tap select 15:5 — Reserved 4:0 SHPB fall DLL tap select 7:5 — Reserved RG_A SHP_B 12:8 SHPB rise DLL tap select 15:13 — Reserved 4:0 SHDB fall DLL tap select 7:5 — Reserved SHD_B H1_B 12:8 SHDB rise DLL tap select 15:13 — Reserved 4:0 H1B fall DLL tap select 7:5 — Reserved 12:8 H1B rise DLL tap select 15:13 — Reserved Fixed at 0 Default = 000b D12 = 0, TRH2 = tMCKP32/64 + D[11:8] × tMCKP/64 D12 = 1, TRH2 = tMCKP32/64 + (16 – D[11:8]) × tMCKP/64 Default = 00000b UPDATE TIMING Register update Fixed at 0 Default = 000b D4 = 0, TFLH = tMCKP32/64 + D[3:0] × tMCKP/64 D4 = 1, TFLH = tMCKP32/64 + (16 – D[3:0]) × tMCKP/64 Default = 00000b Fixed at 0 Default = 000b D12 = 0, TRLH = 0 + D[11:8] × tMCKP/64 D12 = 1, TRLH = 0 + (16 – D[11:8]) × tMCKP/64 Default = 00000b Register update Fixed at 0 Default = 000b D4 = 0, TWR = tMCKP20/64 + D[3:0] × tMCKP/64 D4 = 1, TWR = tMCKP20/64 + (16 – D[3:0]) × tMCKP/64 Default = 00000b Register update Fixed at 0 Default = 000 0000 0000b D4 = 0, TFP = tMCKP13/64 + D[3:0] × tMCKP/64 D4 = 1, TFP = tMCKP13/64 + (16 – D[3:0]) × tMCKP/64 Default = 00000b Fixed at 0 Default = 000b D12 = 0, TRP = tMCKP26/64 + D[11:8] × tMCKP/64 D12 = 1, TRP = tMCKP26/64 + (16 – D[11:8]) × tMCKP/64 Default = 00000b Register update Fixed at 0 Default = 000b D4 = 0, TFD = tMCKP27/64 + D[3:0] × tMCKP/64 D4 = 1, TFD = tMCKP27/64 + (16 – D[3:0]) × tMCKP/64 Default = 00000b Fixed at 0 Default = 000b D12 = 0, TRD = tMCKP58/64 + D[11:8] × tMCKP/64 D12 = 1, TRD = tMCKP58/64 + (16 – D[11:8]) × tMCKP/64 Default = 00000b Register update Fixed at 0 Default = 000b D4 = 0, TFH1 = tMCKP32/64 + D[3:0] × tMCKP/64 D4 = 1, TFH1 = tMCKP32/64 + (16 – D[3:0]) × tMCKP/64 Default = 00000b Fixed at 0 Default = 000b D12 = 0, TRH1 = 0 + D[11:8] × tMCKP/64 D12 = 1, TRH1 = 0 + (16 – D[11:8]) × tMCKP/64 Default = 00000b Register update Fixed at 0 Default = 000b Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): VSP2590 VSP2590 www.ti.com.............................................................................................................................................................................................. SBES012 – OCTOBER 2008 Table 2. Register Definitions (continued) ADDRESS 23 24 25 26 27 28–47 REGISTER BIT NAME DESCRIPTION CIRCUIT OPERATION CONDITION 4:0 H2B fall DLL tap select D4 = 0, TFH2 = 0 + D[3:0] × tMCKP/64 D4 = 1, TFH2 = 0 + (16 – D[3:0]) × tMCKP/64 Default = 00000b 7:5 — Reserved H2_B LH_B 12:8 H2B rise DLL tap select 15:13 — Reserved 4:0 LH B fall DLL tap select 7:5 — Reserved 12:8 LH B rise DLL tap select 15:13 — Reserved 4:0 RGB fall DLL tap select 15:5 — Reserved RG_B 4:0 2MCLK rise DLL tap select 15:5 — Reserved 1:0 LogicCK A rise LogicCK delay 7:2 — Reserved 2MCLK LogicCK_A — Fixed at 0 Default = 000b D12 = 0, TRH2 = tMCKP32/64 + D[11:8] × tMCKP/64 D12 = 1, TRH2 = tMCKP32/64 + (16 – D[11:8]) × tMCKP/64 Default = 00000b UPDATE TIMING Register update Fixed at 0 Default = 000b D4 = 0, TFLH = tMCKP32/64 + D[3:0] × tMCKP/64 D4 = 1, TFLH = tMCKP32/64 + (16 – D[3:0]) × tMCKP/64 Default = 00000b Fixed at 0 Default = 000b D12 = 0, TRLH = 0 + D[11:8] × tMCKP/64 D12 = 1, TRLH = 0 + (16 – D[11:8]) × tMCKP/64 Default = 00000b Register update Fixed at 0 Default = 000b D4 = 0, TWR = tMCKP20/64 + D[3:0] × tMCKP/64 D4 = 1, TWR = tMCKP20/64 + (16 – D[3:0]) × tMCKP/64 Default = 00000b Register update Fixed at 0 Default = 000 0000 0000b D4 = 0, TRMCLKx2 = tMCKP13/64 + D[3:0] × tMCKP/64 D4 = 1, TRMCLKx2 = tMCKP13/64 + (16 – D[3:0]) × tMCKP/64 Default = 00000b Register update Fixed at 0 Default = 000 0000 0000b Effective when sampling clocks are supplied from the DLL Default = 00b Fixed at 0 Default = 00 0000b Effective when sampling clocks are supplied from the DLL Default = 00b 9:8 LogicCK B rise LogicCK delay 15:10 — Reserved Fixed at 0 Default = 00 0000b — — Reserved Fixed at 0 Immediate — Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): VSP2590 29 VSP2590 SBES012 – OCTOBER 2008.............................................................................................................................................................................................. www.ti.com Table 2. Register Definitions (continued) ADDRESS 48 49 50 51 52 53 54 55 56 57–63 30 REGISTER Config OBlevel 1_0_A OBlevel 1_1_A OBlevel 1_0_B OBlevel 1_1_B BIT NAME DESCRIPTION 3:0 — Reserved 4 Muxctrl[0] — 5 — Reserved 6 Muxctrl[2] — 7 — Reserved 8 CTRL_ dgain[0] Start pixel select to change digital gain 9 CTRL_ dgain[1] — 10 CTRL_ OBLEV[0] Start pixel select to change OB level 11 CTRL_ OBLEV[1] — 15:12 — Reserved 11:0 OB level 1_0_A — 15:12 — Reserved 11:0 OB level 1_1_A — 15:12 — Reserved 11:0 OB level 1_0_B — 15:12 — Reserved 11:0 OB level 1_1_B — 15:12 — Reserved 9:0 dgain0 — 15:10 — Reserved 9:0 dgain1 — 15:10 — Reserved 9:0 dgain0 — 15:10 — Reserved 9:0 dgain1 — 15:10 — Reserved Fixed at 0 Default = 00 0000b — — Reserved Fixed at 0 dgain0_A dgain1_A dgain0_B dgain1_B — CIRCUIT OPERATION CONDITION UPDATE TIMING Fixed at 0 Default = 0000b 0 = MUX is disabled (32-bit parallel output) 1 = MUX is active (16-bit parallel output) Default = 0 Fixed at 0 Default = 0 0 = Channel A first (only channel A) 1 = Channel B first (only channel B) Default = 0 Fixed at 0 Default = 0 0 = Even pixel start 1 = Odd pixel start Default = 0 Register update 0 = Use only OBlevel0 1 = Change OB level after every second pixel Default = 0 0 = Even pixel start 1 = Odd pixel start Default = 0 0 = Use only OBlevel0 1 = Change OB level after every second pixel Default = 0 Fixed at 0 Default = 0000b OB level is limited as 1536 to 3072 (LSB) Default = 1000 0000 0000b Fixed at 0 Default = 0000b OB level is limited as 1536 to 3072 (LSB) Default = 1000 0000 0000b Fixed at 0 Default = 0000b OB level is limited as 1536 to 3072 (LSB) Default = 1000 0000 0000b Fixed at 0 Default = 0000b OB level is limited as 1536 to 3072 (LSB) Default = 1000 0000 0000b Fixed at 0 Default = 0000b Digital gain (dB) = dgain0/32 Default = 00 0000 0000b Fixed at 0 Default = 00 0000b Digital gain (dB) = dgain1/32 Default = 00 0000 0000b Fixed at 0 Default = 00 0000b Digital gain (dB) = dgain0/32 Default = 00 0000 0000b Fixed at 0 Default = 00 0000b Digital gain (dB) = dgain1/32 Default = 00 0000 0000b Submit Documentation Feedback Immediate Immediate Immediate Immediate Immediate Immediate Immediate Immediate Immediate Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): VSP2590 VSP2590 www.ti.com.............................................................................................................................................................................................. SBES012 – OCTOBER 2008 Table 2. Register Definitions (continued) ADDRESS 64–95 96–127 128–255 REGISTER VCOMP0-A to VCOMP31-A VCOMP0-B to VCOMP31-B — BIT NAME DESCRIPTION CIRCUIT OPERATION CONDITION 12:0 VCOMP_POS_A Replaced pixel address for V-compensation 14:13 VCOMP_rep_A Replace address 15 — Reserved 12:0 VCOMP_POS_B Replaced pixel address for V-compensation 14:13 VCOMP_rep_B Replace address 15 — Reserved Fixed at 0 Default = 0 — — Reserved Fixed at 0 UPDATE TIMING Pixel address (LSB) Default = 0 0000 0000 0000b — Default = 00b Immediate Fixed at 0 Default = 0 Pixel address (LSB) Default = 0 0000 0000 0000b — Default = 00b Immediate Immediate Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated Product Folder Link(s): VSP2590 31 PACKAGE OPTION ADDENDUM www.ti.com 5-Jun-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty VSP2590ZWV ACTIVE NFBGA ZWV 159 348 Pb-Free (RoHS) SNAGCU Level-2-260C-1 YEAR VSP2590ZWVR ACTIVE NFBGA ZWV 159 1000 Pb-Free (RoHS) SNAGCU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Jun-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device VSP2590ZWVR Package Package Pins Type Drawing NFBGA ZWV 159 SPQ Reel Reel Diameter Width (mm) W1 (mm) 1000 330.0 16.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 7.3 7.3 2.2 12.0 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Jun-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) VSP2590ZWVR NFBGA ZWV 159 1000 342.0 336.0 34.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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