LS5911 LS5912 LS5912C IMPROVED LOW NOISE WIDEBAND MONOLITHIC DUAL N-CHANNEL JFET Linear Integrated Systems FEATURES Improved Replacement for SILICONIX, FAIRCHILD, & NATIONAL: 2N5911 & 2N5912 LOW NOISE (10kHz) en ~ 4nV/√Hz HIGH TRANSCONDUCTANCE (100MHz) gfs ≥ 4000µS G1 1 ABSOLUTE MAXIMUM RATINGS D1 @ 25 °C (unless otherwise stated) S1 3 5 1 7 2 Operating Junction Temperature G1 S2 6 Maximum Temperatures Storage Temperature TO-78 BOTTOM VIEW TO-71 BOTTOM VIEW D1 D2 5 1 7 2 S1 G2 3 SOT-23 TOP VIEW S2 6 D2 G1 D1 S1 1 6 2 5 3 4 G2 PDIP-B PDIP-A -65 to +150 °C S1 1 8 G2 S1 1 8 NC -55 to +150 °C D1 2 7 SS D1 2 7 G2 SS 3 6 D2 G1 3 6 D2 G1 4 5 S2 NC 4 5 S2 Maximum Power Dissipation Continuous Power Dissipation (Total) Maximum Currents Gate Current 50mA Maximum Voltages Gate to Drain -25V Gate to Source -25V SOIC-B SOIC-A 500mW S2 D2 G2 S1 1 8 G2 S1 1 8 NC D1 2 7 SS D1 2 7 G2 SS 3 6 D2 G1 3 6 D2 G1 4 5 S2 NC 4 5 S2 MATCHING ELECTRICAL CHARACTERISTICS @25 °C (unless otherwise stated) SYMBOL CHARACTERISTIC VGS1 − VGS2 Differential Gate to Source Cutoff Voltage Differential Gate to Source Cutoff Voltage Change with Temperature Gate to Source Saturation Current Ratio ∆ VGS1 − VGS2 ∆T IDSS1 IDSS2 IG1 − IG2 gfs1 gfs2 CMRR TYP LS5911 MIN 0.95 Differential Gate Current MIN 0.95 MAX LS5912C MIN MAX UNIT CONDITIONS 10 15 40 mV VDG = 10V, ID = 5mA 20 40 40 µV/°C VDG = 10V, ID = 5mA TA = -55 to +125°C 1 % VDS = 10V, VGS = 0V 20 nA VDG = 10V, ID = 5mA TA = +125°C 1 % VDS = 10V, ID = 5mA f = 1kHz dB VDG = 5V to 10V ID = 5mA 1 0.95 20 Forward Transconductance Ratio2 Common Mode Rejection Ratio MAX LS5912 1 1 0.95 20 0.95 1 0.95 85 STATIC ELECTRICAL CHARACTERISTICS @25 °C (unless otherwise stated) SYM. CHARACTERISTIC TYP LS5911 MIN MAX LS5912 MIN MAX -25 LS5912C MIN MAX BVGSS Gate to Source Breakdown Voltage -25 VGS(off) Gate to Source Cutoff Voltage -1 -5 -1 -5 -1 -5 VGS(F) Gate to Source Forward Voltage -0.3 -4 -0.3 -4 -0.3 -4 7 40 7 40 7 40 -25 CONDITIONS IG = -1µA, VDS = 0V 0.7 VGS Gate to Source Voltage IDSS Drain to Source Saturation Current3 IGSS Gate Leakage Current -1 -50 -50 -50 IG Gate Operating Current -1 -50 -50 -50 Linear Integrated Systems UNIT V VDS = 10V, ID = 1nA IG = 1mA, VDS = 0V VDG = 10V, IG = 5mA mA pA VDS = 10V, VGS = 0V VGS = -15V, VDS = 0V VDG = 10V, ID = 5mA • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261 DYNAMIC ELECTRICAL CHARACTERISTICS @25 °C (unless otherwise stated) SYM. CHARACTERISTIC Forward Transconductance gfs gos LS5911 TYP Output Conductance MIN 4000 10000 4000 10000 4000 10000 100 100 100 f = 100MHz 150 150 150 NF Noise Figure en Equivalent Input Noise Voltage 5 1.2 1 1 1 dB 20 nV/√Hz f = 10kHz 4 10 10 10 nV/√Hz VDG = 10V, ID = 5mA f = 10kHz, RG = 100KΩ VDG = 10V, ID = 5mA f = 100Hz VDG = 10V, ID = 5mA f = 10kHz PDIP TO-78 Six Lead 0.230 DIA. 0.209 0.195 DIA. 0.175 0.35 0.50 0.030 MAX. 2.80 3.00 0.150 0.115 4 0.500 MIN. 0.019 DIA. 0.016 0.305 0.335 DIMENSIONS IN MILLIMETERS 0.046 0.036 0.100 5 6 0.028 0.034 0.048 0.028 1 8 NC 7 SS D1 2 7 G2 3 6 D2 G1 3 6 D2 4 5 S2 NC 4 5 S2 2 SS G1 5 0.295 0.320 SOIC 0.100 S1 D1 6 4 45° G2 8 3 DIMENSIONS IN INCHES 2 3 5 1 76 7 SOIC-B SOIC-A 0.100 0.375 0.145 0.170 0.014 0.018 PDIP-B 1 7 0.250 0.029 0.045 PDIP-A S1 8 2 SEATING PLANE 2 3 1 1 MIN. 0.500 0.200 0.09 0.20 45° 0.060 MAX. 0.040 0.165 0.038 0.185 0.016 0.021 DIM. B 0.100 0.10 0.60 0.335 0.370 0.016 0.019 DIM. A 0.050 1. VDG = 10V, ID = 5mA f = 1MHz 5 1.2 20 1.50 1.75 2.60 3.00 0.00 0.15 pF 5 20 6 LEADS 0.90 1.30 VDG = 10V, ID = 5mA 1.2 TO-71 CONDITIONS µS 7 0.95 3 UNIT f = 100Hz SOT-23 5 MAX f = 1kHz Input Capacitance 2 MIN f = 100MHz Reverse Transfer Capacitance 1.90 LS5912C MAX 4000 10000 4000 10000 4000 10000 Ciss 6 MIN f = 1kHz Crss 1 LS5912 MAX S1 1 8 G2 S1 1 8 NC D1 2 7 SS D1 2 7 G2 SS 3 6 D2 G1 3 6 D2 G1 4 5 S2 NC 4 5 S2 0.021 1 8 2 7 3 6 4 5 0.150 0.157 0.0075 0.0098 0.050 0.189 0.196 0.0040 0.0098 0.2284 0.2440 DIMENSIONS IN INCHES Please contact the factory regarding the availability of optional packages. Absolute maximum ratings are limiting values above which serviceability may be impaired. 2. Pulse Test: PW ≤ 300µs Duty Cycle ≤ 3% 3. Assumes smaller value in numerator. Information furnished by Linear Integrated Systems is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems. Linear Integrated Systems • 4042 Clipper Court • Fremont, CA 94538 • Tel: 510 490-9160 • Fax: 510 353-0261