MX29F004T/B
4M-BIT [512KX8] CMOS FLASH MEMORY
FEATURES
• 524,288 x 8 only
• Single power supply operation
- 5.0V only operation for read, erase and program
operation
• Fast access time: 70/90/120ns
• Low power consumption
- 30mA maximum active current(5MHz)
- 1uA typical standby current
• Command register architecture
- Byte Programming (7us typical)
- Sector Erase
(Sector structure:16KB/8KB/8KB/32KB and 64KBx7)
• Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors
with Erase Suspend capability.
- Automatically program and verify data at specified
address
• Erase suspend/Erase Resume
•
•
•
•
•
•
•
•
- Suspends an erase operation to read data from,
or program data to, another sector that is not being
erased, then resumes the erase.
Status Reply
- Data polling & Toggle bit for detection of program
and erase cycle completion.
Chip protect/unprotect for 5V only system or 5V/
12V system.
100,000 minimum erase/program cycles
Latch-up protected to 100mA from -1V to VCC+1V
Low VCC write inhibit is equal to or less than 3.2V
Package type:
- 32-pin PLCC, TSOP or PDIP
Compatibility with JEDEC standard
- Pinout and software compatible with single-power
supply Flash
20 years data retention
GENERAL DESCRIPTION
The MX29F004T/B is a 4-mega bit Flash memory
organized as 512K bytes of 8 bits. MXIC's Flash
memories offer the most cost-effective and reliable read/
write non-volatile random access memory. The
MX29F004T/B is packaged in 32-pin PLCC, TSOP,
PDIP. It is designed to be reprogrammed and erased in
system or in standard EPROM programmers.
during erase and programming, while maintaining
maximum EPROM compatibility.
The standard MX29F004T/B offers access time as fast
as 70ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus
contention, the MX29F004T/B has separate chip enable
(CE) and output enable (OE ) controls.
MXIC Flash technology reliably stores memory
contents even after 100,000 erase and program
cycles. The MXIC cell is designed to optimize the
erase and programming mechanisms. In addition,
the combination of advanced tunnel oxide
processing and low internal electric fields for erase
and program operations produces reliable cycling.
The MX29F004T/B uses a 5.0V±10% VCC supply
to perform the High Reliability Erase and auto
Program/Erase algorithms.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29F004T/B uses a command register to manage this
functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels
The highest degree of latch-up protection is
achieved with MXIC's proprietary non-epi process.
Latch-up protection is proved for stresses up to
100 milliamps on address and data pin from -1V to
VCC + 1V.
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REV. 1.4, JUN. 12, 2001
1
MX29F004T/B
PIN CONFIGURATIONS
A7
4
32
A17
1
WE
VCC
5
A18
A12
VCC
WE
A17
A14
A13
A8
A9
A11
OE
A10
CE
Q7
Q6
Q5
Q4
Q3
30
29
A14
A6
A13
A5
A8
A4
A3
A9
MX29F004T/B
9
25
A11
A2
OE
A1
A10
A0
CE
21
20
Q5
Q4
Q3
17
Q7
Q6
13
14
GND
Q0
Q1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Q2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MX29F004T/B
A18
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
GND
A16
32 PLCC
A15
32 PDIP
32 TSOP (Standard Type) (8mm x 20mm)
A11
A9
A8
A13
A14
A17
WE
VCC
A18
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MX29F004T/B
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
Q7
Q6
Q5
Q4
Q3
GND
Q2
Q1
Q0
A0
A1
A2
A3
PIN DESCRIPTION
SYMBOL
A0~A18
Q0~Q7
CE
WE
OE
GND
VCC
PIN NAME
Address Input
Data Input/Output
Chip Enable Input
Write Enable Input
Output Enable Input
Ground Pin
+5.0V single power supply
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REV. 1.4, JUN. 12, 2001
2
MX29F004T/B
SECTOR STRUCTURE
MX29F004T TOP BOOT SECTOR ADDRESS TABLE
Sector Size
Address Range (in hexadecimal)
Sector
A18
A17
A16
A15
A14
A13
(Kbytes)
(x8) Address Range
SA0
0
0
0
X
X
X
64
00000h-0FFFFh
SA1
0
0
1
X
X
X
64
10000h-1FFFFh
SA2
0
1
0
X
X
X
64
20000h-2FFFFh
SA3
0
1
1
X
X
X
64
30000h-3FFFFh
SA4
1
0
0
X
X
X
64
40000h-4FFFFh
SA5
1
0
1
X
X
X
64
50000h-5FFFFh
SA6
1
1
0
X
X
X
64
60000h-6FFFFh
SA7
1
1
1
0
X
X
32
70000h-77FFFh
SA8
1
1
1
1
0
0
8
78000h-79FFFh
SA9
1
1
1
1
0
1
8
7A000h-7BFFFh
SA10
1
1
1
1
1
X
16
7C000h-7FFFFh
MX29F004B BOTTEM BOOT SECTOR ADDRESS TABLE
Sector Size
Address Range (in hexadecimal)
Sector
A18
A17
A16
A15
A14
A13
(Kbytes)
(x8) Address Range
SA0
0
0
0
0
0
X
16
00000h-03FFFh
SA1
0
0
0
0
1
0
8
04000h-05FFFh
SA2
0
0
0
0
1
1
8
06000h-07FFFh
SA3
0
0
0
1
X
X
32
08000h-0FFFFh
SA4
0
0
1
X
X
X
64
10000h-1FFFFh
SA5
0
1
0
X
X
X
64
20000h-2FFFFh
SA6
0
1
1
X
X
X
64
30000h-3FFFFh
SA7
1
0
0
X
X
X
64
40000h-4FFFFh
SA8
1
0
1
X
X
X
64
50000h-5FFFFh
SA9
1
1
0
X
X
X
64
60000h-6FFFFh
SA10
1
1
1
X
X
X
64
70000h-7FFFFh
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REV. 1.4, JUN. 12, 2001
3
MX29F004T/B
BLOCK DIAGRAM
WRITE
CE
OE
WE
CONTROL
PROGRAM/ERASE
STATE
INPUT
LOGIC
HIGH VOLTAGE
MACHINE
(WSM)
LATCH
A0-A18
BUFFER
FLASH
REGISTER
ARRAY
ARRAY
Y-DECODER
AND
X-DECODER
ADDRESS
STATE
MX29F004T/B
Y-PASS GATE
SOURCE
HV
COMMAND
DATA
DECODER
SENSE
AMPLIFIER
PGM
DATA
HV
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
Q0-Q7
I/O BUFFER
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4
MX29F004T/B
AUTOMATIC PROGRAMMING
AUTOMATIC ERASE ALGORITHM
The MX29F004T/B is byte programmable using the
Automatic Programming algorithm. The Automatic
Programming algorithm makes the external system do
not need to have time out sequence nor to verify the data
programmed. The typical chip programming time at room
temperature of the MX29F004T/B is less than 4 seconds.
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using standard
microprocessor write timings. The device will
automatically pre-program and verification the entire
array. Then the device automatically times the erase
pulse width, provides the erase verify, and counts the
number of sequences. A status bit toggling between
consecutive read cycles provides feedback to the user
as to the status of the programming operation.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 10 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at room temperature is accomplished in
less than 4 second. The Automatic Erase algorithm
automatically programs the entire array prior to electrical
erase. The timing and verification of electrical erase are
controlled internally within the device.
Register contents serve as inputs to an internal statemachine which controls the erase and programming
circuitry. During write cycles, the command register
internally latches address and data needed for the
programming and erase operations. During a system
write cycle, addresses are latched on the falling edge of
WE or CE, whicheven happens later, and data are
latched on the rising edge of WE or CE, whicheven
happens first.
AUTOMATIC SECTOR ERASE
The MX29F004T/B is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. Sector erase modes
allow sectors of the array to be erased in one erase
cycle. The Automatic Sector Erase algorithm
automatically programs the specified sector(s) prior to
electrical erase. The timing and verification of
electrical erase are controlled internally within the
device.
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality,
reliability, and cost effectiveness. The MX29F004T/B
electrically erases all bits simultaneously using FowlerNordheim tunneling. The bytes are programmed by
using the EPROM programming mechanism of hot
electron injection.
AUTOMATIC PROGRAMMING ALGORITHM
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command register
to respond to its full command set.
MXIC's Automatic Programming algorithm requires the
user to only write program set-up commands (including 2
unlock write cycle and A0H) and a program command
(program data and address). The device automatically
times the programming pulse width, provides the program
verification, and counts the number of sequences. A
status bit similar to DATA polling and a status bit toggling
between consecutive read cycles, provide feedback to
the user as to the status of the programming operation.
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REV. 1.4, JUN. 12, 2001
5
MX29F004T/B
TABLE1. SOFTWARE COMMAND DEFINITIONS
Command
First Bus
Second Bus
Third Bus
Fourth Bus
Fifth Bus
Sixth Bus
Bus
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Cycle
Addr
Data
Addr
Data
Addr
Data
Addr
Data
90H
ADI
DDI
00H
Addr
Data
Addr
Data
Reset
1
XXXH
F0H
Read
1
RA
RD
Read Silicon ID
4
555H
AAH
2AAH 55H
555H
Chip Protect Verify
4
555H
AAH
2AAH 55H
555H 90H
SA
x02
01H
Porgram
4
555H
AAH
2AAH 55H
555H
A0H
PA
PD
Chip Erase
6
555H
AAH
2AAH 55H
555H
80H
555H AAH
2AAH 55H
555H 10H
Sector Erase
6
555H
AAH
2AAH 55H
555H
80H
555H AAH
2AAH 55H
SA
Sector Erase Suspend
1
XXXH
B0H
Sector Erase Resume
1
XXXH
30H
Unlock for chip
6
555H
AAH
2AAH 55H
555H 80H
555H AAH
2AAH 55H
555H 20H
30H
protect/unprotect
Note:
1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacture code,A1=0, A0 =1 for device code A2~A18=Do not care.
(Refer to table 3)
DDI = Data of Device identifier : C2H for manufacture code, 45H/46H for device code.
X = X can be VIL or VIH
RA=Address of memory location to be read.
RD=Data to be read at location RA.
2. PA = Address of memory location to be programmed.
PD = Data to be programmed at location PA.
SA = Address to the sector to be erased.
3. The system should generate the following address patterns: 555H or 2AAH to Address A10~A0.
Address bit A11~A18=X=Don't care for all address commands except for Program Address (PA) and Sector Address (SA).
Write Sequence may be initiated with A11~A18 in either state.
4. For Chip Protect Verify Operation :If read out data is 01H, it means the chip has been protected.If read out data is 00H, it means
the chip is still not being protected.
COMMAND DEFINITIONS
Device operations are selected by writing specific address
and data sequences into the command register. Writing
incorrect address and data values or writing them in the
improper sequence will reset the device to the read mode.
Table 1 defines the valid register command sequences.
Note that the Erase Suspend (B0H) and Erase Resume
(30H) commands are valid only while the Sector Erase
operation is in progress. Either of the two reset command
sequences will reset the device(when applicable).
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6
MX29F004T/B
TABLE 2. MX29F004T/B BUS OPERATION
Mode
Pins
CE
OE
WE
A0
A1
A6
A9
Q0 ~ Q7
L
L
H
L
L
X
VID(2)
C2H
L
L
H
H
L
X
VID(2)
45H/46H
Read
L
L
H
A0
A1
A6
A9
DOUT
Standby
H
X
X
X
X
X
X
HIGH Z
Output Disable
L
H
H
X
X
X
X
HIGH Z
Write
L
H
L
A0
A1
A6
A9
DIN(3)
Chip Protect with 12V
L
VID(2)
L
X
X
L
VID(2)
X
L
VID(2)
L
X
X
H
VID(2)
X
L
L
H
X
H
X
VID(2)
Code(5)
L
H
L
X
X
L
H
X
L
H
L
X
X
H
H
X
L
L
H
X
H
X
H
Code(5)
X
X
X
X
X
X
X
HIGH Z
Read Silicon ID
Manfacturer Code(1)
Read Silicon ID
Device Code(1)
system(6)
Chip Unprotect with 12V
system(6)
Verify Chip Protect
with 12V system
Chip Protect without 12V
system (6)
Chip Unprotect without 12V
system (6)
Verify Chip Protect/Unprotect
without 12V system (7)
Reset
NOTES:
1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1.
2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.
3. Refer to Table 1 for valid Data-In during a write operation.
4. X can be VIL or VIH.
5. Code=00H means unprotected.
Code=01H means protected.
6. Refer to chip protect/unprotect algorithm and waveform.
Must issue "unlock for chip protect/unprotect" command before "chip protect/unprotect without 12V system" command.
7. The "verify chip protect/unprotect without 12V sysytem" is only following "Chip protect/unprotect without 12V system"
command.
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7
MX29F004T/B
READ/RESET COMMAND
SET-UP AUTOMATIC CHIP/SECTOR ERASE
The read or reset operation is initiated by writing the
read/reset command sequence into the command
register. Microprocessor read cycles retrieve array
data. The device remains enabled for reads until the
command register contents are altered.
Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command 80H. Two more "unlock" write cycles
are then followed by the chip erase command 10H.
The Automatic Chip Erase does not require the device
to be entirely pre-programmed prior to executing the
Automatic Chip Erase. Upon executing the Automatic
Chip Erase, the device will automatically program and
verify the entire memory for an all-zero data pattern.
When the device is automatically verified to contain an
all-zero pattern, a self-timed chip erase and verify begin.
The erase and verify operations are completed when the
data on Q7 is "1" at which time the device returns to the
Read mode. The system is not required to provide any
control or timing during these operations.
If program-fail or erase-fail happen, the write of F0H will
reset the device to abort the operation. A valid command
must then be written to place the device in the desired
state.
SILICON-ID-READ COMMAND
Flash memories are intended for use in applications
where the local CPU alters memory contents. As such,
manufacturer and device codes must be accessible
while the device resides in the target system. PROM
programmers typically access signature codes by raising
A9 to a high voltage. However, multiplexing high voltage
onto address lines is not generally desired system
design practice.
When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array(no
erase verification command is required).
The MX29F004T/B contains a Silicon-ID-Read operation
to supplement traditional PROM programming
methodology. The operation is initiated by writing the
read silicon ID command sequence into the command
register. Following the command write, a read cycle with
A1=VIL,A0=VIL retrieves the manufacturer code of C2H.
A read cycle with A1=VIL, A0=VIH returns the device
code of 45H/46H for MX29F004T/B.
If the Erase operation was unsuccessful, the data on Q5
is "1"(see Table 4), indicating the erase operation exceed
internal timing limit.
The automatic erase begins on the rising edge of the last
WE or CE, whicheven happens first pulse in the command
sequence and terminates when the data on Q7 is "1" and
the data on Q6 stops toggling for two consecutive read
cycles, at which time the device returns to the Read
mode.
TABLE 3. EXPANDED SILICON ID CODE
Pins
A0
A1
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Code(Hex)
Manufacture code
VIL
VIL
1
1
0
0
0
0
1
0
C2H
Device code for MX29F004T
VIH
VIL
0
1
0
0
0
1
0
1
45H
Device code for MX29F004B
VIH
VIL
0
1
0
0
0
1
1
0
46H
X
VIH
0
0
0
0
0
0
0
1
01H(Protected)
X
VIH
0
0
0
0
0
0
0
0
00H(Unprotected)
Chip Protection Verification
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8
MX29F004T/B
SECTOR ERASE COMMANDS
memory array (no erase verifIcation command is
required). Sector erase is a six-bus cycle operation.
There are two "unlock" write cycles. These are
followed by writing the set-up command 80H. Two
more "unlock" write cycles are then followed by the
sector erase command 30H. The sector address is
latched on the falling edge of WE or CE, whicheven
happens later, while the command(data) is latched on
the rising edge of WE or CE, whicheven happens first.
Sector addresses selected are loaded into internal
register on the sixth falling edge of WE or CE,
whicheven happens later. Each successive sector load
cycle started by the falling edge of WE or CE,
whicheven happens later must begin within 30us from
the rising edge of the preceding WE or CE, whicheven
happens first. Otherwise, the loading period ends and
internal auto sector erase cycle starts. (Monitor Q3 to
determine if the sector erase timer window is still
open, see section Q3, Sector Erase Timer.) Any
command other than Sector Erase(30H) or Erase
Suspend(B0H) during the time-out period resets the
device to read mode.
The Automatic Sector Erase does not require the
device to be entirely pre-programmed prior to
executing the Automatic Set-up Sector Erase
command and Automatic Sector Erase command.
Upon executing the Automatic Sector Erase
command, the device will automatically program and
verify the sector(s) memory for an all-zero data
pattern. The system is not required to provide any
control or timing during these operations.
When the sector(s) is automatically verified to contain
an all-zero pattern, a self-timed sector erase and
verify begin. The erase and verify operations are
complete when the data on Q7 is "1" and the data on
Q6 stops toggling for two consecutive read cycles, at
which time the device returns to the Read mode. The
system is not required to provide any control or timing
during these operations.
When using the Automatic Sector Erase algorithm,
note that the erase automatically terminates when
adequate erase margin has been achieved for the
Table 4. Write Operation Status
Status
Q7
Q6
Note1
Byte Program in Auto Program Algorithm
Auto Erase Algorithm
Erase Suspend Read
In Progress
Erase Suspend Read
Q3
Q2
Note2
Q7
Toggle
0
N/A
No Toggle
0
Toggle
0
1
Toggle
1
No
0
N/A
Toggle
(Erase Suspended Sector)
Erase Suspended Mode
Q5
Toggle
Data
Data
Data
Data
Data
Q7
Toggle
0
N/A
N/A
Q7
Toggle
1
N/A
No Toggle
0
Toggle
1
1
Toggle
Q7
Toggle
1
N/A
N/A
(Non-Erase Suspended Sector)
Erase Suspend Program
Byte Program in Auto Program Algorithm
Exceeded
Auto Erase Algorithm
Time Limits Erase Suspend Program
Note:
1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.
2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.
See "Q5:Exceeded Timing Limits " for more information.
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9
MX29F004T/B
ERASE SUSPEND
If the program opetation was unsuccessful, the data on
Q5 is "1"(see Table 4), indicating the program operation
exceed internal timing limit. The automatic programming
operation is completed when the data read on Q6 stops
toggling for two consecutive read cycles and the data on
Q7 and Q6 are equivalent to data written to these two
bits, at which time the device returns to the Read
mode(no program verify command is required).
This command only has meaning while the state machine
is executing Automatic Sector Erase operation, and
therefore will only be responded during Automatic Sector
Erase operation. When the Erase Suspend command is
written during a sector erase operation, the device requires
a maximum of 100us to suspend the erase operations.
However, When the Erase Suspend command is written
during the sector erase time-out, the device immediately
terminates the time-out period and suspends the erase
operation. After this command has been executed, the
command register will initiate erase suspend mode. The
state machine will return to read mode automatically after
suspend is ready. At this time, state machine only allows
the command register to respond to the Read Memory
Array, Erase Resume and program commands.
DATA POLLING-Q7
The MX29F004T/B also features Data Polling as a
method to indicate to the host system that the Automatic
Program or Erase algorithms are either in progress or
completed.
While the Automatic Programming algorithm is in
operation, an attempt to read the device will produce the
complement data of the data last written to Q7. Upon
completion of the Automatic Program Algorithm an
attempt to read the device will produce the true data last
written to Q7. The Data Polling feature is valid after the
rising edge of the fourth WE or CE, whicheven happens
first pulse of the four write pulse sequences for automatic
program.
The system can determine the status of the program
operation using the Q7 or Q6 status bits, just as in the
standard program operation. After an erase-suspend
program operation is complete, the system can once
again read array data within non-suspended sectors.
ERASE RESUME
This command will cause the command register to clear
the suspend state and return back to Sector Erase mode
but only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all
other conditions.Another Erase Suspend command can
be written after the chip has resumed erasing.
While the Automatic Erase algorithm is in operation, Q7
will read "0" until the erase operation is competed. Upon
completion of the erase operation, the data on Q7 will
read "1". The Data Polling feature is valid after the rising
edge of the sixth WE or CE, whicheven happens first
pulse of six write pulse sequences for automatic chip/
sector erase.
SET-UP AUTOMATIC PROGRAM
COMMANDS
The Data Polling feature is active during Automatic
Program/Erase algorithm or sector erase time-out.(see
section Q3 Sector Erase Timer)
To initiate Automatic Program mode, A three-cycle
command sequence is required. There are two "unlock"
write cycles. These are followed by writing the Automatic
Program command A0H.
Once the Automatic Program command is initiated, the
next WE or CE pulse causes a transition to an active
programming operation. Addresses are latched on the
falling edge, and data are internally latched on the rising
edge of the WE or CE, whicheven happens first pulse.
The rising edge of WE or CE, whicheven happens first
also begins the programming operation. The system is
not required to provide further controls or timings. The
device will automatically provide an adequate internally
generated program pulse and verify margin.
P/N:PM0554
REV. 1.4, JUN. 12, 2001
10
MX29F004T/B
Q6:Toggle BIT I
Q2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The
system may use either OE or CE to control the read
cycles.) But Q2 cannot distinguish whether the sector is
actively erasing or is erase-suspended. Q6, by
comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish
which sectors are selected for erasure. Thus, both
status bits are required for sectors and mode information.
Refer to Table 4 to compare outputs for Q2 and Q6.
Toggle Bit I on Q6 indicates whether an Automatic
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE or CE,
whicheven happens first pulse in the command
sequence(prior to the program or erase operation), and
during the sector time-out.
During an Automatic Program or Erase algorithm
operation, successive read cycles to any address cause
Q6 to toggle. The system may use either OE or CE to
control the read cycles. When the operation is complete,
Q6 stops toggling.
Reading Toggle Bits Q6/ Q2
Whenever the system initially begins reading toggle bit
status, it must read Q7-Q0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system
can read array data on Q7-Q0 on the following read
cycle.
After an erase command sequence is written, if the chip
has been protected, Q6 toggles and returns to reading
array data.
The system can use Q6 and Q2 together to determine
whether a sector is actively erasing or is erase suspended.
When the device is actively erasing (that is, the Automatic
Erase algorithm is in progress), Q6 toggling. When the
device enters the Erase Suspend mode, Q6 stops
toggling. However, the system must also use Q2 to
determine which sectors are erasing or erase-suspended.
Alternatively, the system can use Q7.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system
also should note whether the value of Q5 is high (see the
section on Q5). If it is, the system should then determine
again whether the toggle bit is toggling, since the toggle
bit may have stopped toggling just as Q5 went high. If
the toggle bit is no longer toggling, the device has
successfuly completed the program or erase operation.
If it is still toggling, the device did not complete the
operation successfully, and the system must write the
reset command to return to reading array data.
If a program address falls within a protected sector, Q6
toggles for approximately 2us after the program command
sequence is written, then returns to reading array data.
Q6 also toggles during the erase-suspend-program
mode, and stops toggling once the Automatic Program
algorithm is complete.
The remaining scenario is that system initially determines
that the toggle bit is toggling and Q5 has not gone high.
The system may continue to monitor the toggle bit and
Q5 through successive read cycles, determining the
status as described in the previous paragraph.
Alternatively, it may choose to perform other system
tasks. In this case, the system must start at the beginning
of the algorithm when it returns to determine the status
of the operation.
Table 4 shows the outputs for Toggle Bit I on Q6.
Q2:Toggle Bit II
The "Toggle Bit II" on Q2, when used with Q6, indicates
whether a particular sector is actively eraseing (that is,
the Automatic Erase alorithm is in process), or whether
that sector is erase-suspended. Toggle Bit I is valid after
the rising edge of the final WE or CE, whicheven
happens first pulse in the command sequence.
P/N:PM0554
REV. 1.4, JUN. 12, 2001
11
MX29F004T/B
with its control register architecture, alteration of the
memory contents only occurs after successful completion
of specific command sequences. The device also
incorporates several features to prevent inadvertent
write cycles resulting from VCC power-up and powerdown transition or system noise.
Q5
Exceeded Timing Limits
Q5 will indicate if the program or erase time has exceeded
the specified limits(internal pulse count). Under these
conditions Q5 will produce a "1". This time-out condition
indicates that the program or erase cycle was not
successfully completed. Data Polling and Toggle Bit are
the only operating functions of the device under this
condition.
Q3
Sector Erase Timer
After the completion of the initial sector erase command
sequence, the sector erase time-out will begin. Q3 will
remain low until the time-out is complete. Data Polling
and Toggle Bit are valid after the initial sector erase
command sequence.
If this time-out condition occurs during sector erase
operation, it specifies that a particular sector is bad and
it may not be reused. However, other sectors are still
functional and may be used for the program or erase
operation. The device must be reset to use other
sectors. Write the Reset command sequence to the
device, and then execute program or erase command
sequence. This allows the system to continue to use the
other active sectors in the device.
If Data Polling or the Toggle Bit indicates the device has
been written with a valid erase command, Q3 may be
used to determine if the sector erase timer window is still
open. If Q3 is high ("1") the internally controlled erase
cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or
Toggle Bit. If Q3 is low ("0"), the device will accept
additional sector erase commands. To insure the
command has been accepted, the system software
should check the status of Q3 prior to and following each
subsequent sector erase command. If Q3 were high on
the second status check, the command may not have
been accepted.
If this time-out condition occurs during the chip erase
operation, it specifies that the entire chip is bad or
combination of sectors are bad.
If this time-out condition occurs during the byte
programming operation, it specifies that the entire sector
containing that byte is bad and this sector maynot be
reused, (other sectors are still functional and can be
reused).
WRITE PULSE "GLITCH" PROTECTION
The time-out condition may also appear if a user tries to
program a non blank location without erasing. In this
case the device locks out and never completes the
Automatic Algorithm operation. Hence, the system
never reads a valid data on Q7 bit and Q6 never stops
toggling. Once the Device has exceeded timing limits,
the Q5 bit will indicate a "1". Please note that this is not
a device failure condition since the device was incorrectly
used.
Noise pulses of less than 5ns(typical) on CE or WE will
not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE = VIL, CE
= VIH or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
DATA PROTECTION
POWER SUPPLY DECOUPLING
The MX29F004T/B is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power
transition. During power up the device automatically
resets the state machine in the Read mode. In addition,
In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected
between its VCC and GND.
P/N:PM0554
REV. 1.4, JUN. 12, 2001
12
MX29F004T/B
CHIP PROTECTION WITH 12V SYSTEM
POWER-UP SEQUENCE
The MX29F004T/B features chip protection, which will
disable both program and erase operations. To activate
this mode, the programming equipment must force VID
on address pin A9 and control pin OE, (suggest VID=12V)
A6=VIL and CE=VIL.(see Table 2) Programming of the
protection circuitry begins on the falling edge of the WE
or CE, whicheven happens later pulse and is terminated
on the rising edge. Please refer to chip protect algorithm
and waveform.
The MX29F004T/B powers up in the Read only mode. In
addition, the memory contents may only be altered after
successful completion of the predefined command
sequences.
CHIP PROTECTION WITHOUT 12V SYSTEM
The MX29F004T/B also feature a chip protection method
in a system without 12V power suppply. The programming
equipment do not need to supply 12 volts to protect all
sectors. The details are shown in chip protect algorithm
and waveform.
To verify programming of the protection circuitry, the
programming equipment must force VID on address pin
A9 ( with CE and OE at VIL and WE at VIH). When A1=1,
it will produce a logical "1" code at device output Q0 for
the protected status. Otherwise the device will produce
00H for the unprotected status. In this mode, the
addresses, except for A1, are don't care. Address
locations with A1 = VIL are reserved to read manufacturer
and device codes.(Read Silicon ID)
CHIP UNPROTECT WITHOUT 12V SYSTEM
The MX29F004T/B also feature a chip unprotection
method in a system without 12V power supply. The
programming equipment do not need to supply 12 volts
to unprotect all sectors. The details are shown in chip
unprotect algorithm and waveform.
It is also possible to determine if chip is protected in the
system by writing a Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
a logical "1" at Q0 for the protected status.
CHIP UNPROTECT WITH 12V SYSTEM
The MX29F004T/B also features the chip unprotect
mode, so that all sectors are unprotected after chip
unprotect is completed to incorporate any changes in
the code.
To activate this mode, the programming equipment
must force VID on control pin OE and address pin A9.
The CE pins must be set at VIL. Pins A6 must be set to
VIH.(see Table 2) Refer to chip unprotect algorithm and
waveform for the chip unprotect algorithm. The
unprotection mechanism begins on the falling edge of
the WE or CE, whicheven happens later pulse and is
terminated on the rising edge.
It is also possible to determine if the chip is unprotected
in the system by writing the Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
00H at data outputs(Q0-Q7) for an unprotected sector.
It is noted that all sectors are unprotected after the chip
unprotect algorithm is completed.
P/N:PM0554
REV. 1.4, JUN. 12, 2001
13
MX29F004T/B
CAPACITANCE (TA = 25oC, f = 1.0 MHz)
SYMBOL
PARAMETER
CIN1
MIN.
TYP
MAX.
UNIT
CONDITIONS
Input Capacitance
8
pF
VIN = 0V
CIN2
Control Pin Capacitance
12
pF
VIN = 0V
COUT
Output Capacitance
12
pF
VOUT = 0V
READ OPERATION
DC CHARACTERISTICS (TA = 0° C TO 70° C, VCC = 5V±10%)
SYMBOL
PARAMETER
MIN.
TYP
MAX.
UNIT
CONDITIONS
ILI
Input Leakage Current
1
uA
VIN = GND to VCC
ILO
Output Leakage Current
10
uA
VOUT = GND to VCC
ISB1
Standby VCC current
1
mA
CE = VIH
5
uA
CE = VCC + 0.3V
ISB2
ICC1
1
Operating VCC current
ICC2
30
mA
IOUT = 0mA, f=5MHz
50
mA
IOUT = 0mA, f=10MHz
VIL
Input Low Voltage
-0.3(NOTE 1)
0.8
V
VIH
Input High Voltage
2.0
VCC + 0.3
V
0.45
VOL
Output Low Voltage
V
IOL = 2.1mA
VOH1
Output High Voltage(TTL)
2.4
V
IOH = -2mA
VOH2
Output High Voltage(CMOS)
Vcc-0.4
V
IOH = -100uA,VCC=VCC min
NOTES:
1. VIL min. = -1.0V for pulse width is equal to or less than 50
2. VIH max. = VCC + 1.5V for pulse width is equal to or less
ns.
than 20 ns
VIL min. = -2.0V for pulse width is equal to or less than 20
If VIH is over the specified maximum value, read operation
ns.
cannot be guaranteed.
±10%)
AC CHARACTERISTICS (TA = 0oC to 70oC, VCC = 5V±
29F004T/B-70
SYMBOL PARAMETER
MIN.
MAX.
29F004T/B-90
MIN.
MAX.
29F004T/B-12
MIN.
MAX.
UNIT CONDITIONS
tACC
Address to Output Delay
70
90
120
ns
CE=OE=VIL
tCE
CE to Output Delay
70
90
120
ns
OE=VIL
tOE
OE to Output Delay
40
40
50
ns
CE=VIL
tDF
OE High to Output Float (Note1)
0
40
ns
CE=VIL
tOH
Address to Output hold
0
ns
CE=OE=VIL
30
0
0
40
0
0
TEST CONDITIONS:
NOTE:
• Input pulse levels: 0.45V/2.4V
1. tDF is defined as the time at which the output achieves the
• Input rise and fall times is equal to or less than 10ns
open circuit condition and data is no longer driven.
• Output load: 1 TTL gate + 100pF (Including scope and jig)
• Reference levels for measuring timing: 0.8V, 2.0V
P/N:PM0554
REV. 1.4, JUN. 12, 2001
14
MX29F004T/B
ABSOLUTE MAXIMUM RATINGS
RATING
VALUE
Ambient Operating Temperature
0oC to 70oC
Storage Temperature
-65oC to 125oC
Applied Input Voltage
-0.5V to 7.0V
Applied Output Voltage
-0.5V to 7.0V
VCC to Ground Potential
-0.5V to 7.0V
A9 & OE
-0.5V to 13.5V
NOTICE:
Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended period may affect reliability.
NOTICE:
Specifications contained within the following tables are
subject to change.
READ TIMING WAVEFORMS
VIH
ADD Valid
Addresses
VIL
tCE
VIH
CE
VIL
WE
VIH
VIL
OE
VIH
tACC
VIL
Outputs
tDF
tOE
VOH
tOH
HIGH Z
HIGH Z
DATA Valid
VOL
COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION
±10%)
DC CHARACTERISTICS (TA = 0oC to 70oC, VCC = 5V±
SYMBOL
PARAMETER
ICC1 (Read)
Operating VCC Current
MIN.
TYP
MAX.
UNIT
CONDITIONS
30
mA
IOUT=0mA, f=5MHz
ICC2
50
mA
IOUT=0mA, F=10MHz
ICC3 (Program)
50
mA
In Programming
ICC4 (Erase)
50
mA
In Erase
mA
CE=VIH, Erase Suspended
ICCES
VCC Erase Suspend Current
2
NOTES:
1. VIL min. = -0.6V for pulse width is equal to or less than 20ns.
3. ICCES is specified with the device de-selected. If the
2. If VIH is over the specified maximum value, programming
device is read during erase suspend mode, current draw is
operation cannot be guranteed.
the sum of ICCES and ICC1 or ICC2.
4. All current are in RMS unless otherwise noted.
P/N:PM0554
REV. 1.4, JUN. 12, 2001
15
MX29F004T/B
AC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V ± 10%
29F004T/B-70
MIN.
MAX.
29F004T/B-90
MIN.
SYMBOL
PARAMETER
tOES
OE setup time
50
50
50
ns
tCWC
Command programming cycle
70
90
120
ns
tCEP
WE programming pulse width
45
45
50
ns
tCEPH1
WE programming pluse width High
20
20
20
ns
tCEPH2
WE programming pluse width High
20
20
20
ns
tAS
Address setup time
0
0
0
ns
tAH
Address hold time
45
45
50
ns
tDS
Data setup time
30
45
50
ns
tDH
Data hold time
0
0
0
ns
tCESC
CE setup time before command write
0
0
0
ns
tDF
Output disable time (Note 1)
tAETC
Total erase time in auto chip erase
4(TYP.)
tAETB
Total erase time in auto sector erase
1.3(TYP.) 10.4
1.3(TYP.) 10.4
1.3(TYP.) 10.4
s
tAVT
Total programming time in auto verify
7
7
7
us
tBAL
Sector address load time
100
100
100
us
tCH
CE Hold Time
0
0
0
ns
30
32
210
MAX.
29F004T/B-12
MIN.
40
4(TYP.)
32
210
4(TYP.)
MAX.
UNIT
40
ns
32
s
210
tCS
CE setup to WE going low
0
0
0
ns
tVLHT
Voltge Transition Time
4
4
4
us
tOESP
OE Setup Time to WE Active
4
4
4
us
tWPP1
Write pulse width for chip protect
10
10
10
us
tWPP2
Write pulse width for chip unprotect
12
12
12
ms
NOTES:
1. tDF defined as the time at which the output achieves the
open circuit condition and data is no longer driven.
P/N:PM0554
REV. 1.4, JUN. 12, 2001
16
MX29F004T/B
SWITCHING TEST CIRCUITS
DEVICE UNDER
1.6K ohm
+5V
TEST
CL
1.2K ohm
DIODES=IN3064
OR EQUIVALENT
CL=100pF Including jig capacitance
SWITCHING TEST WAVEFORMS
2.4V
2.0V
2.0V
TEST POINTS
0.8V
0.8V
0.45V
INPUT
OUTPUT
AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0".
Input pulse rise and fall times are <20ns.
COMMAND WRITE TIMING WAVEFORM
VCC
Addresses
5V
VIH
ADD Valid
VIL
tAH
tAS
WE
VIH
VIL
tOES
tCEPH1
tCEP
tCWC
CE
VIH
VIL
tCS
OE
tCH
VIH
VIL
tDS
tDH
VIH
Data
DIN
VIL
P/N:PM0554
REV. 1.4, JUN. 12, 2001
17
MX29F004T/B
AUTOMATIC PROGRAMMING TIMING WAVEFORM
bit checking after automatic verification starts. Device
outputs DATA during programming and DATA after
programming on Q7.(Q6 is for toggle bit; see toggle bit,
DATA polling, timing waveform)
One byte data is programmed. Verify in fast algorithm
and additional programming by external control are not
required because these operations are executed
automatically by internal control circuit. Programming
completion can be verified by DATA polling and toggle
AUTOMATIC PROGRAMMING TIMING WAVEFORM
Vcc 5V
A11~A18
A0~A10
ADD Valid
2AAH
555H
tAS
WE
ADD Valid
555H
tCWC
tAH
tCEPH1
tCESC
tAVT
CE
tCEP
OE
tDS
Q0,Q1,Q2
tDH
Command In
tDF
Command In
Command In
Data In
DATA
DATA polling
Q4(Note 1)
Q7
Command In
Command #AAH
Command In
Command In
Command #55H
Command #A0H
DATA
Data In
DATA
tOE
(Q0~Q7)
Notes:
(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit
P/N:PM0554
REV. 1.4, JUN. 12, 2001
18
MX29F004T/B
AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data A0H Address 555H
Write Program Data/Address
Toggle Bit Checking
Q6 not Toggled
NO
YES
.
Invalid
Command
NO
Verify Byte Ok
YES
NO
Q5 = 1
Auto Program Completed
YES
Reset
Auto Program Exceed
Timing Limit
P/N:PM0554
REV. 1.4, JUN. 12, 2001
19
MX29F004T/B
AUTOMATIC CHIP ERASE TIMING WAVEFORM
All data in chip are erased. External erase verification is
not required because data is erased automatically by
internal control circuit. Erasure completion can be
verified by DATA polling and toggle bit checking after
automatic erase starts. Device outputs 0 during erasure
and 1 after erasure on Q7.(Q6 is for toggle bit; see toggle
bit, DATA polling, timing waveform)
AUTOMATIC CHIP ERASE TIMING WAVEFORM
Vcc 5V
A11~A18
A0~A10
2AAH
555H
555H
555H
tAS
WE
2AAH
555H
tCWC
tAH
tCEPH1
tAETC
CE
tCEP
OE
tDS tDH
Q0,Q1,
Command In
Command In
Command In
Command In
Command In
Command In
Q4(Note 1)
Q7
DATA polling
Command In
Command In
Command In
Command In
Command In
Command In
Command #AAH
Command #55H
Command #80H
Command #AAH
Command #55H
Command #10H
(Q0~Q7)
Notes:
(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit
P/N:PM0554
REV. 1.4, JUN. 12, 2001
20
MX29F004T/B
AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 10H Address 555H
Toggle Bit Checking
Q6 not Toggled
NO
YES
Invalid
Command
NO
DATA Polling
Q7 = 1
YES
NO
.
Q5 = 1
Auto Chip Erase Completed
YES
Reset
Auto Chip Erase Exceed
Timing Limit
P/N:PM0554
REV. 1.4, JUN. 12, 2001
21
MX29F004T/B
AUTOMATIC SECTOR ERASE TIMING WAVEFORM
checking after automatic erase starts. Device outputs 0
during erasure and 1 after erasure on Q7.(Q6 is for toggle
bit; see toggle bit, DATA polling, timing waveform)
Sector data indicated by A13 to A18 are erased. External
erase verify is not required because data are erased
automatically by internal control circuit. Erasure completion can be verified by DATA polling and toggle bit
AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Vcc 5V
Sector
Address0
A13~A18
A0~A10
555H
2AAH
555H
555H
Sector
Address1
Sector
Addressn
2AAH
tAS
tCWC
tAH
WE
tCEPH1
tBAL
tAETB
CE
tCEP
OE
tDS tDH
Q0,Q1,
Command
In
Command
In
Command
In
Command
In
Command
In
Command
In
Command
In
Command
In
Q4(Note 1)
Q7
DATA polling
Command
In
Command
In
Command
In
Command
In
Command
In
Command
In
Command #AAH Command #55H Command #80H Command #AAH Command #55H Command #30H
(Q0~Q7)
Command
In
Command #30H
Command
In
Command #30H
Notes:
(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit
P/N:PM0554
REV. 1.4, JUN. 12, 2001
22
MX29F004T/B
AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 30H Sector Address
Toggle Bit Checking
Q6 Toggled ?
NO
Invalid Command
YES
Load Other Sector Addrss If Necessary
(Load Other Sector Address)
NO
Last Sector
to Erase
YES
Time-out Bit
Checking Q3=1 ?
NO
YES
Toggle Bit Checking
Q6 not Toggled
NO
YES
NO
Q5 = 1
DATA Polling
Q7 = 1
YES
Reset
Auto Sector Erase Completed
Auto Sector Erase Exceed
Timing Limit
P/N:PM0554
REV. 1.4, JUN. 12, 2001
23
MX29F004T/B
ERASE SUSPEND/ERASE RESUME FLOWCHART
START
Write Data B0H
NO
Toggle Bit checking Q6
not toggled
YES
Read Array or
Program
Reading or
Programming End
NO
YES
Write Data 30H
Continue Erase
Another
Erase Suspend ?
NO
YES
P/N:PM0554
REV. 1.4, JUN. 12, 2001
24
MX29F004T/B
TIMING WAVEFORM FOR CHIP PROTECTION FOR SYSTEM WITH 12V
A1
A6
12V
5V
A9
tVLHT
Verify
12V
5V
OE
tVLHT
tVLHT
tWPP 1
WE
tOESP
CE
Data
01H
F0H
tOE
P/N:PM0554
REV. 1.4, JUN. 12, 2001
25
MX29F004T/B
TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITH 12V
A1
12V
5V
A9
tVLHT
A6
Verify
12V
5V
OE
tVLHT
tVLHT
tWPP 2
WE
tOESP
CE
Data
00H
F0H
tOE
P/N:PM0554
REV. 1.4, JUN. 12, 2001
26
MX29F004T/B
CHIP PROTECTION ALGORITHM FOR SYSTEM WITH 12V
START
PLSCNT=1
OE=VID,A9=VID,CE=VIL
A6=VIL
Activate WE Pulse
Time Out 10us
Set WE=VIH, CE=OE=VIL
A9 should remain VID
Read Data with A1=1
No
PLSCNT=32?
No
Data=01H?
Yes
Yes
Remove VID from A9
Write Reset Command
Device Failed
Chip Protection
Complete
P/N:PM0554
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MX29F004T/B
TIMING WAVEFORM FOR CHIP PROTECTION FOR SYSTEM WITHOUT 12V
A1
A6
Toggle bit polling
Verify
5V
OE
tCEP
WE
* See the following Note!
CE
Data
Don't care
(Note 2)
01H
F0H
tOE
Note: 1. Must issue "unlock for sector protect/unprotect" command
before chip protection for a system without 12V provided.
2. Except F0H
P/N:PM0554
REV. 1.4, JUN. 12, 2001
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MX29F004T/B
TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITHOUT 12V
A1
A6
Toggle bit polling
Verify
5V
OE
tCEP
WE
* See the following Note!
CE
Data
Don't care
(Note 2)
00H
F0H
tOE
Note: 1. Must issue "unlock for sector protect/unprotect" command
before chip unprotection for a system without 12V provided.
2. Except F0H
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REV. 1.4, JUN. 12, 2001
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MX29F004T/B
CHIP PROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V
START
PLSCNT=1
Write "unlock for chip protect/unprotect"
Command(Table1)
OE=VIH, A9=VIH
CE=VIL, A6=VIL
Activate WE Pulse to start
Data don't care
.
Toggle bit checking
Q6 not Toggled
No
Yes
Increment PLSCNT
Set CE=OE=VIL
A9=VIH
Read Data from chip,
A1=1
No
PLSCNT=32?
No
Data=01H?
Yes
Write Reset Command
Device Failed
Chip Protection
Complete
P/N:PM0554
REV. 1.4, JUN. 12, 2001
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MX29F004T/B
CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V
START
PLSCNT=1
Write "unlock for chip protect/unprotect"
Command (Table 1)
Set OE=A9=VIH
CE=VIL, A6=1
Active WE Pulse to start
Data don't care
No
Increment
PLSCNT
Toggle bit checking
Q6 not Toggled
Yes
Set OE=CE=VIL,
A9=VIH, A1=1
No
Read Data from Device
Data=00H?
No
Yes
PLSCNT=1000?
Yes
Device Failed
Write Reset Command
Chip Unprotect
Complete
P/N:PM0554
REV. 1.4, JUN. 12, 2001
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MX29F004T/B
ID CODE READ TIMING WAVEFORM
VCC
5V
ADD
VID
VIH
A9
VIL
ADD
A0
VIH
A1
VIH
VIL
tACC
tACC
VIL
ADD
A2-A8
A10-A18
CE
VIH
VIL
VIH
VIL
WE
VIH
tCE
VIL
OE
VIH
tOE
VIL
tDF
tOH
tOH
VIH
DATA
Q0-Q7
DATA OUT
DATA OUT
VIL
45H/46H
C2H
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REV. 1.4, JUN. 12, 2001
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MX29F004T/B
ORDERING INFORMATION
PLASTIC PACKAGE
(Top Boot Sector as an example, For Bottom Boot Sector ones, MX29F004TXX will be changed to MX29F004Bxx)
PART NO.
ACCESS
OPERATING CURRENT
STANDBY CURRENT
PACKAGE
TIME (ns)
MAX.(mA)
MAX.(uA)
MX29F004TQC-70
70
30
5
32 Pin PLCC
MX29F004TQC-90
90
30
5
32 Pin PLCC
MX29F004TQC-12
120
30
5
32 Pin PLCC
MX29F004TTC-70
70
30
5
32 Pin TSOP
MX29F004TTC-90
90
30
5
(Normal Type)
32 Pin TSOP
(Normal Type)
MX29F004TTC-12
120
30
5
32 Pin TSOP
MX29F004TPC-70
70
30
5
32 Pin PDIP
MX29F004TPC-90
90
30
5
32 Pin PDIP
MX29F004TPC-12
120
30
5
32 Pin PDIP
(Normal Type)
P/N:PM0554
REV. 1.4, JUN. 12, 2001
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MX29F004T/B
ERASE AND PROGRAMMING PERFORMANCE(1)
LIMITS
TYP.(2)
MAX.(3)
UNITS
1.3
10.4
sec
Chip Erase Time
4
32
sec
Byte Programming Time
7
210
us
Chip Programming Time
4
12
sec
PARAMETER
MIN.
Sector Erase Time
Erase/Program Cycles
Note:
100,000
Cycles
1.Not 100% Tested, Excludes external system level over head.
2.Typical values measured at 25°C,5V.
3.Maximum values measured at 25°C,4.5V.
LATCHUP CHARACTERISTICS
MIN.
MAX.
Input Voltage with respect to GND on all pins except I/O pins
-1.0V
13.5V
Input Voltage with respect to GND on all I/O pins
-1.0V
Vcc + 1.0V
-100mA
+100mA
MIN.
UNIT
20
Years
Current
Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time.
DATA RETENTION
PARAMETER
Data Retention Time
P/N:PM0554
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MX29F004T/B
PACKAGE INFORMATION
32-PIN PLASTIC DIP
P/N:PM0554
REV. 1.4, JUN. 12, 2001
35
MX29F004T/B
32-PIN PLASTIC LEADED CHIP CARRIER (PLCC)
P/N:PM0554
REV. 1.4, JUN. 12, 2001
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MX29F004T/B
32-PIN PLASTIC TSOP
P/N:PM0554
REV. 1.4, JUN. 12, 2001
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MX29F004T/B
REVISION HISTORY
Revision
Description
Page
Date
1.0
To remove "Advanced Information" datasheet marking and
contain information on products in full production.
To improve ICC1 spec:from 40mA @5MHz to 30mA @5MHz
1.Program/erase cycle times:10K cycles-->100K cycles
2.To add data retention minimum 20 years
3.To modify timing of sector address loading period while
operating multi-sector erase from 80us to 30us
4.To modify tBAL from 80us to 100us
5.To remove A9 from "timing waveform for sector protection for
system without 12V"
To remove A9 from "timing waveform for chip unprotection for
system without 12V"
Add erase suspend ready max. 100us in ERASE SUSPEND's
section at page 10
To modify "Package Information"
P1
JUL/01/1999
P1,14,15,33
P1,34
P1,34
P9
JUL/12/1999
DEC/20/1999
1.1
1.2
1.3
1.4
P/N:PM0554
P16
P28
P29
P10
MAY/30/2000
P35~37
JUN/12/2001
REV. 1.4, JUN. 12, 2001
38
MX29F004T/B
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-6688
FAX:+886-3-563-2888
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TEL:+32-2-456-8020
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FAX:+65-348-8096
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FAX:+1-408-453-8488
CHICAGO OFFICE:
TEL:+1-847-963-1900
FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
39