INDEX
ADVANCED INFORMATION
MX29F022T/B
2M-BIT[256K x 8]CMOS FLASH MEMORY
FEATURES
• 262,144x 8 only
• Fast access time: 70/90/120ns
• Low power consumption
•
•
•
•
• Status Reply
•
-30mA maximum active current
-1µA typical standby current
Programming and erasing voltage 5V±10%
Command register architecture
-Byte Programming (7us typical)
-Block Erase (16K-Byte x1, 8K-Byte x 2, 32K-Byte
x1, and 64K-Byte x 3)
Auto Erase (chip & block) and Auto Program
-Automatically erase any combination of sectors or
the whole chip with Erase Suspend capability.
-Automatically programs and verifies data atspecified
address
Erase Suspend/Erase Resume
-Suspends an erase operation to read data from,
or program data to, a sector that is not being erased,
then resumes the erase operation.
•
•
•
•
•
•
-Data polling & Toggle bit for detection of program and
erase cycle completion.
Chip protect/unprotect for 5V only system or 5V/12V
system
100,000 minimum erase/program cycles
Latch-up protected to 100mA from -1 to VCC+1V
Boot Code Sector Architecture
-T = Top Boot Sector
-B = Bottom Boot Sector
Hardware RESET pin
-Resets internal state machine to read mode
Low VCC write inhibit is equal to or less than 3.2V
Package type:
-32-pin PDIP
-32-pin PLCC
-32-pin TSOP (Type 1)
GENERAL DESCRIPTION
The MX29F022T/B is a 2-mega bit Flash memory
organized as 256K bytes of 8 bits only. MXIC's Flash
memories offer the most cost-effective and reliable read/
write non-volatile random access memory.The
MX29F022T/B is packaged in 32-pin PDIP, PLCC and
32-pin TSOP(I). It is designed to be reprogrammed and
erased in-system or in-standard EPROM programmers.
MXIC's Flash technology reliably stores memory
contents even after 100,000 erase and program cycles.
The MXIC cell is designed to optimize the erase and
programming mechanisms. In addition, the combination of advanced tunnel oxide processing and low
internal electric fields for erase and programming
operations produces reliable cycling. The MX29F022T/
B uses a 5.0V ± 10% VCC supply to perform the High
Reliability Erase and auto Program/Erase algorithms.
The standard MX29F022T/B offers access time as fast
as 70ns, allowing operation of high-speed microproc
essors without wait states. To eliminate bus contention,
the MX29F022T/B has separate chip enable (CE) and
output enable (OE) controls.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up
protection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29F022T/B uses a command register to manage this
functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining
maximum EPROM compatibility.
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INDEX
MX29F022T/B
32 TSOP (TYPE 1)
PIN CONFIGURATIONS
32 PDIP
RESET
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
GND
VCC
WE
A17
A14
A13
A8
A9
A11
OE
A10
CE
Q7
Q6
Q5
Q4
Q3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
MX29F022T/B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A11
A9
A8
A13
A14
A17
WE
VCC
RESET
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
MX29F022T/B
OE
A10
CE
Q7
Q6
Q5
Q4
Q3
GND
Q2
Q1
Q0
A0
A1
A2
A3
(NORMAL TYPE)
A7
32
BLOCK STRUCTURE
A17
1
WE
VCC
A16
4
RESET
5
A15
A12
32 PLCC
30
29
A6
A13
A5
A8
A4
A9
A3
MX29F022T/B
9
25
A17~A0
3FFFFH
A14
3BFFFH
A11
OE
A1
A10
37FFFH
A0
CE
2FFFFH
Q5
Q4
Q3
VSS
Q7
K-BYTE
8
K-BYTE
32
K-BYTE
64
K-BYTE
64
K-BYTE
64
K-BYTE
1FFFFH
Q6
21
20
17
Q2
Q1
13
14
8
39FFFH
A2
Q0
16 K-BYTE
(BOOT SECTOR)
0FFFFH
00000H
MX29F022T Sector Architecture
PIN DESCRIPTION:
A17~A0
SYMBOL
PIN NAME
A0~A17
Address Input
Q0~Q7
Data Input/Output
3FFFFH
K-BYTE
64
K-BYTE
64
K-BYTE
32
K-BYTE
8
K-BYTE
8
K-BYTE
1FFFFH
CE
Chip Enable Input
WE
Write Enable Input
0FFFFH
RESET
Hardware Reset Pin/Sector Protect Unlock
07FFFH
OE
Output Enable Input
05FFFH
VCC
Power Supply Pin (+5V)
GND
64
2FFFFH
03FFFH
Ground Pin
00000H
16 K-BYTE
(BOOT SECTOR)
MX29F022B Sector Architecture
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MX29F022T/B
Block Diagram
WRITE
CONTROL
CE
OE
WE
RESET
STATE
INPUT
HIGH VOLTAGE
LOGIC
MACHINE
(WSM)
LATCH
BUFFER
STATE
MX29F022T/B
REGISTER
FLASH
ARRAY
Y-DECODER
AND
X-DECODER
ADDRESS
A0-A17
PROGRAM/ERASE
ARRAY
SOURCE
HV
Y-PASS GATE
SENSE
AMPLIFIER
PGM
DATA
HV
COMMAND
DATA
DECODER
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
Q0-Q7
I/O BUFFER
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MX29F022T/B
AUTOMATIC PROGRAMMING
AUTOMATIC ERASE ALGORITHM
The MX29F022T/B is byte programmable using the
Automatic Programming algorithm. The Automatic
Programming algorithm does not require the system to
time out or verify the data programmed. The typical chip
programming time of the MX29F022T/B at room temperature is less than 2 seconds.
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using standard microprocessor write timings. The device will automatically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,
verifily the erase, and counts the number of sequences.
A status bit similar to DATA polling and status bit toggling between consecutive read cycles prodvides feedback to the user as to the status of the programming
operation.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 10ms erase pulses
according to MXIC's High Reliability Chip Erase
algorithm. Typical erasure at room temperature is
accomplished in less than two second. The device is
erased using the Automatic Erase algorithm. The
Automatic Erase algorithm automatically programs the
entire array prior to electrical erase. The timing and
verification of electrical erase are internally controlled
within the device.
AUTOMATIC BLOCK ERASE
Commands are written to the command register using
standard microprocessor write timings. Register contents serve as inputs to an internal state-machine which
controls the erase and programming circuitry. During
write cycles, the command register internally latches
address and data needed for the programming and erase
operations. During a system write cycle addresses are
latched on the falling edge, and data are latched on the
rising edge of WE .
The MX29F022T/B is block(s) erasable using MXIC's
Auto Block Erase algorithm. Block erase modes allow
blocks of the array to be erased in one erase cycle. The
Automatic Block Erase algorithm automatically programs
the specified block(s) prior to electrical erase. The
timing and verification of electrical erase are internally
controlled by the device.
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, reliability, and cost effectiveness. The MX29F022T/B electrically erases all bits simultaneously using FowlerNordheim tunneling. The bytes are programmed one
byte at a time using the EPROM programming mechanism of hot electron injection.
AUTOMATIC PROGRAMMING ALGORITHM
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is completed,
the device stays in read mode. After the state machine
has completed its task, it will allow the command register to respond to its full command set.
MXIC's Automatic Programming algorithm requires the
user to only write a program set-up commands (include
2 unlock arite cycle and A0H) include 2 unlock arite cycle
and A0H and a program command (program data and
address). The device automatically times the programming pulse width, verifies the program verification, and
counts the number of sequences. A status bit similar to
DATA polling and a status bit toggling between consecutive read cycles, provides feedback to the user as to the
status of the programming operation.
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INDEX
MX29F022T/B
Table 1 Softwave Command Definitions
Command
Reset/Read
Reset/Read
Read Silicon ID
Chip Protect Verify
Porgram
Chip Erase
Sector Erase
Sector Erase Suspend
Sector Erase Resume
Unlock for chip
protect/unprotect
First Bus
Bus Cycle
Cycle Addr Data
1
XXXH F0H
4
555H AAH
4
555H AAH
4
555H AAH
4
6
6
1
1
6
555H
555H
555H
XXXH
XXXH
555H
AAH
AAH
AAH
B0H
30H
AAH
Second Bus Third Bus
Fourth Bus Fifth Bus
Sixth Bus
Cycle
Cycle
Cycle
Cycle
Cycle
Addr Data Addr Data Addr Data Addr Data Addr Data
2AAH 55H
2AAH 55H
2AAH 55H
2AAH 55H
2AAH 55H
2AAH 55H
555H F0H RA
555H 90H ADI
555H 90H SA
x02
555H A0H PA
555H 80H 555H
555H 80H 555H
RD
DDI
00H
01H
PD
AAH 2AAH 55H 555H 10H
AAH 2AAH 55H SA
30H
2AAH 55H
555H 80H
AAH 2AAH 55H 555H 20H
555H
Note:
1. ADI = Address of Device identifier; A1=0,A0 =0 for manufacture code,A1=0, A0 =1 for device code (Refer to Table 3).
DDI = Data of Device identifier : C2H for manufacture code, 36H/37H for device code.
X = X can be VIL or VIH
RA=Address of memory location to be read.
RD=Data to be read at location RA.
2. PA = Address of memory location to be programmed.
PD = Data to be programmed at location PA.
SA = Address to the sector to be erased.
3. The system should generate the following address patterns: 555H or 2AAH to Address A0~A10.
Address bit A11~A17=X=Don't care for all address commands except for Program Address (PA) and Sector
Address (SA). Write Sequence may be initiated with A11~A17 in either state.
4. For Chip Protect Verify operation:If read out data is 01H, it means the chip has been protected. If read out data is 00H,
it means the chip is still not being protected.
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INDEX
MX29F022T/B
TABLE 2. MX29F022T/B BUS OPERATION
Pins
Mode
Read Silicon ID
Manfacturer Code(1)
Read Silicon ID
Device Code(1)
Read
Standby
Output Disable
Write
Chip Protect with 12V
system(6)
Chip Unprotect with 12V
system(6)
Verify chip Protect
Code(5)
with 12V system
Chip Protect without 12V
system (6)
Chip Unprotect without 12V
system (6)
Verify Chip Protect/Unprotect
without 12V system (7)
Reset
CE
OE
WE
A0
A1
A6
A9
Q0~Q7
L
L
H
L
L
X
VID(2)
C2H
L
L
H
H
L
X
VID(2)
36H/37H
L
H
L
L
L
L
X
H
H
VID(2)
H
X
H
L
L
A0
X
X
A0
X
A1
X
X
A1
X
A6
X
X
A6
L
A9
X
X
A9
VID(2)
DOUT
HIGH Z
HIGH Z
DIN(3)
X
L
VID(2)
L
X
X
H
VID(2)
X
L
L
H
X
H
X
VID(2)
L
H
L
X
X
L
H
X
L
H
L
X
X
H
H
X
L
L
H
X
H
X
H
Code(5)
X
X
X
X
X
X
X
HIGH Z
NOTES:
1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1.
2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.
3. Refer to Table 1 for valid Data-In during a write operation.
4. X can be VIL or VIH.
5. Code=00H means unprotected.
Code=01H means protected.
6. Refer to chip protect/unprotect algorithm and waveform.
Must issue "unlock for chip protect/unprotect" command before "chip protect/unprotect without 12V system" command.
7. The "verify chip protect/unprotect without 12V sysytem" is only following "chip protect/unprotect without 12V system"
command.
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MX29F022T/B
READ/RESET COMMAND
SET-UP AUTOMATIC CHIP/BLOCK ERASE
COMMANDS
The read or reset operation is initiated by writing the
read/reset command sequence into the command register. Microprocessor read cycles retrieve array data.
The device remains enabled for reads until the command
register contents are altered.
Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command 80H. Two more "unlock" write cycles are then followed by the chip erase command 10H.
The Automatic Chip Erase does not require the device
to be entirely pre-programmed prior to executing the Automatic Chip Erase. Upon executing the Automatic Chip
Erase, the device will automatically program and verify
the entire memory for an all-zero data pattern. When
the device is automatically verified to contain an all-zero
pattern, a self-timed chip erase and verification begin.
The erase and verification operations are completed
when the data on Q7 is "1" at which time the device
returns to the Read mode. The system is not required
to provide any control or timing during these operations.
If program-fail or erase-fail happen, the write of F0H will
reset the device to abort the operation. A valid command must then be written to place the device in the
desired state.
SILICON-ID-READ COMMAND
Flash memories are intended for use in applications
where the local CPU alters memory contents. As such,
manufacturer and device codes must be accessible while
the device resides in the target system. PROM programmers typically access signature codes by raising
A9 to a high voltage. However, multiplexing high voltage onto address lines is not generally desired system
design practice.
When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array(no
erase verify command is required).
The MX29F022T/B contains a Silicon-ID-Read operation to supplement traditional PROM programming methodology. The operation is initiated by writing the read
silicon ID command sequence into the command register. Following the command write, a read cycle with
A1=VIL, A0=VIL retrieves the manufacturer code of C2H.
A read cycle with A1=VIL, A0=VIH returns the device
code of 36H for MX29F022T,37H for MX29F022B.
If the Erase operation was unsuccessful, the data on
Q5 is "1"(see Table 4), indicating the erase operation of
exceed internal timing limit.
The automatic erase begins on the rising edge of the
last WE pulse in the command sequence and terminates
when the data on Q7 is "1" and the data on Q6 stops
toggling for two consecutive read cycles, at which time
the device returns to the Read mode.
TABLE 3. EXPANDED SILICON ID CODE
Pins
Manufacture code
Device code
for MX29F022T
Device code
for MX29F022B
Chip Protection Verification
A0
A1
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Code(Hex)
VIL
VIH
VIL
VIL
1
1
1
0
0
1
0
1
0
0
0
0
1
0
0
0
C2H
36H
VIH
VIL
0
0
1
1
0
1
0
0
37H
X
X
VIH
VIH
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
01H (Protected)
00H (Unprotected)
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INDEX
MX29F022T/B
of WE. Block addresses selected are loaded into
internal register on the sixth falling edge of WE. Each
successive block load cycle started by the falling edge
of WE must begin within 30ms from the rising edge of
the preceding WE. Otherwise, the loading period ends
and internal auto block erase cycle starts. (Monitor Q3
to determine if the sector erase timer window is still open,
see section Q3, Sector Erase Timer.) Any command
other than Block Erase (30H) or Erase Suspend (B0H)
during the time-out period resets the device to read
mode.
SET-UP AUTOMATIC BLOCK ERASE
COMMANDS
The Automatic Block Erase does not require the device
to be entirely pre-programmed prior to executing the
Automatic Set-up Block Erase command and Automatic
Block Erase command. Upon executing the Automatic
Block Erase command, the device will automatically
program and verify the block(s) memory for an all-zero
data pattern. The system does not require to provide
any control or timing during these operations.
When the block(s) is automatically verified to contain an
all-zero pattern,a self-timed block erase and verification
begin. The erase and verification operations are
complete when the data on Q7 is "1" and the data on Q6
stops toggling for two consecutive read cycles, at which
time the device returns to the Read mode. The system
does not required to provide any control or timing
during these operations.
ERASE SUSPEND
This command is only valid while the state machine is
executing Automatic Block Erase operation, and
therefore will only be responded during Automatic/Block
Erase operation. Writing the Erase Suspend command
during the Block Erase time-out immediately terminates
the time-out period and suspends the erase operation.
After this command has been executed, the command
register will initiate erase suspend mode. The state
machine will return to read mode automatically after
suspend is ready. At this time, state machine only
allows the command register to respond to the Read
Memory Array, Erase Resume and Program commands.
The system can determine the status of the program
operation using the Q7 or Q6 status bits, just as in the
standard program operation. After an erase-suspendend
program operation is complete, the system can once
again read array data within non-suspended blocks.
When using the Automatic Block Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array
(no erase verification command is required). Sector
erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
set-up command-80H. Two more "unlock" write cycles
are then followed by the sector erase command-30H.
The sector address is latched on the falling edge of WE,
while the command(data) is latched on the rising edge
Table 4. Write Operation Status
Mode
Standard Mode
Auto Program Algorithm
Auto Erase Algorithm
Exceed Time Limits Auto Program
Auto Sector/Chip Erase
Erase Suspend Mode Reading within Erase Suspended
Sector
Reading within Non-Erase
Suspended Sector
Earse-Suspend-Program
Q7
(Note 1)
Q7
0
Q7
0
1
Q6
Toggle
Toggle
Toggle
Toggle
No toggle
Q5
(Note 2)
0
0
1
1
0
Q3
N/A
1
0
0
N/A
Q2
(Note 1)
No Toggle
Toggle
No Toggle
N/A
Toggle
Data
Data
Data
Data
Data
Q7
Toggle
0
N/A
N/A
Note:
1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for
further details.
2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.
See "Q5:Exceeded Timing Limits " for more information.
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MX29F022T/B
While the Automatic Erase algorithm is in operation, Q7
will read "0" until the erase operation is compete. Upon
completion of the erase operation, the data on Q7 will
read "1". The Data Polling feature is valid after the rising
edge of the secone WE pulse of two write pulse sequences.
ERASE RESUME
This command will cause the command register to clear
the suspend state and return back to Sector Erase mode
but only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all
other conditions.Another Erase Suspend command can
be written after the chip has resumed erasing.
The Data Polling feature is active during Automatic Program/Erase algorithm or sector erase time-out.(see section Q3 Sector Erase Timer)
SET-UP AUTOMATIC PROGRAM COMMANDS
To initiate Automatic Program mode, A three-cycle command sequence is required. There are two "unlock" write
cycles. These are followed by writing the Automatic Program command A0H.
Q6:Toggle BIT I
The MX29F022T/B features a "Toggle Bit" as a method
to indicate to the host system that the Auto Program/
Erase algorithms are either in progress or complete.
Once the Automatic Program command is initiated, the
next WE pulse causes a transition to an active programming operation. Addresses are latched on the falling
edge, and data are internally latched on the rising
edge of the WE pulse. The rising edge of WE also begins the programming operation. The system does not
require to provide further controls or timings. The device will automatically provide an adequate internally
generated program pulse and verify margin.
During an Automatic Program or Erase algorithm operation, successive read cycles to any address cause
Q6 to toggle. The system may use either OE or CE to
control the read cycles. When the operation is complete,
Q6 stops toggling.
After an erase command sequence is written, if the chip
is protected, Q6 toggles and returns to reading array
data.
If the program opetation was unsuccessful, the data on
Q5 is "1", indicating the program operation of internally
exceed timing limit. The automatic programming operation is complete when the data read on Q6 stops toggling for two consecutive read cycles and the data on
Q7 and Q6 are equivalent to data written to these two
bits, at which time the device returns to the Read
mode(no program verify command is required).
WRITE OPERATION STATUS DATA POLLING-Q7
The system can use Q6 and Q2 together to determine
whether a sector is actively erasing or is erase suspended. When the device is actively erasing (that is, the
Automatic Erase algorithm is in progress), Q6 toggling.
When the device enters the Erase Suspend mode, Q6
stops toggling. However, the system must also use Q2
to determine which sectors are erasing or erase-suspended. Alternatively, the system can use Q7(see the
subsection on Q7:Data Polling).
The MX29F022T/B also features Data Polling as a
method to indicate to the host system that the Automatic
Program or Erase algorithms are either in progress or
completed.
If a program address falls within a protected sector, Q6
toggles for approximately 2us after the program command sequence is written, then returns to reading array
data.
While the Automatic Programming algorithm is in
operation, an attempt to read the device will produce
the complement data of the data last written to Q7. Upon
completion of the Automatic Program Algorithm an
attempt to read the device will produce the true data last
written to Q7. The Data Polling feature is valid after the
rising edge of the second WE pulse of the two write pulse
sequences.
Q6 also toggles during the erase-suspend-program
mode, and stops toggling once the Automatic Program
algorithm is complete.
The Write Operation Status table shows the outputs for
Toggle Bit I on Q6. Refer to the toggle bit algorithmg.
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INDEX
MX29F022T/B
Q5 through successive read cycles, determining the
status as described in the previous paragraph.
Alternatively, it may choose to perform other system
tasks. In this case, the system must start at the
beginning of the algorithm when it returns to determine
the status of the operation(top of the toggle bit algorithm
flow chart).
Q2:Toggle Bit II
The "Toggle Bit II" on Q2, when used with Q6, indicates
whether a particular sector is actively eraseing (that is,
the Automatic Erase alorithm is in process), or whether
that sector is erase-suspended. Toggle Bit I is valid after
the rising edge of the final WE pulse in the command
sequence.
Q5
Q2 toggles when the system reads at addresses within
those sectors that have been selected for erasure. (The
system may use either OE or CE to control the read
cycles.) But Q2 cannot distinguish whether the sector
is actively erasing or is erase-suspended. Q6, by
comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish
which sectors are selected for erasure. Thus, both
status bits are required for sectors and mode
information. Refer to Table 4 to compare outputs for Q2
and Q6.
Exceeded Timing Limits
Q5 will indicate if the program or erase time has
exceeded the specified limits(internal pulse count).
Under these conditions Q5 will produce a "1". This
time-out e condition indicates that the program or erase
cycle was not successfully completed. Data Polling and
Toggle Bit are the only operating functions not of the
device under this condition.
If this time-out condition occurs during sector erase
operation, it specifies that a particular sector is bad and
it may not be reused. However, other sectors are still
functional and may be used for the program or erase
operation. The device must be reset to use other
sectors. Write the Reset command sequence to the
device, and then execute program or erase command
sequence. This allows the system to continue to use
the other active sectors in the device.
Reading Toggle Bits Q6/ Q2
Refer to the toggle bit algorithm for the following
discussion. Whenever the system initially begins
reading toggle bit status, it must read Q7-Q0 at least
twice in a row to determine whether a toggle bit is
toggling. Typically, the system would note and store the
value of the toggle bit after the first read. After the
second read, the system would compare the new value
of the toggle bit with the first. If the toggle bit is not
toggling, the device has completed the program or erase
operation. The system can read array data on Q7-Q0
on the following read cycle.
If this time-out condition occurs during the chip erase
operation, it specifies that the entire chip is bad or
combination of sectors are bad.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the
system also should note whether the value of Q5 is
high (see the section on Q5). If it is, the system should
then determine again whether the toggle bit is toggling,
since the toggle bit may have stopped toggling just as
Q5 went high. If the toggle bit is no longer toggling, the
device has successfuly completed the program or erase
operation. If it is still toggling, the device did not
complete the operation successfully, and the system
must write the reset command to return to reading array
data.
If this time-out condition occurs during the byte
programming operation, it specifies that the entire
sector containing that byte is bad and this sector maynot
be reused, (other sectors are still functional and can be
reused).
The time-out condition may also appear if a user tries to
program a non blank location without erasing. In this
case the device locks out and never completes the
Automatic Algorithm operation. Hence, the system never
reads a valid data on Q7 bit and Q6 never stops
toggling. Once the Device has exceeded timing limits,
the Q5 bit will indicate a "1". Please note that this is not
a device failure condition since the device was
incorrectly used.
The remaining scenario is that system initially determines
that the toggle bit is toggling and Q5 has not gone high.
The system may continue to monitor the toggle bit and
P/N:PM0556
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10
INDEX
MX29F022T/B
Q3
POWER SUPPLY DECOUPLING
Sector Erase Timer
In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected between its VCC and GND.
After the completion of the initial sector erase command
sequence th sector erase time-out will begin. Q3 will
remain low until the time-out is complete. Data Polling
and Toggle Bit are valid after the initial sector erase
command sequence.
CHIP PROTECTION WITH 12V SYSTEM
The MX29F022T/B features hardware chip protection,
which will disable both program and erase operations.
To activate this mode, the programming equipment must
force VID on address pin A9 and control pin OE, (suggest VID = 12V) A6 = VIL and CE = VIL.(see Table 2)
Programming of the protection circuitry begins on the
falling edge of the WE pulse and is terminated on the
rising edge. Please refer to chip protect algorithm and
waveform.
If Data Polling or the Toggle Bit indicates the device has
been written with a valid erase command, Q3 may be
used to determine if the sector erase timer window is
still open. If Q3 is high ("1") the internally controlled
erase cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or
Toggle Bit. If Q3 is low ("0"), the device will accept
additional sector erase commands. To insure the
command has been accepted, the system software
should check the status of Q3 prior to and following each
subsequent sector erase command. If Q3 were high
on the second status check, the command may not have
been accepted.
To verify programming of the protection circuitry, the
programming equipment must force VID on address pin
A9 ( with CE and OE at VIL and WE at VIH. When A1=1,
it will produce a logical "1" code at device output Q0 for
the protected status. Otherwise the device will produce
00H for the unprotected status. In this mode, the
addresses,except for A1, are in "don't care" state.
Address locations with A1 = VIL are reserved to read
manufacturer and device codes.(Read Silicon ID)
DATA PROTECTION
The MX29F022T/B is designed to offer protection
against accidental erasure or programming caused by
spurious system level signals that may exist during power
transition. During power up the device automatically
resets the state machine in the Read mode. In addition,
with its control register architecture, alteration of the
memory contents only occurs after successful
completion of specific command sequences. The
device also incorporates several features to prevent
inadvertent write cycles resulting from VCC power-up
and power-down transition or system noise.
It is also possible to determine if the chip is protected in
the system by writing a Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
a logical "1" at Q0 for the protected status.
WRITE PULSE "GLITCH" PROTECTION
To activate this mode, the programming equipment must
force VID on control pin OE and address pin A9. The
CE pins must be set at VIL. Pins A6 must be set to
VIH.(see Table 2) Refer to chip unprotect algorithm and
waveform for the chip unprotect algorithm. The
unprotection mechanism begins on the falling edge of
the WE pulse and is terminated on the rising edge.
CHIP UNPROTECT WITH 12V SYSTEM
The MX29F022T/B also features the chip unprotect
mode, so that all sectors are unprotected after chip
unprotect is completed to incorporate any changes in
the code.
Noise pulses of less than 5ns(typical) on CE or WE will
not initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE = VIL, CE =
VIH or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
P/N:PM0556
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11
INDEX
MX29F022T/B
It is also possible to determine if the chip is unprotected
in the system by writing the Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
00H at data outputs(Q0-Q7) for an unprotected chip. It
is noted that all sectors are unprotected after the chip
unprotect algorithm is complete.
ABSOLUTE MAXIMUM RATINGS
RATING
Ambient Operating Temperature
Storage Temperature
Applied Input Voltage
Applied Output Voltage
VCC to Ground Potential
A9
CHIP PROTECTION WITHOUT 12V SYSTEM
The MX29F022T/B also feature a hardware chip
protection method in a system without 12V power
suppply. The programming equipment do not need to
supply 12 volts to protect all sectors. The details are
shown in chip protect algorithm and waveform.
VALUE
0oC to 70oC
-65oC to 125oC
-0.5V to 7.0V
-0.5V to 7.0V
-0.5V to 7.0V
-0.5V to 13.5V
NOTICE:
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may
affect reliability.
CHIP UNPROTECT WITHOUT 12V SYSTEM
The MX29F022T/B also feature a hardware chip
unprotection method in a system without 12V power
supply. The programming equipment do not need to
supply 12 volts to unprotect all sectors. The details are
shown in chip unprotect algorithm and waveform.
NOTICE:
Specifications contained within the following tables are subject to change.
POWER-UP SEQUENCE
The MX29F022T/B powers up in the Read only mode.
In addition, the memory contents may only be altered
after successful completion of a two-step command
sequence. Vpp and Vcc power up sequence is not
required.
P/N:PM0556
REV. 0.6, DEC. 09, 1998
12
INDEX
MX29F022T/B
CAPACITANCE TA = 25oC, f = 1.0 MHz
SYMBOL
CIN
COUT
PARAMETER
Input Capacitance
Output Capacitance
MIN.
TYP
MAX.
8
12
UNIT
pF
pF
CONDITIONS
VIN = 0V
VOUT = 0V
READ OPERATION
DC CHARACTERISTICS TA = 0oC TO 70oC, VCC = 5V ± 10%
SYMBOL
ILI
ILO
ISB1
ISB2
ICC1
ICC2
VIL
VIH
VOL
VOH
PARAMETER
Input Leakage Current
Output Leakage Current
Standby VCC current
MIN.
TYP
1
Operating VCC current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
-0.3(NOTE1) 0.8
2.0
MAX.
1
10
1
100
50
70
V
VCC + 0.3
0.45
2.4
UNIT
mA
mA
mA
mA
mA
mA
CONDITIONS
VIN = GND to VCC
VOUT = GND to VCC
CE = VIH
CE = VCC + 0.3V
IOUT = 0mA, f=1MHz
IOUT = 0mA, f=10MHz
V
V
V
IOL = 2.1mA
IOH = -2mA
NOTES:
1. VIL min. = -1.0V for pulse width is equal to or less than 50 ns.
VIL min. = -2.0V for pulse width is equal to or less than 20 ns.
2. VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns
If VIH is over the specified maximum value, read operation cannot be guaranteed.
P/N:PM0556
REV. 0.6, DEC. 09, 1998
13
INDEX
MX29F022T/B
AC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V ± 10%
29F022T/B-70 29F022T/B-90 29F022T/B-12
SYMBOL PARAMETER
MIN. MAX. MIN. MAX.
MIN. MAX. UNIT CONDITIONS
tACC
Address to Output Delay
70
90
120 ns
CE=OE=VIL
tCE
CE to Output Delay
70
90
120 ns
OE=VIL
tOE
OE to Output Delay
30
40
50
ns
CE=VIL
tDF
OE High to Output Float (Note1) 0
20
0
30
0
30
ns
CE=VIL
tOH
Address to Output hold
0
0
0
ns
CE=OE=VIL
TEST CONDITIONS:
NOTE:
1.tDF is defined as the time at which the output achieves the
open circuit condition and data is no longer driven.
• Input pulse levels: 0.45V/2.4V
• Input rise and fall times: is equal to or less than 10ns
• Output load: 1 TTL gate + 35pF(Including scope and jig)
• Reference levels for measuring timing: 0.8V, 2.0V
READ TIMING WAVEFORMS
VIH
ADD Valid
A0~17
VIL
tCE
VIH
CE
VIL
WE
VIH
OE
VIH
tACC
VIL
DATA
Q0~7
tDF
tOE
VIL
VOH
HIGH Z
tOH
DATA Valid
HIGH Z
VOL
P/N:PM0556
REV. 0.6, DEC. 09, 1998
14
INDEX
MX29F022T/B
COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION
DC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V ± 10%
SYMBOL
PARAMETER
MIN.
ICC1 (Read)
Operating VCC Current
ICC2
ICC3 (Program)
ICC4 (Erase)
ICCES
VCC Erase Suspend Current
TYP MAX.
30
50
50
50
2
UNIT
mA
mA
mA
mA
mA
CONDITIONS
IOUT=0mA, f=1MHz
IOUT=0mA, F=10MHz
In Programming
In Erase
CE=VIH, Erase Suspended
NOTES:
1. VIL min. = -0.6V for pulse width is equal to or less than 20ns.
2. If VIH is over the specified maximum value, programming operation cannot be guranteed.
3. ICCES is specified with the device de-selected. If the device is read during erase suspend mode, current draw is
the sum of ICCES and ICC1 or ICC2.
4. All current are in RMS unless otherwise noted.
P/N:PM0556
REV. 0.6, DEC. 09, 1998
15
INDEX
MX29F022T/B
AC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V ± 10%
29F022T/B-70 29F022T/B-90 29F022T/B-12
SYMBOL
PARAMETER
MIN.
tOES
OE setup time
50
MAX. MIN.
50
50
ns
tCWC
Command programming cycle
70
90
120
ns
tCEP
WE programming pulse width
35
45
50
ns
tCEPH1
WE programming pluse width High
20
20
20
ns
tCEPH2
WE programming pluse width High
20
20
20
ns
tAS
Address setup time
0
0
0
ns
tAH
Address hold time
45
45
50
ns
tDS
Data setup time
30
45
50
ns
tDH
Data hold time
0
0
0
ns
tCESC
CE setup time before command write
0
0
0
ns
tDF
Output disable time (Note 1)
30
MAX. MIN.
40
MAX.
40
UNIT CONDITIONS
ns
tAETC
Total erase time in auto chip erase
2(TYP.)
2(TYP.)
2(TYP.)
s
tAETB
Total erase time in auto block erase
1(TYP.)
1(TYP.)
1(TYP.)
s
tAVT
Total programming time in auto verify
7
7
7
us
(Byte Program time)
tBAL
Block address load time
80
80
80
us
tCH
CE Hold Time
0
0
0
us
tCS
CE setup to WE going low
0
0
0
us
tVLHT
Voltge Transition Time
4
4
4
us
tOESP
OE Setup Time to WE Active
4
4
4
us
tWPP1
Write pulse width for chip protect
10
10
10
us
tWPP2
Write pulse width for chip unprotect
12
12
12
ms
NOTES:
1.tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.
P/N:PM0556
REV. 0.6, DEC. 09, 1998
16
INDEX
MX29F022T/B
SWITCHING TEST CIRCUITS
1.6K ohm
DEVICE UNDER
TEST
CL
1.2K ohm
+5V
DIODES=IN3064
OR EQUIVALENT
CL=100pF Including jig capacitance
SWITCHING TEST WAVEFORMS
2.4V
2.0V
2.0V
TEST POINTS
0.8V
0.8V
0.45V
INPUT
OUTPUT
AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0".
Input pulse rise and fall times are <20ns.
P/N:PM0556
REV. 0.6, DEC. 09, 1998
17
INDEX
MX29F022T/B
COMMAND WRITE TIMING WAVEFORM
VCC
5V
ADD
A0~17
VIH
WE
VIH
ADD Valid
VIL
tAH
tAS
VIL
tOES
tCEPH1
tCEP
tCWC
CE
VIH
VIL
tCS
OE
VIL
DATA
Q0-7
tCH
VIH
tDS
tDH
VIH
DIN
VIL
P/N:PM0556
REV. 0.6, DEC. 09, 1998
18
INDEX
MX29F022T/B
AUTOMATIC PROGRAMMING TIMING WAVEFORM
polling and toggle bit checking after automatic
verification starts. Device outputs DATA during
programming and DATA after programming on Q7.(Q6 is
for toggle bit; see toggle bit, DATA polling, timing
waveform)
One byte data is programmed. Verifying in fast
algorithm and additional programming by external
control are not required because these operations are
executed automatically by internal control circuit.
Programming completion can be verified by DATA
AUTOMATIC PROGRAMMING TIMING WAVEFOR
Vcc 5V
A11~A17
A0~A10
ADD Valid
2AAH
555H
tAS
WE
ADD Valid
555H
tCWC
tAH
tCEPH1
tCESC
tAVT
CE
tCEP
OE
tDS
Q0~Q1
tDH
Command In
tDF
Command In
Command In
DATA
Data In
DATA polling
,Q4(Note 1)
Q7
Command In
Command #AAH
Command In
Command In
Command #55H
Command #A0H
DATA
Data In
(Q0~Q7)
DATA
tOE
Notes:
(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2:Toggle bit
P/N:PM0556
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INDEX
MX29F022T/B
AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data A0H Address 555H
Write Program Data/Address
Toggle Bit Checking
Q6 not Toggled
NO
YES
Invalid
Command
NO
Verify Byte Ok
YES
NO
Q5 = 1
Auto Program Completed
YES
Reset
Auto Program Exceed
Timing Limit
P/N:PM0556
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INDEX
MX29F022T/B
TOGGLE BIT ALGORITHM
START
Read Q7~Q0
(Note 1)
Read Q7~Q0
NO
Toggle Bit Q6
=Toggle?
YES
NO
Q5=1?
YES
(Note 1,2)
Read Q7~Q0 Twice
Toggle Bit Q6
=Toggle?
YES
Program/Erase Operation Not
Complete, Write Reset Command
Program/Erase Operation Complete
Notes:
1.Read toggle bit Q6 twice to determine whether or not it is toggle. See text.
2.Recheck toggle bit Q6 because it may stop toggling as Q5 changes to "1". See text.
P/N:PM0556
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21
INDEX
MX29F022T/B
AUTOMATIC CHIP ERASE TIMING WAVEFORM
All data in chip are erased. External erase verification is
not required because data is erased automatically by
internal control circuit. Erasure completion can be
verified by DATA polling and toggle bit checking after
automatic erase starts. Device outputs "0" during
erasure and 1 after erasure on Q7.(Q6 is for toggle bit;
see toggle bit, DATA polling, timing waveform)
AUTOMATIC CHIP ERASE TIMING WAVEFORM
Vcc 5V
A11~A17
A0~A10
2AAH
555H
555H
555H
tAS
WE
2AAH
555H
tCWC
tAH
tCEPH1
tCESC
tAETC
CE
tCEP
OE
tDF
tDS tDH
Q0~Q1
Command In
Command In
Command In
Command In
Command In
Command In
DATA polling
,Q4(Note 1)
Q7
Command In
Command #AAH
Command In
Command In
Command In
Command In
Command In
Command #55H
Command #80H
Command #AAH
Command #55H
Command #10H
(Q0~Q7)
Notes:
(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2:Toggle bit
P/N:PM0556
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INDEX
MX29F022T/B
AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 10H Address 555H
NO
Toggle Bit Checking
Q6 not Toggled
YES
Invalid
Command
NO
DATA Polling
Q7 = 1
YES
NO
Auto Chip Erase Completed
Q5 = 1
YES
Reset
Auto Chip Erase Exceed
Timing Limit
P/N:PM0556
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23
INDEX
MX29F022T/B
AUTOMATIC BLOCK ERASE TIMING WAVEFORM
bit checking after automatic erase starts. Device outputs 0 during erasure and 1 after erasure on Q7.(Q6 is
for toggle bit; see toggle bit, DATA polling, timing waveform)
Block data indicated by A13 to A17 are erased. External erase verification is not required because data are
erased automatically by internal control circuit. Erasure
completion can be verified by DATA polling and toggle
AUTOMATIC BLOCK ERASE TIMING WAVEFORM
Vcc 5V
Block
Address 0
A13~A17
A0~A10
2AAH
555H
555H
555H
Block
Address N
2AAH
tAS
WE
Block
Address 1
tCWC
tAH
tCEPH1
tBAL
tCEPH2
tCESC
tAETB
CE
tCEP
OE
tDF
tDS tDH
Q0~Q1,
Command In
Command In
Command In
Command In
Command In
Command In
Command In
Command In
DATA polling
Q4(Note 1)
Q7
Command In
Command #AAH
Command In
Command In
Command In
Command In
Command In
Command In
Command In
Command #55H
Command #80H
Command #AAH
Command #55H
Command #30H
Command #30H
Command #30H
(Q0~Q7)
Notes:
(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3:Time-out bit, Q2:Toggle
P/N:PM0556
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INDEX
MX29F022T/B
AUTOMATIC BLOCK ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 30H Sector Address
Toggle Bit Checking
Q6 Toggled ?
NO
Invalid Command
YES
Load Other Sector Addrss If Necessary
(Load Other Sector Address)
NO
Last Block
to Erase
YES
Time-out Bit
Checking Q3=1 ?
NO
YES
Toggle Bit Checking
Q6 not Toggled
NO
YES
NO
Q5 = 1
DATA Polling
Q7 = 1
YES
Reset
Auto Block Erase Completed
Auto Block Erase Exceed
Timing Limit
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INDEX
MX29F022T/B
ERASE SUSPEND/ERASE RESUME FLOWCHART
START
Write Data B0H
NO
Toggle Bit checking Q6
not toggled
YES
Read Array or
Program
Reading or
Programming End
NO
YES
Write Data 30H
Continue Erase
Another
Erase Suspend ?
NO
YES
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26
INDEX
MX29F022T/B
TIMING WAVEFORM FOR CHIP PROTECTION FOR SYSTEM WITH 12V
A1
A6
12V
5V
A9
tVLHT
Verify
12V
5V
OE
tVLHT
tVLHT
tWPP 1
WE
tOESP
CE
Data
01H
tOE
TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITH 12V
A1
12V
5V
A9
tVLHT
A6
Verify
12V
5V
OE
tVLHT
tVLHT
tWPP 2
WE
tOESP
CE
Data
00H
tOE
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INDEX
MX29F022T/B
CHIP PROTECTION ALGORITHM FOR SYSTEM WITH 12V
START
PLSCNT=1
OE=VID,A9=VID,CE=VIL
A6=VIL
Activate WE Pulse
Time Out 10us
Device Failed
Set WE=VIH, CE=OE=VIL
A9 should remain VID
Read from Sector
Addr=SA, A1=1
No
PLSCNT=32?
No
Data=01H?
Yes
Yes
Remove VID from A9
Write Reset Command
Device Failed
Chip Protection
Complete
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INDEX
MX29F022T/B
CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITH 12V
START
PLSCNT=1
Set OE=A9=VID
CE=VIL,A6=1
Activate WE Pulse
Time Out 12ms
Increment
PLSCNT
Set OE=CE=VIL
A9=VID,A1=1
Read Data from Device
No
Data=00H?
No
PLSCNT=1000?
Yes
Yes
Remove VID from A9
Write Reset Command
Device Failed
Chip Unprotect
Complete
P/N:PM0556
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29
INDEX
MX29F022T/B
TIMING WAVEFORM FOR CHIP PROTECTION FOR SYSTEM WITHOUT 12V
A1
A6
5V
A9
Q6 Toggle bit polling
Verify
5V
OE
tCEP
WE
* See the following Note!
CE
Data
01H
Don't care
tOE
Note: Must issue "unlock for chip protect/unprotect" command
before chip protection for a system without 12V provided.
TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITHOUT 12V
A1
5V
A9
A6
Q6 Toggle bit polling
Verify
5V
OE
tCEP
WE
* See the following Note!
CE
Data
00H
Don't care
tOE
Note: Must issue "unlock for chip protect/unprotect" command
before chip unprotection for a system without 12V provided.
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INDEX
MX29F022T/B
CHIP PROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V
START
PLSCNT=1
Write "Unlock for chip protect/unprotect"
Command
OE=VID,A9=VID
CE=VIL,A6=VIL
Activate WE Pulse to start
Data don't care
Toggle bit checking
Q6 not Toggle
No
Yes
Set CE=OE=VIL
A9=VIH
Increment PLSCNT
Read from Sector
Addr. =SA,A1=1
No
No
PLSCNT=32?
Yes
Data=01H?
Yes
Device Failed
Write Reset Command
Chip Protection
Complete
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INDEX
MX29F022T/B
CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V
START
PLSCNT=1
Write "unlock for chip protect/unprotect"
Command (Table 1)
Set OE=A9=VIH
CE=VIL,A6=1
Activate WE Pulse to start
Data don't care
No
Toggle bit checking
Q6 not Toggled
Increment
PLSCNT
Yes
Set OE=CE=VIL
A9=VIH,A1=1
Read Data from Device
No
Data=00H?
No
Yes
PLSCNT=1000?
Yes
Write Reset Command
Device Failed
Chip Unprotect
Complete
P/N:PM0556
REV. 0.6, DEC. 09, 1998
32
INDEX
MX29F022T/B
ID CODE READ TIMING WAVEFORM MODE
VCC
5V
VID
VIH
VIL
ADD
A9
tACC
tACC
A1
VIH
VIL
ADD
A2-A8
A10-A17
CE
VIH
VIL
VIH
VIL
WE
VIH
tCE
VIL
OE
VIH
tOE
VIL
tDF
tOH
tOH
VIH
DATA
Q0-Q7
DATA OUT
DATA OUT
VIL
36H/37H
C2H
P/N:PM0556
REV. 0.6, DEC. 09, 1998
33
INDEX
MX29F022T/B
ORDERING INFORMATION
PLASTIC PACKAGE
PART NO.
ACCESS TIME
OPERATING CURRENT
STANDBY CURRENT
PACKAGE
(ns)
MAX.(mA)
MAX.(uA)
MX29F022TPC-70
70
30
1
32 Pin PDIP
MX29F022TPC-90
90
30
1
32 Pin PDIP
MX29F022TPC-12
120
30
1
32 Pin PDIP
MX29F022TTC-70
70
30
1
32 Pin TSOP
MX29F022TTC-90
90
30
1
32 Pin TSOP
(Normal Type)
(Normal Type)
MX29F022TTC-12
120
30
1
32 Pin TSOP
MX29F022TQC-70
70
30
1
32 Pin PLCC
MX29F022TQC-90
90
30
1
32 Pin PLCC
MX29F022TQC-12
120
30
1
32 Pin PLCC
MX29F022BPC-70
70
30
1
32 Pin PDIP
MX29F022BPC-90
90
30
1
32 Pin PDIP
MX29F022BPC-12
120
30
1
32 Pin PDIP
MX29F022BTC-70
70
30
1
32 Pin TSOP
MX29F022BTC-90
90
30
1
32 Pin TSOP
(Normal Type)
(Normal Type)
(Normal Type)
MX29F022BTC-12
120
30
1
32 Pin TSOP
MX29F022BQC-70
70
30
1
32 Pin PLCC
MX29F022BQC-90
90
30
1
32 Pin PLCC
MX29F022BQC-12
120
30
1
32 Pin PLCC
(Normal Type)
P/N:PM0556
REV. 0.6, DEC. 09, 1998
34
INDEX
MX29F022T/B
PACKAGE INFORMATION
32-PIN PLASTIC DIP
ITEM
MILLIMETERS
INCHES
A
42.13 max.
1.660 max.
B
1.90 [REF]
.075 [REF]
C
2.54 [TP]
.100 [TP]
D
.46 [Typ.]
.050 [Typ.]
E
38.07
1.500
F
1.27 [Typ.]
.050 [Typ.]
G
3.30 ± .25
.130 ± .010
H
.51 [REF]
I
3.94 ± .25
1.55 ± .010
J
5.33 max.
.210 max.
K
15.22 ± .25
.600 ± .101
L
13.97 ± .25
.550 ± .010
M
.25 [Typ.]
.010 [Typ.]
32
17
16
1
A
.020 [REF]
K
L
F
D
NOTE: Each lead certerline is located within
.25mm[.01 inch] of its true position [TP] at a maximum at maximum material condition.
C
I
J
H
G
0~15¡
M
B
E
32-PIN PLASTIC LEADED CHIP CARRIER (PLCC)
A
ITEM
MILLIMETERS
INCHES
A
12.44 ± .13
.490 ± .005
B
11.50 ± .13
.453 ± .005
C
14.04 ± .13
.553 ± .005
D
14.98 ± .13
.590 ± .005
E
1.93
.076
F
3.30 ± .25
.130 ± .010
G
2.03 ± .13
.080 ± .005
H
.51 ± .13
.020 ± .005
I
1.27 [Typ.]
.050 [Typ.]
J
.71 [REF]
.028 [REF]
K
.46 [REF]
.018 [REF]
L
10.40/12.94
.410/.510
(W)
(W) (L)
(L)
M
.89R
.035R
N
.25[Typ.]
.010[Typ.]
B
1
4
32
30
5
29
9
25
13
C
D
21
14
20
17
E
F
G
NOTE: Each lead certerline is located within
.25mm[.01 inch] of its true position [TP] at a
maximum at maximum material condition.
N
H
M
I
J
K
L
P/N:PM0556
REV. 0.6, DEC. 09, 1998
35
INDEX
MX29F022T/B
32-PIN PLASTIC TSOP
ITEM
MILLIMETERS
INCHES
A
20.0 ± .20
.078 ± .006
B
18.40 ± .10
.724 ± .004
C
8.20 max.
.323 max.
D
0.15 [Typ.]
.006 [Typ.]
E
.80 [Typ.]
.031 [Typ.]
F
.20 ± .10
.008 ± .004
G
.30 ± .10
.012 ± .004
H
.50 [Typ.]
.020 [Typ.]
I
.45 max.
.018 max.
J
0 ~ .20
0 ~ .008
K
1.00 ± .10
.039 ± .004
L
1.27 max.
.050 max.
M
.50
.020
N
0 ~5°
.500
A
B
C
N
M
K
L
D
E
F
G
H
I
J
NOTE: Each lead certerline is located within
.25mm[.01 inch] of its true position [TP] at a
maximum at maximum material condition.
P/N:PM0556
REV. 0.6, DEC. 09, 1998
36
INDEX
MX29F022T/B
REVISION HISTORY
Revision
0.1
0.2
0.3
0.4
0.5
0.6
Description
This protect is featured with functions of chip protect/unprotect.
Chip Protect Verification is added on the software command table.
Modify the block diagram
Modify the Q3 status into "0" for Exceeded Time Limits in
Write Operation Status Table
Change IOH value at DC CHARACTERISTICS
Change resistance value at SWITCHING TEST CIRCUIT
Modify Table 1 software command definitions
Modify "Chip protection with 12V system" section
To correct typing error
P/N:PM0556
Page
Date
JUN/29/1998
AUG/18/1998
AUG/28/1998
P9
P13
P17
P5
P11
P28,29
31,32
SEP/14/1998
NOV/04/1998
DEC/09/1998
REV. 0.6, DEC. 09, 1998
37
INDEX
MX29F022T/B
MACRONIX INTERNATIONAL CO., LTD.
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TEL:+886-3-578-8888
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MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice.
38