MICRON MT9V111

Preliminary‡
MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
Features
1/4-Inch SOC VGA CMOS Active-Pixel
Digital Image Sensor
MT9V111I29STC
Features
Table 1:
• DigitalClarity™ CMOS Imaging Technology
• System-On-a-Chip (SOC)—Completely integrated
camera system
• Ultra low-power, low cost CMOS image sensor
• Superior low-light performance
• Up to 30 fps progressive scan at 27 MHz for highquality video at VGA resolution
• On-chip Image Flow Processor (IFP) performs
sophisticated processing: color recovery and
correction, sharpening, gamma, lens shading
correction, on-the-fly defect correction, 2X fixed
zoom
• Image decimation to arbitrary size with smooth,
continuous zoom and pan
• Automatic exposure, white balance and black
compensation, flicker avoidance, color saturation,
and defect identification and correction, auto frame
rate, back light compensation
• Xenon and LED-type flash support
• Two-wire serial programming interface
• ITU_R BT.656 (YCbCr), YUV, 565RGB, 555RGB, and
444RGB output data formats
Parameter
Optical Format
Active Imager Size
Active Pixels
Pixel Size
Color Filter Array
Shutter Type
Maximum Data Rate/
Master Clock
VGA (640 x 480)
Frame
Rate
CIF (352 x 288)
QVGA (320 x
240)
ADC Resolution
Responsivity
Dynamic Range
SNRMAX
Supply Voltage
Power Consumption
Operating Temperature
Packaging
Applications
•
•
•
•
Cellular phones
PDAs
PC Camera
Toys and other battery-powered products
09005aef80e90084
MT9V111_1.fm - Rev. G 1/05 EN
Key Performance Parameters
Typical Value
1/4-inch (4:3)
3.58mm(H) x 2.69mm(V)
4.48mm (Diagonal)
640H x 480V (VGA)
5.6um x 5.6um
RGB Bayer Pattern
Electronic Rolling Shutter (ERS)
12−13.5 MPS/24−27 MHz
15 fps at 12 MHz (default),
programmable up to 30 fps
at 27 MHz
Programmable up to 60 fps
Programmable up to 90 fps
10-bit, on-chip
1.9 V/lux-sec (550nm)
60dB
45dB
2.8V +0.25V
<80mW at 2.8V, 15 fps at 12MHz
-20°C to +60°C
44-Ball ICSP, wafer or die
General Description
The Micron® Imaging MT9V111 is a 1/4-inch VGA-format CMOS active-pixel digital image sensor, the result
of combining the MT9V011 image sensor core with
Micron Imaging's third-generation digital image flow
processor technology. The MT9V111 has an active imaging pixel array of 649 x 489, capturing high-quality color
images at VGA resolution. The sensor is a complete
camera-on-a-chip solution and is designed specifically
to meet the demands of battery-powered products such
as cellular phones, PDAs, and toys. It incorporates
sophisticated camera functions on-chip and is programmable through a simple two-wire serial interface.
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron
to meet Micron’s production data sheet specifications. Products and specifications discussed herein are subject to change by Micron without notice.
Preliminary
MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
Table of Contents
Table of Contents
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Image Flow Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Overview of Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Output and Formatting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Output Data Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
IFP Register List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
IFP Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Sensor Core Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Sensor Core Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Propagation Delays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Propagation Delays for PIXCLK and Data Out Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Propagation Delays for FRAME_VALID and LINE_VALID Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Appendix A – Sensor Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Serial Bus Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Bus Idle State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Start Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Stop Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Slave Address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Data Bit Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
No-Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Two-wire Serial Interface Sample Write and Read Sequences
(with Saddr = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
16-Bit Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
16-Bit Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Eight-Bit Write Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Eight-Bit Read Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Two-wire Serial Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Appendix B – Overview Of Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Default Sensor Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Auto Exposure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Automatic White Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Flicker Avoidance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Decimation, Zoom, and Pan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Interpolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Special Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Image Mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Test Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Gamma Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
09005aef80e90084
MT9V111TOC.fm - Rev. G 1/05 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
Preliminary
MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
List of Figures
Figure 1:
Figure 2:
Figure 3:
Figure 4:
Figure 5:
Figure 6:
Figure 7:
Figure 8:
Figure 9:
Figure 10:
Figure 11:
Figure 12:
Figure 13:
Figure 14:
Figure 15:
Figure 16:
Figure 17:
Figure 18:
Figure 19:
Figure 20:
Figure 21:
Figure 22:
Figure 23:
Figure 24:
Figure 25:
Figure 26:
Chip Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Internal Register Grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Typical Configuration (Connection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
44-Ball ICSP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Image Flow Processor Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Sensor Core Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Pixel Array Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Pixel Color Pattern Detail (Top Right Corner) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Spatial Illustration of Image Readout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Propagation Delays for PIXCLK and Data Out Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Propagation Delays for FRAME_VALID and LINE_VALID Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Data Output Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Spectral Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Die Center - Image CenterOffset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Row Timing and FRAME_VALID/LINE_VALID Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Timing Diagram Showing a Write to Reg0x09 with Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Timing Diagram Showing a Read from Reg0x09; Returned Value 0x0284 . . . . . . . . . . . . . . . . . . . . . . .38
Timing Diagram Showing a Bytewise Write to Reg0x09 with Value 0x0284. . . . . . . . . . . . . . . . . . . . . .39
Timing Diagram Showing a Bytewise Read from Reg0x09; Returned Value 0x0284 . . . . . . . . . . . . . .39
Serial Host Interface Start Condition Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Serial Host Interface Stop Condition Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Serial Host Interface Data Timing for Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Serial Host Interface Data Timing for Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Acknowledge Signal Timing After an 8-bit Write to the Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Acknowledge Signal Timing After an 8-bit Read from the Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
44-Ball ICSP Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
09005aef80e90084
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3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
Preliminary
MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
List of Tables
List of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Table 11:
Table 12:
Table 13:
Table 14:
Table 15:
Table 16:
Table 17:
Table 18:
Table 19:
Key Performance Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Ball Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
YUV/YCbCr Output Data Ordering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
RGB Output Data Ordering in Default Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Byte Ordering in 8 + 2 Bypass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
IFP Register List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
IFP Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Sensor Core Register List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Sensor Core Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Frame Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Frame Time—Larger than One Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Non-Default Register Settings Optimizing 15 fps at 12 MHz Operation . . . . . . . . . . . . . . . . . . . . . . . .42
Non-Default Register Settings Optimizing 30 fps at 27 MHz Operation . . . . . . . . . . . . . . . . . . . . . . . .42
Relation Between IFP R55[9:5] Setting and Frame Rate Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Decimation, Zoom, and Pan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
YCbCr Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
YUV Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
09005aef80e90084
MT9V111LOT.fm - Rev. G 1/05 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
General Description
General Description
This SOC VGA CMOS image sensor features DigitalClarityMicron’s breakthrough,
low-noise CMOS imaging technology that achieves CCD image quality (based on signalto-noise ratio and low-light sensitivity) while maintaining the inherent size, cost and
integration advantages of CMOS.
The MT9V111 is a fully-automatic, single-chip camera, requiring only a power supply,
lens and clock source for basic operation. Output video is streamed via a parallel eightbit DOUT port as shown in Figure 1. Output pixel clock is used to latch the data, while
FRAME_VALID and LINE_VALID signals indicate the active video. The sensor can be put
in an ultra-low power sleep mode by asserting the STANDBY pin. Output pads can also
be tri-stated by de-asserting the OE# pin. The MT9V111 internal registers can be configured using a two-wire serial interface.
The MT9V111 can be programmed to output progressive scan images up to 30 fps in an
8-bit ITU_R BT.656 (YCbCr) formerly CCIR656, YUV, 565RGB, 555RGB, or 444RGB formats. The FRAME_VALID and LINE_VALID signals are output on dedicated pins, along
with a pixel clock that is synchronous with valid data.
Figure 1: Chip Block Diagram
SCLK
SDATA
SADDR
CLK
STANDBY
OE#
VDD/DGND
VAA/AGND
VAAPIX
Communication Bus
Image Flow Processor
Sensor Core
. Based on MT9V011
. 668H x 496V (VGA+ Reference)
. 1/4-inch optical format
. Auto Black compensation
. Programmable analog gain
. Programmable exposure
. Low power, 10-bit ADCs
. Color correction, gamma,
DOUT(7:0)
lens shading correction
. Auto exposure, white balance
. Interpolation and defect
correction
. Flicker avoidance
PIXCLK
FRAME_VALID
LINE_VALID
FLASH
SRAM Line Buffers
The MT9V111 can accept the input clock of up to 27 MHz, delivering 30 fps. With poweron defaults (see Appendix B for recommended defaults), the camera is configured to
deliver 15 fps at 12 MHz and automatically slows down the frame rate in low-light conditions to achieve longer exposures and better image quality.
Internally, the MT9V111 consists of a sensor core and an image flow processor. The sensor core functions to capture raw Bayer-encoded images that are input into the IFP as
shown in Figure 1. The IFP processes the incoming stream to create interpolated, colorcorrected output and controls the sensor core to maintain the desirable exposure and
color balance.
Sensor core and IFP registers are grouped into two separate address spaces, as shown in
Figure 2. The internal registers can be accessed via the two-wire serial interface. Selecting the desired address space can be accomplished by programming register R1 which
remains present in both register sets.
09005aef80e90084
MT9V111_2.fm - Rev. G 1/05 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
General Description
Figure 2: Internal Register Grouping
Note:
R0
R1
R0
R1
Sensor Core
Registers
(R2..R255)
IFP
Registers
(R2..R255)
R1=4
R1=1
Program R1 to select the desired space (4 = sensor core registes, 1 = IFP/SOC registers).
Figure 3 shows MT9V111 typical connections. For low-noise operation, the MT9V111
requires separate supplies for analog and digital power. Incoming digital and analog
ground conductors can be tied together right next to the die. Both power supply rails
should be decoupled to ground using capacitors. The use of inductance filters is not recommended.
Figure 3: Typical Configuration (Connection)
VDD
VDD
VAA
VAAPIX
ADC_TEST
VAA
1.5KΩ
SADDR
1.5KΩ
1KΩ
RESET#
Two-wire
serial bus
{
Master
Clock
DOUT(7:0)
FRAME_VALID
LINE_VALID
PIXCLK
SDATA
SCLK
{
10µF
To CMOS
camera port
CLKIN
FLASH
To Xenon flash
trigger or LED enable
SCAN_EN
DGND
Note:
09005aef80e90084
MT9V111_2.fm - Rev. G 1/05 EN
AGND
STANDBY
DGND
OE#
AGND
1.5KΩ resistor value is recommended, but may be greater for slower two-wire speed.
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
Ball Assignment
Ball Assignment
Figure 4: 44-Ball ICSP Package
1
2
3
4
5
6
7
A
DGND
DOUT2
DOUT4
DGND
DOUT6
VDD
DGND
B
DOUT1
VDD
DOUT3
VDD
DOUT7
VDD
VDD
C
NC
DOUT0
DOUT5
VDD
SCAN
DGND
D
DGND
_EN
OE#
NC
E
PIXCLK FLASH
F
FRAME_
VALID
VDD
SCLK
G
DGND
CLKIN
SDATA
DGND
VDD
RESET# STAND
SADDR
AGND
ADC_
TEST
VAAPIX
DGND
VAA
VAA
AGND
LINE_
VALID
BY
Top View
(Ball Down)
Table 2:
Ball Description
Ball
Numbers
Name
Type
Description
G2
F3
F4
CLKIN
SCLK
SADDR
Input
Input
Input
F6
E6
E7
D6
ADC_TEST
RESET#
STANDBY
OE#
Input
Input
Input
Input
C6
G3
E2
E1
SCAN_EN
SDATA
FLASH
PIXCLK
Input
I/O
Output
Output
E3
F1
B5
LINE_VALID
FRAME_VALID
DOUT7
Output
Output
Output
Master Clock into sensor. Default is 12 MHz (27 MHz maximum).
Serial Clock.
Serial Interface address select: Reg0xB8 when HIGH (default).
Reg0x90 when LOW.
Tie to VAAPIX (factory use only).
Asynchronous reset of sensor when LOW. All registers assume factory defaults.
When HIGH puts the imager in ultra-low power standby mode.
Output_Enable_Bar pin. When HIGH tri-state all outputs except SDATA (tie
LOW for normal operation).
Tie to Digital ground.
Serial data I/O.
Flash Strobe.
Pixel Clock Out. Pixel data output are valid during rising edge of this clock. IFP
Reg0x08 [9] inverts polarity.
Frequency = Master Clock.
Active HIGH during line of selectable valid pixel data.
Active HIGH during frame of valid pixel data.
ITU_R BT.656/RGB data bit 7 (MSB).
09005aef80e90084
MT9V111_2.fm - Rev. G 1/05 EN
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
Ball Assignment
Table 2:
Ball Description (Continued)
Ball
Numbers
A5
C3
A3
B3
A2
B1
C2
A6,B2,B4,B
6,
B7,C5,E5,F
2
G5,G6
F7
F5,G7
A1,D1,A4,
A7,C7,D7,G
1,G4
C1,D2
09005aef80e90084
MT9V111_2.fm - Rev. G 1/05 EN
Name
Type
Description
DOUT6
DOUT5
DOUT4
DOUT3
DOUT2
DOUT1
DOUT0
VDD
Output
Output
Output
Output
Output
Output
Output
Supply
ITU_R BT.656/RGB data bit 6.
ITU_R BT.656/RGB data bit 5.
ITU_R BT.656/RGB data bit 4.
ITU_R BT.656/RGB data bit 3.
ITU_R BT.656/RGB data bit 2.
ITU_R BT.656/RGB data bit 1.
ITU_R BT.656/RGB data bit 0 (LSB).
Digital Power (2.8V).
VAA
VAAPIX
AGND
DGND
Supply
Supply
Supply
Supply
Analog Power (2.8V).
Pixel Array Power (2.8V).
Analog Ground.
Digital Ground.
NC

No connect.
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
Image Flow Processor
Image Flow Processor
Overview of Architecture
The image flow processor consists of a color processing pipeline and a measurement
and control logic block as shown in Figure 5. The stream of raw data from the sensor
enters the pipeline and undergoes a number of transformations. Image stream processing starts from conditioning the black level and applying a digital gain. The lens shading
block compensates for signal loss caused by the lens. Next, the data is interpolated to
recover missing color components for each pixel and defective pixels are corrected. The
resulting interpolated RGB data passes through the current color correction matrix
(CCM), gamma, and saturation corrections and is formatted for final output.
The measurement and control logic continuously accumulates statistics about image
brightness and color. Indoor 50/60 Hz flicker is detected and automatically updated
when possible. Based on these measurements the IFP calculates updated values for
exposure time and sensor analog gains, which are sent to the sensor core via the communication bus.
Color correction is achieved through linear transformation of the image with a 3 x 3
color correction matrix. Color saturation can be adjusted in the range from zero (black
and white) to 1.25 (125% of full color saturation).
Gamma correction compensates for non-linear dependence of the display device output vs. driving signal (e.g. monitor brightness vs. CRT voltage).
Output and Formatting
Processed video can be output in the form of a standard ITU_R BT.656 or RGB stream.
ITU_R BT.656 (default) stream contains 4:2:2 data with optional embedded synchronization codes. This kind of output is typically suitable for subsequent display by standard
video equipment. For JPEG/MPEG compression, YUV/ encoding is suitable. RGB functionality is provided to support LCD devices. The MT9V111 can be configured to output
16-bit RGB (RGB565), 15-bit RGB (RGB555) as well as two types of 12-bit RGB (RGB444).
The user can configure internal registers to swap odd and even bytes, chrominance
channels and luminance and chrominance components to facilitate interface to application processors.
09005aef80e90084
MT9V111_2.fm - Rev. G 1/05 EN
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
Image Flow Processor
Figure 5: Image Flow Processor Block Diagram
IMAGE SENSOR
LENS CORRECTION
DEMOSAICING
AE, AWB,
FLICKER AVOIDANCE
COLOR CORRECTION
FLASH CONTROL
GAMMA CORRECTION
OUTPUT FORMATTING
The MT9V111 features smooth, continuous zoom and pan. This functionality is available when the IFP output is downsized in the decimation block. The decimation block
can downsize the original VGA image to any integer size, including QVGA, QQVGA, CIF
and QCIF with no loss to the field of view. The user can program the desired size of the
output image in terms of horizontal and vertical pixel count. In addition the user can
program the size of a region for downsizing. Continuous zoom is achieved every time
the region of interest is less than the entire VGA image. The maximum zoom factor is
equal to the ratio of VGA to the size of the region of interest. For example, an image rendered on a 160x120 display can be zoomed by 640/160=480/120=4 times. Continuous
pan is achieved by adjusting the starting coordinates of the region of interest.
Also a fixed 2X up-zoom is implemented by means of windowing down the sensor core.
In this mode the IFP receives a QVGA-sized input data and outputs a VGA-size image.
The sub-window can be panned both vertically and horizontally by programming sensor core registers.
The MT9V111 supports both LED and Xenon-type flash light sources using a dedicated
output pad. For Xenon devices the pad generates a strobe to fire when the imager's shutter is fully open. For LED the pad can be asserted or de-asserted asynchronously. Flash
modes are configured and engaged over the two-wire serial interface using IFP Reg0x98.
09005aef80e90084
MT9V111_2.fm - Rev. G 1/05 EN
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
Output Data Ordering
Output Data Ordering
In YCbCr the first and second bytes can be swapped. Luma/chroma bytes can be
swapped as well. R and B channels are bit-wise swapped when chroma swap is enabled.
See IFP Reg0x3A for channel swapping configuration.
Table 3:
YUV/YCbCr Output Data Ordering
Mode
Default (no swap)
Swapped CrCb
Swapped YC
Swapped CrCb, YC
Table 4:
1st Byte
2nd Byte
3rd Byte
4th Byte
Cbi
Cri
Yi
Yi
Yi
Yi
Cbi
Cri
Cri
Cbi
Yi+1
Yi+1
Yi+1
Yi+1
Cri
Cbi
RGB Output Data Ordering in Default Mode
Mode (Swap Disabled)
Byte
D7
D6
D5
D4
D3
D2
D1
D0
RGB 565
First
Second
First
Second
First
Second
First
Second
R7
G4
0
G4
R7
B7
0
G7
R6
G3
R7
G3
R6
B6
0
G6
R5
G2
R6
G2
R5
B5
0
G5
R4
B7
R5
B7
R4
B4
0
G4
R3
B6
R4
B6
G7
0
R7
B7
G7
B5
R3
B5
G6
0
R6
B6
G6
B4
G7
B4
G5
0
R5
B5
G5
B3
G6
B3
G4
0
R4
B4
RGB 555
RGB 444x
RGB x444
A bypass mode is available whereby raw Bayer 10-bits data is output as two bytes. See
IFP Reg8[7].
Table 5:
Byte Ordering in 8 + 2 Bypass Mode
Byte Ordering
8+2 Bypass
09005aef80e90084
MT9V111_2.fm - Rev. G 1/05 EN
First
Second
D9
0
D8
0
D7
0
11
D6
0
D5
0
D4
0
D3
D1
D2
D0
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
IFP Register List
IFP Register List
Table 6:
IFP Register List
Address
09005aef80e90084
MT9V111_2.fm - Rev. G 1/05 EN
Dec
Hex
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
Defaults
Dec
Hex
1
110
10531
1316
11
28686
0
51200
146
22
8
171
147
88
77
169
160
0x0001
0x006E
0x2923
0x0524
0x000B
0x700E
0x0000
0xC800
0x0092
0x0016
0x0008
0x00AB
0x0093
0x0058
0x004D
0x00A9
0x00A0
R/O
R/O
R/O
373
0x0175
22
0x0016
67
0x0043
12
0x000C
0
0x0000
21
0x0015
31
0x001F
22
0x0016
152
0x0098
76
0x004C
160
0x00A0
51220
0xC814
0
0x0000
55648
0xD960
55648
0xD960
32512
0x7F00
17684
0x4514
65283
0xFF03
65296
0xFF10
26624
0x6800
36211
0x8D73
12
Description
Reserved
Register Address Space Selection
Color Correction Register 1
Color Correction Register 2
Color Correction Register 3
Aperture Correction (Sharpening)
Operating Mode Control
Image Flow Processor Soft Reset
Output Format Control
Color Correction Register 4
Color Correction Register 5
Color Correction Register 6
Color Correction Register 7
Color Correction Register 8
Color Correction Register 9
Color Correction Register 10
Color Correction Register 11
Color Correction Register 12
White Balance Register 1
White Balance Register 2
White Balance Register 3
Color Correction Register 13
Color Correction Register 14
Color Correction Register 15
Color Correction Register 16
Color Correction Register 17
Color Correction Register 18
Color Correction Register 19
Color Correction Register 20
Color Correction Register 21
Color Correction Register 22
White Balance Register 4
White Balance Register 5
AWB Tint add-on color
White Balance Register 6
White Balance Register 7
White Balance Register 8
AWB Speed and Color Saturation Control
Horizontal Boundaries of AE Measurement Window
Vertical Boundaries of AE Measurement Window
White Balance Register 9
White Balance Register 10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
IFP Register List
Table 6:
IFP Register List (Continued)
Address
09005aef80e90084
MT9V111_2.fm - Rev. G 1/05 EN
Defaults
Dec
Hex
Dec
Hex
42
43
2A
2B
128
30760
0x0080
0x7828
44
2C
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
74
75
76
77
78
79
82
83
84
85
86
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
4A
4B
4C
4D
4E
4F
52
53
54
55
56
Description
White Balance Register 11
Horizontal Boundaries of AE Measurement Window
for Back Light Compensation
46140
0xB43C Vertical Boundaries of AE Measurement Window
for Back Light Compensation
57504
0xE0A0 Boundaries of AWB Measurement Window
4196
0x1064 AE Target and Accuracy Control
68
0x0044 AE Speed and Sensitivity Control
R/O
White Balance Register 12
R/O
White Balance Register 13
R/O
White Balance Register 14
5230
0x146E Auto Exposure Register 1
16
0x0010 Luminance Offset Control
61456
0xF010 Clipping Limits for Output Luminance
30736
0x7810 Auto Exposure Register 2
768
0x0300 White Balance Register 15
1144
0x0478 Auto Exposure Register 3
680
0x02A8 Auto Exposure Register 4
0
0x0000 Output Format Control 2
1066
0x042A Black Level Register 1
1024
0x0400 Black Level Register 2
4570
0x11DA Auto Exposure Register 5
3327
0x0CFF White Balance Register 16
0
0x0000 Auto Exposure Register 6
7696
0x1E10 Auto Exposure Register 7
5143
0x1417 Auto Exposure Register 8
26128
0x6610 Auto Exposure Register 9
28010
0x6D6A Auto Exposure Register 10
29040
0x7170 Auto Exposure Register 11
29811
0x7473 Auto Exposure Register 12
0
0x0000 Auto Exposure Register 13
24
0x0018 Defect Correction Register 1
0
0x0000 Test Pattern Generator
R/O
Reserved
R/O
Reserved
R/O
Auto Exposure Register 14
R/O
Auto Exposure Register 15
16
0x0010 Reserved
R/O
Reserved
R/O
Reserved
7700
0x1E14 Gamma Correction Register 1
17966
0x462E Gamma Correction Register 2
34666
0x876A Gamma Correction Register 3
47008
0xB7A0 Gamma Correction Register 4
13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
IFP Register List
Table 6:
IFP Register List (Continued)
Address
09005aef80e90084
MT9V111_2.fm - Rev. G 1/05 EN
Defaults
Dec
Hex
Dec
87
88
89
90
91
92
93
94
95
96
97
98
99
100
102
103
104
105-125
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
152
153
154
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
66
67
68
69-8D
7F
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
98
99
9A
57548
0
248
298
2
4366
5137
26684
12296
2
Hex
0xE0CC
0x0000
0x00F8
0x012A
0x0002
0x110E
0x1411
0x683C
0x3008
0x0002
R/O
4112
0x1010
R/O
5499
0x157B
R/O
16400
0x4010
17
0x0011
R/O
N/A
6
0x0006
56588
0xDD0C
1268
0x04F4
15377
0x3C11
57868
0xE20C
758
0x02F6
12817
0x3211
56588
0xDD0C
244
0x00F4
12822
0x3216
34866
0x8832
63453
0xF7DD
15372
0x3C0C
127
0x007F
47646
0x6A1E
63468
0xF7EC
14088
0x3708
100
0x0064
48926
0x6F1E
63470
0xF7EE
12815
0x320F
100
0x0064
1040
0x0410
R/O
R/O
14
Description
Gamma Correction Register 5
Gamma Correction Register 6
Auto Exposure Register 16
Auto Exposure Register 17
Flicker Control
Reserved
Reserved
Color Correction Register 23
Color Correction Register 24
Color Correction Register 25
Reserved
AE Digital Gains
Reserved
Reserved
Reserved
AE Digital Gains Limit
Reserved
Reserved
8-bit Serial Interface Helper
Lens Shading Correction Register 1
Lens Shading Correction Register 2
Lens Shading Correction Register 3
Lens Shading Correction Register 4
Lens Shading Correction Register 5
Lens Shading Correction Register 6
Lens Shading Correction Register 7
Lens Shading Correction Register 8
Lens Shading Correction Register 9
Lens Shading Correction Register 10
Lens Shading Correction Register 11
Lens Shading Correction Register 12
Lens Shading Correction Register 13
Lens Shading Correction Register 14
Lens Shading Correction Register 15
Lens Shading Correction Register 16
Lens Shading Correction Register 17
Lens Shading Correction Register 18
Lens Shading Correction Register 19
Lens Shading Correction Register 20
Lens Shading Correction Register 21
Lens Shading Correction Register 22
Flash Control
Line Counter
Frame Counter
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
IFP Register List
Table 6:
IFP Register List (Continued)
Address
09005aef80e90084
MT9V111_2.fm - Rev. G 1/05 EN
Dec
Hex
155
156
157
158
165
166
167
168
169
170
9B
9C
9D
9E
A5
A6
A7
A8
A9
AA
Defaults
Dec
8
42158
0
640
640
0
480
480
Hex
R/O
0x0008
0xA4AE
R/O
0x0000
0x0280
0x0280
0x0000
0x01E0
0x01E0
15
Description
Reserved
Reserved
Reserved
Reserved
Horizontal Pan In Decimation
Horizontal Zoom In Decimation
Horizontal Output Size In Decimation
Vertical Pan In Decimation
Vertical Zoom In Decimation
Vertical Output Size In Decimation
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
IFP Register Description
IFP Register Description
Table 7:
Register
1
0x01
5
0x05
6
0x06
7
0x07
IFP Register Description
Bits
Default
Name
7:0
1
Register address space selection.
This register controls the address space for the two-wire serial interface communications. Set Reg0x01 = 1 to
select IFP address space and Reg0x01 = 4 for sensor space. Reg0x01 is always accessible regardless of the page
currently selected.
3:0
11
Aperture correction (sharpening).
2:0
3
Sharpening factor:
”000” — no sharpening.
”001” — 25% sharpening.
”010” — 50% sharpening.
”011” — 75% sharpening.
”100” — 100% sharpening.
”101” — 125% sharpening.
”110” — 150% sharpening.
”111” — 200% sharpening.
3
1
Automatically reduces sharpness in low light.
15:0
28686
Operating mode control.
0
1
0
1
3:2
3
4
0
5
6
7
9:8
10
11
12
13
14
15
0
0
0
0
0
0
0
1
1
1
0
0
09005aef80e90084
MT9V111_2.fm - Rev. G 1/05 EN
Reserved.
“1” — enables auto white balance.
“0” — stops AWB at the current values.
Back light compensation:
”00” — AE measurement window is specified by Reg0x26 and Reg0x27 (“large
window”).
“01” — AE measurement window is specified by Reg0x2B and Reg0x2C (“center
window”).
“10” and “11” — AE measurement window is a weighted sum of “large window” and
“center window” with center window given twice the weight.
“1” — bypass color correction matrix.
“0” — normal color processing.
Reserved.
Reserved.
“1” — ITU_R BT.656 synchronization codes are embedded in the image.
N/A
Reserved.
Reserved.
Enable aperture correction knee.
“1” — enables on-the-fly defect correction.
“1” — enable auto exposure.
Reserved.
Image flow processor soft reset.
Asserts reset on all IFP registers.
Example: write Reg0x07 = 1 followed by Reg0x07 = 0 to reset IFP.
16
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©2004 Micron Technology, Inc. All rights reserved.
MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
IFP Register Description
Table 7:
Register
8
0x08
33
0x21
37
0x25
IFP Register Description (Continued)
Bits
Default
Name
15:0
0
51200
0
1
0
2
3
4
5
6
7
8
9
10
11
12
0
0
0
0
0
0
0
0
0
1
0
13
14
15
15:0
0
1
1
0
Output format control.
Toggles the assumption about Bayer CFA (horizontal shift).
“0” — row containing blue comes first.
“1” — row with red comes first.
Toggles the assumption about Bayer CFA (vertical shift).
“0” — green comes first.
“1” — red or blue comes first.
Disable Cr. Forces output Cr = 128 in YCbCr mode and R = 0 in RGB.
Disable Y. Force output Y = 128 in YCbCr mode and G = 0 in RGB.
Disable Cb. Force output Cb = 128 in YCbCr mode and B = 0 in RGB.
Monochrome. Forces Cr=Cb=128 in YCbCr or R,B = G in RGB mode.
N/A
Entire image processing is bypassed and raw 8+2 Bayer data output directly.
“1” — enables lens shading correction.
Inverts output pixel clock.
Reserved.
Enable automatic flicker avoidance.
“1” output mode is RGB.
“0” — output mode is YCbCr. See also Reg0x3A[7:6]. This bit is subject to synchronous
update, see Reg0xA5.
N/A
Reserved.
Reserved.
AWB tint.
7:0
0
Blue channel add-on.
15:8
0
Red channel add-on.
In the AWB mode, this register specifies gain “add-ons” to the values determined by AWB, allowing to
“skew” the overall color of the image.
14:0
17700
AWB speed and color saturation control.
2:0
4
AWB reaction delay:
“000” — fastest.
"111” — slowest.
6:3
4
AWB speed.
“000” — fastest.
"111” — slowest.
10:8
5
Reserved.
13:11
0
U/V saturation. Specify overall attenuation of the color saturation:
”000” — full color saturation.
”001” — 75% of full saturation.
“010” — 50% of full saturation.
”011” — 37.5% of full saturation.
”100” — 25% of full saturation.
”101” — 150% of full saturation.
”110” — black and white.
14
1
“1” — enables automatic color saturation control in low light. The automatic
saturation control acts “in addition” to the saturation specified in Bits13:11.
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MT9V111_2.fm - Rev. G 1/05 EN
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MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
IFP Register Description
Table 7:
Register
38
0x26
39
0x27
43
0x2B
44
0x2C
45
0x2D
46
0x2E
47
0x2F
IFP Register Description (Continued)
Bits
Default
Name
15:0
65283
Horizontal boundaries of AE measurement window.
7:0
3
Left window boundary.
15:8
255
Right window boundary.
This register specifies left and right boundaries of the window used by AE measurement engine. The values
programmed in the registers are desired boundaries divided by four.
15:0
65296
Vertical boundaries of AE measurement window.
7:0
16
Bottom window boundary.
15:8
255
Top window boundary.
This register specifies top and bottom boundaries of the window used by AE
measurement engine. The values programmed in the registers are desired boundaries
divided by two.
15:0
30760
Horizontal boundaries of AE measurement window for back light compensation.
7:0
40
Left window boundary.
15:8
120
Right window boundary.
This register specifies left and right boundaries of the window used by AE
measurement engine in backlight compensation mode, see Reg6[3:2]. The values
programmed in the registers are desired boundaries divided by four.
15:0
46140
Vertical boundaries of AE measurement window for back light compensation.
7:0
60
Top window boundary.
15:8
180
Bottom window boundary.
This register specifies top and bottom boundaries of the window used by AE measurement engine in
backlight compensation mode, see Reg6[3-2]. The values programmed in the registers are desired boundaries
divided by two.
15:0
57504
Boundaries of AWB measurement window.
3:0
0
Left window boundary.
7:4
10
Right window boundary.
11:8
0
Top window boundary.
15:12
14
Bottom window boundary.
This register specifies the boundaries of the window used by AWB measurement engine. The values
programmed in the registers are desired boundaries divided by 32 for vertical limits and by 64 for horizontal.
15:0
4196
Auto exposure target and accuracy control.
7:0
100
Target luminance.
15:8
16
Tracking accuracy.
This register specifies luminance target of the auto exposure algorithm and the size of the margin around the
target in which no AE adjustment is made.
7:0
68
Auto exposure speed and sensitivity control.
2:0
4
AE reaction delay:
“000” — fastest.
"111” — slowest.
5:3
0
AE speed:
“000” — fastest.
"111” — slowest.
7:6
0
AE step size:
“00” — medium speed when going down, slow when going up.
”01” — medium speed.
”10” — fast speed.
”11” — fast when going down, medium when going up.
09005aef80e90084
MT9V111_2.fm - Rev. G 1/05 EN
18
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MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
IFP Register Description
Table 7:
Register
52
0x34
53
0x35
58
0x3A
72
0x48
91
0x5B
98
0x62
103
0x67
IFP Register Description (Continued)
Bits
Default
Name
15:0
16
Luminance offset control. Use this register to adjust LCD brightness.
7:0
16
Y offset in YCbCr mode.
15:8
0
Offset in RGB mode.
This register specifies constant offset added to the luminance or RGB components prior to the output. Use
this register to adjust LCD brightness.
15:0
61456
Clipping limits for output luminance.
7:0
16
Lowest value of output luminance.
15:8
240
Highest value of output luminance.
This register specifies upper and low limits to which the output YCbCr data is clipped.
7:0
0
Output format control 2.
0
0
In YUV output mode swaps Cb and Cr channels. In RGB, swaps R and B. This bit is
subject to synchronous update.
1
0
Swap chrominance byte with luminance byte in YCbCr/YUV output. In RGB, swap odd
and even bytes. This bit is subject to synchronous update.
2
0
Average two nearby chrominance bytes.
4:3
0
Test ramp output:
“00” — off.
“01” — by column.
“10” — by row.
“11” — by frame.
5
0
Output R,G,B or Cr,Y,Cb values are shifted 3 bits up; use with Reg0x3A[4:3] to test LCDs
with low color depth.
7:6
0
RGB output format:
“00” = 16-bit RGB565.
”01” = 15-bit RGB555.
“10” = 12-bit RGB444.
“11” = 12-bit RGBx444.
7:0
0
Test pattern generator.
2:0
0
Test pattern selection.
7
0
“1” — force WB digital gains to 1.0.
This register enables color bar test-pattern generation at the input of the image processor. Values greater
than "0" turn test pattern generation on. The brightness of the flat-color areas depends on the value
programmed in this register.
2:0
2
Flicker control.
0
0
“1”— manual mode.
“0” — auto flicker detection.
1
1
If R0x5B [0] = “1” then '“0”- 50Hz AC; “1”- 60Hz AC.
15:0
4112
AE digital gains.
7:0
16
Current digital gain applied before lens shading correction.
15:8
16
Current digital gain applied during lens shading correction.
When R6 [14] = 1, registers are read-only and show current digital gains. When R6 [14] = 0, writing into
registers sets current digital gains. LC digital gain, R98 [15:8], is unity if LC is disabled, R8 [8] = 0. The
combined gain of R98 [15:8] and LC must be less than 16. See also R103.
15:0
16400
AE digital gains limits.
7:0
16
Maximal digital gain applied before lens shading correction.
15:8
64
Maximal digital gain applied during lens shading correction.
Value 16 corresponds real digital gain of 1.0. As AE increases gain in dark conditions, pre-LC gain is used first.
Post-LC gain is used only after pre-LC gain reaches its maximum allowed limit. See also R98.
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MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
IFP Register Description
Table 7:
Register
127
0x7F
152
0x98
153
0x99
154
0x9A
165
0xA5
166
0xA6
IFP Register Description (Continued)
Bits
Default
Name
7:0
0
Eight-bit, Two-wire serial interface helper.
Internal MT9V111 registers are up to 16-bit wide. To execute 16-bit reads and writes, eight-bit two-wire serial
interface devices need special handling by using Reg0x7F. A 16-bit write is done by writing the upper eight
bits to the desired register and then writing the lower eight bits to Reg0x7F. The register is not updated until
all 16 bits have been written. It is not possible to just update half a register. To read eight-bytes at a time,
read the upper eight bits from the desired register; then read the lower eight bits from Reg0x7F.
15:0
1040
Flash control.
7:0
16
Strobe duration, x512 CLK_IN. Value of 255 is special, enabling infinite duration.
8
0
Invert pin state.
9
0
“1” = fire every frame continuously.
“0” = fire only once per arming.
10
1
Strobe source select.
“1” = end of shutter enable.
“0” = end of frame enable.
12:11
0
Delay; skips programmed number of frames after arming and before firing.
13
0
Write “1” to arm flash and set it to fire. Flash will fire after delay set in Reg0x98 [12-11].
14
R/O
“1” = Flash has fired in current frame.
15
R/O
State of the output flash pin.
The flash control supports both Xenon and LED light sources using a dedicated output pad. For Xenon flashes
the pad generates a strobe to fire when the imager's shutter is fully open. For LED the pad can be asserted or
de-asserted asynchronously. To turn LED off and on program Reg0x98 [8]. To fire a Xenon flash, arm the
strobe trigger by setting Reg0x98 [13]=1. The strobe will appear when the shutter fully opens. Strobe length
is set by Reg0x98 [7-0]. Other available modes include continuous vs. single firing and skipping a
programmable number of frames after arming and before firing.
12:0
R/O
Line counter.
Use line counter to determine the number of line currently being output.
15:0
R/O
Frame counter.
Use frame counter to determine number of frames output so far.
15:0
0
Horizontal pan in decimation.
9:0
0
Horizontal pan.
15
W/O
“1” = freeze update of decimation parameters.
Decimation control registers work to downsize output image to any size. The output image size is specified in
Reg0xA7 and Reg0xAA for horizontal and vertical directions respectively. For example, to downsize the VGA
output to QQVGA set Reg0xA7 = 160 and Reg0xAA = 20. Whenever output image is downsized, the zoom
feature becomes available. To zoom in, program Reg0xA6 and Reg0xA9 with the size of window to be
decimated. For example, in QQVGA setting Reg0xA6 = 320 and Reg0xA9 = 240 results in 2X zoom. Here the
output image of 160 x 120 is created from a pre-decimation window of 320 x 240 instead of the full VGA 640
x 480. Whenever the output image is zoomed, pan controls become available. To pan a zoomed image
program Reg0xA5 and Reg0xA8 to offset the pre-decimation window in to the right and bottom respectively.
When implementing a smooth zoom and pan, it is useful to synchronize the update of all decimation
registers to avoid jerks in the output video. When writing a batch of decimation settings, set bit 15 of each
datum to”1” to freeze the update. Set bit 15 of the last datum in the batch to “0” to enable normal
operation. The entire batch of decimation settings will then be synchronously loaded on the next frame start.
15:0
640
Horizontal zoom in decimation.
9:0
640
Horizontal size of window before decimation.
15
W/O
“1” = freeze update of decimation parameters.
See R0xA5 for details.
09005aef80e90084
MT9V111_2.fm - Rev. G 1/05 EN
20
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©2004 Micron Technology, Inc. All rights reserved.
MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
IFP Register Description
Table 7:
Register
167
0xA7
168
0xA8
169
0xA9
170
0xAA
IFP Register Description (Continued)
Bits
Default
Name
15:0
640
Horizontal output size in decimation.
9:0
640
Horizontal size of output image.
15
W/O
“1” = freeze update of decimation parameters.
See R0xA5 for details.
15:0
0
Vertical pan in decimation.
8:0
0
Vertical pan.
15
W/O
“1” = freeze update of decimation parameters.
See R0xA5 for details.
15:0
480
Vertical zoom in decimation.
8:0
480
Vertical size of window before decimation.
15
W/O
“1” = freeze update of decimation parameters.
See R0xA5 for details.
15:0
480
Vertical output size in decimation.
8:0
480
Vertical size of output image.
15
W/O
“1” = freeze update of decimation parameters.
See R0xA5 for details.
09005aef80e90084
MT9V111_2.fm - Rev. G 1/05 EN
21
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
Sensor Core Overview
Sensor Core Overview
The sensor consists of a pixel array of 668 x 496 total, analog readout chain, 10-bit ADC
with programmable gain and black offset, and timing and control.
Note: See Sensor Core (MT9V011) data sheet for more details.
Figure 6: Sensor Core Block Diagram
Control Register
Active Pixel
Sensor Array
Communication
Bus to IFP
Timing and Control
Clock
Sync. Signals
Analog Processing
10-bit Data
to IFP
ADC
The sensor core’s pixel array is configured as 668 columns by 496 rows (shown in
Figure 7). The first 18 columns and the first 6 rows of pixels are optically black and can
be used to monitor the black level. The last column and the last row of pixels are also
optically black. The black row data is used internally for the automatic black level adjustment. There are 649 columns by 489 rows of optically active pixels, which provides a
four-pixel boundary around the VGA (640 x 480) image to avoid boundary affects during
color interpolation and correction. The additional active column and additional active
row are used to allow horizontally and vertically mirrored readout to also start on the
same color pixel, as shown in Figure 7.
Figure 7: Pixel Array Description
(0, 0)
6 black rows
1 black column
VGA (640 x 480)
+ 4 pixel boundary for
color correction
+ additional active column
+ additional active row
= 649 x 489 active pixels
(667,495)
18 black columns
1 black row
The sensor core uses the RGB Bayer color pattern (shown in Figure 8). Even-numbered
rows contain green and red color pixels, and odd-numbered rows contain blue and
green color pixels. Even-numbered columns contain green and blue color pixels; oddnumbered columns contain red and green color pixels.
09005aef80e90084
MT9V111_2.fm - Rev. G 1/05 EN
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©2004 Micron Technology, Inc. All rights reserved.
MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
Sensor Core Overview
Figure 8: Pixel Color Pattern Detail (Top Right Corner)
column readout direction
..
.
row
readout
direction
...
black pixels
G
R
G
R
G
R
G
B
G
B
G
B
G
B
G
R
G
R
G
R
G
B
G
B
G
B
G
B
G
R
G
R
G
R
G
B
G
B
G
B
G
B
Pixel
(18,6)
(First Optical
clear pixel)
..
.
The sensor core image data is read-out in a progressive scan. Valid image data is surrounded by horizontal and vertical blanking, as shown in Figure 9. The amount of horizontal and vertical blanking is programmable through the sensor core registers Reg0x05
and Reg0x06, respectively. LINE_VALID is HIGH during the shaded region of the figure.
See “Appendix A – Sensor Timing” on page 35 for the description of FRAME_VALID timing.
Figure 9: Spatial Illustration of Image Readout
P0,0 P0,1 P0,2.....................................P0,n-1 P0,n
P1,0 P1,1 P1,2.....................................P1,n-1 P1,n
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
VALID IMAGE
HORIZONTAL
BLANKING
Pm-1,0 Pm-1,1.....................................Pm-1,n-1 Pm-1,n 00 00 00 .................. 00 00 00
Pm,0 Pm,1.....................................Pm,n-1 Pm,n
00 00 00 .................. 00 00 00
09005aef80e90084
MT9V111_2.fm - Rev. G 1/05 EN
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
VERTICAL BLANKING
VERTICAL/HORIZONTAL
BLANKING
00 00 00 ..................................... 00 00 00
00 00 00 ..................................... 00 00 00
00 00 00 .................. 00 00 00
00 00 00 .................. 00 00 00
23
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©2004 Micron Technology, Inc. All rights reserved.
MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
Sensor Core Registers
Sensor Core Registers
Table 8:
Sensor Core Register List
Register
09005aef80e90084
MT9V111_2.fm - Rev. G 1/05 EN
Default Value
Dec
Hex
Description
Dec
Hex
0
1
2
3
4
5
6
7
8
9
10
11
12
13
18
19
30
32
33
34
39
40
43
44
45
46
47
48
49
50
51
52
53
54
55
59
60
61
62
63
64
65
66
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0X08
0x09
0x0A
0x0B
0x0C
0x0D
0x12
0x13
0x1E
0x20
0x21
0x22
0x27
0x28
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
Reserved
Register Address Select
Column Start1
Window Height1
Window Width1
Horizontal Blanking
Vertical Blanking1
Output Control1
Row Start1
Shutter Width2
Reserved
Reserved
Shutter Delay2
Reserved
2X Zoom Col Start
2X Zoom Row Start
Digital Zoom
Read Mode
Reserved
Reserved
Reserved
Reserved
Green1 Gain2
Blue Gain2
Red Gain2
Green2 Gain2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Global Gain2
Chip Version (R/O)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1
18
487
647
38
4
12306
6
248
0
0
0
0
176
124
0
4096
0
0
36
0
32
32
32
32
63408
30725
42
0
12303
256
32
33338
10
0x01
0x0012
0x01E7
0x0287
0x0026
0x0004
0x3012
0x0006
0x00F8
0x0000
0x0000
0x0000
0x0000
0x00B0
0x007C
0x0000
0x1000
0x0000
0x0000
0x0024
0x0000
0x0020
0x0020
0x0020
0x0020
0xF7B0
0x7805
0x002A
0x0000
0x300F
0x0100
0x0020
0x823A
0x000A
24
N/A
2080
1679
0x0820
0x068F
N/A
1696
480
209
2178
0x06A0
0x01E0
0x00D1
0x0882
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
Sensor Core Registers
Table 8:
Sensor Core Register List (Continued)
Register
Default Value
Dec
Hex
Description
Dec
Hex
88
89
90
91
92
93
94
95
96
97
98
99
100
101
241
247
248
249
250
251
252
253
255
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x60
0x61
0x62
0x63
0x64
0x65
0xF1
0xF7
0xF8
0xF9
0xFA
0xFB
0xFC
0xFD
0xFF
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Chip Version (R/O)
248
1859
1063
0x00F8
0x0743
0x0427
R/O
R/O
R/O
R/O
41757
0
0
1048
0
0
0
1
0xA31D
0x0000
0x0000
0x0418
0x0000
0x0000
0x0000
0x0001
R/O
R/O
44
0x002C
R/O
R/O
R/O
R/O
33338
0x823A
Notes: 1. Do not change these registers. Contact Micron support for settings different from
defaults.
2. IFP controls these registers when AE, AWE, or flicker avoidance are enabled.
09005aef80e90084
MT9V111_2.fm - Rev. G 1/05 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
Sensor Core Registers
Table 9:
Register
(Dec)
(Hex)
Sensor Core Register Description
Bit
Description
Register Address Selector
1
0
Selects the IFP/SOC registers (0–170).
0X01
001= Select IFP registers—default = 0x01.
2
Selects the core registers (0–255).
100 = Select core registers.
Window Control
These registers control the size of the window. Register values are one less than actual height and width.
2
9:0 First column to be read out—default = 0x0012 (18).
0x02
See Reg0x08 for row adjustment.
3
8:0 Window height (number of rows - 1)—default = 0x01E7 (487).
0x03
4
9:0 Window width (number of columns - 1)—default = 0x0287 (647).
0x04
Minimum value for Reg0x04 = 0x0009.
Blanking Control
These registers control the blanking time in a row (called column fill-in or horizontal blanking) and between frames
(vertical blanking). Horizontal blanking is specified in terms of pixel clocks. Vertical blanking is specified in terms of row
readout times. Register values are one less than actual height and width.
5
9:0 Horizontal blanking (number of columns)—default = 0x0026 (38 pixel clocks).
0x05
Minimum value for Reg0x05 = 0x009.
6
11:0 Vertical Blanking (number of rows -1)—default = 0x0004 (4 rows).
0x06
Minimum recommended value for Reg0x06 = 0x0003.
Output Control
This register controls various features of the output format for the sensor.
7
1:0 Reserved.
0x07
4
Controls internal sampling time. This must be “0” when CLK_IN frequency is greater than 13.5 MHz.
15:5 Reserved.
Row Start
8
8:0 First row to be read out—default = 0x0006 (6).
0x08
Minimum value for Reg0x08 = 0x0004.
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MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
Sensor Core Registers
Table 9:
Register
(Dec)
(Hex)
Sensor Core Register Description (Continued)
Bit
Description
Pixel Integration Control
These registers (along with the window sizing and blanking registers) control the integration time for the pixels.
Reg0x09: number of rows of integration
Reg0x0C: reset delay, default = 0x0000 (0). This is the number of master clocks that the timing and control logic waits
before asserting the reset for a given row.
The actual total integration time, tINT, is:
tINT = Reg0x09 x Row Time - Overhead Time - Reset Delay, where:
Row Time = (Reg0x04 + 1 + 113 + Reg0x05) x 2 master clock periods
Overhead Time = K x 57 master clock periods
Reset Delay = K x Reg0x0C master clock periods
If the value in Reg0x0C exceeds (row time - 444)/K master clock cycles, the row time will be extended by (K x Reg0x0C (row time - 444)) clock cycles
where
K = 4 when Reg0x07[4] = 0 and
K = 2 when Reg0x07[4] = 1
In this expression the row time term corresponds to the number of rows integrated. The overhead time is the time
between the READ cycle and the RESET cycle, and the final term is the effect of the reset delay. Typically, the value of
Reg0x09 is limited to the number of rows per frame (which includes vertical blanking rows), such that the frame rate is not
affected by the integration time. If Reg0x09 is increased beyond the total number of rows per frame, the MT9V111 will
add additional blanking rows as needed.
9
11:0 Number of rows of integration—default = 0x00F8 (248).
0x09
Shutter Delay
12
9:0
Default = 0x0000 (0). This is the number of master clocks x K that the timing and control logic waits
0x0C
before asserting the reset for a given row.
Reset (Soft)
13
0
This register is used to reset the sensor to its default, power-up state. To reset, first write a “1” into bit
0x0D
0 of this register to put the MT9V111 in reset mode, then write a "0" into bit 0 to resume operation.
2X Zoom
18
9:0 Address of starting column in 2X zoom mode. Bit 0 of Reg0x1E must be set.
0x12
19
8:0 Address of starting row in 2X zoom mode. Bit 0 of Reg0x1E must be set.
0x13
30
0
Zoom by 2X. This bit must be set when using Reg0x12 and Reg0x13.
0x1E
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MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
Sensor Core Registers
Table 9:
Register
(Dec)
(Hex)
Sensor Core Register Description (Continued)
Bit
Description
Read Mode
This register is used to control many aspects of the readout of the sensor.
32
To preserve a right-reading image and the correct color order, all four of these bits should be set to “1” to
0x20
invert the image.
5
1 = readout starting 1 column later.
0 = normal readout.
7
1 = readout starting 1 row later.
0 = normal readout.
14 1 = read out from right to left (mirrored).
0 = normal readout.
15 1 = read out from bottom to top (upside down).
0 = normal readout.
Gain Settings
The gain is individually controllable for each color in the Bayer pattern as shown in the register chart. Formula for gain
setting:
Gain = (Bit [8] + 1) x (Bit [7] + 1) x (Bit [6–0] x 0.03125)
Since Bit [7] and Bit [8] of the gain registers are multiplicative factors for the gain settings, there are alternative ways of
achieving certain gains. Some settings offer superior noise performance to others, despite the same overall gain.
The following lists the recommended gain settings:
Increments
Recommended Settings
Gain
1.000 to 1.969
0.03125
0x020 to 0x03F
2.000 to 7.938
0.0625
0x0A0 to 0x0FF
8.000 to 15.875
0.125
0x1C0 to 0x1FF
43
Green1 gain—default = 0x0020 (32) = 1x gain.
0x2B
6:0 Initial Gain = bits (6:0) x 0.03125.
7, 8 Analog Gain = (bit 8 + 1) x (bit 7 + 1) x initial gain (each bit gives 2x gain).
9,10 Total Gain = (bit 9 + 1) x (bit 10 + 1) x analog gain (each bit gives 2x gain).
44
Blue Gain—default = 0x0020 (32) = 1x gain.
0x2C
6:0 Initial Gain = bits (6:0) x 0.03125.
7, 8 Analog Gain = (bit 8 + 1) x (bit 7 + 1) x initial gain (each bit gives 2x gain).
9,10 Total Gain = (bit 9 + 1) x (bit 10 + 1) x analog gain (each bit gives 2x gain).
45
Red Gain—default = 0x0020 (32) = 1x gain.
0x2D
6:0 Initial Gain = bits (6:0) x 0.03125.
7, 8 Analog Gain = (bit 8 + 1) x (bit 7 + 1) x initial gain (each bit gives 2x gain.)
9,10 Total Gain = (bit 9 + 1) x (bit 10 + 1) x analog gain (each bit gives 2x gain).
46
Green2 Gain—default = 0x0020 (32) = 1x gain.
0x2E
6:0 Initial Gain = bits (6:0) x 0.03125.
7, 8 Analog Gain = (bit 8 + 1) x (bit 7 + 1) x initial gain each bit gives 2x gain).
9,10 Total gain = (bit 9 + 1) x (bit 10 + 1) x analog gain (each bit gives 2x gain).
Global Gain
53
Global Gain—default = 0x0020 (32) = 1x gain. This register can be used to set all four gains at once.
0x35
When read, it will return the value stored in Reg0x2B.
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MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
Sensor Core Registers
Table 9:
Register
(Dec)
(Hex)
Sensor Core Register Description (Continued)
Bit
6:0
7, 8
9,10
Chip Version
54
15:0
0x36
255
15:0
0xFF
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Description
Initial Gain = bits (6:0) x 0.03125
Analog Gain = (bit 8 + 1) x (bit 7 + 1) x initial gain (each bit gives 2x gain).
Total Gain = (bit 9 + 1) x (bit 10 + 1) x analog gain (each bit gives 2x gain).
This read-only register contains the chip identification number. Reg0xFF (255) is a repeat of this
register.
Mirrors the chip identification in Reg0x36.
29
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MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
Electrical Specifications
Electrical Specifications
The recommended die operating temperature ranges from -20°C to +40°C. The sensor
image quality may degrade above +40°C.
Table 10: DC Electrical Characteristics
VDD = VAA = 2.8 ± 0.25V; TA = 25°C
Symbol
Definition
VIH
VIL
IIN
Input High Voltage
Input Low Voltage
Input Leakage Current
VOH
VOL
IOH
IOL
IOZ
IAA
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Tri-state Output Leakage Current
Analog Operating Supply Current
IDD
Digital Operating Supply Current
IAA Standby Analog Standby Supply Current
IDD Standby Digital Standby Supply Current
Condition
MIN
TYP
VDD - 0.25
-0.3
No Pull-up Resistor; VIN = VDD or
-5
DGND
VDD - 0.2
Default settings, CLOAD = 10pF
CLKIN = 12 MHz
CLKIN = 27 MHz
Default settings, CLOAD = 10pF
CLKIN = 12 MHz
CLKIN = 27 MHz
STDBY = VDD
STDBY = VDD
MAX
Unit
VDD + 0.25
0.8
5.0
V
V
µA
0.2
15.0
20.0
5.0
V
V
mA
mA
µA
10.0
10.0
20.0
20.0
25.0
25.0
mA
5.0
10.0
0.0
0.0
8.0
15.0
2.5
2.5
20.0
20.0
5.0
5.0
mA
µA
µA
Notes: 1. To place the chip in standby mode, first raise STANDBY to VDD, then wait two master clock
cycles before turning off the master clock. Two master clock cycles are required to place
the analog circuitry into standby, low-power mode.
2. When STANDBY is de-asserted, standby mode is exited immediately (within several master
clocks), but the current frame and the next two frames will be invalid. The fourth frame
will contain a valid image.
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MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
Electrical Specifications
Table 11: AC Electrical Characteristics
VDD = VAA = 2.8 ± 0.25V; TA = 25°C
Symbol
fCLKIN
t
R
tF
t
PLHP
t
PHLP
t
DSETUP
tDHOLD
tDSETUP
tDHOLD
tOH
tPLHF,L
tPHLF,L
tOUTR
tOUTF
Definition
Condition
Input Clock Frequency
Clock Duty Cycle
Input Clock Rise Time
Input Clock Fall Time
CLKIN to PIXCLK propagation delay:
LOW-to-HIGH
HIGH-to-LOW
PIXCLK to DOUT(7:0) at 27 MHz
Setup Time
Hold Time
PIXCLK to DOUT(7:0) at 12 MHz
Setup Time
Hold Time
Data Hold Time from PIXCLK falling edge
CLKIN to FRAME_VALID and LINE_VALID propagation
delay:
LOW-to-HIGH
HIGH-to-LOW
Output Rise Time
Output Fall Time
MIN
45
TYP
MAX
Unit
12
50
2.0
2.0
27
55
MHz
%
ns
ns
CLOAD = 10pF
12
10
ns
13.0
13.0
ns
25.0
25.0
9.0
ns
CLOAD = 10pF
CLOAD = 10pF
ns
CLOAD = 10pF
ns
CLOAD = 10pF
CLOAD = 10pF
9.0
7.5
7.0
9.0
ns
ns
Notes: 1. For 30 fps operation with a 27 MHz clock, it is very important to have a precise duty cycle
equal to 50%. With a slower frame rate and a slower clock the clock duty cycle can be
relaxed.
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MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
Propagation Delays
Propagation Delays
Propagation Delays for PIXCLK and Data Out Signals
The typical output delay, relative to the master clock edge, is 7.5 ns. Note that the data
outputs change on the falling edge of the master clock, with the pixel clock rising on the
subsequent rising edge of the master clock.
Propagation Delays for FRAME_VALID and LINE_VALID Signals
The LINE_VALID and FRAME_VALID signals change on the same falling master clock
edge as the data output. The LINE_VALID goes HIGH on the same falling master clock
edge as the output of the first valid pixel's data and returns LOW on the same master
clock falling edge as the end of the output of the last valid pixel's data.
As shown in Figure 12, Data Output Timing Diagram, on page 33, FRAME_VALID goes
HIGH 6 pixel clocks prior to the time that the first LINE_VALID goes HIGH. It returns
LOW at a time corresponding to 6 pixel clocks after the last LINE_VALID goes LOW.
Figure 10: Propagation Delays for PIXCLK and Data Out Signals
tR
tF
CLKIN
tPLHP
tPHLP
PIXCLK
tPLHD, tPHLD
DOUT (7:0)
DOUT (7:0)
DOUT (7:0)
tOH
DOUT (7:0)
DOUT (7:0)
Figure 11: Propagation Delays for FRAME_VALID and LINE_VALID Signals
tPLHF,L
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tPHLF,L
CLKIN
CLKIN
FRAME_VALID
LINE_VALID
FRAME_VALID
LINE_VALID
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MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
Propagation Delays
Figure 12: Data Output Timing Diagram
PIXCLK
FRAME_VALID
tLVHOLD
tLVSETUP
LINE_VALID
DOUT(7:0)
tFVHOLD
tFVSETUP
tDSETUP
Cb0 Y0
Cr0 Y1
Ylast
Cb0
Ylast
Cb0
tDHOLD
Note:
PIXCLK = MAX 27 MHz
= / setup time for FRAME_VALID before rising edge of PIXCLK / = 18ns
tFVHOLD = / hold time for FRAME_VALID after rising edge of PIXCLK / = 18ns
tLVSETUP = / setup time for LINE_VALID before rising edge of PIXCLK / = 18ns
tLVHOLD = / hold time for LINE_VALID after rising edge of PIXCLK / = 18ns
tDSETUP = / setup time for DOUT before rising edge of PIXCLK / = 13ns
tDHOLD = / hold time for DOUT after rising edge of PIXCLK / = 13ns
Frame start: FF00 00A0
Line start: FF00 0080
Line end: FF00 0090
Frame end: FF00 00B0
tFVSETUP
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MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
Propagation Delays
Figure 13: Spectral Response
Relative Response
1.2
Blue
Green (B)
Green (R)
1.0
Relative Response
Red
0.8
0.6
0.4
0.2
0.0
350
450
550
650
750
850
950
1050
Wavelength (nm)
Figure 14: Die Center - Image CenterOffset
- Direction
+ Direction
0
11.0um
Die
Center
+ Direction
ARRAY
0
-91.3um
- Direction
Pixel Array Center
Pixel (0, 0)
Note:
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Not to scale.
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MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
Appendix A – Sensor Timing
Appendix A – Sensor Timing
Figure 15: Row Timing and FRAME_VALID/LINE_VALID Signals
...
FRAME_VALID
...
LINE_VALID
...
Number of master clocks
Note:
P1
A
Q
A
Q
A
P2
The signals in Figure 15 are defined in Table 12.
Table 12: Frame Time
Parameter
Name
Equation (Master Clocks)
A
Active Data Time
(Reg0x04 - 7) x 2
P1
Frame Start Blanking
(Reg0x05 + 112) x 2
P2
Frame End Blanking
14 CLKS
Q
Horizontal Blanking
(Reg0x05 + 121) x 2
(MIN Reg0x05 value = 9)
A+Q
Row Time
(Reg0x04 + Reg0x05 +114) x 2
V
Vertical Blanking
(Reg0x06 + 9) x (A + Q) + (Q - P1 - P2)
Nrows x (A + Q) Frame Valid Time
(Reg0x03 - 7) x (A + Q) - (Q - P1 - P2)
F
(Reg0x03 + Reg0x06 + 2) x (A + Q)
Total Frame Time
Note:
Default Timing
At 12 MHz
= 1,280 pixel clocks
= 1,280 master clocks
= 106.7us
= 300 pixel clocks
= 300 master clocks
= 25.0us
= 14 pixel clocks
= 14 master clocks
= 1.17us
= 318 pixel clocks
= 318 master clocks
= 26.5us
= 1,598 pixel clocks
= 1,598 master clocks
= 133.2us
= 20, 778 pixel clocks
= 20,778 master clocks
= 1.73ms
= 767,036 pixel clocks
= 767,036 master clocks
= 63.92ms
= 787,814 pixel clocks
= 787,814 master clocks
= 65.65ms
In order to avoid flicker, frame time is 65.65ms.
Sensor timing is shown above in terms of master clock cycle. The vertical blanking and
total frame time equations assume that the number of integration rows (bits 11 through
0 of Reg0x09) is less than the number of active row plus blanking rows (Reg0x03 + 1 +
Reg0x06 + 1). If this is not the case, the number of integration rows must be used instead
to determine the frame time, as shown in Table 13.
Table 13: Frame Time—Larger than One Frame
Parameter
Name
Equation (Master Clocks)
Default Timing
V’
Vertical Blanking (long integration time)
(Reg0x09 - Reg0x03) x (A + Q)
F’
Total Frame Time (long integration time)
(Reg0x09 + 1) x (A + Q)
–
–
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MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
Serial Bus Description
Serial Bus Description
Registers are written to and read from the MT9V111 through the two-wire serial interface bus. The sensor is a serial interface slave and is controlled by the serial clock (SCLK),
which is driven by the serial interface master. Data is transferred into and out of the
MT9V111 through the serial data (SDATA) line. The SDATA line is pulled up to 2.8V offchip by a 1.5KΩ resistor. Either the slave or master device can pull the SDATA line down—
the serial interface protocol determines which device is allowed to pull the SDATA line
down at any given time. The registers are 16 bits wide and can be accessed through 16bit or eight-bit two-wire serial bus sequences.
Protocol
The two-wire serial interface defines several different transmission codes, as follows:
• a start bit
• the slave device eight-bit address. SADDR is used to select between two different
addresses in case of conflict with another device. If SADDR is LOW, the slave address is
0x90; if SADDR is HIGH, the slave address is 0xB8.
• a(n) (no) acknowledge bit
• an eight-bit message
• a stop bit
Sequence
A typical read or write sequence begins by the master sending a start bit. After the start
bit, the master sends the slave device's eight-bit address. The last bit of the address
determines if the request will be a read or a write, where a "0" indicates a write and a "1"
indicates a read. The slave device acknowledges its address by sending an acknowledge
bit back to the master.
If the request was a write, the master then transfers the 8-bit register address to which a
write should take place. The slave sends an acknowledge bit to indicate that the register
address has been received. The master then transfers the data eight bits at a time, with
the slave sending an acknowledge bit after each 8 bits. The MT9V111 uses 16-bit data for
its internal registers, thus requiring two eight-bit transfers to write to one register. After
16 bits are transferred, the register address is automatically incremented, so that the
next 16 bits are written to the next register address. The master stops writing by sending
a start or stop bit.
A typical read sequence is executed as follows. First the master sends the write-mode
slave address and eight-bit register address, just as in the write request. The master then
sends a start bit and the read-mode slave address. The master then clocks out the register data eight bits at a time. The master sends an acknowledge bit after each eight-bit
transfer. The register address is auto-incremented after every 16 bits is transferred. The
data transfer is stopped when the master sends a no-acknowledge bit.
The MT9V111 allows for eight-bit data transfers through the two-wire serial interface by
writing (or reading) the most significant eight bits to the register and then writing (or
reading) the least significant eight bits to Reg0x7F (127).
Bus Idle State
The bus is idle when both the data and clock lines are HIGH. Control of the bus is initiated with a start bit, and the bus is released with a stop bit. Only the master can generate
the start and stop bits.
Start Bit
The start bit is defined as a HIGH-to-LOW transition of the data line while the clock line
is HIGH.
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MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
Serial Bus Description
Stop Bit
The stop bit is defined as a LOW-to-HIGH transition of the data line while the clock line
is HIGH.
Slave Address
The 8-bit address of a two-wire serial interface device consists of seven bits of address
and 1 bit of direction. A “0” in the least significant bit (LSB) of the address indicates write
mode, and a “1” indicates read mode. The write address of the sensor is 0xB8, while the
read address is 0xB9; this only applies when SADDR is set HIGH.
Data Bit Transfer
One data bit is transferred during each clock pulse. The serial interface clock pulse is
provided by the master. The data must be stable during the HIGH period of the serial
clock—it can only change when the two-wire serial interface clock is LOW. Data is transferred eight bits at a time, followed by an acknowledge bit.
Acknowledge Bit
The master generates the acknowledge clock pulse. The transmitter (which is the master
when writing, or the slave when reading) releases the data line, and the receiver indicates an acknowledge bit by pulling the data line LOW during the acknowledge clock
pulse.
No-Acknowledge Bit
The no-acknowledge bit is generated when the data line is not pulled down by the
receiver during the acknowledge clock pulse. A no-acknowledge bit is used to terminate
a read sequence.
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MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
Two-wire Serial Interface Sample Write and Read Sequences
Two-wire Serial Interface Sample Write and Read Sequences
(with SADDR = 1)
16-Bit Write Sequence
A typical write sequence for writing 16 bits to a register is shown in Figure 16. A start bit
given by the master, followed by the write address, starts the sequence. The image sensor will then give an acknowledge bit and expects the register address to come first, followed by the 16-bit data. After each eight-bit the image sensor will give an acknowledge
bit. All 16 bits must be written before the register will be updated. After 16 bits are transferred, the register address is automatically incremented, so that the next 16 bits are
written to the next register. The master stops writing by sending a start or stop bit.
Figure 16: Timing Diagram Showing a Write to Reg0x09 with Value 0x0284
SCLK
SDATA
Reg0x09
0xB8 ADDR
START
ACK
0000 0010
ACK
1000 0100
ACK
STOP
ACK
16-Bit Read Sequence
A typical read sequence is shown in Figure . First the master has to write the register
address, as in a write sequence. Then a start bit and the read address specifies that a read
is about to happen from the register. The master then clocks out the register data eight
bits at a time. The master sends an acknowledge bit after each eight-bit transfer. The
register address is auto-incremented after every 16 bits is transferred. The data transfer
is stopped when the master sends a no-acknowledge bit.
Figure 17: Timing Diagram Showing a Read from Reg0x09; Returned Value 0x0284
SCLK
SDATA
0xB8 ADDR
START
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Reg 0x09
ACK
0xB9 ADDR
ACK
0000 0010
ACK
38
1000 0100
ACK
STOP
NACK
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MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
Two-wire Serial Interface Sample Write and Read Sequences
Eight-Bit Write Sequence
All registers in the camera are treated and accessed as 16-bit, even when some registers
do not have all 16-bits used. However, certain hosts only support 8-bit serial communication access. The camera provides a special accommodation for these hosts.
To be able to write one byte at a time to the register a special register address is added.
The 8-bit write is done by first writing the upper 8 bits to the desired register and then
writing the lower 8 bits to the special register address (Reg0x7F). The register is not
updated until all 16 bits have been written. It is not possible to just update half of a register. In Figure 18, a typical sequence for 8-bit writing is shown. The second byte is written
to the special register (Reg0x7F).
Figure 18: Timing Diagram Showing a Bytewise Write to Reg0x09 with Value
0x0284
SCLK
SDATA
0xB8 ADDR
0000 0010
Reg0x09
0xB8 ADDR
1000 0100
Reg0x7F
STOP
START
START
ACK
ACK
ACK
ACK
ACK
ACK
Eight-Bit Read Sequence
To read one byte at a time the same special register address is used for the lower byte.
The upper 8 bits are read from the desired register. By following this with a read from the
special register (Reg0x7F) the lower 8 bits are accessed, as shown in Figure 19 The master sets the no-acknowledge bits.
Figure 19: Timing Diagram Showing a Bytewise Read from Reg0x09; Returned
Value 0x0284
SCLK
SDATA
0xB8 ADDR
0xB9 ADDR
Reg0x09
0000 0010
START
START
ACK
ACK
NACK
ACK
SCLK
SDATA
0xB8 ADDR
0xB9 ADDR
Reg0x7F
1000 0100
STOP
START
START
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MT9V111_2.fm - Rev. G 1/05 EN
ACK
ACK
ACK
39
NACK
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©2004 Micron Technology, Inc. All rights reserved.
MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
Two-wire Serial Interface Sample Write and Read Sequences
Two-wire Serial Bus Timing
The two-wire serial interface operation requires a certain minimum of master clock
cycles between transitions. These are specified below in master clock cycles.
Figure 20: Serial Host Interface Start Condition Timing
4
5
SCLK
SDATA
Figure 21: Serial Host Interface Stop Condition Timing
4
5
SCLK
SDATA
Note:
All timing are in units of master clock cycle.
Figure 22: Serial Host Interface Data Timing for Write
4
4
SCLK
SDATA
Note:
SDATA is driven by an off-chip transmitter.
Figure 23: Serial Host Interface Data Timing for Read
5
SCLK
SDATA
Note:
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SDATA is pulled LOW by the sensor, or allowed to be pulled HIGH by a pull-up resistor offchip.
40
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©2004 Micron Technology, Inc. All rights reserved.
MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
Two-wire Serial Interface Sample Write and Read Sequences
Figure 24: Acknowledge Signal Timing After an 8-bit Write to the Sensor
3
6
SCLK
Sensor pulls down
SDATA pin
SDATA
Figure 25: Acknowledge Signal Timing After an 8-bit Read from the Sensor
6
7
SCLK
SDATA
Note:
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Sensor tri-states SDATA pin
(turns off pull down)
After a read, the master receiver must pull down SDATA to acknowledge receipt of data
bits. When read sequence is complete, the master must generate a no acknowledge by
leaving SDATA to float HIGH. On the following cycle, a start or stop bit may be used.
41
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©2004 Micron Technology, Inc. All rights reserved.
MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
Appendix B – Overview Of Programming
Appendix B – Overview Of Programming
Default Sensor Configuration
In its default configuration, the sensor outputs up to 15 fps at 12 MHz master clock frequency. Auto exposure, automatic white balance, 60Hz flicker avoidance, defect correction, and automatic noise suppression in low light conditions are enabled. The frame
rate is controlled by AE and can be slowed down to 5 fps in low light. Lens shading correction is disabled. Gamma correction uses gamma = 0.6. Image data are output in
YCbCr ITU_R.BT.656 VGA format, with Y, Cb, and Cr values ranging from 16 to 240.
The use of the non-default register settings shown in Table 14 are recommended to optimize sensor performance in the above configuration.
Table 14: Non-Default Register Settings Optimizing 15 fps at 12 MHz Operation
Note:
Core:
R5 = 46, R7[4] = 0, R33 = 58369, R47 = 63414
IFP:
R51= 5137, R56 = 2168, R57= 290, R59 = 1068, R62 = 4095, R64 = 7696, R65 = 5143,
R66 = 4627,
R67 = 4370, R68 = 28944, R69 = 29811
Non-default register settings required for an optimal 30 fps, 27 MHz operation are shown
in Table 15
Table 15: Non-Default Register Settings Optimizing 30 fps at 27 MHz Operation
Note:
Core:
R5 = 132, R6 = 10, R7[4] = 0, R33 = 58369
IFP:
R51 = 5137, R57 = 290, R59 = 1068, R62 = 4095, R89 = 504, R90 = 605, R92 = 8222,
R93 = 10021,
R100 = 4477
To obtain register settings for other frame rates and clock speeds, please contact a Micron
FAE.
Auto Exposure
Target image brightness and accuracy of AE are set by IFP R46[7:0] and R46[15:8],
respectively. For example, to overexpose images, set IFP R46[7:0] = 120. To change
image brightness on LCD in RGB preview mode, use IFP R52[15:8]. AE logic can be programmed to keep the frame rate constant or vary it within certain range, by writing to
IFP R55[9:5] one of the values tabulated in Table 16.
Table 16: Relation Between IFP R55[9:5] Setting and Frame Rate Range
Minimum Frame
Rate
Maximum Frame Rate = 15 fps
Maximum Frame Rate =
30 fps
30 fps
15 fps
7.5 fps
5 fps
N/A
8
16
24
4
8
16
24
The speed of AE is set using IFP R47. The speed should be high in preview modes and
lower for video output to avoid sudden changes in brightness between frames.
Auto exposure is disabled by setting IFP R6[14] = 0. When AE, AWB, and flicker avoidance are all disabled (IFP R6[14] = 0, IFP R6[1] = 0, and IFP R8[11] = 0), exposure and analog gains can be adjusted manually (see core registers R9, R12, and R43 through R46).
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©2004 Micron Technology, Inc. All rights reserved.
MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
Appendix B – Overview Of Programming
Automatic White Balance
AWB can be disabled by setting IFP R6[1]=0. Use IFP R37[2:0] and R37[6:3] to speed up
AWB response. Please note that speeding AWB up may result in color oscillation. If necessary, AWB range can be restricted by changing the upper limit in IFP R36[14:8] and
lower limit in IFP R36[6:0].
Flicker Avoidance
Use IFP R91 to choose automatic/manual, 50Hz/60Hz flicker avoidance and IFP R8[11]
= 0 to disable this feature.
Flash
For flash programming, see IFP R152 description.
Decimation, Zoom, and Pan
For output decimation programming, see IFP R165 description. Table 17 provides a few
examples.
Table 17: Decimation, Zoom, and Pan
Note:
Ifp Registers
CIF Output (Correct Aspect
Ratio)
QVGA Output
2:1 Zoom
QVGA Output
1:1 Zoom
R165
R166
R167
R168
R169
R170
26
586
352
0
480
288
160
320
320
120
240
240
0
640
320
0
480
240
For fixed 2x upsize zoom, set core R30[0] = 1.
Interpolation
Use IFP R5[2:0] to adjust image sharpness. By default, sharpness is automatically
reduced in low-light conditions (see IFP R5[3]). For RGB565 16-bit capture, set IFP
R6[12] = 0 and IFP R5[3] = 0 to avoid contouring.
Special Effects
To switch from color to gray scale output, set IFP R8[5] = 1. Contact a Micron FAE for
register settings producing other special effects (e.g. sepia output).
Image Mirroring
To mirror images horizontally, set core R32[14] = 1 and IFP R8[0] = 1. To flip images vertically, set core R32[15] = 1 and IFP R8[1] = 1.
Test Pattern
See IFP R72 and IFP Reg58[5:3] description.
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43
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
Appendix B – Overview Of Programming
Gamma Correction
See Table 18 and Table for register settings required to setup non-default gamma correction. Please note that these settings determine output signal range. Use YCbCr settings with ITU_R BTU-compatible devices. Use YUV settings for JPEG capture and RGB
preview; switching to YUV mode requires setting IFP R52 = 0 and IFP R53 = 65281.
Table 18: YCbCr Settings
Gamma
0.45
0.5
0.55
0.6
(Default)
0.7
1.0
IFP R83
IFP R84
IFP R85
IFP R86
IFP R87
12836
23876
39039
49326
57552
10781
21563
37495
48553
57551
8984
19508
35952
47780
57549
7700
17709
34409
47008
57548
5389
14627
31581
45207
57545
2052
8208
24640
41088
57536
Table 19: YUV Settings
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Gamma
0.45
0.5
0.55
0.6
0.7
1.0
IFP R83
IFP R84
IFP R85
IFP R86
IFP R87
14377
26957
44432
56005
65260
12321
24643
42631
54976
65259
10267
22331
40831
54202
65257
8726
20276
39031
53173
65255
6159
16680
35945
51371
65252
2308
9234
27720
46481
65241
44
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MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
Appendix B – Overview Of Programming
Figure 26: 44-Ball ICSP Package Outline Drawing
0.95 (FOR REFERENCE ONLY)
1.17 ±0.10
B
SEATING PLANE
0.10 A
A
0.22
(FOR REFERENCE ONLY)
0.175
(FOR REFERENCE ONLY)
0.575 ±0.050
4.50
0.375 ±0.075
BALL A1
BALL A1 ID
0.75 TYP
BALL A7
44X Ø0.35
BALL A1
CORNER
5.30 CTR
PIXEL
(0,0)
3.500 ±0.075
DIMENSIONS APPLY TO SOLDER
BALLS POST REFLOW. THE PREREFLOW DIAMETER IS Ø0.33
3.400 ±0.075
3.50 ±0.05
CL
4.50
2.688
5.30
CTR
CTR
7.00 ±0.075
0.100
(FOR REFERENCE
ONLY)
OPTICAL
CENTER
PACKAGE
CENTER
2.25
0.75 TYP
CL
2.25
3.50 ±0.05
OPTICAL AREA
3.584 CTR
MAXIMUM ROTATION OF OPTICAL AREA RELATIVE TO PACKAGE EDGES: 1º
MAXIMUM TILT OF OPTICAL AREA RELATIVE TO B : 0.3º
MAXIMUM TILT OF OPTICAL AREA RELATIVE TO TOP OF COVER GLASS: 0.3º
7.00 ±0.075
LID MATERIAL: BOROSILICATE GLASS 0.40 THICKNESS
IMAGE SENSOR DIE
SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2%Ag
OR 96.5% Sn, 3%Ag, 0.5% Cu
SOLDER MASK DEFINED BALL PADS: Ø 0.27
SUBSTRATE MATERIAL: PLASTIC LAMINATE
ENCAPSULANT: EPOXY
Notes: 1. All dimensions in millimeters.
2. ICSP package information is preliminary.
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
[email protected] www.micron.com Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range
for production devices. Although considered final, these specifications are subject to change, as further product
development and data characterization sometimes occur.
09005aef80e90084
MT9V111_2.fm - Rev. G 1/05 EN
45
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
MT9V111 - 1/4-Inch SOC VGA Digital Image Sensor
Revision History
Revision History
Rev. G, Production ...........................................................................................................................................................1/05
• Modified tOH definition in Table 11, AC Electrical Characteristics, on page 31
• Updated Figure 10, Propagation Delays for PIXCLK and Data Out Signals, on page 32
Rev. F, Production ............................................................................................................................................................8/04
• Updated 44-Ball ICSP Package Outline Drawing
Rev. E ................................................................................................................................................................................7/04
• Replaced 28-Pin PLCC package information with the 44-Ball ICSP
• Updated Table 12 (Frame Time)
• Updated Electrical Specifications
Rev. D, Preliminary ..........................................................................................................................................................3/04
• Modify for external web posting - streamlined register descriptions
• Add Appendix B
Rev. C, Preliminary ..........................................................................................................................................................2/04
• Added Key Performance Parameter Table, Update Register Tables, Update Electrical Specification Table,
Added Figures (Image Center Offset, Die Placement, 28-Pin PLCC Package Outline Drawing and Spectral
Response)
Rev. B, Preliminary, Draft ................................................................................................................................................1/04
• Format edits on 1/15/04
Rev. A, Preliminary, Draft ..............................................................................................................................................12/03
• Initial Release of document
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MT9V111_2.fm - Rev. G 1/05 EN
46
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.