1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
1/2-INCH CMOS ACTIVEPIXEL CMOS IMAGE
SENSOR
MT9V403
Features
Description
Micron Part Number: MT9V403C12ST
The Micron® Imaging MT9V403 VGA-based CMOS
active-pixel sensor has a 1/2-inch optical format and
delivers superb resolution at a turbocharged 200 fps,
making it the perfect solution for machine vision
assembly lines, airbag deployment, golf swing analysis,
and special effects in movies. The freeze-frame shutter
allows the signal charges of all pixels to be integrated
in parallel—all pixels start integrating simultaneously
and stop integrating simultaneously. The charges are
then sampled into pixel analog memories (one memory per pixel) and consequently, row by row, are digitized and read out-of-chip. The sensor works in
master, snapshot, or slave mode. In master mode it
generates the readout timing on-chip. In snapshot
mode it accepts an external trigger and then generates
the readout timing. In slave mode the sensor accepts
external readout timing. The integration time is programmed through the two-wire serial interface (master or snapshot mode) or controlled via externallygenerated control signals (slave mode).
The scanning mode can be progressive or interlaced. There is also an option to scan just a window of
interest by choosing start row and column and stop
row and column. The user can control the frame rate
and row rate through the use of vertical and horizontal
blanking as well as the master clock frequency.
The readout of the data out of the chip can be done
simultaneously with integration and ADC operation
due to the two-cell SRAM which allows data from the
previously converted row to be shifted into the output
memory for readout.
The sensor’s ADCs contain special self-calibrating
circuitry that allow the sensor to reduce its own column-wise fixed pattern noise. The calibration coefficients can be read from, and written to, the sensor.
• Array Format: Active: 659H x 494V
• Pixel Size and Type: 9.9µm x 9.9µm TrueSNAP™
(shuttered-node active pixel)
• Optical Format: 1/2-inch
• Frame Rate: 0-200 frames/sec progressive scan
• Data Rate: 66 MB/s (master clock 66 MHz)
• Responsivity: 2.0 V/lux-sec with source Illumination
at 550nm
• SNR: 45dB
• ADC: On-chip, 10-bit
• Power: 130mW at 200 fps
• Supply Voltage: +3.3V
• Internal Intra-Scene Dynamic Range: 60dB
• Operating Temperature: -5°C to +70°C
• Output: 10-bit digital through a single port
• Shutter: TrueSNAP freeze-frame electronic shutter
• Interface Mode: Master/Snapshot/Slave (with
simultaneous or sequential exposure/readout)
• Shutter Efficiency: 98.5%
• Shutter Exposure Time:
• Master Mode or Snapshot Mode: 2 rows to 256
frames (20µs to 1.3 sec with 66 MHz clock)
• Slave Mode: user controlled
• Gain: 1x–18x (step size = 1) or 0.5x–9x
(step size = 0.5)
• Control Interface: Two-wire serial interface
• Package: 48-pin CLCC
• Timing and Control:
On-chip:
• ADC controls, output multiplexing, ADC calibration via two-wire serial interface, exposure time,
read/write ADC calibration coefficients, window
size and location, gain, biases, master vs. snapshot vs. slave, simultaneous vs. continuous exposure/readout, progressive vs. interlace, ADC
reference, vertical and horizontal blanking.
Off-chip:
• Exposure trigger (snapshot mode), exposure and
readout timing (slave mode)
• Color Specifications: monochrome or color (Bayer
pattern)
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
1
©2004 Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Figure 1: Block Diagram
Expose
Frame
Row
Sensor
Interface
Block
System
Clock
Control
Logic
Row
Decoder
Gain Control
Pixel Array
Column PGA
Reset
System
Clock
System
Data
Table 1:
Two-Wire
Serial
Interface
Calibration Data
Column ADCs and
calibration memory
Readout Control
667H x 10 SRAM (x2)
ADC and Output Registers
Output (9:0)
Pin Description
PIN
NUMBERS SIGNAL NAME
TYPE
DESCRIPTIONS
Clock input for entire chip. Maximum design frequency is 66 MHz (50 percent,
±5 percent duty cycle).
Global logic RESET function (asynchronous). Active low pulse with minimum
duration 200ns.
Slave mode input signal. Starts row processing sequence of the pixel row (i.e.,
pixel readout, ADC conversion, and writing of data to ADC registers). The rising
edge of ROW_STRT should be synchronous with the falling edge of SYSCLK. A
one-clock cycle wide active high pulse. The two-wire serial interface register
setting switches this pin between input and output.
Slave mode input signal. An active LOW signal that enables the column counter
and initiates the readout process. Causes the 10-bit output port to be updated
with data on the rising edge of the system clock. The two-wire serial interface
register setting switches this pin between input and output.
Trigger for snapshot mode. The two-wire serial interface register setting
switches this pin between input and output. No connection should be made in
slave mode.
Slave mode input signal. Active low pulse that resets all photodetectors,
starting a new integration cycle. No connection should be made in master
mode or snapshot mode.
Slave mode input signal. Active low pulse that controls transfer of charge from
photodetector to memory inside each pixel for the entire pixel array. No
connection should be made in master mode or snapshot mode.
Slave mode input signal. Active low pulse to reset all pixel memories. No
connection should be made in master mode or snapshot mode.
Serial port clock. Maximum frequency is 1 MHz.
Bias setting voltage for VLN_AMP or VLN_OUT. VLN_AMP and VLN_OUT can be
individually disconnected from their internal biases via the two-wire serial
interface and driven by this input.
Bias setting voltage for pixel source following operating current.
Bias setting voltage for the column source follower operating current.
Dark offset cancellation. Polarity of offset is set via the two-wire serial
interface.
Op amp bias.
37
SYSCLK
Input
33
LRST_N
Input
30
ROW_STRT
Input
31
LD_SHFT_N
Input
29
EXPOSE
Input
26
PG_N
Input
25
TX_N
Input
24
RESMEM
Input
38
18
SCLK
VLNS
Input
Input
17
19
13
VLN1
VLP
VOFF
Input
Input
Input
16
VREF
Input
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Table 1:
Pin Description (continued)
PIN
NUMBERS SIGNAL NAME
TYPE
DESCRIPTIONS
ADC reference voltage that sets the maximum input signal level, setting the
size of the least significant bit (LSB) in the analog to digital conversion process.
ADC bias.
ADC reference used for the calibration operation.
Slave mode input signal. Active low pulse to reset row and column counters,
providing frame synchronization. Low duration should be at least two-clock
cycles wide. An input that is held LOW also sets the sensor in LOW, per standby
mode, until it is released. Signal is pulled up on-chip.
The user should ground this pin.
Offset that may be needed for very short exposure conditions.
Bias setting voltage for the ADC operating current.
Serial port data.
9
VREF1
Input
8
7
32
VREF1DRV
VREF2
FRAME_SYNC_N
Input
Input
Input
14
23
21
39
VTEST
VRSTLOW
VLN2
SDATA
30
FRAME_VALID
Input
Input
Input
Input/
Output
Output
31
ROW_VALID
Output
29
EXPOSE
Output
41
40
45
42
46
47
48
1
2
3
12, 22
20
10, 11, 15
6, 27, 36,
43
4, 5, 28, 34,
35, 44
DATA9
DATA8
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
VAA
VRST_PIX
AGND
VDD
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Power
Power
Power
Power
Master mode and snapshot mode output signal. Active HIGH during readout.
The two-wire serial interface register setting switches this pin between input
and output.
Master mode and snapshot mode output signal. Active HIGH when image data
are on data output bus. The two-wire serial interface register setting switches
this pin between input and output.
Master mode output signal. Active HIGH during exposure. The two-wire serial
interface register setting switches this pin between input and output.
Pixel output data bit 9 (MSB).
Pixel output data bit 8.
Pixel output data bit 7.
Pixel output data bit 6.
Pixel output data bit 5.
Pixel output data bit 4.
Pixel output data bit 3.
Pixel output data bit 2.
Pixel output data bit 1.
Pixel output data bit 0 (LSB).
3.3V power supply for analog signal processing circuitry.
Power supply for pixel array. Set for 2.5V.
Ground for analog signal processing circuitry.
3.3V digital power supply.
DGND
Power
Ground for digital circuitry.
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Pixel Data Format
signals utilized in master mode are depicted in
Figure 4. In master mode, the start of the integration
period is determined internal to the MT9V403.
The pixel array descriptions and details are shown
below.
Figure 4: Master Mode Interface
Signals
Figure 2: Pixel Array Description
(502, 667)
8
EXPOSE
SYSCLK
Dark and Isolation
Pixels
FRAME_VALID
Active Pixel Array
494
CONTROLLER
ROW_VALID
MT9V4O3
DATA
(1, 1)
LRST_N
659
8
The integration time is pre-programmed via the
two-wire serial interface and indicated by the EXPOSE
signal going HIGH. When the sensor commences, the
readout process the FRAME_VALID, ROW_VALID, and
DATA signals are output, as shown in Figure 5 on
page 5.
The master mode row synchronization waveform
relationships are as shown in Figure 5 on page 5. The
FRAME_VALID signal goes HIGH, indicating the start
of frame, and 2.5 clock cycles later the ROW_VALID
signal goes HIGH, indicating the start of the first row.
The first data bit is valid on the first falling edge of
SYSCLK after ROW_VALID goes HIGH. The remaining
665 pixels for the row are valid on the subsequent falling edges of SYSCLK, after which ROW_VALID returns
to the LOW state. (Please note that in master mode 648
pixels are readout for each row.) The ROW_VALID will
then be an active HIGH envelope for subsequent rows
and the FRAME_VALID signal will be an active HIGH
envelope for subsequent frames. The time required for
one complete row operation is 671 clock cycles: 1 clock
cycle delay + 666 columns + 4 clock cycles when
ROW_VALID is LOW. With a SYSCLK of 66 MHz, this
translates into a row time of 10.2µs and a frame time of
5.1ms for full resolution (502 rows). This assumes there
is no vertical blanking or horizontal blanking and that
the exposure time is less than 5.1ms. If exposure time
becomes greater than 5.1ms, the frame time then
becomes the inverse of the exposure time (1/[exposure
time]).
Figure 3: Pixel Color Pattern Detail
(Bottom Left Corner)
black pixels
G
R
G
R
G
R
G
B
G
B
G
B
G
B
G
R
G
R
G
R
G
B
G
B
G
B
G
B
G
R
G
R
G
R
G
B
G
B
G
B
G
B
G
R
G
R
G
R
G
Output Format and Timing
The sensor can operate in three interface modes:
master, snapshot, or slave mode. Additionally, master
mode can be setup to allow simultaneous integration
and readout (simultaneous master mode) or sequential integration and readout (sequential master mode).
Mode selection is done via the two-wire serial interface, taking less than one frame time to switch
between modes.
The default register settings program the imager to
read out the visible pixels. Therefore, the start row is 1,
start column is 9, end row is 480 and the end column is
648.
Master Mode
In master mode the sensor internally generates the
timing to initiate exposure and readout. The interface
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Figure 5: Master Mode Row Timing Diagram
1
SYSCLK
(input)
652
12
671
1
12
((
))
((
))
ROW _VALID
(output)
DATA [9:0]
(output)
653
671
+
169
((
))
((
))
Horizontal Blanking
((
))
XXX
9
10
((
))
((
))
648
XXX
649
((
))
((
))
9
10
NOTE:
Horizontal blanking is nominally 35 rows, and may be increased using register 5.
by changing the number of rows being readout (i.e.,
window size). Table 2 shows some examples of how the
frame rate changes with window resolution and clock
speed.
In master mode the frame rate is controlled by
inserting vertical and/or horizontal blanking periods
during readout, or by changing the input master clock
(SYSCLK) frequency (i.e., slowing the sensor down), or
Table 2:
Frame Rate vs. Resolution and Clock Speed
No blanking, exposure < readout
RESOLUTION (# ROWS)
CLOCK SPEED (SYSCLK)
FRAME RATE (FRAMES/SECOND)
502 (full resolution)
251
125
63
502 (full resolution)
251
125
63
502 (full resolution)
66 MHz
66 MHz
66 MHz
66 MHz
24 MHz
24MHz
24 MHz
24 MHz
10 MHz
196
392
784
1568
70
140
280
560
30
grammable number of rows after the frame is readout
(if exposure time < readout time) or exposed (if exposure time > readout time). Table 3 on page 6 shows the
various scenarios for calculating the frame time, where
VB is the vertical blanking in rows (255 rows maximum) specified in register 6. The default vertical
blanking is one SYSCLK cycle, so the true vertical
blanking time is the number of blanking rows programmed plus one clock cycle.
When horizontal blanking is utilized, the
ROW_VALID stays LOW for an additional user-programmable number of clock cycles after each row
readout. As a result the row time becomes:
RT = (1 + 66 6+ 4 + HB) x (1/fsysclk)
where HB is the horizontal blanking in SYSCLK
cycles (255 clock maximum) specified in register 5.
When vertical blanking is utilized, the FRAME_
VALID signal stays LOW for an additional user pro-
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Table 3:
Determination of Frame Timing
EXPOSURE TIME > READOUT TIME
READOUT TIME > EXPOSURE TIME
Frame Time = Exposure Time
Frame Time = Exposure Time + VB
Frame Time = N x RT
Frame Time = (N + VB) x RT
No Blanking
With Vertical Blanking
NOTE:
N = number of rows in image
RT = row time
VB = vertical blanking rows (255 rows maximum); set in register 6
HB = horizontal blanking in SYSCLK cycles (255 maximum); set forth in register 6
Simultaneous Master Mode
There are two possible operation methods for master mode: simultaneous master mode and sequential
master mode. One of these operation modes must be
selected via the two-wire serial interface. In simultaneous master mode the exposure period occurs during
readout. The frame synchronization waveforms are
shown in Figure 6 and Figure 7. This is the fastest
mode of operation since the exposure and readout are
happening in parallel rather than sequentially. Please
note that with this speed optimized timing the first row
readout is the last row of the previous frame that is still
in the row memory.
Figure 6: Simultaneous Master Mode Frame Synchronization Waveforms
readout time > exposure time
EXPOSE
(output)
((
))
((
))
FRAME_VALID
(output)
((
))
((
))
Exposure Time
((
))
((
))
Vertical Blanking
ROW_VALID
(output)
DATA [9:0]
(output)
((
))
((
))
XXX
Row Row
1
2
((
))
((
))
XXX
((
))
Row Row
N-1 N
((
))
((
))
XXX
((
))
Row Row Row XXX Row Row Row
481
1
2
478 479 480
((
))
((
))
XXX
((
))
Row Row
N-1 N
((
))
((
))
XXX
((
))
Row Row Row
478 479 480
NOTE:
Vertical blanking is nominally 1 SYSCLK and 0 row times, and may be increased by using register 6.
Figure 7: Simultaneous Master Mode Frame Synchronization Waveforms
exposure time > readout time
EXPOSE
(output)
((
))
((
))
Vertical Blanking
((
))
FRAME_VALID
(output)
((
))
ROW_VALID
(output)
DATA [9:0]
(output)
Exposure Time
XXX
Row Row
1
2
((
))
((
))
((
))
Row Row Row
478 479 480
((
))
((
))
XXX
((
))
Row Row Row
1
2
481
((
))
((
))
Row Row Row
478 479 480
NOTE:
Vertical blanking is nominally 1 SYSCLK and 0 row times, and may be increased by using register 6.
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Sequential Master Mode
In sequential master mode the exposure period is
followed by readout. The frame synchronization wave-
forms for sequential master mode are shown in
Figure 8.
Figure 8: Sequential Master Mode Frame Synchronization Waveforms
EXPOSE
(output)
((
))
((
))
((
))
((
))
Vertical Blanking
((
))
FRAME_VALID
(output)
((
))
ROW_VALID
(output)
((
))
((
))
((
))
((
))
DATA [9:0]
(output)
((
))
XXX
((
))
((
))
((
))
Row Row
1
2
Row Row Row
478 479 480
((
))
((
))
XXX
((
))
((
))
Row Row
1
2
((
))
((
))
Row Row Row XXX
478 479 480
NOTE:
Vertical blanking is nominally 1 SYSCLK and 0 row times, and may be increased by using register 6.
Snapshot Mode
the two-wire serial interface register) during readout is
allowed, but the user controls the vertical blanking by
controlling the input EXPOSE pulse.
In snapshot mode the sensor accepts an input trigger signal that initiates exposure, which is immediately
followed by readout. The interface signals utilized in
snapshot mode are depicted in Figure 9. In snapshot
mode the start of the integration period is determined
by the externally applied EXPOSE pulse that the user
inputs to the MT9V403. The integration time is preprogrammed via the two-wire interface. After each frame's
integration period is complete, the readout process
commences and the FRAME_VALID, ROW_ VALID, and
DATA signals are output.
Snapshot mode can be used to capture a single
image or a sequence of images. The frame rate is controlled only by changing the period of the user supplied EXPOSE pulse train. The frame synchronization
waveforms for snapshot mode are shown in Figure 9.
Insertion of horizontal blanking periods (specified via
Figure 9: Snapshot Mode Interface
Signals
EXPOSE
SYSCLK
FRAME_VALID
CONTROLLER
ROW_VALID
MT9V4O3
DATA
LRST_N
Figure 10: Snapshot Mode Frame Synchronization Waveforms
EXPOSE
(input)
FRAME_VALID
(output)
ROW_VALID
(output)
DATA [9:0]
(output)
*
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
XXX
((
))
((
))
((
))
Exposure Time
Row Row
1
2
Row Row Row
478 479 480
((
))
XXX
((
))
((
))
Row Row
1
2
((
))
((
))
Row Row Row XXX
478 479 480
* Row_Valid goes HIGH after (2.5 + (column start -1)) clocks + 1 row time
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Slave Mode
The column counter selects the column output
SRAM cells for off-chip readout at the speed of
SYSCLK. LD_SHFT_N enables the column counter
when LOW. Data is output 3.5 clocks after LD_SHFT_N
goes LOW. The column counter is zeroed when
LD_SHFT_N is HIGH; if LD_SHFT is not high the
counter will continue.
The row counter and column counter may be
zeroed using the CLEAR signal, which is driven by register 14. The user can set the CLEAR signal by writing
to this register through the two-wire serial interface or
by pulling down the FRAME_SYNC_N signal for two
clock cycles.
When operating in slave mode, the user should keep
in mind that both the row and column counters count
between the START and STOP values, which are set in
registers 1–4 via the two-wire serial interface. Sufficient time should be allocated to allow the counters to
complete. It must also be emphasized that the row
sequencer always requires 671 clock cycles independent of the START and STOP values (i.e., window size).
Horizontal blanking may be achieved between rows by
holding LD_SHFT_N HIGH and delaying the application of the ROW_STRT rising edge.
Additionally, it is possible to operate the sensor in a
pipelined manner or non-pipelined manner in slave
mode (master mode is always pipelined). Pipelined
operation means that a row of data is read out of the
sensor at the same time that a new row is converted.
This is accomplished through the dual SRAM banks
that store one row for readout in one bank while the
other bank is being filled with a newly converted row.
As mentioned above, the ROW_STRT triggers the row
conversion and LD_SHFT_N enables the data output.
These can be applied nearly simultaneously to achieve
pipelined operation or applied sequentially, offset by
the row processing time, for non-pipelined operation.
Slave mode allows the user much greater control of
the sensor. The interface signals utilized in slave mode
are depicted in Figure 11. The user can start and stop
integration through the use of PG_N and TX_N,
respectively. The use of the RESMEM signal to reset
pixel memories prior to ending exposure (TX_N) is
optional. The readout process is controlled by usersupplied row control signals (ROW_STRT and
LD_SHFT_N). Additionally, the FRAME_SYNC _N signal may be used for frame synchronization.
Figure 11: Slave Mode Interface
Signals
PG_N
TX_N
SYSCLK
FRAME_SYNC_N
CONTROLLER
ROW_STRT
MT9V4O3
LD_SHFT_N
DATA
LRST_N
Figure 12 on page 9 shows the block diagram of the
sensor for slave mode operation, where the sensor's
digital block requires external synchronization inputs
to trigger generation of the row conversion and readout sequence. The internal structure of the digital
block in slave mode includes row counter, column
counter, and row sequencer. The rising edge of the
ROW_STRT signal increments the row counter to the
next value and triggers the row sequencer. The row
sequence duration is always equal to 671 clocks, which
is fixed by the column parallel architecture. The duration of the ROW_STRT signal should be one clock
cycle.
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
NOTE:
8
To reduce horizontal temporal noise in slave
mode, delay readout by 80 SYSCLK.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Figure 12: Slave Mode Block Diagram
TX_N
PG_N
CLEAR
ROW_STRT
Row Counter
(1 to 502 MAX)
RESMEM
Row Driver
Pixel Array
Row Sequencer
(1 to 671)
Column
Processing
Circuitry
(PGA, ADC)
Column Counter
(1 to 667 MAX)
667 x a10
Output SRAM (x2)
SYSCLK
LD_SHFT_N
Output(9:0)
CLEAR
FRAME_SYNC_N
Two-Wire
Serial
Interface
Reg14
CLEAR
Simultaneous Slave Mode
There are two possible operation methods for slave
mode: simultaneous slave and sequential slave mode.
The method of operation selected is determined by the
means in which the user supplies the control signals.
In simultaneous slave mode the exposure period
occurs during readout. The row and frame synchroni-
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
zation waveforms are shown in Figures 13 and 14,
respectively. This is the fastest mode of operation since
the exposure and readout are happening in parallel
rather than sequentially. The PG_N, TX_N, and RESMEM pulses should have a minimum duration of 338
clock cycles and be applied between the 100th and
600th clocks of a given row.
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Figure 13: Simultaneous Slave Mode Row Timing Diagram Example (Default
Settings)
1
>100 <600
SYSCLK
(input)
((
))
((
))
((
))
PG_N/TX_N/
RESMEM
(input)
671
((
))
((
))
Minimum 338
SYSCLK
((
))
((
))
((
))
((
))
ROW_STRT
(input)
((
))
((
))
((
))
LD_SHFT_N
(input)
((
))
((
))
((
))
((
))
((
))
((
((
))
))
( ( XXX( (
))
))
FRAME_SYNC_N
(input)
DATA [9:0]
(output)
XXX
9
10
647
XXX
648
9
10
Figure 14: Simultaneous Slave Mode Frame Synchronization Waveforms Example
PG_N
(input)
RESMEM
(input)
TX_N
(input)
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
Exposure Time
FRAME_SYNC_N
(input)
ROW_STRT
(input)
LD_SHFT_N
(input)
DATA [9:0]
(output)
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
Row
502
Row
1
Row
2
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
Row
N-1
Row
N
((
))
((
))
Row
499
Row
500
10
Row
501
Row
502
Row
1
Row
2
((
))
((
))
Row Row
N-1
N
((
))
((
))
Row Row
499 500
Row
501
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Sequential Slave Mode
In sequential slave mode the exposure period is followed by readout. The row and frame synchronization
waveforms are shown in Figures 15 and 16, respectively.
Figure 15: Sequential Slave Mode Row Timing Diagram Example
1
SYSCLK
(input)
((
))
RESMEM
(input)
((
))
TX_N
(input)
FRAME_SYNC_N
(input)
ROW_STRT
(input)
LD_SHFT_N
(input)
DATA [9:0]
(output)
671
((
))
((
))
((
))
((
))
((
))
((
))
>10 SYSCLK
((
))
Minimum 338
SYSCLK
((
))
((
))
((
))
>10 SYSCLK
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
1
XXX
2
((
))
((
))
666
667
1
XXX
2
3
4
Figure 16: Sequential Slave Mode Frame Synchronization Waveforms Example
PG_N
(input)
Minimum Duration
338 SYSCLK
Exposure Time
RESMEM
(input)
Minimum Duration
338 SYSCLK
TX_N
(input)
FRAME_SYNC_N
(input)
ROW_STRT
(input)
LD_SHFT_N
(input)
DATA [9:0]
(output)
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
Row
502
Row Row Row Row
1
2
3
4
((
))
((
))
Exposure Time
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
Row Row Row Row Row
497 498 499 500 501
11
Row
502
Row
1
Row
2
Row
3
Row
4
((
))
((
))
Row Row
497 498
Row
499
Row Row
500 501
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
N2. For N1 = 500 and N2 = 2, the dynamic range
enhancement is approximately 48 dB. Figure 18 shows
output signal vs. photocurrent. The knee point is
dependent on the VRSTLOW bias, which determines
the charge capacity of the photodiode. The saturation
level of photodiode must be less than the saturation
level of the ADC. Setting VRSTLOW to 1.2V is enough
for the default gain settings. The slope of the curve
after the knee point or compression level is determined by the N1/N2 ratio.
To increase intrascene dynamic range of the sensor
in slave mode, the user can implement dual sampling.
This is possible by applying an additional TX pulse
during the integration period. By doing this, one combines two photo signals after different exposures.
Figure 17 shows an example of the timing. N1 is the
number of rows in the first exposure. N2 is the number
of rows in the second exposure. N1 = 502 for the full
frame exposure time. The intrascene dynamic range
capability of the sensor is extended by the factor N1/
Figure 17: Extended High Dynamic Range Timing in Slave Mode
N2
Exposure
TX_N
N1
PG_N
DATA [9:0]
XXX
((
))
((
))
((
))
((
))
XXX
Readout Time
Figure 18: Output Signal vs. Photocurrent
ADC saturation level
Signal
Compressed
region
RI
Iph
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Serial Bus Description
Registers are written to and read from the MT9V403
through the two-wire serial interface bus. The
MT9V403 is a two-wire serial interface slave with
device ID "1011100x" and is controlled by the two-wire
serial interface clock (SCLK), which is driven by the
two-wire serial interface master. Data is transferred
into and out through the two-wire serial interface data
(SDATA) line. The SDATA line is pulled up to 3.3V offchip by a 1.5KΩ resistor. Either the slave or master
device can pull the SDATA line down—the two-wire
serial interface protocol determines which device is
allowed to pull the SDATA line down at any given time.
slave address. The master then clocks out the register
data eight bits at a time. The master sends an acknowledge bit after each eight-bit transfer. The register
address should be incremented after every 16 bits is
transferred. The data transfer is stopped when the
master sends a no-acknowledge bit.
Protocol
Start Bit
The two-wire serial host interface bus defines several different transmission codes, as follows:
• a start bit
• the slave device eight-bit address
• a(n) (no) acknowledge bit
• an eight-bit message
• a stop bit
The start bit is defined as a HIGH-to-LOW transition
of the data line while the clock line is HIGH.
Bus Idle State
The bus is idle when both the data and clock lines
are HIGH. Control of the bus is initiated with a start
bit, and the bus is released with a stop bit. Only the
master can generate the start and stop bits.
Stop Bit
The stop bit is defined as a LOW-to-HIGH transition
of the data line while the clock line is HIGH.
Slave Address
Sequence
The eight-bit address of a two-wire serial interface
device consists of seven bits of address and one bit of
direction. A “0” in the LSB of the address indicates
write mode, and a “1” indicates read mode.
A typical read or write sequence begins by the master sending a start bit. After the start bit, the master
sends the slave device's eight-bit address. The last bit
of the address determines if the request will be a read
or a write, where a “0” indicates a write (i.e., address
B8h) and a “1” indicates a read (i.e., address B9h). The
slave device acknowledges its address by sending an
acknowledge bit back to the master.
If the request was a write, the master then transfers
the eight-bit register address to which a write should
take place. The slave sends an acknowledge bit to indicate that the register address has been received. The
master then transfers the data eight bits at a time, with
the slave sending an acknowledge bit after each eightbits. The MT9V403 uses a 16-bit data for its internal
registers, thus requiring two eight-bit transfers to write
to one register. To write/read this 16-bit data, first perform a write/read the eight MSBs, then perform
another write/read for eight LSBs. After 16 bits are
transferred, the register address should be incremented, so that the next 16 bits are written to the next
register address. The master stops writing by sending a
start or stop bit.
A typical read sequence is executed as follows. First
the master sends the write-mode slave address and
eight-bit register address, just as in the write request.
The master then sends a start bit and the read-mode
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
Data Bit Transfer
One data bit is transferred during each clock pulse.
The two-wire serial interface clock pulse is provided by
the master. The data must be stable during the HIGH
period of the two-wire serial interface clock—it can
only change when the two-wire serial interface clock is
LOW. Data is transferred eight bits at a time, followed
by an acknowledge bit.
Acknowledge Bit
The master generates the acknowledge clock pulse.
The transmitter (which is the master when writing, or
the slave when reading) releases the data line, and the
receiver indicates an acknowledge bit by pulling the
data line LOW during the acknowledge clock pulse.
No-Acknowledge Bit
The no-acknowledge bit is generated when the data
line is not pulled down by the receiver during the
acknowledge clock pulse. A no-acknowledge bit is
used to terminate a read sequence.
13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Two-Wire Serial Interface Sample Write and Read Sequences
Example of a 16-Bit Write Sequence
sor will give an acknowledge bit. All 16 bits must be
written before the register will be updated. After 16 bits
are transferred, the register address should be incremented, so that the next 16 bits are written to the next
register. The master stops writing by sending a start or
stop bit.
A typical write sequence for writing 16 bits to a register is shown in Figure 19. A start bit given by the master, followed by the write address, starts the sequence.
The image sensor will then give an acknowledge bit
and expects the register address to come first, followed
by the 16-bit data. After each eight bit, the image sen-
Figure 19: Timing Diagram Showing a Write to Register 9 with the Value 644
SCLK
SDATA
B8h ADDR
START
Reg0x09
0000 0010
ACK
ACK
Example of a 16-Bit Read Sequence
1000 0100
ACK
STOP
ACK
bits at a time. The master sends an acknowledge bit
after each eight-bit transfer. The register address
should be incremented after every 16 bits is transferred. The data transfer is stopped when the master
sends a no-acknowledge bit.
A typical read sequence is shown in Figure 20. First
the master has to write the register address, as in a
write sequence. Then a start bit and the read address
specifies that a read is about to happen from the register. The master then clocks out the register data eight
Figure 20: Timing Diagram Showing a Read from Register 9; Returned Value is 642
SCLK
SDATA
B8b ADDR
START
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
Reg0x09
ACK
B9h ADDR
ACK
ACK
14
1000 0010
0000 0010
ACK
STOP
NACK
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Registers
Table 4:
Complete Register Description
READ/
WRITE
CONTROL
REGISTER
NAME
Read only
W/R
W/R
W/R
W/R
W/R
W/R
W/R
Reg0
Reg1
Reg2
Reg3
Reg4
Reg5
Reg6
Reg7
W/R
W/R
Reg8
Reg9
W/R
Reg10
W/R
Reg12
W/R
Reg13
W/R
Reg14
Write only
W/R
Reg15
Reg16
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
FUNCTION
DEFAULT CONTENTS
REGISTER
ADDRESS
Chip Version.
Row start address.
Column start address.
Stop row address.
Stop column address.
Number of blank columns (horizontal blanking).
Number of blank rows (vertical blanking).
Control mode.
Bit 0 = 1 simultaneous mode.
Bit 0 = 0 sequential mode.
Bit 1 = 1 snapshot mode.
Bit 2 = 1 master mode.
Bits 3–7 not used; set to 0.
Possible combinations are”00000101,” “00000100,”
“00000010,” “00000000”.
The last combination means slave mode.
Number of frame times in integration time.
Number of rows times in integration time.
Maximum = 502. Minimum = 2.
Interlaced mode control.
Bit 0 = 1 interlaced mode 1. Readout of both fields even
and odd.
Bit 1 = 1 interlaced mode 1 = 2.
Readout of only one field – even or odd. Depends on
start row.
Bits 2–7 not used; set to 0
Calibration control.
Bit 0 = 1 calibration at the beginning of every frame.
Dark offset enable and pixel memory reset pulse
duration control.
Bit 0 = 1 long reset pulse.
Bit 1 = 1 dark offset of ADC input signal using VOFF is
enabled.
Bits 2–7 not used; set to 0.
Clear signal control.
Bit 0 = 1 reset row and column counters in digital block.
Sensor is in idle mode. The two-wire serial interface
works and it is still possible to WRITE/READ in registers.
Changes of registers content follows without delay.
Normally, change of register content occurs only at the
beginning of next frame in cases where the two-wire
serial interface data is not busy.
ADC calibration data input register.
VLN_AMP bias control.
Bit 7 = 1 disable internal bias.
Bit 0 = 1 high bias.
Bit 1 = 1 low bias.
Bits 3–6, 8–15 not used, set to 0.
0000001100000001
*******000000001
******0000001001
*******111100000
******1010001000
********10101001
********00100011
********00000101
00000000
00000001
00000010
00000011
00000100
00000101
00000110
00000111
********00000000
*******111110110
00001000
00001001
********00000000
00001010
********00000000
00001100
********00000000
00001101
********00000000
00001110
*********0000000
0000000000000000
00001111
00010000
15
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Table 4:
READ/
WRITE
CONTROL
Complete Register Description (continued)
REGISTER
NAME
W/R
Reg17
W/R
Reg18
W/R
Reg19
W/R
Reg20
W/R
Reg21
W/R
Reg22
W/R
Reg23
W/R
Reg29
W/R
Reg43
W/R
Reg44
W/R
Reg45
W/R
Reg46
W/R
Reg53
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
FUNCTION
VLN2 bias control.
Bit 7 = 1 disable internal bias.
Bit 0 = 1 high bias.
Bit 1 = 1 low bias.
Bits 3–15 not used, set to 0.
VLN_OUT bias control.
Bit 7 = 1disable internal bias.
Bit 0 = 1 high bias.
Bit 1 = 1 low bias.
Bits 3–6, 8–15 not used, set to 0.
VLN1 bias control.
Bit 7 = disable internal bias.
Bit 0 = 1 high bias.
Bit 1 = 1 low bias.
Bits 3–6, 8–15 not used, set to 0.
VLP bias control.
Bit 7 = 1 disable internal control.
Bit 0 = 1 high bias.
Bit 1 = 1 low bias.
Bits 3–6, 8–15 not used, set to 0.
VREF bias control.
Bit 0-3 = bias value.
Bit 7 = 1 disable internal bias.
Bits 4–6, 8–15 not used, set to 0.
VREF2 bias control.
Bit 0-3 bias value.
Bit 7= 1 disable internal bias.
Bits 4–6, 8–15 not used, set to 0.
VOFF bias control.
Bit 0-3 bias value.
Bit 6 = 1 sign of offset is negative.
Bit 7 = 1 disable internal bias.
Bits 4–5, 8–15 not used, set to 0.
VLN2 bias booster.
Bit 3 = 1 high bias.
Blue gain settings.
Default gain is 2.
Gain settings range is from 1 (00000001) to 18
(00010010).
Green 1 gain settings. Default gain is 2.
Gain settings range is from 1 (00000001) to 18
(00010010).
Green 2 gain settings. Default gain is 2.
Gain settings range is from 1 (00000001) to 18
(00010010).
Red gain settings. Default gain is 2.
Gain settings range is from 1 (00000001) to 18
(00010010).
Global gain control.
Bit 0 = 1 gain is multiplied by factor of 0.5
16
DEFAULT CONTENTS
REGISTER
ADDRESS
0000000000000000
00010001
0000000000000000
00010010
0000000000000000
00010011
0000000000000000
00010100
0000000000001010
00010101
0000000000001010
00010110
0000000000000000
00010111
0000000000000000
00011101
********00000010
00101011
********00000010
00101100
********00000010
00101101
********00000010
00101110
*********0000000
00110101
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Table 4:
READ/
WRITE
CONTROL
Complete Register Description (continued)
REGISTER
NAME
W/R
Reg59
Read only
Reg143
FUNCTION
DEFAULT CONTENTS
REGISTER
ADDRESS
0000000000001100
0011101
*********0000000
10001111
VREF1 bias control.
Bits 0-3 bias value.
Bit 7 = 1 disable internal bias.
Bits 4-6, 8-15 not used, set to 0.
ADC calibration data output register.
Register Start-up Sequence
end of calibration and the integration process takes
place during this frame but valid data for the first pixel
row is not output until the second frame.
All two-wire serial interface parameters can be written to registers at any time but they do not take effect
until the subsequent frame. Writing to two-wire serial
interface registers has no effect on the output timing
(i.e., it does not slow down or stop output); the exception to this rule is when the sensor is commanded to
perform ADC calibration.
Upon powering up the MT9V403, the sensor should
be reset by bringing the LRST_N pin LOW. This will initialize all of the registers to their default values. Upon
the release of reset, the sensor will perform ADC calibration. The default mode is simultaneous master
mode with the horizontal blanking register set to 169
and the vertical blanking register set to 35. The default
frame size is 648 x 480 pixels, excluding dark pixels.
The first frame starts just three SYSCLK cycles after the
Feature Description
Signal Path
An example of the signal path is shown below in
Figure 21.
Figure 21: Signal Path
Pixel
Photo
Detector
End
Exposure
Switch (TX)
Pixel
Memory
Start Exposure
Switch (PG)
VRST_PIX
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
Reset
Memory
Switch
(RESMEM)
VAA
Column Processing
VREF2
ADC
Calibration
DAC
7
Buffer PGA Buffer
VREF1
Sample
& Hold
+
Σ
VLP VLN_AMP
VLN_OUT
VLN1
VREF
Σ
ADC
10
To
ADC
registers
VLN2
Offset
VOFF/20
17
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Window Location and Size
When windowing is utilized, the user should be
aware of how the sensor timing is impacted. A key
point to note is that the row time is always 671 clock
cycles, independent of how many columns are actually
read out of the sensor. Figure 23 provides a master
mode row timing example for windowing from column
100 to column 200. This shows how changing the number of columns in a window will not change the timing
nor the frame rate. Figure 24 provides a master mode
frame timing example for windowing from row 300 to
row 400. This shows how changing the number of rows
in a window will increase the frame rate.
There is also an option to scan just a window of
interest by using the two-wire serial interface to specify the coordinates of the upper right most pixel and
the lower left most pixel to define the desired windowing area as shown in Figure 22. The user can increase
the frame rate by decreasing the number of rows in a
window. Decreasing the number of columns has no
effect on frame rate. For example, for the full 667 column by 502 row resolution the MT9V403 operates at
196 fps, but if the vertical resolution is decreased by
half (i.e., 251 rows) the frame rate increases proportionally so the frame rate is doubled to 392 fps.
Figure 22: Windowing Example
(502,667)
STOP WINDOW
(ROW,COLUMN)
START WINDOW
(ROW,COLUMN)
(1, 1)
Figure 23: Row Timing for Master Mode and Snapshot Mode with Windowing
1
671
SYSCLK
(input)
((
))
((
))
1
((
))
((
))
((
))
((
))
((
))
((
))
ROW_VALID
(output)
((
))
((
))
DATA [9:0]
(output)
XXX
((
))
((
))
100
101
XXX
((
))
((
))
Start
Column
199
200
((
))
((
))
((
))
((
))
XXX
100
101
XXX
((
))
( ( 199
))
200
Stop
Column
Figure 24: Frame Timing for Master Mode and Snapshot Mode with Windowing
((
))
FRAME_VALID
(output)
((
))
XXX
Row Row
300 301
((
))
((
))
XXX
((
))
Row Row
N-1
N
((
))
((
))
XXX
((
))
Row Row Row
397 398 399
Start
Row
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
((
))
Vertical Blanking
ROW_VALID
(output)
DATA [9:0]
(output)
((
))
XXX
Row Row
300 301
((
))
((
))
((
))
Row Row
N-1
N
((
))
((
))
((
))
Row Row Row
397 398 399
Stop
Row
18
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
delay. Even though the windowed columns can be
readout at the beginning of a row, the user must still
wait the required 671 clock cycles for the row processing to complete before initiating the processing of the
next row with ROW_STRT. Figure 26 provides a slave
mode frame timing example for windowing from row
300 to row 400 which—similar to the master mode—
shows how changing the number of rows in a window
will increase the frame rate.
In slave mode the user has more control of the sensor but the same basic rules apply; the row time is still
always 671 clock cycles. Figure 25 provides a slave
mode row timing example for windowing from column
100 to column 200. The row processing is initiated by
raising ROW_STRT and requires 671 clock cycles to
complete. The user can readout the desired window of
columns by lowering LD_SHFT_N and the specified
columns will appear on the output with a 3.5 SYSCLK
Figure 25: Row Timing for Slave Mode with Windowing
1
671
SYSCLK
(input)
ROW_STRT
(input)
((
))
((
))
((
))
((
))
((
))
((
))
1
3.5 SYSCLK DELAY
LD_SHFT_N
(input)
DATA [9:0]
(output)
XXX
100
((
))
((
))
102
101
Start
Column
199
((
))
((
))
200
Stop
Column
Figure 26: Frame Timing for Slave Mode with Windowing
FRAME_SYNC_N
(input)
ROW_STRT
(input)
LD_SHFT_N
(input)
DATA [9:0]
(output)
Row
400
Row
300
Row
301
Row
302
Row
303
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
Row
395
Row
396
Row
397
Row
398
Start
Row
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
Row
399
Row
400
Row
300
Row
301
Row
302
Row
303
((
))
((
))
Row
395
Row
396
Row
397
Row
398
Row
399
Stop
Row
19
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Electronic Shutter Exposure Control
frame times (1.3 sec @ 200 fps) or the inverse of the
frame rate.
When in simultaneous master mode, the maximum
integration time is limited by the inverse of the frame
rate because one cannot integrate longer than a frame
time. With a 66 MHz clock and full resolution (502
rows) the maximum integration time is 5ms
(= 1/200 fps). In sequential master mode or snapshot
mode the maximum integration time is limited to 256
frame times. Table 5 shows some examples of how the
maximum integration time changes with resolution
and clock speed.
For the master and snapshot mode the electronic
shutter's exposure duration (integration time) is programmed via the two-wire serial interface. The
MT9V403 shutter can be operated to generate continuous video output (simultaneous master mode or
sequential master mode) or capture single images
(snapshot mode).
The minimum integration time in master or snapshot mode is 2 row times. With a 66 MHz SYSCLK the
minimum integration time is 20µs (10µs row time ±2
rows). The maximum integration time is either is 256
Table 5:
Maximum Integration Time vs. Resolution and Clock Speed
Sequential mode or snapshot mode
RESOLUTION (# OF ROWS)
CLOCK SPEED (SYSCLK)
FRAME TIME
{= N x 671 x 1/FSYSCLK}
MAXIMUM
INTEGRATION TIME
502 (full resolution)
251
125
63
502 (full resolution)
251
125
63
502 (full resolution)
66 MHz
66 MHz
66 MHz
66 MHz
24 MHz
24 MHz
24 MHz
24 MHz
10 MHz
5.1ms
2.6ms
1.3ms
0.6ms
14ms
7ms
5.1ms
1.8ms
33ms
1.3 sec
0.7 sec
0.3 sec
0.2 sec
3.6 sec
1.8 sec
0.9 sec
0.4 sec
8 sec
Readout Scanning
which shows alternating readout of the even-numbered and odd-numbered rows in consecutive frames.
There is also an option that allows sequential readout
of only the odd or even rows of a frame (effectively a X2
vertical subsampling of the image).
The MT9V403 can operate in either progressive scan
or interlaced scan modes. Progressive scan is the
default mode. In the interlace scan mode there are two
readout options. The frame synchronization waveforms for interlaced scanning are shown in Figure 27,
Figure 27: Frame Synchronization Waveforms for Interlaced Scanning
Odd Field Marker
FRAME_VALID
ROW_VALID
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
Row 2
Row 4
Row 494
20
Row 1
Row 493
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©2004 Micron Technology. Inc.
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Gain Settings
should not have to be changed for different imaging
conditions.
VLN2: Internal default value should be used as the
starting point. VLN2 controls the current in the ADC
comparators and there is a safe range where this voltage has no effect; settings below this range will cause
the comparators to fail. For high-speed operation,
VLN2 may need to be increased to remove random
white spots. VLN2 may be further increased with register 17 by setting bit 0 to “1.” If this does not completely
solve the problem, set bit 7 in register 18 to disable
VLN_OUT.
There are four independent gain controls which are
programmed via the two-wire serial interface. The four
gains correspond to four cells of the Bayer pattern
color filter array: red, green1, blue, and green2. The
gain step size can be set to 1 or 0.5. When the step size
is 1 the gain can programmed in 18 steps from X1 to
X18. When the step size is 0.5, the gain can be programmed 18 steps from X1 to X9. Global gain control is
achieved by changing the four gains equally and
simultaneously.
To obtain the desired analog signal chain gain, set
the following registers as shown in Table 6.
Analog Biases
VRST_PIX: Should be set to 2.5V.
VREF2: Internal default value is recommended.
VLN1: Internal default value is recommended.
VOFF: Internal default value is recommended.
VREF1: Internal default value is recommended.
VLP: Internal default value is recommended.
VLN_OUT: Internal default value is recommended.
VLN_AMP: Internal default value is recommended.
VREF: Internal default value is recommended.
VLN1, VLP, VOFF, VREF, VREF1, VLN2 VREF2,
VLN_AMP, and VLN_OUT are generated on-chip and
can be adjusted via a two-wire serial interface. Also,
the user may disable internal bias via a two-wire serial
interface and apply external voltages to the sensor.
VREF1DRV is generated on-chip but its internal bias
cannot be disabled. VRST_PIX and VRSTLOW are not
generated internally and external voltages must be
applied.
ADC Calibration
Considerations when Setting Analog
Voltages
The MT9V403 contains a special self-calibrating circuitry that enables it to reduce its own column-wise
fixed-pattern noise. This calibration process consists
of connecting a calibration signal to each of the 167
ADC inputs and estimating and storing these 167 offsets (as 7 bits) to subtract from subsequent samples.
Self-calibration automatically occurs after global logic
reset (LRST_N) or the two-wire serial interface (register
12), and programs new offset values for each ADC into
calibration memory. These values may be different
from those calculated in the previous calibration if
there has been a change in environment (e.g., temperature). The accuracy of calibration is approximately
1mVrms.
The starting point for setting the analog voltages
should be the values suggested in the typical values
columns of the Tables 7 and 8. Additionally, Figure 21
on page 17, the “Signal Path Diagram,” indicates how
the analog voltages affect the image. Other considerations follow:
VRSTLOW: Functions as a pixel anti-blooming control. For high illumination conditions (typically used in
conjunction with a short integration time) black/white
spots may appear. To eliminate these artifacts, this
voltage should be set to ~0.4V. Once set, this value
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
21
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©2004 Micron Technology. Inc.
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Table 6:
Pixel Gain Matrix
REGISTERS 43-46
0000 0001
0000 0010
0000 0011
0000 0100
0000 0101
0000 0110
0000 0111
0000 1000
0000 1001
0000 1010
0000 1011
0000 1100
0000 1101
0000 1110
0000 1111
0001 0000
0001 0001
0001 0010
0000 0001
0000 0010
0000 0011
0000 0100
0000 0101
0000 0110
0000 0111
0000 1000
0000 1001
0000 1010
0000 1011
0000 1100
0000 1101
0000 1110
0000 1111
0001 0000
0001 0001
0001 0010
REGISTER 53
TOTAL GAIN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1.0
2.0
3.0
4.0
5.0
6.0
7.
8.0
9.0
10.0
11.0
12.0
13.0
14.0
15.0
16.0
17.0
18.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
12. A timing diagram for the two-wire serial interface
initiated calibration is shown in Figure 28.
In master mode and snapshot mode, during twowire serial interface initiated calibration, ROW_VALID
goes HIGH for 146 SYSCLK immediately after
FRAME_VALID goes HIGH to indicate that the calibration process is occurring. The output of the sensor is
interrupted during the calibration process to prevent
output noise from corrupting the calibration. After the
calibration process is complete, ROW_VALID goes
ADC calibration takes 146 SYSCLK cycles. Nominally, calibration should be initiated through the application of LRST_N, in which case the calibration takes
place upon release of the LRST_N. Some applications
may require initiating calibration by asynchronously
writing a one- to two-wire serial interface to register
12, in which case the calibration is delayed until the
beginning of the next frame. Calibration will continue
to occur every frame until a zero is written to register
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
22
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
user hold LD_SHFT_N HIGH during this calibration
process to minimize calibration noise. When the calibration is complete, LD_SHFT_N may be lowered to
commence the normal frame readout process.
LOW and the normal data readout process commences when it returns HIGH. For two-wire serial
interface initiated calibration in slave mode, the first
ROW_STRT pulse of the calibration frame initiates the
146 SYSCLK calibration process. It is suggested that the
Figure 28: Two-Wire Serial Interface Initiated Calibration
GLOBAL LOGIC RESET
146 SYSCLK
FRAME_VALID
ROW_VALID
DATA [9:0]
XXX
In a similar manner, a special read-only two-wire
serial interface register (register 143) is dedicated to
calibration data output. Calibration data can be continuously read from this register with an 8-bit read. To
read from the calibration register, the typical two-wire
serial interface write sequence is adhered to, including
address (register 143), followed by 167 8-bit transfers
(note that each coefficient utilizes the 7 LSBs of the
eight-bits two-wire serial interface word). This reading
process must be continuous (ADC 1 to ADC 167) and
coefficients cannot be selectively read.
The calibration coefficients can be read from the
MT9V403 and written to it, making it possible to further reduce column-wise fixed pattern noise by externally calculating and writing the proper offset values to
the MT9V403. For example, the user may choose to
calculate the more precise offset values by averaging
several frames and uploading the coefficients to the
MT9V403. The user may also calculate coefficients for
several temperature values and upload the appropriate values based on the environment.
A special write-only two-wire serial interface register (register 15) is dedicated to the calibration data
input. Calibration data can be continuously written to
this register with an eight-bit write. To write to the calibration register, the typical two-wire serial interface
write sequence is adhered to, including address (register 15), followed by 167 eight-bit transfers (note that
each coefficient utilizes the 7 LSBs of the eight-bit twowire serial interface word). This writing process must
be continuous (ADC 1 to ADC 167) and coefficients
cannot be selectively written.
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
First Valid
Row
Anti-Eclipse Circuit
The MT9V403 includes a pixel memory reset pulse
duration control. This control enables a mode where
the reset of the pixel is held for a longer period of time.
This can be implemented by setting bit 0 to 7 in register 13. In some extremely bright lighting conditions,
this extended reset may prevent the eclipse-like phenomena (black spots on a bright background) to which
some CMOS sensors are prone.
23
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©2004 Micron Technology. Inc.
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Digital Ground
6
VDD
27
VDD
36
VDD
43
VDD
Analog Ground
Digital +3.3V
Analog +3.3V
VAA 12
VAA 22
Figure 29: Board Connections
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
Digital +3.3V
1.5kΩ
Controller
Interface
39
32
37
29
31
38
30
33
26
25
24
SDATA
FRAME_SYNC_N
SYSCLK
EXPOSE
ROW_VALID/LD_SHFT_N
SCLK
FRAME_VALID/ROW_STRT
LRST_N
PG_N
TX
RESMEM
8
VREF1DRV
VLN2
3
2
1
48
47
46
42
45
40
41
Output
Analog +3.3V
21
1kΩ
10µF
10µF
0.1µF
0.1µF
Analog +3.3V
Pixel
Data
17
VLN1
VRST_PIX
Analog +3.3V
20
1kΩ
1kΩ
10µF
10µF
0.1µF
Analog +3.3V
1kΩ
0.1µF
19
VLP
VREF
10µF
1kΩ
10µF
0.1µF
Analog +3.3V
Analog +3.3V
16
0.1µF
9
VREF1
VOFF
1kΩ
10µF
Analog +3.3V
13
1kΩ
10µF
0.1µF
0.1µF
14
VRSTLOW
VTEST1
Analog +3.3V
23
1kΩ
10µF
0.1µF
4
5
28
34
35
44
0.1µF
Digital Ground
VLNS
AGND
AGND
AGND
10µF
VREF2
Analog +3.3V
18
1kΩ
10µF
0.1µF
10
11
15
7
1kΩ
DGND
DGND
DGND
DGND
DGND
DGND
Analog +3.3V
Analog Ground
NOTE:
1. VLN1, VLP, VOFF, VREF, VREF1, VLN2, and VREF2 are generated on-chip, but user may disable internal bias (via twowire serial interface) and apply external voltages to sensor. VREF1DRV is generated on chip but its internal bias cannot be disabled. VRST_PIX and VRSTLOW are not generated internally and external voltages must be applied.
2. All bias pins should be decoupled with 0.1µF ceramic and 10µF electrolytic capacitors. (Please see board connections.)
Capacitors should be placed as physically close as possible to the MT9V403 package.
3. Digital outputs can drive standard CMOS circuits with 30pF load, but less load capacitance results in less substrate
noise on-chip. This is recommended to minimize load capacitance for better noise performance.
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
24
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©2004 Micron Technology. Inc.
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Figure 30: Propagation Delays for Data Output, Frame Valid, and Row Valid Signals
TplhD, TphlD
SYSCLK
DOUT(9:0)
tr
TplhF
TphlF
SYSCLK
SYSCLK
FRAME_VALID
FRAME_VALID
tr
tr
TplhL
TphlL
SYSCLK
SYSCLK
ROW_VALID
ROW_VALID
tr
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
tr
25
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©2004 Micron Technology. Inc.
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Electrical Specifications
Table 7:
AC Electrical Characteristics
VPWR = 3.3 ±0.3V; TA = 25°C
SYMBOL
tPLHD
DEFINITION
CONDITION
MIN
TYP
MAX
UNIT
Data output propagation delay for LOW-to-HIGH transition
CLOAD = 10pF
2
ns
Data output propagation delay for HIGH-to-LOW transition
CLOAD = 10pF
2
ns
t
PLHL
ROW_VALID propagation delay for LOW-to-HIGH transition
CLOAD = 10pF
2
ns
tPHLL
ROW_VALID propagation delay for HIGH-to-LOW transition
CLOAD = 10pF
2
ns
t
FRAME_VALID propagation delay for LOW-to-HIGH transition CLOAD = 10pF
2
ns
tPHLF
FRAME_VALID propagation delay for HIGH-to-LOW transition CLOAD = 10pF
2
ns
t
PHLD
PLHLF
Table 8:
DC Electrical Characteristics
VPWR = 3.3 ±0.3V; TA = 25°C
SYMBOL
VLN_AMP
VLN2
VLN_OUT
VLN1
VLP
VREF
VREF2
VREF1
VOFF
VRST_PIX
VRSTLOW
VTEST
VREF1DRV
VIH
VIL
IIN
VOH
VIH
IOH
IPWR
DEFINITION
Input High Voltage
Input Low Voltage
Input Leakage Current
Output High Voltage
Output Low Voltage
Output High Current
Supply Current
CONDITION
MIN
TYP1
MAX
UNIT
Internal/External
Internal/External
Internal/External
Internal/External
Internal/External
Internal/External
Internal/External
Internal/External
Internal/External
External Only
External Only
External Only
Internal Only
0.5
0.5
0.5
0.5
1.5
1
0
0
0
1
0
2.5
-0.3
-300
Internal (0.7)
Internal (1.1)
Internal (0.8)
Internal (0.7)
Internal (1.9)
Internal (1.6)
Internal (1)
Internal (1)
Internal (0)
2.5
0 - 0.4
0
open
1.5
1.5
1.5
1.5
2.5
2
2
2
3
3.3
1
VPWR + 0.3
0.8
+300
V
V
V
V
V
V
V
V
V
V
V
No Pull-up Resistor;
VIN - VPWR or VGND
VPWR - 0.2
100
CLK_IN = 42 MHz; default setting
220
0.2
20
V
V
V
uA
V
mV
mA
mA
NOTE:
1. Where indicated, internally generated biases are typically utilized. The parenthetical number indicates typical value
if external voltage is applied.
2. This device contains circuitry to protect the inputs against damage from high static voltages or electric fields, but the
user is advised to take precautions to avoid the application of any voltage higher than the maximum rated.
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
26
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Two-Wire Serial Bus Timing
The two-wire serial bus operation requires a certain
minimum number of master clock cycles between
transitions. These are specified below in master clock
cycles.
Figure 31: Serial Host Interface Start
Condition Timing
Figure 33: Serial Host Interface Data
Timing for Write
5
4
4
4
SCLK
SCLK
SDATA
SDATA
NOTE:
SDATA is driven by an off-chip transmitter.
Figure 34: Serial Host Interface Data
Timing for Read
Figure 32: Serial Host Interface Stop
Condition Timing
5
4
5
SCLK
SCLK
SDATA
SDATA
NOTE:
NOTE:
All timing are in units of master clock cycle.
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
SDATA is pulled LOW by the sensor, or allowed to be
pulled HIGH by a pull-up resistor off-chip.
27
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©2004 Micron Technology. Inc.
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Figure 35: Acknowledge Signal Timing After an 8-Bit Write from Sensor
3
6
SCLK
Sensor pulls down
SDATA pin
SDATA
Figure 36: Acknowledge Signal Timing After an 8-Bit Read to Sensor
6
7
SCLK
SDATA
Sensor tri-states SDATA pin
(turns off pull down)
NOTE:
After a read, the master receiver must pull down SDATA to acknowledge receipt of data bits. When read sequence is
complete, the master must generate a no acknowledge by leaving SDATA to float HIGH. On the following cycle, a start or
stop bit may be used.
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
28
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©2004 Micron Technology. Inc.
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Electrical Specifications
Table 9:
Image Sensor Characteristics
TA = 25°C
SYMBOL
PARAMETER
RI
Responsivity (ADC VREF1 = 1V)
DSNU
VDRK
Dyn_I
PRNU
NSAT
NE
KDRK
Dark signal non-uniformity
Output referred dark signal
Internal dynamic range
Photo response non-uniformity
Pixel saturation level
Input referred noise: Overlapped conversion and digital readout (200 fps)
Dark current temperature coefficient
TYP
UNIT
1,800
LSB/lux-sec.
0.5
100
60
1
110,000
98
100
%rms
mV/sec
dB
%rms
electrons
electrons
%/8°C
Table 10: Pixel Array
SYMBOL
Resolution
Pixel Size
Pixel Pitch
Pixel Fill Factor
Shutter Efficiency
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
PARAMETER
Number of pixels in active image
X-Y dimensions
Center-to-center pixel spacing
Area of drawn active area
Equals: 1-(leakage into in pixel memory)
29
TYP
UNIT
659 x 494
9.9
9.9
50
98.5
pixels
µm
µm
%
%
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Figure 37: Quantum Efficiency – Monochrome
35
Quantum Efficiency (%)
30
25
20
15
10
5
0
350
450
550
650
750
850
950
1050
Wavelength (nm)
Figure 38: Quantum Efficiency – Color
25
Blue
Green (B)
Green (R)
Red
Quantum Efficiency (%)
20
15
10
5
0
350
450
550
650
750
850
950
1050
Wavelength (nm)
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
30
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Figure 39: Pixel Array Offset Drawing
14.22±.013 (Square)
9.149
(502, 667)
8.915
4.97
1.318±0.2
6.61
(1, 1)
PIN 1
0.267±0.25
NOTE:
1. All dimensions are in millimeters.
2. Tolerance on die placement is ±0.25mm.
3. Rotation <2°.
4. Tilt ±2 mils.
Figure 40: Package Drawing – Top View
14.07
14.52
42
31
43
30
13.16 sq
13.26 sq
6
19
7
18
NOTE:
1. Dimensions in mm.
-------------2. MAX
MIN
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
31
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Figure 41: Package View – Bottom View
11.18 TYP
1.02 TYP
1.52 TYP
31
42
43
30
48
Pin No.1
index
0.51 TYP
19
6
18
7
1.75
2.25
1.02 TYP
Figure 42: Package Drawing - Side View
0.50
0.60
glass
1.01
1.27
0.746
1.178
0.710
0.740
0.246
0.578
Die
1.11
1.34
0.38
0.56
1.91
2.46
NOTE:
1. Dimensions in millimeters.
2. Borosilicate: glass with refractive index: 1.52nm at 546nm.
-------------3. MAX
MIN
Data Sheet Designation
No Marking: This data sheet contains minimum and maximum limits specified over the complete power supply
and temperature range for production devices. Although considered final, these specifications are
subject to change, as further product development and data characterization sometimes occur.
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: [email protected], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron, the M logo, the Micron logo, and TrueSNAP are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
32
Micron Technology, Inc., reserves the right to change products or specifications without notice..
©2004 Micron Technology, Inc
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Revision History
Rev B, ...............................................................................................................................................................................1/04
• Removed Preliminary Status
• Updated Figure 13
• Updated IIN Input Leakage current specifications in the DC Characteristics Table
• Added high-static note to DC Characteristics Table
Rev 0.7, Preliminary ........................................................................................................................................................8/03
• Initial Release of document
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
33
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.