MOSEL VITELIC PRELIMINARY V436516Y04V 128MB 144-PIN UNBUFFERED SDRAM SODIMM, 16MX64 3.3VOLT Features Description ■ JEDEC-standard 144 pin, Small-Outline, Dual in line Memory Module (SODIMM) ■ Serial Presence Detect with E2PROM ■ Nonbuffered ■ Fully Synchronous, All Signals Registered on Positive Edge of System Clock ■ Single +3.3V (± 0.3V) Power Supply ■ All Device Pins are LVTTL Compatible ■ 4096 Refresh Cycles every 64 ms ■ Self-Refresh Mode ■ Internal Pipelined Operation; Column Address can be changed every System Clock ■ Programmable Burst Lengths: 1, 2, 4, or 8 ■ Auto Precharge and Precharge all Banks by A10 ■ Data Mask Function by DQM ■ Mode Register Set Programming ■ Programmable (CAS Latency: 2, 3 Clocks) ■ SDRAM Performance The V436516Y04V memory module is organized 16,777,216 x 64 bits in a 144 pin SODIMM. The 16M x 64 memory module uses 8 Mosel-Vitelic 8M x 16 SDRAM. The x64 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required. 8M x 16 8M x 16 59 1 Speed Grade Configuration V436516Y04VATG-75PC -75PC,CL=2,3(133MHZ) 16Mx64 V436516Y04VATG-75 V436516Y04VATG-10PC 8M x 16 -75, CL=3 143 Pin 144 on Backside 1 (133MHZ) -10PC,CL=2,3(100MHZ) 8M x 16 61 Pin 2 on Backside V436516Y04V Rev. 1.0 October 2001 Part Number 16Mx64 16Mx64 MOSEL VITELIC V436516Y04V Pin Configurations (Front Side/Back Side) Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 VSS VSS DQ0 DQ32 DQ1 DQ33 DQ2 DQ34 DQ3 DQ35 VDD VDD DQ4 DQ36 DQ5 DQ37 DQ6 DQ38 DQ7 DQ39 VSS VSS DQMB0 DQMB4 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 DQMB1 DQMB5 VDD VDD A0 A3 A1 A4 A2 A5 VSS VSS DQ8 DQ40 DQ9 DQ41 DQ10 DQ42 DQ11 DQ43 VDD VDD DQ12 DQ44 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 DQ13 DQ45 DQ14 DQ46 DQ15 DQ47 VSS VSS NC NC NC NC CLK0 CKE0 VDD VDD RAS CAS WE CKE1 CS0 NC CS1 NC 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 NC CLK1 VSS VSS NC NC NC NC VDD VDD DQ16 DQ48 DQ17 DQ49 DQ18 DQ50 DQ19 DQ51 VSS VSS DQ20 DQ52 DQ21 DQ53 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 DQ22 DQ54 DQ23 DQ55 VDD VDD A6 A7 A8 BA0 VSS VSS A9 BA1 A10 A11 VDD VDD DQMB2 DQMB6 DQMB3 DQMB7 VSS VSS 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 DQ24 DQ56 DQ25 DQ57 DQ26 DQ58 DQ27 DQ59 VDD VDD DQ28 DQ60 DQ29 DQ61 DQ30 DQ62 DQ31 DQ63 VSS VSS SDA SCL VDD VDD Note: 1. RAS, CAS, WE CASx, CSx are active low signals. Pin Names A0–A11, BA0, BA1 Address, Bank Select DQ0–DQ63 Data Inputs/Outputs RAS Row Address Strobes CAS Column Address Strobes WE Write Enable CS0, CS1 Chip Select DQMB0–DQMB7 Output Enable CKE0, CKE1 Clock Enable CLK0–CLK1 Clock SDA Serial Input/Output SCL Serial Clock VDD Power Supply VSS Ground NC No Connect (Open) V436516Y04V Rev. 1.0 October 2001 2 MOSEL VITELIC V436516Y04V Part Number Information V 4 3 65 16 Y 0 4 V A T G - XX SPEED 75 = PC133 CL3 75PC=PC133 CL2,3 10PC=PC100 CL2,3 LEAD FINISH G = GOLD MOSEL VITELIC MANUFACTURED SDRAM 3.3V COMPONENT PACKAGE, T = TSOP WIDTH DEPTH COMPONENT REV LEVEL 168 PIN REGISTERED DIMM X16 COMPONENT LVTTL REFRESH RATE4K 4 BANKS Block Diagram CS0 WE DQMB0 WE CS UDQM DQ0–7 DQMB4 WE UDQM DQMB1 LDQM DQ8–15 DQMB5 LDQM DQMB2 WE CS UDQM DQ16–23 DQMB6 WE UDQM U0 DQ32–39 U2 U1 DQMB3 CS DQ40–47 CS DQ43–54 U3 LDQM DQ24–31 DQMB7 LDQM WE CS UDQM DQ0–7 DQMB4 WE UDQM DQ55–63 CS1 WE DQMB0 U4 LDQM DQ8–15 DQMB5 LDQM DQMB2 WE CS UDQM DQ16–23 DQMB6 WE UDQM U5 LDQM DQ24–31 U0–U7 A0–A11, BA0, BA1 U0–U7 CKE0 U0–U3 CKEI U4–U7 RAS U0–U7 DQMB7 CS DQ43–54 DQ55–63 LDQM U0, U1 CLK0 U2, U3 0Ω U4, U5 0Ω CLKI U6, U7 SPD U0–U7 SCL Note: All resistors are 10 Ohms V436516Y04V Rev. 1.0 October 2001 DQ40–47 U7 VDD VSS CAS DQ32–39 U6 DQMB1 DQMB3 CS 3 A0 A1 A2 SDA MOSEL VITELIC V436516Y04V Serial Presence Detect Information written into the E2PROM device during module production using a serial presence detect protocol (I2C synchronous 2-wire bus) A serial presence detect storage device – – is assembled onto the module. Information about the module configuration, speed, etc. is E2PROM SPD-Table for -75 modules: Hex Value Byte Number Function Described SPD Entry Value 133 MHz -75PC 133 MHZ -75 100 MHZ -10PC 0 Number of SPD bytes 128 80 80 80 1 Total bytes in Serial PD 256 08 08 08 2 Memory Type SDRAM 04 04 04 3 Number of Row Addresses (without BS bits) 12 0C 0C 0C 4 Number of Column Addresses (for x16 SDRAM) 9 09 09 09 5 Number of DIMM Banks 2 02 02 02 6 Module Data Width 64 40 40 40 7 Module Data Width (continued) 0 00 00 00 8 Module Interface Levels LVTTL 01 01 01 9 SDRAM Cycle Time at CL=3 7.5 ns/10.0 ns 75 75 A0 10 SDRAM Access Time from Clock at CL=3 5.4 ns/6.0 ns 54 54 60 11 Dimm Config (Error Det/Corr.) none 00 00 00 12 Refresh Rate/Type Self-Refresh, 15.6µs 80 80 80 13 SDRAM width, Primary x16 10 10 10 14 Error Checking SDRAM Data Width n/a / x8 00 00 00 15 Minimum Clock Delay from Back to Back Random Column Address tccd = 1 CLK 01 01 01 16 Burst Length Supported 1, 2, 4, 8 0F 0F 0F 17 Number of SDRAM Banks 4 04 04 04 18 Supported CAS Latencies CL = 2 & 3 06 06 06 19 CS Latencies CS Latency = 0 01 01 01 20 WE Latencies WL = 0 01 01 01 21 SDRAM DIMM Module Attributes Non Buffered/Non Reg. 00 00 00 22 SDRAM Device Attributes: General Vcc tol ± 10% 0E 0E 0E 23 Minimum Clock Cycle Time at CAS Latency = 2 7.5 ns/10.0 ns 75 A0 A0 24 Maximum Data Access Time from Clock for CL = 2 5.4 ns/6.0 ns 54 60 60 25 Minimum Clock Cycle Time at CL = 1 Not Supported 00 00 00 26 Maximum Data Access Time from Clock at CL = 1 Not Supported 00 00 00 27 Minimum Row Precharge Time tRP 15 ns/20 ns 0F 14 14 28 Minimum Row Active to Row Active Delay tRRD 14 ns/15 ns 0E 0F 0F 29 Minimum RAS to CAS Delay tRCD 15 ns/20 ns 0F 14 14 V436516Y04V Rev. 1.0 October 2001 4 MOSEL VITELIC V436516Y04V SPD-Table for -75 modules: (Continued) Hex Value Byte Number Function Described SPD Entry Value 133 MHz -75PC 133 MHZ -75 100 MHZ -10PC 30 Minimum RAS Pulse Width tRAS 42 ns/45 ns 2A 2D 2D 31 Module Bank Density (Per Bank) 64 MByte 10 10 10 32 SDRAM Input Setup Time 1.5 ns/2.0 ns 15 15 20 33 SDRAM Input Hold Time 0.8 ns/1.0 ns 08 08 10 34 SDRAM Data Input Setup Time 1.5 ns/2.0 ns 15 15 20 35 SDRAM Data Input Hold Time 0.8 ns/1.0 ns 08 08 10 00 00 00 02 02 12 36-61 Superset Information (May be used in Future) 62 SPD Revision 63 Checksum for Bytes 0 - 62 D2 17 84 Manufacturers’s Information (Optional) 00 00 00 64 64 64 00 00 00 64-125 126 Max. Frequency Specification 127 Frequency Support Details 128+ Unused Storage Location Revision 2/1.2 133 MHz Absolute Maximum Ratings Parameter Max. Units Voltage on VDD Supply Relative to VSS -1 to 4.6 V Voltage on Input Relative to VSS -1 to 4.6 V Operating Temperature 0 to +70 °C -55 to 125 °C 3.5 W Storage Temperature Power Dissipation DC Characteristics TA = 0°C to 70°C; VSS = 0 V; VDD, VDDQ = 3.3V ± 0.3V Limit Values Symbol Parameter Min. Max. Unit VIH Input High Voltage 2.0 VCC +0.3 V V IL Input Low Voltage –0.5 0.8 V V OH Output High Voltage (IOUT = –2.0 mA) 2.4 — V VOL Output Low Voltage (IOUT = 2.0 mA) — 0.4 V II(L) Input Leakage Current, any input (0 V < VIN < 3.6 V, all other inputs = 0V) –10 10 µA IO(L) Output leakage current (DQ is disabled, 0V < VOUT < VCC) –10 10 µA V436516Y04V Rev. 1.0 October 2001 5 MOSEL VITELIC V436516Y04V Capacitance TA = 0°C to 70°C; VDD = 3.3V ± 0.3V, f = 1 MHz Symbol Parameter Limit Values Unit 105 pF CI1 Input Capacitance (A0 to A11, RAS, CAS, WE) CI2 Input Capacitance (CS0, CSI) 32 pF CICL Input Capacitance (CLK0-CLK1) 40 pF CI3 Input Capacitance (CKE0, CKEI) 65 pF CI4 Input Capacitance (DQMB0-DQMB7) 20 pF CSC Input Capacitance (SCL, SA0-2) 8 pF CIO Input/Output Capacitance 10 pF Standby and Refresh Currents1 TA = 0°C to 70°C, VCC = 3.3V ± 0.3V Symbol Parameter Test Conditions 75PC/75 10PC Unit Note ICC1 Operating Current Burst length = 4, CL = 3 tRC> = tRC(min), tCK> = tCK(min) 600 540 mA 1,2 ICC2P Precharged Standby Current in Power Down Mode CKE< = VIL(max), tCK> = tCK(min) 12 12 mA ICC2N Precharged Standby Current in Non-Power Down Mode CKE> = VIH(min), tCK> = tCK(min), Input changed once in 3 cycles 180 140 mA ICC3P Active Standby Current in Power Down Mode CKE< = VIL(max), tCK> = tCK(min) 80 80 mA ICC3N Active Standby Current in Non-Pow- CKE> = VIH(min), tCK> = tCK(min), Iner Down Mode put changed one time 220 180 mA CS = High ICC4 Burst Operating Current tRC = Infinite, CL = 3, tCK> = tCK(min) 440 360 mA 1, 2 ICC5 Auto Refresh Current tRC>= tRC(min) 1000 840 mA 1,2 ICC6 Self Refresh Current CKE = <0,2 V 12 12 mA 1,2 L-Version 6.4 6.4 mA V436516Y04V Rev. 1.0 October 2001 6 CS = High MOSEL VITELIC V436516Y04V AC Characteristics TA = 0° to 70°C; VSS = 0V; VCC = 3.3V ± 0.3V, tT = 1 ns Limit Values -75PC # Symbol Parameter -75 -10PC Min. Max. Min. Max. Min. Max. Unit Clock Cycle Time CAS Latency = 3 CAS Latency = 2 7.5 7.5 – – 7.5 10 – – 10 10 – – s ns ns Clock Frequency CAS Latency = 3 CAS Latency = 2 – – 133 133 – – 133 100 – – 100 100 MHz MHz Access Time from Clock CAS Latency = 3 CAS Latency = 2 – _ 5.4 5.4 – _ 5.4 6.0 – _ 6.0 6.0 ns ns Note Clock and Clock Enable 1 2 3 tCK tCK tAC 2, 4 4 tCH Clock High Pulse Width 2.5 – 2.5 – 3 – ns 5 tCL Clock Low Pulse Width 2.5 – 2.5 – 3 – ns 6 tT Transition Tim 0.3 1.2 0.3 1.2 0.3 1.2 ns Setup and Hold Times 7 tIS Input Setup Time 1.5 – 1.5 – 2.0 – ns 5 8 tIH Input Hold Time 0.8 – 0.8 – 1.0 – ns 5 9 tCKS Input Setup Time 1.5 – 1.5 – 2.0 – ns 5 10 tCKH CKE Hold Time 0.8 – 0.8 – 1.0 – ns 5 11 tRSC Mode Register Set-up Time 15 – 15 – 20 – ns 12 tSB Power Down Mode Entry Time 0 7.5 0 7.5 0 10 ns Row to Column Delay Time 15 – 20 – 20 – ns 6 Common Parameters 13 tRCD 14 tRP Row Precharge Time 15 – 20 – 20 – ns 6 15 tRAS Row Active Time 42 100K 45 100K 45 100K ns 6 16 tRC Row Cycle Time 70 – 70 – 70 – ns 6 17 tRRD Activate(a) to Activate(b) Command Period 14 – 15 – 15 – ns 6 18 tCCD CAS(a) to CAS(b) Command Period 1 – 1 – 1 – CLK Refresh Period (4096 cycles) — 64 — 64 — 64 ms Self Refresh Exit Time 10 Refresh Cycle 19 tREF 20 tSREX V436516Y04V Rev. 1.0 October 2001 7 10 10 ns MOSEL VITELIC V436516Y04V AC Characteristics TA = 0° to 70°C; VSS = 0V; VCC = 3.3V ± 0.3V, tT = 1 ns (Continued) Limit Values -75PC # Symbol Parameter -75 -10PC Min. Max. Min. Max. Min. Max. Unit Note 2.7 – 2.7 – 2.7 – ns 2 Read Cycle 21 tOH Data Out Hold Time 22 tLZ Data Out to Low Impedance Time 1 – 1 – 1 – ns 23 tHZ Data Out to High Impedance Time – 5.4 – 5.4 – 5.4 ns 24 tDQZ DQM Data Out Disable Latency – 2 – 2 – 2 CLK Write Recovery Time 1 – 1 – 1 – CLK DQM Write Mask Latency 0 – 0 – 0 – CLK Write Cycle 25 tWR 26 tDQW Notes: 1. The specified values are valid when addresses are changed no more than once during tCK(min.) and when No Operation commands are registered on every rising clock edge during tRC(min). Values are shown per module bank. 2. The specified values are valid when data inputs (DQ’s) are stable during tRC(min.). 3. All AC characteristics are shown for device level. An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 4. AC timing tests have VIL = 0.4V and V IH = 2.4V with the timing referenced to the 1.4V crossover point. The transition time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0V. + 1.4 V tCH 2.4V CLOCK 50 Ohm 0.4V tCL tSETUP Z=50 Ohm tT I/O tHOLD 50 pF 1.4V INPUT tAC tAC tLZ I/O tOH 50 pF 1.4V OUTPUT tHZ V436516Y04V Rev. 1.0 October 2001 8 Measurement conditions for tac and toh 7 MOSEL VITELIC V436516Y04V 5. If clock rising time is longer than 1 ns, a time (tT/2 -0.5) ns has to be added to this parameter. 6. Rated at 1.5V 7. If tT is longer than 1 ns, a time (tT -1) ns has to be added to this parameter. 8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “wake-up” the device. 9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. 10. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels. 11. tDAL is equivalent to tDPL + tRP. Package Diagram 144 Pin SODIMM 0.039 1.25 0.787 59 1 Pin 2 on Backside 61 143 3.3V Pin 144 on Backside 2.661 NOTE: 1. All dimensions in inches. Tolerances ±0.005 unless otherwise specified. V436516Y04V Rev. 1.0 October 2001 9 0.140 MOSEL VITELIC V436516Y04V Label Information Module Density MOSEL VITELIC Part Number Criteria of PC100 or PC133 (refer to MVI datasheet) DIMM manufacture date code V436516Y04VXXX-XX CLX 128MBCLX CLX 512MB V436664S24VATG-10PC V436616R24XXX-XX 128MB PC133U-XXX-542-A XXXX-XXXXXX 0130-K682165 Assembly in Taiwan CAS Latency 2 = CL2 3 = CL3 PC133 U - XXX - 54 2 - A UNBUFFERED DIMM 816Based based Gerber file Intel® PC100 x 16 CL = 3 or 2 (CLK) tRCD = 3 or 2 (CLK) tRP = 3 or 2 (CLK) V436516Y04V Rev. 1.0 October 2001 JEDEC SPD Revision 2 tAC = 5.4 ns 10 MOSEL VITELIC WORLDWIDE OFFICES V436516Y04V U.S.A. TAIWAN SINGAPORE UK & IRELAND 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 10 ANSON ROAD #23-13 INTERNATIONAL PLAZA SINGAPORE 079903 PHONE: 65-3231801 FAX: 65-3237013 NO 19 LI HSIN ROAD SCIENCE BASED IND. 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