MOSEL V826664G24S

MOSEL VITELIC
V826664G24S
512 MB 200-PIN DDR UNBUFFERED SODIMM
2.5 VOLT 64M x 64
PRELIMINARY
Features
Description
■ JEDEC 200 Pin DDR Unbuffered Small-Outline,
Dual In-Line memory module (SODIMM);
67,108,864 x 64 bit organization.
■ Utilizes High Performance 32M x 8 DDR
SDRAM in SOC Packages
■ Single +2.5V (± 0.2V) Power Supply
■ Programmable CAS Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)
■ Auto Refresh (CBR) and Self Refresh
■ All Inputs, Outputs are SSTL-2 Compatible
■ 8192 Refresh Cycles every 64 ms
■ Serial Presence Detect (SPD)
■ DDR SDRAM Performance
The V826664G24S memory module is organized
67,108,864 x 64 bits in a 200 pin memory module.
The 64M x 64 memory module uses 16 MoselVitelic 32M x 8 DDR SDRAM. The x64 modules are
ideal for use in high performance computer systems
where increased memory density and fast access
times are required.
Component Used
tCK
tAC
Clock Frequency
(max.)
-6
-7
-75
-8
Units
166
143
133
125
MHz
(PC333) (PC266A) (PC266B) (PC200)
Clock Access Time
CAS Latency = 2.5
6
7
7.5
8
ns
Module Speed
A1
PC1600 (100MHz @ CL2)
B0
PC2100B (133MHz @ CL2.5)
B1
PC2100A (133MHz @ CL2)
C0
PC2700 (166MHz @ CL2.5)
V826664G24S Rev. 1.0 August 2002
1
V826664G24S
MOSEL VITELIC
Part Number Information
V
8
2
66
64 G
2
4
S
DDR SDRAM
2.5V
S
G - XX
COMPONENT
PACKAGE, S = SOC
WIDTH
DEPTH
COMPONENT
REV LEVEL
200 PIN Unbuffered
SODIMM X8 COMPONENT
STTL
REFRESH
RATE 8K
V826664G24S Rev. 1.0 August 2002
X
SPEED
A1 (100MHz@CL2)
B0 ([email protected])
B1 (133MHz@CL2)
LEAD FINISH C0 ([email protected])
G = GOLD
MOSEL VITELIC
MANUFACTURED
2
4 BANKS
V826664G24S
MOSEL VITELIC
Block Diagram
CS1#
CS0#
DQS0
DQS7
DM0
DM7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM CS# DQS
DQ
U10
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM CS# DQS
DQ
U11
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS2
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM CS# DQS
DQ
U50
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM CS# DQS
DQ
U51
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM CS# DQS
DQ
U60
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM CS# DQS
DQ
U61
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM CS# DQS
DQ
U70
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM CS# DQS
DQ
U71
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM CS# DQS
DQ
U80
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM CS# DQS
DQ
U81
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS5
DM2
DM5
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM CS# DQS
DQ
U20
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM CS# DQS
DQ
U21
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS4
DQS3
DM4
DM3
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM CS# DQS
DQ
U30
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM CS# DQS
DQ
U31
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS6
DQS1
DM6
DM1
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM CS# DQS
DQ
U40
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM CS# DQS
DQ
U41
DQ
DQ
DQ
DQ
DQ
DQ
DQ
120
CK0
CK0#
BA0, BA1: DDR SDRAMs U1-U8
BA0, BA1
A0-A12: DDR SDRAMs U1-U8
A0-A12
RAS#
CAS#
RAS#: DDR SDRAMs U1-U8
CKE0
CKE0: DDR SDRAMs U10-U80
CKE1
CKE1: DDR SDRAMs U11-U81
WE#
WE#: DDR SDRAMs U1-U8
120
CAS#: DDR SDRAMs U1-U8
SERIAL PD
SCL
WP
U20
A0 A1 A2
SDA
SA0 SA1 SA2
V826664G24S Rev. 1.0 August 2002
DDR SDRAM X 8
3
CK1
CK1#
DDR SDRAM X 8
CK2
CK2#
120
VDDQ
DDR SDRAMs
VDD
DDR SDRAMs
VREF
DDR SDRAMs
VSS
DDR SDRAMs
V826664G24S
MOSEL VITELIC
Pin Configurations (Front Side/Back Side)
Pin
Front
Pin
Front
Pin
Front
Pin
Back
Pin
Back
Pin
Back
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
VREF
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
CK0
VSS
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
DQ27
VDD
CB0
CB1
VSS
DQS8
CB2
VDD
CB3
DU
VSS
CK2
CK2
VDD
CKE1
DU(A13)
A12
A9
VSS
A7
A5
A3
A1
VDD
A10/AP
BA0
WE
S0
DU
VSS
DQ32
DQ33
VDD
DQS4
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
DQ42
DQ43
VDD
VDD
VSS
VSS
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
DQ56
VDD
DQ57
DQS7
DQ58
DQ58
DQ59
VDD
SDA
SCL
VDDSPD
VDDID
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
DU/(RESET)
VSS
VSS
VDD
VDD
CKE0
DU(BA2)
A11
A8
VSS
A6
A4
A2
A0
VDD
BA1
RAS
CAS
S1
DU
VSS
DQ36
DQ37
VDD
DM4
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
CK1
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
DU
Key
41
43
45
47
49
51
53
55
57
59
61
63
65
DQ16
DQ17
VDD
DQS2
DQ18
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
Key
42
44
46
48
50
52
54
56
58
60
62
64
66
DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
Notes:
*
These pins are not used in this module.
Pin Names
Pin
Pin Description
Pin
Pin Description
A0~A12
Address Input (Multiplexed)
VDD
Power Supply (2.5V)
BA0~BA1
Bank Select Address
VDDQ
Power Supply for DQS(2.5V)
DQ0~DQ63
Data Input/Output
VSS
Ground
DQS0~DQS7
Data Strobe Input/Output
VREF
Power Supply for Reference
CK0~CK2, CK0~CK2,
Clock Input
VDDSPD
CKE0, CKE1
Clock Enable Input
Serial EEPOM Power Supply (2.3V
to 3.6V)
CS0 , CS1
Chip Select Input
SDA
Serial Data I/O
RAS
Row Address Strobe
SCL
Serial Clock
CAS
Column Address Strobe
SA0~2
Address in EEPROM
WE
Write Enable
VDDID
VDD Identification Flag
DM0~DM7
Data - In Mask
NC
No Connection
V826664G24S Rev. 1.0 August 2002
4
V826664G24S
MOSEL VITELIC
Serial Presence Detect Information
Bin Sort:
A1 (PC1600 @ CL2)
B0 (PC2100B @ CL2.5)
B1 (PC2100A @ CL2)
C0 (PC2700 @ CL2.5)
Function Supported
Byte #
Function described
A1
B0
B1
Hex value
C0
A1
B0
0
Defines # of Bytes written into serial memory at module manufacturer
128bytes
80h
1
Total # of Bytes of SPD memory device
256bytes
08h
2
Fundamental memory type
SDRAM DDR
07h
3
# of row address on this assembly
13
0Dh
4
# of column address on this assembly
10
0Ah
5
# of module Rows on this assembly
2 Bank
02h
6
Data width of this assembly
64 bits
40h
7
.........Data width of this assembly
-
00h
8
VDDQ and interface standard of this assembly
SSTL 2.5V
04h
9
DDR SDRAM cycle time at CAS Latency =2.5
10
DDR SDRAM Access time from clock at CL=2.5
11
DIMM configuration type(Non-parity, Parity, ECC)
12
Refresh rate & type
13
Primary DDR SDRAM width
14
Error checking DDR SDRAM data width
15
Minimum clock delay for back-to-back random column
address
16
DDR SDRAM device attributes : Burst lengths supported
17
DDR SDRAM device attributes : # of banks on each DDR SDRAM
18
8ns
7.5ns
7ns
6ns
±0.8ns ±0.75ns ±0.75ns ±0.70ns
75h
70h
60h
80h
75h
75h
70h
00h
7.8us & Self refresh
82h
x8
08h
N/A
00h
tCCD =1CLK
01h
2,4,8
0Eh
4 banks
04h
DDR SDRAM device attributes : CAS Latency supported
2,2.5
0Ch
19
DDR SDRAM device attributes : CS Latency
0CLK
01h
20
DDR SDRAM device attributes : WE Latency
1CLK
02h
21
DDR SDRAM module attributes
Differential clock /
non Registered
20h
22
DDR SDRAM device attributes : General
+/-0.2V voltage tolerance
00h
23
DDR SDRAM cycle time at CL =2
24
DDR SDRAM Access time from clock at CL =2
25
DDR SDRAM cycle time at CL =1.5
-
-
-
-
00h
26
DDR SDRAM Access time from clock at CL =1.5
-
-
-
-
00h
27
Minimum row precharge time (=tRP)
20ns
20ns
20ns
18ns
50h
28
Minimum row activate to row active delay(=tRRD )
15ns
15ns
15ns
12ns
3Ch
V826664G24S Rev. 1.0 August 2002
10ns
7.5ns
7.5ns
±0.8ns ±0.75ns ±0.75ns ±0.70ns
5
C0
80h
Non-parity, ECC
10ns
B1
A0h
A0h
75h
75h
80h
75h
75h
70h
50h
50h
48h
3Ch
3Ch
30h
V826664G24S
MOSEL VITELIC
Serial Presence Detect Information (cont.)
Function Supported
Byte #
Function described
Hex value
A1
B0
B1
C0
A1
B0
B1
C0
29
Minimum RAS to CAS delay(=tRCD )
20ns
20ns
20ns
18ns
50h
50h
50h
48h
30
Minimum active to precharge time(=tRAS)
50ns
45ns
45ns
42ns
32h
2Dh
2Dh
2Ah
31
Module ROW density
32
Command and address signal input setup time
1.1ns
0.9ns
0.9ns
0.75ns
B0h
90h
90h
75h
33
Command and address signal input hold time
1.1ns
0.9ns
0.9ns
0.75ns
B0h
90h
90h
75h
34
Data signal input setup time
0.6ns
0.5ns
0.5ns
0.45ns
60h
50h
50h
45h
35
Data signal input hold time
0.6ns
0.5ns
0.5ns
0.45ns
60h
50h
50h
45h
36-40
256MB
40h
Superset information (may be used in future)
00h
41
SDRAM device minimum active to active/auto-refresh time
(=tRC)
70ns
65ns
65ns
60ns
46h
41h
41h
3Ch
42
SDRAM device minimum active to autorefresh to active/auto-refresh
time (=tRFC )
80ns
75ns
75ns
72ns
50h
4Bh
4Bh
48h
43
SDRAM device maximum device cycle time (=tCK MAX)
12ns
12ns
12ns
12ns
30h
30h
30h
30h
44
SDRAM device maximum skew between DQS and DQ signals
(=tDQSQ)
0.6ns
0.5ns
0.5ns
0.45ns
3Ch
32h
32h
2Dh
45
SDRAM device maximum read datahold skew factor (=tQHS)
0.75ns 0.75ns 0.60ns
A0h
75h
75h
60h
F3h
4Ch
46-61
Superset information (may be used in future)
62
SPD data revision code
63
Checksum for Bytes 0 ~ 62
64
Manufacturer JEDEC ID code
65 -71
72
73-90
1ns
-
00h
Initial release
00h
Mosel Vitelic
....... Manufacturer JEDEC ID code
E8h
23h
40h
00h
Manufacturing location
02=Taiwan 05=China 0A=S-CH
Module part number (ASCII)
V826664G24S
91
Manufacturer revison code (For PCB)
0
00
92
Manufacturer revison code (For component)
0
00
93
Manufacturing date (Week)
-
-
94
Manufacturing date (Year)
-
-
Assembly serial #
-
-
99~127 Manufacturer specific data (may be used in future)
Undefined
00h
128~25 Open for customer use
5
Undefined
00h
95~98
V826664G24S Rev. 1.0 August 2002
6
V826664G24S
MOSEL VITELIC
DC Operating Conditions
(TA = 0 to 70°C, Voltage referenced to VSS = 0V)
Parameter
Symbol
Min
Typ.
Max
Unit
Power Supply Voltage
VDD
2.3
2.5
2.7
V
Power Supply Voltage
VDDQ
2.3
2.5
2.7
V
Input High Voltage
VIH
VREF + 0.15
-
VDDQ + 0.3
V
Input Low Voltage
VIL
-0.3
-
VREF - 0.15
V
I/O Termination Voltage
VTT
VREF - 0.04
VREF
VREF + 0.04
V
VREF
1.15
1.25
1.35
V
II
-2
-
2
µA
Output Leakage Current
IOz
-5
-
5
µA
Output High Current (VOUT = 1.95V)
IOH
-16.8
-
-
mA
Output Low Current (VOUT = 0.35V)
IOL
16.8
-
-
mA
Reference Voltage
Input Leakage Current
Note
1
2
3
Notes: 1. VDDQ must not exceed the level of VDD .
2. VIL (min) is acceptable -1.5V AC pulse width with <=5ns of duration.
3. The value of VREF is approximately equal to 0.5VDDQ.
AC Operating Conditions
(TA = 0 to 70 °C, Voltage referenced to VSS = 0V)
Parameter
Symbol
Min
Input High (Logic 1) Voltage, DQ, DQS and DM signals
VIH(AC)
VREF + 0.31
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
VIL(AC)
Input Differential Voltage, CK and CK inputs
VID(AC)
Input Crossing Point Voltage, CK and CK inputs
VIX(AC)
Max
Unit
Note
V
VREF - 0.31
V
0.7
VDDQ + 0.6
V
1
0.5*VDDQ-0.2
0.5*VDDQ+0.2
V
2
Notes: 1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the
same.
V826664G24S Rev. 1.0 August 2002
7
V826664G24S
MOSEL VITELIC
AC Operating Test Conditions (TA = 0 to 70°C, Voltage referenced to VSS = 0V)
Parameter
Value
Unit
Reference Voltage
VDDQ x 0.5
V
Termination Voltage
VDDQ x 0.5
V
AC Input High Level Voltage (VIH, min)
VREF + 0.31
V
AC Input Low Level Voltage (VIL, max)
VREF - 0.31
V
VREF
V
Output Timing Measurement Reference Level Voltage
VTT
V
Input Signal maximum peak swing
1.5
V
Input minimum Signal Slew Rate
1
V/ns
Termination Resistor (RT)
50
Ohm
Series Resistor (R S)
25
Ohm
Output Load Capacitance for Access Time Measurement (C L)
30
pF
Input Timing Measurement Reference Level Voltage
Vtt=0.5*VDDQ
RT=50Ω
Output
Z0=50Ω
CLOAD=30pF
VREF
=0.5*V DDQ
Output Load Circuit (SSTL_2)
Input/Output Capacitance
(VDD = 2.5V, VDDQ = 2.5V, TA = 25°C, f = 1MHz)
Parameter
Symbol
Min
Max
Unit
Input capacitance (A0 ~ A11, BA0 ~ BA1, RAS, CAS, WE)
CIN1
36
45
pF
Input capacitance (CKE0)
CIN2
36
45
pF
Input capacitance (CS0)
CIN3
34
42
pF
Input capacitance (CLK1, CLK2)
CIN4
34
38
pF
Data & DQS input/output capacitance (DQ 0~DQ63)
COUT
8
9
pF
Input capacitance (DM0~DM8)
CIN5
8
9
pF
V826664G24S Rev. 1.0 August 2002
8
V826664G24S
MOSEL VITELIC
DDR SDRAM IDD SPEC TABLE
C0
DDR333@CL=2.5
B1
DDR266@CL=2
B0
DDR266@CL=2.5
A1
DDR200@CL=2
Typical
Typical
Typical
Typical
IDD0
880
800
800
640
mA
IDD1
1120
1000
1000
800
mA
IDD2P
450
380
380
260
mA
IDD2F
365
360
360
320
mA
IDD2Q
340
280
280
240
mA
IDD3P
450
380
380
260
mA
IDD3N
460
400
400
320
mA
IDD4R
1360
1360
1360
1120
mA
IDD4W
1680
1480
1480
1200
mA
IDD5
1600
1480
1480
1200
mA
Normal
54
54
54
54
mA
Low power
30
30
30
30
mA
2800
2600
2600
2120
mA
Symbol
IDD6
IDD7A
Unit
Notes
Optional
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Detailed test conditions for DDR SDRAM IDD1 & IDD
IDD1 : Operating current: One bank operation
1. Typical Case : Vdd = 2.5V, T=25’ C
2. Worst Case : Vdd = 2.7V, T= 10’ C
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
per clock cycle. lout = 0mA
4. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
V826664G24S Rev. 1.0 August 2002
9
V826664G24S
MOSEL VITELIC
AC Characteristics (AC operating conditions unless otherwise noted)
(PC333)
Parameter
(PC266A)
(PC266B)
(PC200)
Symbol
Min
Max
Min
Max
Min
Max
Min
Row Cycle Time
tRC
60
-
65
-
65
-
70
-
ns
Auto Refresh Row Cycle Time
tRFC
72
-
75
-
75
-
80
-
ns
Row Active Time
tRAS
42
120K
45
120K
45
120K
50
120K
ns
Row Address to Column Address Delay
tRCD
18
-
20
-
20
-
20
-
ns
Row Active to Row Active Delay
tRRD
12
-
15
-
15
-
15
-
ns
Column Address to Column Address Delay
tCCD
1
-
1
-
1
-
1
-
CLK
Row Precharge Time
tRP
18
-
20
-
20
-
20
-
ns
Write Recovery Time
tWR
12
-
15
-
15
-
15
-
ns
Last Data-In to Read Command
tDRL
1
-
1
-
1
-
1
-
CLK
Auto Precharge Write Recovery + Precharge
Time
tDAL
35
-
35
-
35
-
35
-
ns
CAS Latency = 2.5
tCK
6
12
7
12
7.5
12
8
12
ns
7.5
12
7.5
12
10
12
10
12
ns
System Clock Cycle
Time
CAS Latency = 2
Max Unit Note
Clock High Level Width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
CLK
Clock Low Level Width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
CLK
Data-Out edge to Clock edge Skew
tAC
-0.75
0.75
-0.75
0.75
-0.75
0.75
-0.8
0.8
ns
DQS-Out edge to Clock edge Skew
tDQSCK
-0.75
0.75
-0.75
0.75
-0.75
0.75
-0.8
0.8
ns
DQS-Out edge to Data-Out edge Skew
tDQSQ
-
0.45
-
0.5
-
0.5
-
0.6
ns
Data-Out hold time from DQS
tQH
tHPmin
-0.75ns
-
tHPmin
-0.75ns
-
tHPmin
-0.75ns
-
tHPmin
-0.75ns
-
ns
1
Clock Half Period
tHP
tCH/L
min
-
tCH/L
min
-
tCH/L
min
-
tCH/L
min
-
ns
1
Input Setup Time (fast slew rate)
tIS
0.75
-
0.9
-
0.9
-
1.1
-
ns
2,3,5,6
Input Hold Time (fast slew rate)
tIH
0.75
-
0.9
-
0.9
-
1.1
-
ns
2,3,5,6
Input Setup Time (slow slew rate)
tIS
0.8
-
1.0
-
1.0
-
1.1
-
ns
2,4,5,6
Input Hold Time (slow slew rate)
tIH
0.8
-
1.0
-
1.0
-
1.1
-
ns
2,4,5,6
Write DQS High Level Width
tDQSH
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
CLK
Write DQS Low Level Width
tDQSL
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
CLK
CLK to First Rising edge of DQS-In
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
0.75
1.25
CLK
Data-In Setup Time to DQS-In (DQ & DM)
tDS
0.45
-
0.5
-
0.5
-
0.6
-
ns
7
Data-in Hold Time to DQS-In (DQ & DM)
tDH
0.45
-
0.5
-
0.5
-
0.6
-
ns
7
DQ & DM Input Pulse Width
tDIPW
1.75
-
1.75
-
1.75
-
2
-
ns
Read DQS Preamble Time
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
CLK
Read DQS Postamble Time
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
CLK
tWPRES
0
-
0
-
0
-
0
-
CLK
Write DQS Preamble Setup Time
V826664G24S Rev. 1.0 August 2002
10
V826664G24S
MOSEL VITELIC
AC Characteristics (cont.)
(PC333)
Parameter
(PC266A)
(PC266B)
(PC200)
Symbol
Min
Max
Min
Max
Min
Max
Min
tWPREH
0.25
-
0.25
-
0.25
-
0.25
-
CLK
Write DQS Postamble Time
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
CLK
Mode Register Set Delay
tMRD
2
-
2
-
2
-
2
-
CLK
Power Down Exit Time
tPDEX
10
-
10
-
10
-
10
-
ns
Exit Self Refresh to Non-Read Command
tXSNR
75
-
75
-
75
-
80
-
ns
Exit Self Refresh to Read Command
tXSRD
200
-
200
-
200
-
200
-
CLK
Average Periodic Refresh Interval
tREFI
-
7.8
-
7.8
-
7.8
-
7.8
us
Write DQS Preamble Hold Time
Max Unit Note
Notes: 1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2. Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, CS, RAS, CAS, WE.
3. For command/address input slew rate >=1.0V/ns
4. For command/address input slew rate >=0.5V/ns and <1.0V/ns
5. CK, CK slew rates are >=1.0V/ns
6. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed
by design or tester correlation.
7. Data latched at both rising and falling edges of Data Strobes(DQS) : DQ, DM
8. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Ambient Temperature
TA
0 ~ 70
°C
Storage Temperature
TSTG
-55 ~ 125
°C
VIN , V OUT
-0.5 ~ 3.6
V
VDD
-0.5 ~ 3.6
V
VDDQ
-0.5 ~ 3.6
V
Output Short Circuit Current
IOS
50
mA
Power Dissipation
PD
16
W
TSOLDER
260 • 10
°C • Sec
Voltage on Any Pin relative to VSS
Voltage on VDD relative to VSS
Voltage on VDDQ relative to V SS
Soldering Temperature • Time
Note: Operation at above absolute maximum rating can adversely affect device reliability
V826664G24S Rev. 1.0 August 2002
11
8
V826664G24S
MOSEL VITELIC
Package Dimensions
Units : Inches (Millimeters)
2.70
(67.60)
2.50
(63.60)
39 41
0.456
11.40
0.086
2.15
199
1.896
(47.40)
0.17
(4.20)
0.096
(2.40)
0.07
(1.8)
0.79
(20.00)
0.24
(6.0)
1
Z
1.25
(31.75)
Full R 2x
0.16 ± 0.039
(4.00 ± 0.10)
2- 0.07
(1.80)
Y
0.098
2.45
200
0.157 Min
(4.00 Min)
0.157 Min
(4.00 Min)
0.150 Max
(3.80 Max)
0.04 ± 0.0039
(1.00 ± 0.10)
0.16 ± 0.0039
(4.00 ± 0.10)
0.04 ± 0.0039
(1.00 ± 0.1)
Detail Z
0.018 ± 0.001
(0.45 ± 0.03)
0.01
(0.25)
0.024 TYP
(0.60 TYP)
Detail Y
Tolerances : ±.006(.15) unless otherwise specified
V826664G24S Rev. 1.0 August 2002
0.102 Min
40 42
(2.55 Min)
2
12
V826664G24S
MOSEL VITELIC
Label Information
Module Density
MOSEL VITELIC
Part Number
Criteria of PC2700
DIMM manufacture date code
V826664G24SXXX-XX 512MB CLXX
PC2700U-2533-X-XX
XXXX-XXXXXXX
Assembly in Taiwan
PC2700 U - 2533 - X - X
CAS Latency
X
Revision number of the reference design used
"1" : 1st Revision
"2" : 2nd Revision
blank : not applicable
UNBUFFERED DIMM
CL = 2.5 (CLK)
tRCD = 3 (CLK)
tRP = 3 (CLK)
Gerber file used for this design
"A" : Reference design for raw card A is used for this assembly
SPD Revision
"B" : Reference design for raw card B is used for this assembly
"C" : Reference design for raw card C is used for this assembly
"Z" : None of the reference design were used for this assembly
Module Density
MOSEL VITELIC
Part Number
Criteria of PC2100 or PC1600
DIMM manufacture date code
V826664G24SXXX-XX 512MB CLXX
PC2100U-2533-XXX-X
XXXX-XXXXXXX
Assembly in Taiwan
PC2100 U - 2533 - XX X - X
UNBUFFERED SODIMM
Gerber file
CL = 2.5 (CLK)
tRCD = 3 (CLK)
tRP = 3 (CLK)
V826664G24S Rev. 1.0 August 2002
SPD Revision
CYCLE TIME
13
CAS Latency
V826664G24S
MOSEL VITELIC
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© Copyright , MOSEL VITELIC Corp.
Printed in U.S.A.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
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V826664G24S Rev. 1.0 August 2002
14