V43644Y04V(C)TG-75 3.3 VOLT 4M x 64 HIGH PERFORMANCE PC133 UNBUFFERED SODIMM MOSEL VITELIC PRELIMINARY Features Description ■ JEDEC-standard 144 pin, Small-Outline, Dual in line Memory Module (SODIMM) ■ Serial Presence Detect with E2PROM ■ Fully Synchronous, All Signals Registered on Positive Edge of System Clock ■ Single +3.3V (± 0.3V) Power Supply ■ All Device Pins are LVTTL Compatible ■ 4096 Refresh Cycles every 64 ms ■ Self-Refresh Mode ■ Internal Pipelined Operation; Column Address can be changed every System Clock ■ Programmable Burst Lengths: 1, 2, 4, 8 or Full Page ■ Auto Precharge and Precharge all Banks by A10 ■ Data Mask Function by DQM ■ Mode Register Set Programming ■ Programmable (CAS Latency: 3 Clocks) The V43644Y04V(C)TG-75 memory module is organized 4,194,304 x 64 bits in a 144 pin SODIMM. The 4M x 64 memory module uses 4 Mosel-Vitelic 4M x 16 SDRAM. The x64 modules are ideal for use in high performance computer systems where increased memory density and fast access times are required. 4M x 16 Configuration V43644Y04V(C)TG-75 -75PC (133 MHz) 4M x 64 61 143 Pin 2 on Backside V43644Y04V(C)TG-75 Rev. 1.3 October 2000 Speed Grade 4M x 16 59 1 Part Number Pin 144 on Backside 1 V43644Y04V(C)TG-75 MOSEL VITELIC Pin Configurations (Front Side/Back Side) Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 VSS VSS DQ0 DQ32 DQ1 DQ33 DQ2 DQ34 DQ3 DQ35 VDD VDD DQ4 DQ36 DQ5 DQ37 DQ6 DQ38 DQ7 DQ39 VSS VSS DQMB0 DQMB4 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 DQMB1 DQMB5 VDD VDD A0 A3 A1 A4 A2 A5 VSS VSS DQ8 DQ40 DQ9 DQ41 DQ10 DQ42 DQ11 DQ43 VDD VDD DQ12 DQ44 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 DQ13 DQ45 DQ14 DQ46 DQ15 DQ47 VSS VSS NC NC NC NC CLK0 CKE0 VDD VDD RAS CAS WE NC CS0 NC NC NC 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 NC CLK1 VSS VSS NC NC NC NC VDD VDD DQ16 DQ48 DQ17 DQ49 DQ18 DQ50 DQ19 DQ51 VSS VSS DQ20 DQ52 DQ21 DQ53 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 DQ22 DQ54 DQ23 DQ55 VDD VDD A6 A7 A8 BA0 VSS VSS A9 BA1 A10 A11 VDD VDD DQMB2 DQMB6 DQMB3 DQMB7 VSS VSS 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 DQ24 DQ56 DQ25 DQ57 DQ26 DQ58 DQ27 DQ59 VDD VDD DQ28 DQ60 DQ29 DQ61 DQ30 DQ62 DQ31 DQ63 VSS VSS SDA SCL VDD VDD Note: 1. RAS, CAS, WE CASx, CSx are active low signals. Pin Names A0–A11, BA0, BA1 Address, Bank Select DQ0–DQ63 Data Inputs/Outputs RAS Row Address Strobes CAS Column Address Strobes WE Write Enable CS0 Chip Select DQMB0–DQMB7 Output Enable CKE0 Clock Enable CLK0–CLK1 Clock SDA Serial Input/Output SCL Serial Clock VDD Power Supply VSS Ground NC No Connect (Open) V43644Y04V(C)TG-75 Rev. 1.3 October 2000 2 V43644Y04V(C)TG-75 MOSEL VITELIC Part Number Information V 4 3 64 4 Y 0 4 V C G T – 75 PC133 (133 MHZ) MOSEL-VITELIC MANUFACTURED GOLD SDRAM TSOP 3.3V WIDTH LVTTL DEPTH COMPONENT REVISION LEVEL BLANK = REV B C = REV C 4 BANKS 144 PIN UNBUFFERED SODIMM x16 COMPONENT REFRESH RATE 4K V43644Y04V(C)TG-75-02 Block Diagram CS0 WE RAS CAS DQMB0 UDQMB DQ32–39 U0 DQMB1 LDQMB DQMB2 UDQMB U2 DQ8–15 DQ40–47 DQ16–23 VDD VSS LDQMB DQ24–31 U0–U3 U0–U3 UDQMB DQMB6 DQMB7 LDQMB DQ55–63 10Ω U0–U3 CLK0 CKE0 DQMB5 U3 U0–U3 A0–A11, BA0, BA1 LDQMB DQ48–54 U1 DQMB3 DQMB4 UDQMB DQ0–7 10Ω U0–U3 CLK1 10Ω 10 pF SPD SCL A0 A1 A2 SDA V43644Y04V(C)TG-75-03 V43644Y04V(C)TG-75 Rev. 1.3 October 2000 3 V43644Y04V(C)TG-75 MOSEL VITELIC Serial Presence Detect Information written into the E2PROM device during module production using a serial presence detect protocol (I2C synchronous 2-wire bus) A serial presence detect storage device E PROM - is assembled onto the module. Information about the module configuration, speed, etc. is 2 SPD-Table for 75 modules: Hex Value Byte Number Function Described SPD Entry Value 4Mx64 0 Number of SPD bytes 128 80 1 Total bytes in Serial PD 256 08 2 Memory Type SDRAM 04 3 Number of Row Addresses (without BS bits) 12 0C 4 Number of Column Addresses (for x16 SDRAM) 8 08 5 Number of DIMM Banks 1 01 6 Module Data Width 64 40 7 Module Data Width (continued) 0 00 8 Module Interface Levels LVTTL 01 9 SDRAM Cycle Time at CL=3 7.5 ns 75 10 SDRAM Access Time from Clock at CL=3 5.4 ns 54 11 Dimm Config (Error Det/Corr.) none 00 12 Refresh Rate/Type Self-Refresh, 15.6µs 80 13 SDRAM width, Primary x16 10 14 Error Checking SDRAM Data Width n/a / x8 00 15 Minimum Clock Delay from Back to Back Random Column Address tccd = 1 CLK 01 16 Burst Length Supported 1, 2, 4, 8 & full Page 8F 17 Number of SDRAM Banks 4 04 18 Supported CAS Latencies CL = 3 04 19 CS Latencies CS Latency = 0 01 20 WE Latencies WL = 0 01 21 SDRAM DIMM Module Attributes Non Buffered/Non Reg. 00 22 SDRAM Device Attributes: General Vcc tol ± 10% 0E 23 Minimum Clock Cycle Time at CAS Latency = 2 Not Supported 00 24 Maximum Data Access Time from Clock for CL = 2 Not Supported 00 25 Minimum Clock Cycle Time at CL = 1 Not Supported 00 26 Maximum Data Access Time from Clock at CL = 1 Not Supported 00 27 Minimum Row Precharge Time 20 ns 14 28 Minimum Row Active to Row Active Delay tRRD 15 ns 0F 29 Minimum RAS to CAS Delay tRCD 20 ns 14 30 Minimum RAS Pulse Width tRAS 45 ns 2D V43644Y04V(C)TG-75 Rev. 1.3 October 2000 4 V43644Y04V(C)TG-75 MOSEL VITELIC SPD-Table for 75 modules: (Continued) Hex Value Byte Number Function Described SPD Entry Value 4Mx64 32 MByte 08 31 Module Bank Density (Per Bank) 32 SDRAM Input Setup Time 1.5 ns 15 33 SDRAM Input Hold Time 0.8 ns 08 34 SDRAM Data Input Setup Time 1.5 ns 15 35 SDRAM Data Input Hold Time 0.8 ns 08 62-61 Superset Information (May be used in Future) 62 SPD Revision 63 Checksum for Bytes 0 - 62 64 Manufacturer’s JEDEC ID Code 65-71 72 00 Revision 2 02 8B Mosel Vitelic 40 Manufacturer’s JEDEC ID Code (cont.) 00 Manufacturing Location 1 = US, 2 = Taiwan 73-90 Module Part Number (ASCII) V43644Y04V(C)TG-75 91-92 PCB Identification Code Current PCB Revision 93 Assembly Manufacturing Date (Year) Binary Coded year (BCD) 94 Assembly Manufacturing Date (Week) Binary Coded week (BCD) 95-98 Assembly Serial Number byte 95 = LSB, byte 98 = MSB 99-125 Reserved 00 126 Intel Specification for Frequency 64 127 Reserved 00 128+ Unused Storage Location 00 DC Characteristics TA = 0°C to 70°C; VSS = 0 V; VDD, VDDQ = 3.3V ± 0.3V Limit Values Symbol Parameter Min. Max. Unit VIH Input High Voltage 2.0 VCC+0.3 V VIL Input Low Voltage –0.5 0.8 V VOH Output High Voltage (IOUT = –2.0 mA) 2.4 — V VOL Output Low Voltage (IOUT = 2.0 mA) — 0.4 V II(L) Input Leakage Current, any input (0 V < VIN < 3.6 V, all other inputs = 0V) –10 10 µA IO(L) Output leakage current (DQ is disabled, 0V < VOUT < VCC) –10 10 µA V43644Y04V(C)TG-75 Rev. 1.3 October 2000 5 V43644Y04V(C)TG-75 MOSEL VITELIC Capacitance TA = 0°C to 70°C; VDD = 3.3V ± 0.3V, f = 1 MHz Limit Values Symbol Parameter Max. 4M x 64 Unit CI1 Input Capacitance (A0 to A11, RAS, CAS, WE) 10 pF CI2 Input Capacitance (CS0-CS3) 10 pF CICL Input Capacitance (CLK0-CLK3) 30 pF CI3 Input Capacitance (CKE0, CKE1) 10 pF CI4 Input Capacitance (DQM0-DQM7) 10 pF CIO Input/Output Capacitance (I/O1-I/064) 10 pF CSC Input Capacitance (SCL, SA0-2) 8 pF CSD Input/Output Capacitance (SA0-SA2) 10 pF Operating Currents TA = 0°C to 70°C, VCC = 3.3V ± 0.3V (Recommended operating conditions otherwise noted) Max. Symbol Parameter & Test Condition ICC1 Operating Current tRC = tRCMIN., tRC = tCKMIN. Active-precharge command cycling, without Burst Operation 1 bank operation Precharge Standby Current in Power Down Mode CS =VIH, CKE≤ VIL(max) ICC2P ICC2PS ICC2N Precharge Standby Current in Non-Power Down Mode CS =VIH, CKE≥ VIL(max) ICC2NS ICC3 ICC3P No Operating Current tCK = min, CS = VIH(min) bank ; active state ( 4 banks) -75 Unit Note 600 mA 7 tCK = min. 8 mA 7 tCK = Infinity 4 mA 7 tCK = min. 160 mA tCK = Infinity 20 mA CKE ≥ VIH(MIN.) 200 mA CKE ≥ VIL(MAX.) (Power down mode) 32 mA ICC4 Burst Operating Current tCK = min Read/Write command cycling 600 mA 7,8 ICC5 Auto Refresh Current tCK = min Auto Refresh command cycling 600 mA 7 ICC6 Self Refresh Current Self Refresh Mode, CKE=0.2V 4 mA 2 mA L-version Notes: 1. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and tRC. Input signals are changed one time during tCK. 2. These parameter depend on output loading. Specified values are obtained with output open. V43644Y04V(C)TG-75 Rev. 1.3 October 2000 6 V43644Y04V(C)TG-75 MOSEL VITELIC AC Characteristics TA = 0° to 70°C; VSS = 0V; VCC = 3.3V ± 0.3V, tT = 1 ns Limit Values -75 # Symbol Parameter Min. Max. Unit Clock Cycle Time CAS Latency = 3 CAS Latency = 2 7.5 10 – – s ns ns Clock Frequency CAS Latency = 3 CAS Latency = 2 – – 133 100 MHz MHz Access Time from Clock CAS Latency = 3 CAS Latency = 2 – _ 5.4 6 ns ns Note Clock and Clock Enable 1 2 3 tCK tCK tAC 2, 4 4 tCH Clock High Pulse Width 2.5 – ns 5 tCL Clock Low Pulse Width 2.5 – ns 6 tT Transition Tim 0.3 1.2 ns Setup and Hold Times 7 tIS Input Setup Time 1.5 – ns 5 8 tIH Input Hold Time 0.8 – ns 5 9 tCKS Input Setup Time 1.5 – ns 5 10 tCKH CKE Hold Time 0.8 – ns 5 11 tRSC Mode Register Set-up Time 15 – ns 12 tSB Power Down Mode Entry Time 0 7.5 ns Row to Column Delay Time 20 – ns 6 Common Parameters 13 tRCD 14 tRP Row Precharge Time 20 – ns 6 15 tRAS Row Active Time 45 100K ns 6 16 tRC Row Cycle Time 60 – ns 6 17 tRRD Activate(a) to Activate(b) Command Period 15 – ns 6 18 tCCD CAS(a) to CAS(b) Command Period 1 – CLK 64 ms Refresh Cycle 19 tREF Refresh Period (4096 cycles) — 20 tSREX Self Refresh Exit Time 10 V43644Y04V(C)TG-75 Rev. 1.3 October 2000 7 ns V43644Y04V(C)TG-75 MOSEL VITELIC AC Characteristics TA = 0° to 70°C; VSS = 0V; VCC = 3.3V ± 0.3V, tT = 1 ns (Continued) Limit Values -75 # Symbol Parameter Min. Max. Unit Note 2.7 – ns 2 Read Cycle 21 tOH Data Out Hold Time 22 tLZ Data Out to Low Impedance Time 1 – ns 23 tHZ Data Out to High Impedance Time – 5.4 ns 24 tDQZ DQM Data Out Disable Latency – 2 CLK 25 tWR Write Recovery Time 1 – CLK 26 tDQW DQM Write Mask Latency 0 – CLK 7 Write Cycle Notes: 1. The specified values are valid when addresses are changed no more than once during tCK(min.) and when No Operation commands are registered on every rising clock edge during tRC(min). Values are shown per module bank. 2. The specified values are valid when data inputs (DQ’s) are stable during tRC(min.). 3. All AC characteristics are shown for device level. An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 4. AC timing tests have VIL = 0.4V and VIH = 2.4V with the timing referenced to the 1.4V crossover point. The transition time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0V + 1.4 V tCH 2.4V CLOCK 50 Ohm 0.4V tCL tSETUP Z=50 Ohm tT I/O tHOLD 50 pF 1.4V INPUT tAC tAC tLZ I/O tOH 50 pF 1.4V OUTPUT tHZ V43644Y04V(C)TG-75 Rev. 1.3 October 2000 8 Measurement conditions for tac and toh V43644Y04V(C)TG-75 MOSEL VITELIC 5. If clock rising time is longer than 1 ns, a time (tT/2 -0.5) ns has to be added to this parameter. 6. Rated at 1.5V 7. If tT is longer than 1 ns, a time (tT -1) ns has to be added to this parameter. 8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “wake-up” the device. 9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. 10. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels. 11. tDAL is equivalent to tDPL + tRP. Package Diagram 144 Pin SODIMM 0.039 1.00 0.787 28 1 Pin 2 on Backside 29 143 3.3V Pin 144 on Backside 0.140 2.661 NOTE: 1. All dimensions in inches. Tolerances ±0.005 unless otherwise specified. V43644Y04V(C)TG-75-04 V43644Y04V(C)TG-75 Rev. 1.3 October 2000 9 V43644Y04V(C)TG-75 MOSEL VITELIC Label Information MOSEL VITELIC Part Number Criteria of PC100 or PC133 (refer to MVI datasheet) V43644Y04VCTG-75 PC133U-333-542-A Taiwan XXXX-XXXXXXX DIMM manufacture date code Trace Code PC133 U - 333 - 54 2 - A UNBUFFERED DIMM Gerber file Intel® PC100 x 8 Based CL = 3 (CLK) tRCD = 3 (CLK) tRP = 3 (CLK) V43644Y04V(C)TG-75 Rev. 1.3 October 2000 JEDEC SPD Revision 2.0 tAC = 5.4 ns 10 V43644Y04V(C)TG-75-05 MOSEL VITELIC WORLDWIDE OFFICES V43644Y04V(C)TG-75 U.S.A. TAIWAN SINGAPORE UK & IRELAND 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0952 7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 886-2-2545-1213 FAX: 886-2-2545-1209 10 ANSON ROAD #23-13 INTERNATIONAL PLAZA SINGAPORE 079903 PHONE: 65-3231801 FAX: 65-3237013 NO 19 LI HSIN ROAD SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. 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