DATA SHEET MOS INTEGRATED CIRCUIT µPD23C16040BL, 23C16080BL 16M-BIT MASK-PROGRAMMABLE ROM 2M-WORD BY 8-BIT (BYTE MODE) / 1M-WORD BY 16-BIT (WORD MODE) PAGE ACCESS MODE Description The µPD23C16040BL and µPD23C16080BL are 16,777,216 bits mask-programmable ROM. The word organization is selectable (BYTE mode : 2,097,152 words by 8 bits, WORD mode : 1,048,576 words by 16 bits). The active levels of OE (Output Enable Input) can be selected with mask-option. The µPD23C16040BL and µPD23C16080BL are packed in 48-pin PLASTIC TSOP(I) and 44-pin PLASTIC SOP. Features • Word organization 2,097,152 words by 8 bits (BYTE mode) 1,048,576 words by 16 bits (WORD mode) • Page access mode BYTE mode : 8 byte random page access (µPD23C16040BL) 16 byte random page access (µPD23C16080BL) WORD mode : 4 word random page access (µPD23C16040BL) 8 word random page access (µPD23C16080BL) • Operating supply voltage : VCC = 2.7 V to 3.6 V Operating supply Access time / Power supply current (Active mode) Standby current voltage Page access time mA (MAX.) (CMOS level input) VCC ns (MAX.) µPD23C16040BL µPD23C16080BL µA (MAX.) 3.0 V ± 0.3 V 90 / 25 40 55 30 3.3 V ± 0.3 V 85 / 25 The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. M15720EJ3V0DS00 (3rd edition) Date Published March 2003 NS CP(K) Printed in Japan The mark shows major revised points. 2001 µPD23C16040BL, 23C16080BL Ordering Information Part Number Package µPD23C16040BLGY-xxx-MJH 48-pin PLASTIC TSOP(I) (12 x 18) (Normal bent) µPD23C16040BLGY-xxx-MKH 48-pin PLASTIC TSOP(I) (12 x 18) (Reverse bent) µPD23C16040BLGX-xxx Note 44-pin PLASTIC SOP (15.24 mm (600)) µPD23C16080BLGY-xxx-MJH 48-pin PLASTIC TSOP(I) (12 x 18) (Normal bent) µPD23C16080BLGY-xxx-MKH 48-pin PLASTIC TSOP(I) (12 x 18) (Reverse bent) µPD23C16080BLGX-xxx Note 44-pin PLASTIC SOP (15.24 mm (600)) Note Under development (xxx : ROM code suffix No.) 2 Data Sheet M15720EJ3V0DS µPD23C16040BL, 23C16080BL Pin Configurations /xxx indicates active low signal. 48-pin PLASTIC TSOP(I) (12 x 18) (Normal bent) [ µPD23C16040BLGY-xxx-MJH ] [ µPD23C16080BLGY-xxx-MJH ] Marking Side WORD, /BYTE 1 48 GND A16 2 47 GND A15 3 46 O15, A−1 A14 4 45 O7 A13 5 44 O14 A12 6 43 O6 A11 7 42 O13 A10 8 41 O5 A9 9 40 O12 O4 A8 10 39 A19 11 38 VCC NC 12 37 VCC NC 13 36 NC A18 14 35 O11 A17 15 34 O3 A7 16 33 O10 A6 17 32 O2 A5 18 31 O9 A4 19 30 O1 A3 20 29 O8 A2 21 28 O0 A1 22 27 /OE or OE or DC A0 23 26 GND /CE 24 25 GND A0 to A19 : Address inputs O0 to O7, O8 to O14 : Data outputs O15, A–1 : Data output 15 (WORD mode), LSB Address input (BYTE mode) WORD, /BYTE : Mode select /CE : Chip Enable /OE or OE : Output Enable VCC : Supply voltage GND NC DC Note : Ground : No Connection : Don’t Care Note Some signals can be applied because this pin is not connected to the inside of the chip. Remark Refer to Package Drawings for the 1-pin index mark. Data Sheet M15720EJ3V0DS 3 µPD23C16040BL, 23C16080BL 48-pin PLASTIC TSOP(I) (12 x 18) (Reverse bent) [ µPD23C16040BLGY-xxx-MKH ] [ µPD23C16080BLGY-xxx-MKH ] Marking Side GND 48 1 WORD, /BYTE GND 47 2 A16 O15, A−1 46 3 A15 O7 45 4 A14 O14 44 5 A13 O6 43 6 A12 O13 42 7 A11 O5 41 8 A10 O12 40 9 A9 O4 39 10 A8 VCC 38 11 A19 VCC 37 12 NC NC 36 13 NC O11 35 14 A18 O3 34 15 A17 O10 33 16 A7 O2 32 17 A6 O9 31 18 A5 O1 30 19 A4 O8 29 20 A3 O0 28 21 A2 /OE or OE or DC 27 22 A1 GND 26 23 A0 GND 25 24 /CE A0 to A19 : Address inputs O0 to O7, O8 to O14 : Data outputs O15, A–1 : Data output 15 (WORD mode), LSB Address input (BYTE mode) WORD, /BYTE : Mode select /CE : Chip Enable /OE or OE : Output Enable VCC : Supply voltage GND NC DC Note : Ground : No Connection : Don’t Care Note Some signals can be applied because this pin is not connected to the inside of the chip. Remark Refer to Package Drawings for the 1-pin index mark. 4 Data Sheet M15720EJ3V0DS µPD23C16040BL, 23C16080BL 44-pin PLASTIC SOP (15.24 mm (600)) [ µPD23C16040BLGX-xxx ] [ µPD23C16080BLGX-xxx ] Marking Side NC 1 44 NC A18 2 43 A19 A17 3 42 A8 A7 4 41 A9 A6 5 40 A10 A5 6 39 A11 A4 7 38 A12 A3 8 37 A13 A2 9 36 A14 A1 10 35 A15 A0 11 34 A16 /CE 12 33 WORD, /BYTE GND 13 32 GND /OE or OE or DC 14 31 O15, A−1 O0 15 30 O7 O8 16 29 O14 O1 17 28 O6 O9 18 27 O13 O2 19 26 O5 O10 20 25 O12 O3 21 24 O4 O11 22 23 VCC A0 to A19 : Address inputs O0 to O7, O8 to O14 : Data outputs O15, A–1 : Data output 15 (WORD mode), LSB Address input (BYTE mode) WORD, /BYTE : Mode select /CE : Chip Enable /OE or OE : Output Enable VCC : Supply voltage GND NC DC Note : Ground : No Connection : Don’t Care Note Some signals can be applied because this pin is not connected to the inside of the chip. Remark Refer to Package Drawings for the 1-pin index mark. Data Sheet M15720EJ3V0DS 5 µPD23C16040BL, 23C16080BL Input / Output Pin Functions Pin name WORD, /BYTE Input / Output Input Function The pin for switching WORD mode and BYTE mode. High level : WORD mode (1M-word by 16-bit) Low level : BYTE mode (2M-word by 8-bit) A0 to A19 Input (Address inputs) Address input pins. A0 to A19 are used differently in the WORD mode and the BYTE mode. WORD mode (1M-word by 16-bit) A0 to A19 are used as 20 bits address signals. BYTE mode (2M-word by 8-bit) A0 to A19 are used as the upper 20 bits of total 21 bits of address signal. (The least significant bit (A−1) is combined to O15.) O0 to O7, O8 to O14 Output (Data outputs) Data output pins. O0 to O7, O8 to O14 are used differently in the WORD mode and the BYTE mode. WORD mode (1M-word by 16-bit) The lower 15 bits of 16 bits data outputs to O0 to O14. (The most significant bit (O15) combined to A−1.) BYTE mode (2M-word by 8-bit) 8 bits data outputs to O0 to O7 and also O8 to O14 are high impedance. O15, A−1 Output, Input O15, A−1 are used differently in the WORD mode and the BYTE mode. WORD mode (1M-word by 16-bit) (Data output 15, LSB Address input) The most significant output data bus (O15). BYTE mode (2M-word by 8-bit) The least significant address bus (A−1). /CE Input (Chip Enable) Chip activating signal. When the OE is active, output states are following. High level : High-Z Low level : Data out /OE or OE or DC Input (Output Enable, Don't care) Output enable signal. The active level of OE is mask option. The active level of OE can be selected from high active, low active and Don’t care at order. VCC − Supply voltage GND − Ground NC − Not internally connected. (The signal can be connected.) 6 Data Sheet M15720EJ3V0DS µPD23C16040BL, 23C16080BL Block Diagram O9 O8 O0 A0 O1 O10 O2 O11 O3 O13 O12 O4 O5 O6 O14 O15, A 1 O7 A2 A3 Y-Selector A4 Logic/Input Y-Decoder Output Buffer A1 WORD, /BYTE /OE or OE or DC A5 A9 A10 A11 A12 A13 Memory Cell Matrix 1,048,576 words by 16 bits / 2,097,152 words by 8 bits A14 Input Buffer A8 X-Decoder A7 Address Input Buffer A6 /CE A15 A16 A17 A18 A19 Data Sheet M15720EJ3V0DS 7 µPD23C16040BL, 23C16080BL Mask Option The active levels of output enable pin (/OE or OE or DC) are mask programmable and optional, and can be selected from among " 0 " " 1 " " x " shown in the table below. Option /OE or OE or DC OE active level 0 /OE L 1 OE H x DC Don’t care Operation modes for each option are shown in the tables below. Operation mode (Option : 0) /CE /OE Mode Output state L L Active Data out H H H or L High-Z Standby High-Z Operation mode (Option : 1) /CE OE Mode Output state L L Active High-Z H H H or L Data out Standby High-Z Operation mode (Option : x) /CE DC Mode Output state L H or L Active Data out H H or L Standby High-Z Remark L : Low level input H : High level input 8 Data Sheet M15720EJ3V0DS µPD23C16040BL, 23C16080BL Electrical Specifications Absolute Maximum Ratings Parameter Symbol Rating Unit VCC –0.3 to +4.6 V Input voltage VI –0.3 to VCC+0.3 V Output voltage VO –0.3 to VCC+0.3 V Operating ambient temperature TA –10 to +70 °C Storage temperature Tstg –65 to +150 °C Supply voltage Condition Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Capacitance (TA = 25 °C) Parameter Symbol MAX. Unit 10 pF 12 pF MAX. Unit 2.0 VCC + 0.3 V VCC = 3.0 V ± 0.3 V –0.3 +0.5 V VCC = 3.3 V ± 0.3 V –0.3 +0.8 2.4 Input capacitance CI Output capacitance CO Test condition MIN. TYP. f = 1 MHz DC Characteristics (TA = –10 to +70 °C, VCC = 2.7 to 3.6 V) Parameter Symbol High level input voltage VIH Low level input voltage VIL Test conditions High level output voltage VOH IOH = –100 µA Low level output voltage VOL IOL = 2.1 mA MIN. TYP. V 0.4 V Input leakage current ILI VI = 0 V to VCC –10 +10 µA Output leakage current ILO VO = 0 V to VCC, Chip deselected –10 +10 µA Power supply current ICC1 /CE = VIL (Active µPD23C16040BL VCC = 3.0 V ± 0.3 V 40 mA VCC = 3.3 V ± 0.3 V 40 µPD23C16080BL VCC = 3.0 V ± 0.3 V 55 VCC = 3.3 V ± 0.3 V 55 mode), IO = 0 mA Standby current ICC3 /CE = VCC – 0.2 V (Standby mode) Data Sheet M15720EJ3V0DS 30 µA 9 µPD23C16040BL, 23C16080BL AC Characteristics (TA = –10 to +70 °C, VCC = 2.7 to 3.6 V) Parameter Symbol VCC = 3.0 V ± 0.3 V Test condition MIN. TYP. MAX. VCC = 3.3 V ± 0.3 V MIN. TYP. Unit MAX. Address access time tACC 90 85 ns Page access time tPAC 25 25 ns Address skew time tSKEW 10 10 ns Note Chip enable access time tCE 90 85 ns Output enable access time tOE 25 25 ns Output hold time tOH 0 Output disable time tDF 0 WORD, /BYTE access time tWB 0 25 0 90 ns 25 ns 85 ns Note tSKEW indicates the following three types of time depending on the condition. 1) When switching /CE from high level to low level, tSKEW is the time from the /CE low level input point until the next address is determined. 2) When switching /CE from low level to high level, tSKEW is the time from the address change start point to the /CE high level input point. 3) When /CE is fixed to low level, tSKEW is the time from the address change start point until the next address is determined. Since specs are defined for tSKEW only when /CE is active, tSKEW is not subject to limitations when /CE is switched from high level to low level following address determination, or when the address is changed after /CE is switched from low level to high level. Remark tDF is the time from inactivation of Chip Enable input (/CE) or Output Enable input (/OE or OE) to high impedance state output. AC Test Conditions Input waveform (Rise / Fall time ≤ 5 ns) 1.4 V Test points 1.4 V 1.4 V Test points 1.4 V Output waveform Output load 1TTL + 100 pF 10 Data Sheet M15720EJ3V0DS µPD23C16040BL, 23C16080BL Cautions on power application To ensure normal operation, always apply power using /CE following the procedure shown below. 1) Input a high level to /CE during and after power application. 2) Hold the high level input to /CE for 200 ns or longer (wait time). 3) Start normal operation after the wait time has elapsed. Power Application Timing Chart 1 (When /CE is made high at power application) Wait time Normal operation /CE (Input) 200 ns or longer VCC Power Application Timing Chart 2 (When /CE is made high after power application) Wait time Normal operation /CE (Input) 200 ns or longer VCC Caution Other signals can be either high or low during the wait time. Data Sheet M15720EJ3V0DS 11 µPD23C16040BL, 23C16080BL Read Cycle Timing Chart 1 tSKEW tSKEW tSKEW A0 to A19, (Input) A−1 Note1 tACC tACC tACC /CE (Input) tDF Note2 tCE tDF Note2 /OE or OE (Input) tOE O0 to O7, (Input) O8 to O15 Note3 High-Z tOH Data out tOH High-Z Data out tOH Data out Notes 1. During WORD mode, A–1 is O15. 2. tDF is the time from inactivation of Chip Enable input (/CE) or Output Enable input (/OE or OE) to high impedance state output. 3. During BYTE mode, O8 to O14 are high impedance and O15 is A–1. 12 Data Sheet M15720EJ3V0DS µPD23C16040BL, 23C16080BL Read Cycle Timing Chart 2 (Page Access Mode) Upper address Note 1 (Input) A2 to A19 A3 to A19 tACC /CE (Input) tCE /OE or OE (Input) tOE Page address Note 1 A–1 Note 2, A0, A1 A–1 Note 2, A0, A1, A2 (Input) tPAC Note 5 tPAC Note 5 tDF Note 3 tOH tOH Data Out Data Out tOH High-Z O0 to O7, (Output) O8 to O15 Note 4 High-Z Data Out Notes 1. The address differs depending on the product as follows. Part Number Upper address Page address µPD23C16040BL A2 to A19 A–1, A0, A1 µPD23C16080BL A3 to A19 A–1, A0, A1, A2 2. During WORD mode, A–1 is O15. 3. tDF is the time from inactivation of Chip Enable input (/CE) or Output Enable input (/OE or OE) to high impedance state output. 4. During BYTE mode, O8 to O14 are high impedance and O15 is A–1. 5. The definition of page access time is as follows. [ µPD23C16040BL ] Page access time Upper address (A2 to A19) /CE input condition /OE or OE input condition Before tCE – tPAC Before stabilizing of page inputs condition tPAC Before tACC – tPAC address (A–1, A0, A1) [ µPD23C16080BL ] Page access time Upper address (A3 to A19) /CE input condition /OE or OE input condition Before tCE – tPAC Before stabilizing of page inputs condition tPAC Before tACC – tPAC address (A–1, A0, A1, A2) Data Sheet M15720EJ3V0DS 13 µPD23C16040BL, 23C16080BL WORD, /BYTE Switch Timing Chart A–1 (Input) High-Z High-Z WORD, /BYTE (Input) tOH O0 to O7 (Output) tACC Data Out tOH Data Out tWB Data Out tDF O8 to O15 (Output) Remark 14 High-Z Data Out Chip Enable (/CE) and Output Enable (/OE or OE) : Active. Data Sheet M15720EJ3V0DS Data Out µPD23C16040BL, 23C16080BL Package Drawings 48-PIN PLASTIC TSOP(I) (12x18) 1 detail of lead end 48 F G R Q 24 L 25 S E P I A J C S D K N B M M S NOTES ITEM MILLIMETERS 1. Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. A 12.0±0.1 B 0.45 MAX. 2. "A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.) C 0.5 (T.P.) D 0.22±0.05 E 0.1±0.05 F 1.2 MAX. G 1.0±0.05 I 16.4±0.1 J 0.8±0.2 K 0.145±0.05 L 0.5 M 0.10 N 0.10 P 18.0±0.2 Q 3° +5° −3° R S 0.25 0.60±0.15 S48GY-50-MJH1-1 Data Sheet M15720EJ3V0DS 15 µPD23C16040BL, 23C16080BL 48-PIN PLASTIC TSOP(I) (12x18) detail of lead end 1 48 E S L Q R 24 G 25 F K N S D S I J M M B C A P NOTES 1. Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.) ITEM A MILLIMETERS 12.0±0.1 B 0.45 MAX. C 0.5 (T.P.) D 0.22±0.05 E 0.1±0.05 F 1.2 MAX. G 1.0±0.05 I 16.4±0.1 J 0.8±0.2 K 0.145±0.05 L 0.5 M 0.10 N 0.10 P 18.0±0.2 Q 3° +5° −3° R 0.25 S 0.60±0.15 S48GY-50-MKH1-1 16 Data Sheet M15720EJ3V0DS µPD23C16040BL, 23C16080BL 44-PIN PLASTIC SOP (15.24 mm (600)) 44 23 detail of lead end P 1 22 A H F I G J S N C D M S B L K M E NOTE ITEM Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition. A B MILLIMETERS 27.83+0.4 −0.05 0.78 MAX. C 1.27 (T.P.) D 0.42 +0.08 −0.07 E F G 0.15±0.1 3.0 MAX. 2.7±0.05 H 16.04±0.3 I J 13.24±0.1 1.4±0.2 K 0.22 +0.08 −0.07 L M N P 0.8±0.2 0.12 0.10 3° +7° −3° P44GX-50-600A-4 Data Sheet M15720EJ3V0DS 17 µPD23C16040BL, 23C16080BL Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the µPD23C16040BL and µPD23C16080BL. Types of Surface Mount Device µPD23C16040BLGY-MJH : 48-pin PLASTIC TSOP(I) (12 x 18) (Normal bent) µPD23C16040BLGY-MKH : 48-pin PLASTIC TSOP(I) (12 x 18) (Reverse bent) µPD23C16040BLGX : 44-pin PLASTIC SOP (15.24 mm (600)) µPD23C16080BLGY-MJH : 48-pin PLASTIC TSOP(I) (12 x 18) (Normal bent) µPD23C16080BLGY-MKH : 48-pin PLASTIC TSOP(I) (12 x 18) (Reverse bent) µPD23C16080BLGX : 44-pin PLASTIC SOP (15.24 mm (600)) 18 Data Sheet M15720EJ3V0DS µPD23C16040BL, 23C16080BL Revision History Edition/ Date Page Type of This Previous edition edition Location Preliminary Data Sheet → Data Sheet 3rd edition/ Throughout Throughout Modification Mar. 2003 Description (Previous edition → This edition) revision p.2 p.2 Addition Ordering Information Under development (44-pin PLASTIC SOP) p.10 p.10 Addition AC Characteristics Address skew time (tSKEW ) p.11 – Addition Cautions on power application p.12 p.11 Modification Read Cycle Timing Chart 1 Note Data Sheet M15720EJ3V0DS 19 µPD23C16040BL, 23C16080BL [MEMO] 20 Data Sheet M15720EJ3V0DS µPD23C16040BL, 23C16080BL [MEMO] Data Sheet M15720EJ3V0DS 21 µPD23C16040BL, 23C16080BL [MEMO] 22 Data Sheet M15720EJ3V0DS µPD23C16040BL, 23C16080BL NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF THE APPLIED WAVEFORM OF INPUT PINS AND THE UNUSED INPUT PINS FOR CMOS Note: Input levels of CMOS devices must be fixed. CMOS devices behave differently than Bipolar or NMOS devices. If the input of a CMOS device stays in an area that is between V IL (MAX.) and V IH (MIN.) due to the effects of noise or some other irregularity, malfunction may result. Therefore, not only the input waveform is fixed, but also the waveform changes, it is important to use the CMOS device under AC test conditions. For unused input pins in particular, CMOS devices should not be operated in a state where nothing is connected, so input levels of CMOS devices must be fixed to high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet M15720EJ3V0DS 23 µPD23C16040BL, 23C16080BL These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited. • The information in this document is current as of March, 2003. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. 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