DATA SHEET MOS INTEGRATED CIRCUIT µPD444010L-X 4M-BIT CMOS STATIC RAM 512K-WORD BY 8-BIT EXTENDED TEMPERATURE OPERATION Description The µPD444010L-X is a high speed, low power, 4,194,304 bits (524,288 words by 8 bits) CMOS static RAM. The µPD444010L-X has two chip enable pins (/CE1, CE2) to extend the capacity. The µPD444010L-X is packed in 48-pin plastic TSOP (I). Features • 524,288 words by 8 bits organization • Fast access time: 70, 85, 100, 120, 150, 200 ns (MAX.) • Low voltage operation (B version : VCC = 2.7 to 3.6 V, C version : VCC = 2.2 to 3.6 V, D version : VCC = 1.8 to 3.6 V) ★ • Low VCC data retention (B version: 2.0 V (MIN.), C version: 1.5 V (MIN.), D version: 1.5 V (MIN.)) • Operating ambient temperature: TA = –25 to +85 °C • Output Enable input for easy application • Two Chip Enable inputs: /CE1, CE2 Part number Access time Operating supply Operating ambient ns (MAX.) voltage temperature At operating At standby At data retention V °C mA (MAX.) µA (MAX.) µA (MAX.) −25 to +85 40 7 7 µPD444010L-BxxX 70, 85 2.7 to 3.6 µPD444010L-CxxX 100, 120 2.2 to 3.6 µPD444010L-DxxX Note 150, 200 1.8 to 3.6 Supply current Note Under development The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. M13960EJ3V0DS00 (3rd edition) Date Published November 1999 NS CP (K) Printed in Japan The mark ★ shows major revised points. © 1998 µPD444010L-X Ordering Information Part number Package µPD444010LGY-B70X-MJH 48-pin Plastic TSOP (I) (12×18) (Normal bent) µPD444010LGY-B70X-MKH 48-pin Plastic TSOP (I) (12×18) (Reverse bent) µPD444010LGY-B85X-MJH 48-pin Plastic TSOP (I) (12×18) (Normal bent) µPD444010LGY-B85X-MKH 48-pin Plastic TSOP (I) (12×18) (Reverse bent) µPD444010LGY-C10X-MJH 48-pin Plastic TSOP (I) (12×18) (Normal bent) µPD444010LGY-C10X-MKH 48-pin Plastic TSOP (I) (12×18) (Reverse bent) µPD444010LGY-C12X-MJH 48-pin Plastic TSOP (I) (12×18) (Normal bent) µPD444010LGY-C12X-MKH 48-pin Plastic TSOP (I) (12×18) (Reverse bent) µPD444010LGY-D15X-MJH Note 48-pin Plastic TSOP (I) (12×18) (Normal bent) µPD444010LGY-D15X-MKH Note 48-pin Plastic TSOP (I) (12×18) (Reverse bent) µPD444010LGY-D20X-MJH Note 48-pin Plastic TSOP (I) (12×18) (Normal bent) µPD444010LGY-D20X-MKH Note 48-pin Plastic TSOP (I) (12×18) (Reverse bent) Access time Operating Operating ns (MAX.) supply voltage temperature V °C 2.7 to 3.6 −25 to +85 70 B version 85 100 2.2 to 3.6 C version 1.8 to 3.6 D version 120 150 200 Note Under development 2 Remark Data Sheet M13960EJ3V0DS00 µPD444010L-X Pin Configurations (Marking Side) /xxx indicates active low signal. 48-pin Plastic TSOP (I) (12× ×18) (Normal bent) [ µPD444010LGY-BxxX-MJH ] [ µPD444010LGY-CxxX-MJH ] [ µPD444010LGY-DxxX-MJH ] ★ A16 A15 A14 A13 A12 A11 A9 A8 NC NC /WE CE2 IC NC NC NC A18 A7 A6 A5 A4 A3 A2 A1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 A0 - A18 : Address inputs I/O1 - I/O8 : Data inputs / outputs /CE1, CE2 : Chip Enable 1, 2 /WE : Write Enable /OE : Output Enable VCC : Power supply GND : Ground NC : No Connection IC Note A17 NC GND A10 I/O8 NC I/O7 NC I/O6 NC I/O5 VCC NC I/O4 NC I/O3 NC I/O2 NC I/O1 /OE GND /CE1 A0 : Internal Connection Note Leave this pin unconnected or connect to GND. Remark Refer to Package Drawings for the 1-pin marking. Data Sheet M13960EJ3V0DS00 3 µPD444010L-X 48-pin Plastic TSOP (I) (12× ×18) (Reverse bent) [ µPD444010LGY-BxxX-MKH ] [ µPD444010LGY-CxxX-MKH ] [ µPD444010LGY-DxxX-MKH ] A17 NC GND A10 I/O8 NC I/O7 NC I/O6 NC I/O5 VCC NC I/O4 NC I/O3 NC I/O2 NC I/O1 /OE GND /CE1 A0 ★ 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 A0 - A18 : Address inputs I/O1 - I/O8 : Data inputs / outputs /CE1, CE2 : Chip Enable 1, 2 /WE : Write Enable /OE : Output Enable VCC : Power supply GND : Ground NC : No Connection IC Note : Internal Connection Note Leave this pin unconnected or connect to GND. Remark Refer to Package Drawings for the 1-pin marking. 4 Data Sheet M13960EJ3V0DS00 A16 A15 A14 A13 A12 A11 A9 A8 NC NC /WE CE2 IC NC NC NC A18 A7 A6 A5 A4 A3 A2 A1 µPD444010L-X Block Diagram VCC GND A0 Address buffer A18 Row decoder Memory cell array 4,194,304 bits I/O1 Sense / Switch Input data controller I/O8 Output data controller Column decoder Address buffer /CE1 CE2 /OE /WE Truth Table /CE1 CE2 /OE /WE Mode I/O Supply current H × × × Not selected High impedance ISB × L × × L H H H Output disable L H L H Read DOUT L H × L Write DIN ICCA Remark × : Don’t care Data Sheet M13960EJ3V0DS00 5 µPD444010L-X Electrical Specifications Absolute Maximum Ratings Parameter Symbol Supply voltage Condition Rating VCC –0.5 –0.5 Note Note Unit to +4.0 V to VCC+0.4 (4.0 V MAX.) V Input / Output voltage VT Operating ambient temperature TA –25 to +85 °C Storage temperature Tstg –55 to +125 °C Note –3.0 V (MIN.) (Pulse width : 30 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Symbol Supply voltage VCC High level input voltage VIH Low level input voltage VIL Operating ambient temperature TA Condition µPD444010L-BxxX µPD444010L-CxxX µPD444010L-DxxX Unit MIN. MAX. MIN. MAX. MIN. MAX. 2.7 3.6 2.2 3.6 1.8 3.6 V 2.7 V ≤ VCC ≤ 3.6 V 2.4 VCC+0.4 2.4 VCC+0.4 2.4 VCC+0.4 V 2.2 V ≤ VCC < 2.7 V – – 2.0 VCC+0.3 2.0 VCC+0.3 1.8 V ≤ VCC < 2.2 V – – – – 1.6 VCC+0.2 –0.3 Note –25 +0.5 +85 –0.3 Note –25 +0.3 +85 –0.3 Note –25 +0.2 V +85 °C Note –1.5 V (MIN.) (Pulse width: 30 ns) Capacitance (TA = 25 °C, f = 1 MHz) Parameter Symbol Test condition MIN. TYP. MAX. Unit Input capacitance CIN VIN = 0 V 8 pF Input / Output capacitance CI/O VI/O = 0 V 10 pF Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These parameters are periodically sampled and not 100% tested. 6 Data Sheet M13960EJ3V0DS00 µPD444010L-X DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) Parameter Symbol VCC ≥ 2.7 V VCC ≥ 2.2 V VCC ≥ 1.8 V µPD444010L-BxxX µPD444010L-CxxX µPD444010L-DxxX Test condition Unit MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. Input leakage ILI VIN = 0 V to VCC –1.0 +1.0 –1.0 +1.0 –1.0 +1.0 µA VI/O = 0 V to VCC, /CE1 = VIH or –1.0 +1.0 –1.0 +1.0 –1.0 +1.0 µA mA current I/O leakage ILO current CE2 = VIL or /WE = VIL or /OE = VIH Operating ICCA1 supply current ICCA2 /CE1 = VIL, CE2 = VIH, 40 – 40 – 40 Minimum cycle time, VCC ≤ 2.7 V – – – 38 – 38 II/O = 0 mA VCC ≤ 2.2 V – – – – – 35 /CE1 = VIL, CE2 = VIH, II/O = 0 mA 10 10 10 VCC ≤ 2.7 V – 8 8 ≤ 2.2 V – – 6 8 8 8 VCC ICCA3 – /CE1 ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, Cycle = 1 MHz, II/O = 0 mA, VIL ≤ 0.2 V, VCC ≤ 2.7 V – 6 6 VIH ≥ VCC – 0.2 V VCC ≤ 2.2 V – – 6 0.6 0.6 0.6 mA µA Standby ISB /CE1 = VIH or CE2 = VIL, supply current ISB1 /CE1 ≥ VCC − 0.2 V, CE2 ≥ VCC − 0.2 V ISB2 High level VOH VOL 7 0.5 7 0.5 7 VCC ≤ 2.7 V – – 0.4 6 0.4 6 VCC ≤ 2.2 V – – – – 0.3 5 0.5 7 0.5 7 0.5 7 VCC ≤ 2.7 V – – 0.4 6 0.4 6 VCC ≤ 2.2 V – – – – 0.3 5 CE2 ≤ 0.2 V IOH = –0.5 mA output voltage Low level 0.5 2.4 2.4 2.4 VCC ≤ 2.7 V – 1.8 1.8 VCC ≤ 2.2 V – – 1.5 IOL = 1.0 mA 0.4 0.4 V 0.4 V output voltage Remarks 1. VIN : Input voltage VI/O : Input / Output voltage 2. These DC characteristics are in common regardless of package types and access time. Data Sheet M13960EJ3V0DS00 7 µPD444010L-X AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) AC Test Conditions [ µPD444010L-B70X, µPD444010L-B85X ] Input Waveform (Rise and Fall Time ≤ 5 ns) 2.4 V 1.5 V Test points 1.5 V 1.5 V Test points 1.5 V 1.1 V Test points 1.1 V 1.1 V Test points 1.1 V 0.5 V Output Waveform Output Load 1TTL + 50 pF [ µPD444010L-C10X, µPD444010L-C12X ] Input Waveform (Rise and Fall Time ≤ 5 ns) 2.0 V 0.3 V Output Waveform Output Load 1TTL + 30 pF [ µPD444010L-D15X, µPD444010L-D20X ] Input Waveform (Rise and Fall Time ≤ 5 ns) 1.6 V 0.9 V Test points 0.9 V 0.9 V Test Points 0.9 V 0.2 V Output Waveform Output Load 1TTL + 30 pF 8 Data Sheet M13960EJ3V0DS00 µPD444010L-X Read Cycle Parameter VCC ≥ 2.7 V Symbol VCC ≥ 2.2 V VCC ≥ 1.8 V Unit Condition µPD444010L µPD444010L µPD444010L µPD444010L µPD444010L µPD444010L -B70X -B85X -C10X -C12X -D15X -D20X MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. Read cycle time tRC Address access time tAA 70 70 85 85 100 100 120 120 150 150 200 200 ns ns /CE1 access time tCO1 70 85 100 120 150 200 ns CE2 access time tCO2 70 85 100 120 150 200 ns /OE to output valid tOE 35 40 50 60 70 100 ns Output hold from address change tOH 10 10 10 10 10 10 ns /CE1 to output in low impedance tLZ1 10 10 10 10 10 10 ns CE2 to output in low impedance tLZ2 10 10 10 10 10 10 ns /OE to output in low impedance tOLZ 5 5 5 5 5 5 ns /CE1 to output in high impedance tHZ1 25 30 35 40 50 70 ns CE2 to output in high impedance tHZ2 25 30 35 40 50 70 ns /OE to output in high impedance tOHZ 25 30 35 40 50 70 ns Note 1 Note 2 Notes 1. The output load is 1TTL + 50 pF (µPD444010L-BxxX) or 1TTL + 30 pF (µPD444010L-CxxX, -DxxX). 2. The output load is 1TTL + 5 pF. Remark These AC characteristics are in common regardless of package types. Read Cycle Timing Chart tRC Address (Input) tAA tOH /CE1 (Input) tHZ1 tCO1 tLZ1 CE2 (Input) tCO2 tHZ2 tLZ2 /OE (Input) tOE tOHZ tOLZ I/O (Output) Remark High impedance Data out In read cycle, /WE should be fixed to high level. Data Sheet M13960EJ3V0DS00 9 µPD444010L-X Write Cycle Parameter VCC ≥ 2.7 V Symbol µPD444010L -B70X VCC ≥ 2.2 V VCC ≥ 1.8 V Unit Condition µPD444010L µPD444010L µPD444010L µPD444010L µPD444010L -B85X -C10X -C12X -D15X -D20X MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. Write cycle time tWC 70 85 100 120 150 200 ns /CE1 to end of write tCW1 55 70 80 100 120 160 ns CE2 to end of write tCW2 55 70 80 100 120 160 ns Address valid to end of write tAW 55 70 80 100 120 160 ns Address setup time tAS 0 0 0 0 0 0 ns Write pulse width tWP 50 55 60 85 100 140 ns Write recovery time tWR 0 0 0 0 0 0 ns Data valid to end of write tDW 30 35 40 60 80 100 ns Data hold time tDH 0 0 0 0 0 0 ns /WE to output in high impedance tWHZ Output active from end of write tOW 25 5 30 5 35 5 40 5 50 5 Note The output load is 1TTL + 5 pF. Remark These AC characteristics are in common regardless of package types. 10 Data Sheet M13960EJ3V0DS00 70 5 ns ns Note µPD444010L-X Write Cycle Timing Chart 1 (/WE Controlled) tWC Address (Input) tCW1 /CE1 (Input) tCW2 CE2 (Input) tAW tAS tWP tWR /WE (Input) tOW tWHZ I/O (Input / Output) Indefinite data out tDW High impedance Data in tDH High impedance Indefinite data out Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite in phase with output signals. Remarks 1. Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2. 2. If /CE1 changes to low level at the same time or after the change of /WE to low level, or if CE2 changes to high level at the same time or after the change of /WE to low level, the I/O pins will remain high impedance state. 3. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level, read operation is executed. Therefore /OE should be at high level to make the I/O pins high impedance. Data Sheet M13960EJ3V0DS00 11 µPD444010L-X Write Cycle Timing Chart 2 (/CE1 Controlled) tWC Address (Input) tAS tCW1 /CE1 (Input) tCW2 CE2 (Input) tAW tWP tWR /WE (Input) tDW High impedance Data in I/O (Input) tDH High impedance Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite in phase with output signals. Remark 12 Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2. Data Sheet M13960EJ3V0DS00 µPD444010L-X Write Cycle Timing Chart 3 (CE2 Controlled) tWC Address (Input) tCW1 /CE1 (Input) tAS tCW2 CE2 (Input) tAW tWP tWR /WE (Input) tDW High impedance I/O (Input) Data in tDH High impedance Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated. 2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite in phase with output signals. Remark Write operation is done during the overlap time of a low level /CE1, /WE and a high level CE2. Data Sheet M13960EJ3V0DS00 13 µPD444010L-X Low VCC Data Retention Characteristics (TA = –25 to +85 °C) Parameter Symbol VCC ≥ 2.7 V VCC ≥ 2.2 V VCC ≥ 1.8 V µPD444010L µPD444010L µPD444010L -B××X -C××X -D××X Test Condition Unit MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. Data retention supply voltage Data retention supply current Chip deselection to data retention mode Operation recovery time VCCDR1 /CE1 ≥ VCC − 0.2 V, CE2 ≥ VCC − 0.2 V 2.0 3.6 1.5 3.6 1.5 3.6 VCCDR2 CE2 ≤ 0.2 V 2.0 3.6 1.5 3.6 1.5 3.6 ICCDR1 VCC = 3.0 V, /CE1 ≥ VCC − 0.2 V, CE2 ≥ VCC − 0.2 V or CE2 ≤ 0.2 V 0.5 7 0.5 7 0.5 7 ICCDR2 VCC = 3.0 V, CE2 ≤ 0.2 V 0.5 7 0.5 7 0.5 7 µA tCDR 0 0 0 ns tR tRC Note tRC Note tRC Note ns Note tRC : Read cycle time 14 V Data Sheet M13960EJ3V0DS00 µPD444010L-X Data Retention Timing Chart (1) /CE1 Controlled tCDR Data retention mode tR 3.0 V Note VCC (MIN.) VCC /CE1 VIH (MIN.) VCCDR (MIN.) /CE1 ≥ VCC – 0.2 V VIL (MAX.) GND Note B version : 2.7 V, C version : 2.2 V, D version : 1.8 V Remark On the data retention mode by controlling /CE1, the input level of CE2 must be CE2 ≥ VCC − 0.2 V or CE2 ≤ 0.2 V. The other pins (Address, I/O, /WE, /OE) can be in high impedance state. (2) CE2 Controlled tCDR Data retention mode tR 3.0 V VCC (MIN.) Note VCC VIH (MIN.) VCCDR (MIN.) CE2 VIL (MAX.) CE2 ≤ 0.2 V GND Note B version : 2.7 V, C version : 2.2 V, D version : 1.8 V Remark The other pins (/CE1, Address, I/O, /WE, /OE) can be in high impedance state. Data Sheet M13960EJ3V0DS00 15 µPD444010L-X Package Drawings ★ 48-PIN PLASTIC TSOP(I) (12x18) 1 detail of lead end 48 F G R Q 24 L 25 S E P I A J C S D K N B M M S NOTES ITEM MILLIMETERS 1. Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. A 12.0±0.1 B 0.45 MAX. 2. "A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.) C 0.5 (T.P.) D 0.22±0.05 E 0.1±0.05 F 1.2 MAX. G 1.0±0.05 I 16.4±0.1 J 0.8±0.2 K 0.145±0.05 L 0.5 M 0.10 N 0.10 P 18.0±0.2 Q +5° 3° −3° R S 0.25 0.60±0.15 S48GY-50-MJH1-1 16 Data Sheet M13960EJ3V0DS00 µPD444010L-X ★ 48-PIN PLASTIC TSOP(I) (12x18) detail of lead end 1 48 E S L Q R 24 G 25 F K N S D S I J M M B C A P NOTES 1. Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. 2. "A" excludes mold flash. (Includes mold flash : 12.4 mm MAX.) ITEM A MILLIMETERS 12.0±0.1 B 0.45 MAX. C 0.5 (T.P.) D 0.22±0.05 E 0.1±0.05 F 1.2 MAX. G 1.0±0.05 I 16.4±0.1 J 0.8±0.2 K 0.145±0.05 L 0.5 M 0.10 N 0.10 P 18.0±0.2 Q 3° +5° −3° R 0.25 S 0.60±0.15 S48GY-50-MKH1-1 Data Sheet M13960EJ3V0DS00 17 µPD444010L-X Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the µPD444010L-X. Types of Surface Mount Device µPD444010LGY-BxxX-MJH: 48-pin Plastic TSOP (I) (12×18) (Normal bent) µPD444010LGY-BxxX-MKH: 48-pin Plastic TSOP (I) (12×18) (Reverse bent) µPD444010LGY-CxxX-MJH: 48-pin Plastic TSOP (I) (12×18) (Normal bent) µPD444010LGY-CxxX-MKH: 48-pin Plastic TSOP (I) (12×18) (Reverse bent) µPD444010LGY-DxxX-MJH: 48-pin Plastic TSOP (I) (12×18) (Normal bent) µPD444010LGY-DxxX-MKH: 48-pin Plastic TSOP (I) (12×18) (Reverse bent) 18 Data Sheet M13960EJ3V0DS00 µPD444010L-X NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet M13960EJ3V0DS00 19 µPD444010L-X [ MEMO ] • The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. • NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. • Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. • While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. • NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. M7 98. 8