DATA SHEET MOS INTEGRATED CIRCUIT µPD61051, 61052 MPEG2 AUDIO/VIDEO ENCODER The µPD61051 and µPD61052 are LSIs of MPEG audio and video encoding, decoding and transcoding. The µPD61051 has MPEG2 video encoder, MPEG audio encoding DSP, 32-bit RISC CPU, video input/output unit which contains a processing filter and a time base corrector (TBC), and MPEG system layer which contains the multiplexer and de-multiplexer. It combines with 64 M or 128 Mbit SDRAM and it uses. The µPD61052 has a Dolby™ Digital Consumer Encoder in addition to the µPD61051. The µPD61051, 61052 are the optimal choice for consumer digital video recording replay equipment to process a MPEG. FEATURES • Video encode - Stream standard: MPEG2 video MP@ML, SP@ML standard, MPEG1 standard Picture size: Horizontal: 720, 704, 544, 480, 352 dots/line Vertical: 480, 240, 576, 288 line/frame Single pass variable bit rate (VBR), constant bit rate (CBR) encoding Transcoding: Bit rate conversion, VBR ⇔ CBR • Video input/output Format: 8-bit Y/Cb/Cr 4:2:2 (ITU-R BT.656) Pre analysis: Film detect, scene changing detect, and motion estimation assist TBC, VBI data slicer Audio encoding • MPEG system processing • • • Package: 208-pin fine pitch QFP Power supply: 1200 mW (Typ.) Power supply voltage: 3.3±0.165 V, 2.5±0.2 V (Internal circuit power) - Bit length: 16 bits, 20 bits, 24 bits - Sampling rate: 32 kHz, 44.1 kHz, 48 kHz - MPEG1 audio layer 2 standard based - Dolby Digital Consumer Encoder standard based (Only the µPD61052) - Elementary stream and PCM audio input/output - Multiplex: MPEG2-PS, MPEG2-TS, DVD-Video, and DVD-VR - De-multiplex: MPEG2-PS, MPEG2-TS - Transcoding: MPEG2 format conversion (MPEG2-TS ⇔ MPEG2-PS) - Partial TS generation "Dolby" is a trademark of Dolby Laboratories. To use the µPD61052, a license from Dolby Laboratories Licensing Corporation is necessary. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. S15082EJ4V0DS00 (4th edition) Date Published November 2003 NS CP (K) Printed in Japan The mark shows major revised points. 2002 µPD61051, 61052 APPLICATION D-VHS, DVD video recorder, HDD video recorder ORDERING INFORMATION Part Number Package µPD61051GD-LML Note µPD61051GD-LML-A µPD61052GD-LML Note µPD61052GD-LML-A Note 208-pin plastic QFP (Fine pitch) (28×28) 208-pin plastic QFP (Fine pitch) (28×28) 208-pin plastic QFP (Fine pitch) (28×28) 208-pin plastic QFP (Fine pitch) (28×28) Lead-free product MCLKE Video Input Unit MCLK MCS MRAS MCAS MWE CCS CRE CWE/CSDI CA5-CA0/FA5-FA0 CD7-CD0/FD7-FD0 CWAIT/FOE CINT CMODE1/CSDO CMODE0/CSCLK OVOUT7-OVOUT0/FA19-FA14 OVCLK IVCLK IVIN7-IVIN0 IVFLD IVVSYNC IVHSYNC BLOCK DIAGRAM Video Output Unit CMODE2 GPO6/OVVSYNC GPO5/OVHSYNC GPIO4-GPIO0 Host CPU Interface Unit SDRAM Interface Unit MA13-MA0 OSREQ OSVLD/OSRDY OSSYNC OSCLK/OSSTB OS7-OS0/FA13-FA6 Internal CPU MD31-MD0 MDQM Stream Interface Unit Video Encode/Transcode Unit PSTOP SCLK (27 MHz) PLL Audio DSP Engine STCLK Data Sheet S15082EJ4V0DS PWM RESET OABD OABCK OALRCK AMCLK IABD IABCK IALRCK System Control Unit 2 ISREQ ISVLD ISCLK/ISSTB IS7-IS2 IS1/ISERR IS0 µPD61051, 61052 PERIPHERAL CONNECTION SDRAM SDRAM Video Input Audio Input NTSC/PAL Decoder ADC BT.656 MPEG2 AV Encoder µPD61051/61052 PCM Video Output TS Decoder MPEG Decoder PCM DAC Audio Output Host CPU 1394 In/Out 1394 PHY 1394 AV Link TS Stream Interface AV HDD Data Sheet S15082EJ4V0DS 3 µPD61051, 61052 This LSI deals with two kinds of methods to connect a system controller. Parallel Bus Interface 64M SDRAM NTSC/PAL Decoder Audio ADC BT.656 µPD61051/61052 PCM BT.656 NTSC/PAL Encoder PCM Audio ADC/DAC 27 MHz STC Clock MPEG TS/PS MPEG TS/PS User Interface Host CPU Serial Bus Interface 64M SDRAM NTSC/PAL Decoder Audio ADC BT.656 PCM µPD61051/61052 27 MHz STC Clock MPEG TS/PS User Interface 4 BT.656 NTSC/PAL Encoder PCM Audio ADC/DAC MPEG TS/PS SPI Host CPU Instruction ROM Data Sheet S15082EJ4V0DS µPD61051, 61052 PIN CONFIGURATION (TOP VIEW) • 208-pin plastic QFP (Fine pitch) (28×28) 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 OVOUT7 OVOUT6 OVOUT5/FA19 OVOUT4/FA18 OVOUT3/FA17 OVOUT2/FA16 OVOUT1/FA15 OVOUT0/FA14 GND OVCLK VDD2 GPO6/OVVSYNC GND GPO5/OVHSYNC VDD3 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 GND CA5/FA5 VDD2 CA4/FA4 CA3/FA3 CA2/FA2 CA1/FA1 CA0/FA0 NDO NDI NMOD GND NRST VDD2 NCLK GND CD7/FD7 VDD3 CD6/FD6 CD5/FD5 CD4/FD4 CD3/FD3 CD2/FD2 GND CD1/FD1 VDD2 CD0/FD0 CWAIT/FOE CRE CCS CMODE2 CWE/CSDI µPD61051GD-LML µPD61051GD-LML-A µPD61052GD-LML µPD61052GD-LML-A 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 CMODE1/CSDO CMODE0/CSCLK GND CINT VDD2 RESET GND MD15 VDD3 MD14 MD13 MD12 MD11 MD10 GND MD9 VDD2 MD8 MD0 GND MD1 VDD3 MD2 MD3 MD4 MD5 GND MD6 VDD2 MD7 MDQM MWE GND MCAS VDD3 MRAS MCS GND MCLK VDD2 MCLKE MA11 MA9 MA8 GND MA7 VDD3 MA6 MA5 GND MA4 VDD2 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 ISCLK/ISSTB ISVLD ISREQ OS0/FA6 OS1/FA7 OS2/FA8 OS3/FA9 VDD2 OS4/FA10 GND OS5/FA11 OS6/FA12 OS7/FA13 OSCLK/OSSTB OSSYNC OSVLD/OSRDY VDD3 OSREQ VDD2 MD23 GND GND MD22 MD21 MD20 MD19 MD18 MD17 MD16 VDD2 MD24 GND MD25 VDD3 MD26 GND MD27 MD28 MD29 MD30 MD31 VDD2 MA0 GND MA1 VDD3 MA2 GND MA3 MA10 MA12 MA13 VDD2 AMCLK GND OALRCK OABCK OABD IALRCK IABCK IABD GND IVFLD IVHSYNC VDD2 IVVSYNC GND IVIN0 IVIN1 IVIN2 IVIN3 IVIN4 IVIN5 IVIN6 IVIN7 VDD2 IVCLK GND GND SCLK PSTOP PVDD2 PGND PVDD2 PGND STCLK GND VDD2 GND GND VDD3 PWM GND IS0 IS1/ISERR IS2 IS3 IS4 IS5 VDD2 IS6 GND IS7 ISSYNC Data Sheet S15082EJ4V0DS 5 µPD61051, 61052 PIN LIST AMCLK :Audio Main Clock MA0 to MA13 :Memory Address CA0/FA0 to CA5/FA5 :Host CPU Address/ MCAS :Memory Column Address Strobe Instruction ROM Address MCLK :Memory Clock :Host CPU Chip Select MCLKE :Memory Clock Enable MCS :Memory Chip Select Instruction ROM Data MD0 to MD31 :Memory Data CINT :Host CPU Interrupt MDQM :Memory DQ Mask Enable CMODE0/CSCLK :Host CPU Mode/ MRAS :Memory Row Address Strobe SPI Clock MWE :Memory Write Enable :Host CPU Mode/ NCLK :N-wire Clock SPI Data Output NDI :N-wire Data Input CMODE2 :Host CPU Mode NDO :N-wire Data Output CRE :Host CPU Read Enable NMOD :N-wire Mode CWAIT/FOE :Host CPU Wait/ NRST :N-wire Reset Instruction ROM Output Enable OABCK :Output Audio Bit Clock :Host CPU Write Enable/ OABD :Output Audio Bit Data SPI Data Input OALRCK :Output Audio LR Clock GND :Ground OS0/FA6 to OS7/FA13 :Output Stream Data/ GPIO0 to GPIO4 :General Purpose IO GPO5/OVHSYNC :General Purpose Output/ CCS CD0/FD0 to CD7/FD7 :Host CPU Data/ CMODE1/CSDO CWE/CSDI Instruction ROM Address OSCLK/OSSTB Output Video Horizontal Sync GPO6/OVVSYNC :Output Stream Data Clock/ Output Stream Data Strobe :General Purpose Output/ OSREQ :Output Stream Data Request Output Video Vertical Sync OSSYNC :Output Stream Data Sync IABCK :Input Audio Bit Clock OSVLD/OSRDY :Output Stream Data Valid/ IABD :Input Audio Bit Data IALRCK :Input Audio LR Clock OVCLK :Output Video Clock IS0, IS2 to IS7 :Input Stream Data OVOUT0/FA14 to :Output Video Data/ IS1/ISERR :Input Stream Data/ Input Stream Error OVOUT5/FA19 Instruction ROM Address ISCLK/ISSTB :Input Stream Data Clock/ OVOUT6,OVOUT7 :Output Video Data Input Stream Data Strobe PGND :PLL Ground ISREQ :Input Stream Data Request PSTOP :PLL Stop ISSYNC :Input Stream Data Sync PVDD2 :PLL 2.5 V Power Supply ISVLD :Input Stream Data Valid PWM :PWM Output IVCLK :Input Video Clock RESET :Reset IVFLD :Input Video Field Index SCLK :System Clock IVHSYNC :Input Video Horizontal Sync STCLK :System Time Clock IVIN0 to IVIN7 :Input Video Data VDD2 :2.5 V Power Supply IVVSYNC :Input Video Vertical Sync VDD3 :3.3 V Power Supply 6 Output Stream Data Ready Data Sheet S15082EJ4V0DS µPD61051, 61052 CONTENTS 1. PIN FUNCTION ............................................................................................................................... 9 1.1 Video Input Interface............................................................................................................................. 9 1.2 Video Output Interface.......................................................................................................................... 9 1.3 Audio Input Interface ............................................................................................................................ 9 1.4 Audio Input/output Interface .............................................................................................................. 10 1.5 Stream Input Interface ........................................................................................................................ 10 1.6 Stream Output Interface ..................................................................................................................... 11 1.7 SDRAM Interface ................................................................................................................................. 11 1.8 1.9 Host CPU Interface.............................................................................................................................. 12 1.8.1 Parallel bus interface................................................................................................................. 12 1.8.2 Serial bus interface.................................................................................................................... 12 Clock, Reset......................................................................................................................................... 13 1.10 N-Wire................................................................................................................................................... 13 1.11 GPIO ..................................................................................................................................................... 14 1.12 Power Supply ...................................................................................................................................... 14 1.13 Recommended Connections of Unused Pins ................................................................................... 15 2. FEATURE OVERVIEW.................................................................................................................. 16 2.1 2.2 2.3 2.4 Video .................................................................................................................................................... 16 2.1.1 Encoding ................................................................................................................................... 16 2.1.2 Transcoding............................................................................................................................... 16 2.1.3 Input/output processing ............................................................................................................. 17 Audio .................................................................................................................................................... 19 2.2.1 Encoding ................................................................................................................................... 19 2.2.2 Transcoding (DEMUX, MUX) .................................................................................................... 19 2.2.3 Input/output processing ............................................................................................................. 19 MPEG System Processing.................................................................................................................. 22 2.3.1 System time clock ..................................................................................................................... 22 2.3.2 Multiplex .................................................................................................................................... 23 2.3.3 De-multiplex .............................................................................................................................. 23 2.3.4 Transcode ................................................................................................................................. 24 Stream Interface .................................................................................................................................. 25 2.4.1 Parallel steam data interface ..................................................................................................... 25 2.4.2 Serial stream data interface....................................................................................................... 29 2.5 Host CPU Interface.............................................................................................................................. 32 2.6 SDRAM Interface ................................................................................................................................. 33 2.7 Memory Connection Diagram ............................................................................................................ 34 2.8 Memory Map ........................................................................................................................................ 36 3. SYSTEM INTERFACE REGISTER .............................................................................................. 38 3.1 Register Mapping (General Mapping)................................................................................................ 39 3.2 Register Functions.............................................................................................................................. 40 3.2.1 Common register....................................................................................................................... 40 3.2.2 Data transfer register................................................................................................................. 40 3.2.3 Internal CPU interrupt register................................................................................................... 47 3.2.4 Interrupt mask register .............................................................................................................. 47 Data Sheet S15082EJ4V0DS 7 µPD61051, 61052 3.2.5 Download interrupt register ....................................................................................................... 47 3.2.6 Interrupt register ........................................................................................................................ 48 3.2.7 Reset register ............................................................................................................................ 48 3.2.8 ROM access cycle register........................................................................................................ 49 3.2.9 Port setup register ..................................................................................................................... 49 4. SYSTEM INTERFACE PROCEDURE.......................................................................................... 50 4.1 4.2 Outline .................................................................................................................................................. 51 Firmware Download ............................................................................................................................ 52 4.2.1 Host CPU to instruction RAM of internal CPU ........................................................................... 52 4.2.2 External ROM to instruction RAM of internal CPU..................................................................... 53 4.2.3 Host CPU to SDRAM................................................................................................................. 54 4.2.4 External ROM to SDRAM .......................................................................................................... 55 4.3 SDRAM Write during Executing ......................................................................................................... 56 4.4 SDRAM Read during Executing ......................................................................................................... 57 4.5 SDRAM Initialization............................................................................................................................ 58 4.6 Operation Mode Setting by Changing Firmware .............................................................................. 59 4.7 Transfer Ending................................................................................................................................... 60 4.8 Transfer Error Handling ...................................................................................................................... 61 4.8.1 Transfer error handling 1 ........................................................................................................... 61 4.8.2 Transfer error handling 2 ........................................................................................................... 62 4.8.3 Transfer error handling 3 ........................................................................................................... 63 5. EXAMPLE FOR COMMON REGISTER USAGE....................................................................... 64 5.1 Register Map Example ........................................................................................................................ 65 5.2 Example of the Common Register Which A Firmware Defines ....................................................... 67 5.2.1 COMCODE: Command code register........................................................................................ 66 5.2.2 ESTS: Status register ................................................................................................................ 66 6. ELECTRICAL CHARACTERISTICS............................................................................................. 68 7. PACKAGE DRAWING ................................................................................................................ 102 8. RECOMMENDED SOLDERING CONDITIONS......................................................................... 103 8 Data Sheet S15082EJ4V0DS µPD61051, 61052 1. PIN FUNCTION Sharing pin is bold faced in name and explains the feature shown. 1.1 Video Input Interface The video input is based on the ITU-R BT.656 format. The horizontal synchronization signal, and the vertical synchronization signal, the field index can be used without using SAV and EAV to provide at ITU-R BT. 656, too. Name IO Pin Function Number 1.2 Active Polarity IVIN7 to IVIN0 I 23 to 16 Video data IVCLK I 25 Video clock (27 MHz) ↑ IVHSYNC I 12 Horizontal synchronization L IVVSYNC I 14 Vertical synchronization L IVFLD I 11 Field index Video Output Interface The video output is based on the ITU-R BT.656 format. It is able to output horizontal and vertical synchronization signals with SAV/EAV. These synchronization signals are chosen output by the firmware. These ports become GPO until the firmware initializes after hardware reset. At the time of the odd field, OVVSYNC falls in the 4th clock after falling of OVHSYNC. At the time of the even field, OVVSYNC falls in to the H/2+4th clock the OVHSYNC falling. Name IO Pin Function Number OVOUT7, OVOUT6 O OVOUT5 to OVOUT0/ O FA19 to FA14 1.3 Active Polarity 208, 207 Video data 206 to Video data 201 OVCLK O 199 Video clock (27 MHz) ↑ GPO5/OVHSYNC O 195 Horizontal synchronization L GPO6/OVVSYNC O 197 Vertical synchronization L Audio Input Interface Name IO Pin Function Number Active Polarity IALRCK I 7 Left/Right clock IABCK I 8 Bit clock IABD I 9 Bit data Data Sheet S15082EJ4V0DS ↑ 9 µPD61051, 61052 1.4 Audio Input/output Interface After hardware reset, it becomes input. OALRCK, OABCK and OABD connect with 3.3 V VDD through the 10 kΩ pull up resistance. Firmware controls input/output of those pins. Name IO Pin Function Number OALRCK IO 4 Left/Right clock OABCK IO 5 Bit clock OABD IO 6 Bit data I 2 Audio clock AMCLK 1.5 Active Polarity ↑ ↑ Stream Input Interface Stream input corresponds to MPEG TS/PS stream. When slave mode (MPEG2-TS input with using valid signal), data input is possible to select 8 bits parallel data or serial data mode. When serial data mode, data input to IS0. Active polarity of ISREQ is selected by the port setup register. Active polarity of ISCLK/ISSTB, ISSYNC ISERR and ISVLD are selected by firmware. These are unsettled after the turning on. Name IO Pin Function Number ISREQ O 55 Active Polarity Stream data request Only parallel interface, this pin is active. After reset, default is active low. ISCLK/ISSTB I 53 Stream data strobe After reset, default is ISCLK. ISCLK/ISSTB I 53 Stream data clock After reset, default is active high edge. ISSYNC I 52 Stream data synchronization After reset, default is active high. ISVLD I 54 Stream data valid After reset, default is active low. IS1/ISERR I 43 Stream error After reset, default is active high. IS1/ISERR I 43 Stream data input IS7 to IS2, IS0 I 51,49, 47 Stream data input to 44, 42 Remark 10 In this table, means of reset are hardware reset by the RESET pin and ALL RESET of the reset register. Data Sheet S15082EJ4V0DS µPD61051, 61052 1.6 Stream Output Interface This interface outputs MPEG TS/PS stream. When in master mode (MPEG2-TS output with using valid signal), data output is possible to select 8bits parallel data or serial data mode. In serial mode, data output from OS0. Active polarity of OSVLD is selected by the port setup register. Active polarity of OSCLK/OSSTB and OSSYNC are selected by firmware. These are unsettled after the turning on. Name IO Pin Function Active Number Polarity OSREQ I 70 Stream data request in slave mode OSCLK/OSSTB O 66 Stream data strobe L After reset, default is active high edge. OSCLK/OSSTB O 66 Stream data clock After reset, default is OSSTB. OSSYNC O 67 Stream data synchronization After reset, default is active high. OSVLD/OSRDY O 68 Stream data valid After reset, default is OSRDY. OSVLD/OSRDY O 68 Stream data ready prepared After reset, default is active low. OS7 to OS0/ O FA13 to FA6 Remark 1.7 65 to 63, Stream data output 61, 59 to 56 In this table, means of reset are hardware reset by the RESET pin and ALL RESET of the reset register. SDRAM Interface Name IO Pin Number Function Active Polarity MA13 to MA0 O 104, 103, 115, 102, 114, 113, 111, Address of row/column 109, 108, 106, 101, 99, 97, 95 MD31 to MD0 IO 93 to 89, 87, 85, 83, 72, 75 to 81, Data 149, 147 to 143, 141, 139, 127, 129, 131 to 134, 136, 138 (Built-in 50 kΩ pull up resistor) MCLK O 118 Clock ↑ MCKE O 116 Clock enable H MCS O 120 Chip selection L MRAS O 121 Row address strobe L MCAS O 123 Column address strobe L MWE O 125 Write enable L MDQM O 126 Data input/output mask enable L Data Sheet S15082EJ4V0DS 11 µPD61051, 61052 1.8 Host CPU Interface It chooses a parallel bus connection and a serial bus connection by the setting of CMODE2. Name IO Pin Function Number CMODE2 I 158 Active Polarity Host CPU interface select L: Parallel, H: Serial 1.8.1 Parallel bus interface Name IO Pin Number Function Active Polarity CA5 to CA0/ I 187, 185 to 181 Address 172, 170 to 166, 164, 162 Data FA5 to FA0 CD7 to CD0/ FD7 to FD0 IO CWE/CSDI I 157 Write enable L CRE I 160 Read enable L CCS I 159 Chip selection L CINT O 153 Interrupt H CWAIT/FOE O 161 Wait CMODE0/CSCLK I 155 Setting of polarity of CWAIT L: Low wait, H: High wait CMODE1/CSDO I 156 Setting of operation of CWAIT (Built-in 50 kΩ pull up resistor) L: Wait operation.(after ready, pin continues ready) H: Ready operation.(after ready, pin turns to wait) 1.8.2 Serial bus interface When connecting a serial bus, it downloads instruction of internal CPU from instruction ROM. (1) Serial bus interface Name IO Pin Function Number CMODE0/CSCLK I 155 Active Polarity SPI serial interface clock ↑ Fix CSCLK to high level during CCS is disable (high level). CWE/CSDI I 157 CMODE1/CSDO O 156 SPI serial interface data input SPI serial interface data output (Built-in 50 kΩ pull up resistor) 12 CCS I 159 Chip selection L CINT O 153 Interrupt H Data Sheet S15082EJ4V0DS µPD61051, 61052 (2) Instruction ROM interface Name IO Pin Number Function Active Polarity CA5 to CA0/ O 187, 185 to 181 Address 65 to 63, 61, 59 Address FA5 to FA0 OS7 to OS0/ O FA13 to FA6 to 56 OVOUT5 to OVOUT0/ O 206 to 201 Address 172, 170 to Data FA19 to FA14 CD7 to CD0/ I FD7 to FD0 166, 164, 162 CWAIT/FOE 1.9 O 161 Output enable L Clock, Reset Name IO Pin Number Function Active Polarity SCLK I 28 System clock ↑ STCLK I 34 System time clock ↑ PSTOP I 29 Internal PLL operation control H L: Normal, H: Internal PLL stop PWM O 40 PWM output RESET I 151 Reset L 1.10 N-Wire IE Port for firmware of Internal CPU evaluation When not connecting an in-circuit emulator, take countermeasures against noise by pulling up the NDI pin to avoid the pin becoming low level. Name IO Pin Number Function Active Polarity NMOD I 178 Pin used when connecting IE H Pull up when connecting IE NCLK I 174 Serial clock ↑ NRST I 176 N-wire reset L NDI I 179 Data input NDO O 180 Data output Data Sheet S15082EJ4V0DS 13 µPD61051, 61052 1.11 GPIO GPIO becomes input after hardware reset by the RESET pin and ALL RESET by the reset register. GPIO connect with 3.3 V VDD through the 10 kΩ pull up resistance. Name IO Pin Function Active Number Polarity GPIO0 IO 189 Firmware use pin GPIO1 IO 190 Firmware use pin GPIO2 IO 191 Firmware use pin GPIO3 IO 192 Firmware use pin GPIO4 IO 193 Firmware use pin GPO5/OVHSYNC O 195 Firmware use pin GPO6/OVVSYNC O 197 Firmware use pin 1.12 Power Supply Name IO Pin Number Function Active Polarity VDD3 - 39, 69, 86, 98, 110, 122, 135, 148, 3.3 V power supply for interface 171, 194 VDD2 - 1, 13, 24, 36, 48, 60, 71, 82, 94, 105, 117, 128, 140, 152, 163, 175, 186, 198 GND - 3, 10, 15, 26, 27, 35, 37, 38, 41, 2.5 V power supply for the internal circuit GND 50, 62, 73, 74, 84, 88, 96, 100, 107, 112, 119, 124, 130, 137, 142, 150, 154, 165, 173, 177, 188, 196, 200 14 PVDD2 - 30, 32 2.5 V power supply for PLL PGND - 31, 33 GND for PLL Data Sheet S15082EJ4V0DS µPD61051, 61052 1.13 Recommended Connections of Unused Pins Connect unused pins as follows. Name IO Connection IVIN7 to IVIN0 I GND IVCLK I GND IVHSYNC I GND IVVSYNC I GND IVFLD I GND OVOUT7, OVOUT6 O Open OVOUT5 to OVOUT0/FA19 to FA14 O Open OVCLK O Open IALRCK I GND IABCK I GND IABD I GND OALRCK IO Pull up with 10 kΩ resistor OABCK IO Pull up with 10 kΩ resistor OABD IO Pull up with 10 kΩ resistor AMCLK I GND ISREQ O Open ISCLK/ISSTB I GND ISSYNC I GND ISVLD I GND IS7 to IS0 I GND OSREQ I GND OSSYNC O Open CA5 to CA0/FA5 to FA0 IO Open CD7 to CD0/FD7 to FD0 IO Pull up with 10 kΩ resistor CRE I GND CINT O Open CWAIT/FOE O Open PWM O Open NMOD I Pull up with 4.7 kΩ resistor NCLK I Pull up with 4.7 kΩ resistor NRST I Pull down with 50 kΩ resistor NDI I Pull up with 4.7 kΩ resistor NDO O Pull up with 4.7 kΩ resistor GPIO4 to GPIO0 IO Pull up with 10 kΩ resistor GPO5/OVHSYNC O Open GPO6/OVVSYNC O Open Data Sheet S15082EJ4V0DS 15 µPD61051, 61052 2. FEATURE OVERVIEW The functions and I/O interfaces are set using firmware. Supported functions differ depending on firmware. 2.1 Video This LSI can do flexible encoding and transcoding by using the firmware control of internal CPU and an exclusive use circuit. NTSC/PAL video format, which is possible of the encoding is as in Table 2-1. NTSC/PAL video format of the transcoding is under 720 dots by 480/576 line/frame. Table 2-1. Video Format MPEG2 2.1.1 MPEG1 Video format Yes No 720 dots by 480/576 line/frame Yes No 704 dots by 480/576 line/frame Yes No 544 dots by 480/576 line/frame Yes No 480 dots by 480/576 line/frame Yes No 352 dots by 480/576 line/frame Yes Yes 352 dots by 240/288 line/frame Encoding It encodes the video that was converted from the 4:2:2 format into the 4:2:0 format in the video input/output unit with MPEG2 standard MP@ML, SP@ML and the MPEG1 standard. It is encoding in variable bit rate (single path VBR encoding) or constant bit rate (CBR). The pre analysis supports high quality picture encoding. Encode supports frame structure. • Using the following, only 64 Mbits SDRAM is needed. Encoding with locally decoding and/or time base corrector (TBC) PAL encoding • DVD encoding needs equal to 128 Mbits SDRAM area. • The motion estimation size P picture: ±128 dots (H) by ±64 lines (V) B picture: ±96 dots (H) by ±48 lines (V), ±64 dots (H) by ±32 lines (V) • I/P picture period in MP@ML : M ≤ 3 • Dual prime estimate, only at the time of M = 1. 2.1.2 Transcoding It transcodes the stream of MPEG2 standard MP@ML based. It is possible for the bit rate conversion. 16 Data Sheet S15082EJ4V0DS µPD61051, 61052 2.1.3 Input/output processing (1) Video input The video input format is ITU-R BT.656 (8-bit Y/Cb/Cr the 4:2:2 format) and 8-bit Y/Cb/Cr which deals with the 4:2:0 format. The horizontal synchronization signal, the vertical synchronization signal and the field index can be used without using SAV and EAV. In this case, IVFLD can be used by taking with IVVSYNC or it judges a field judgment in the polarity of IVHSYNC behind the falling edge two clock of IVVSYNC. It judges that an odd field is 'H' and an even field is 'L'. IVVSYNC and IVHSYNC need the high / low period more than 3 IVCLK. The video-input unit watches over the synchronization signals and detects synchronous error. (2) Picture size conversion filter For adapting to the bit rate of the stream, the picture size of the encoding can be changed. In addition, picture size changed with the external filter to the 4:2:0 format can be inputted directly, too. Table 2-2. Input Video Data Arrangement Format Line Data arrangement 4:2:2 Odd/even lines Cb0, Y0, Cr0, Y1, Cb1, Y2, Cr1, Y3, Cb2, Y4, Cr2, Y5, … 4:2:0 Odd lines Cb0, Y0, Cr0, Y1, Cb1, Y2, Cr1, Y3, Cb2, Y4, Cr2, Y5, … Even lines (-), Y0, (-), Y1, (-), Y2, (-), Y3, (-), Y4, (-), Y5, … (3) Time base corrector (TBC) It has a frame-type TBC. It is possible to make stable encoding of the channel changing and the nonstandard video signal such as VTR. When using TBC, it needs over 64 Mbits SDRAM. The following video signals can be corrected. Table 2-3. Correctable Video Signals Horizontal Sync Vertical Sync NTSC 1626 to 1806 IVCLK/H 246 to 278 H/V PAL 1628 to 1828 IVCLK/H 294 to 330 H/V Remark IVCLK: 27 MHz (4) Noise reduction Respectively the noise reduction of the luminance signal and the color signal can be set three levels (5) Slicer Slicer decodes the luminance signal to the vertical blanking data. It detects VBID, Closed Caption, and Wide Screen Signal. The host CPU can read, and stop encoding and re-write the copy control information in VBID and the Wide Screen Signal, on the host CPU interface. Data Sheet S15082EJ4V0DS 17 µPD61051, 61052 Table 2-4. Slicer TV method NTSC PAL VBI data Detection line VBID 20, 283 Closed caption 21, 284 Wide screen signal 23 (336) (6) Video output It converts an input video or a local-decoded video into picture size of 720 dots by 480/576 line and outputs with the ITU-R BT.656 format. Horizontal and vertical synchronization signals are switched from GPO. Field detection is easy due to vertical synchronization signal delays 4VCLK since horizontal synchronization signal. Figure 2-1. Video Output (a) Odd Field 3H OVVSYNC (NTSC) 2.5H OVVSYNC (PAL) OVHSYNC OVCLK OVVSYNC 4OVCLK OVHSYNC (b) Even Field OVVSYNC (NTSC) OVVSYNC (PAL) 3H 2.5H OVHSYNC H/2+4 OVCLK 18 Data Sheet S15082EJ4V0DS µPD61051, 61052 2.2 Audio This LSI encodes the MPEG audio encoding and transcode with the internal DSP. 2.2.1 Encoding It encodes MPEG1 audio layer 2 or Dolby Digital Consumer Encoder (only the µPD61052). In addition, it is possible to bypass internal audio encode DSP, when the audio elementary stream is encoded by an external audio encoder are inputted. 2.2.2 Transcoding (DEMUX, MUX) It is possible to multiplex two de-multiplexed audio streams. It analyzes MPEG1 audio stream, and extracts the information to multiplex and notify to the host CPU. 2.2.3 Input/output processing Two PCM audio signals can be inputted to the audio input interface and the audio input-output interface. When inputting two audio signals, an audio signal is encoded, and another one bypasses the audio encoding DSP, and transfers to the multiplexer. When inputting an audio elementary stream that has been encoded by the external audio encoder and PCM audio, it can multiplex two audio elementary streams. The PCM audio or the audio elementary stream can be outputted from the audio input-output interface. The audio clock (AMCLK) types the clock by which a phase was locked up STC clock (STCLK). Table 2-4. Audio Input/output Item Input/output format Data length 16 bits, 20 bits, 24 bits Sampling frequency 32 kHz, 44.1 kHz, 48 kHz Justification of transfer MSB first 2 I S Compatible/Left justified/Right justified Format PCM Audio, IEC60958 based Data Sheet S15082EJ4V0DS 19 µPD61051, 61052 Figure 2-2. Audio Input (a) MSB First Right Justified Mode Lch Don't care LSB MSB ≈≈≈ ≈ ≈ Don't care ≈ ≈ ≈≈ ≈ IALRCK (OALRCK) IABCK (OABCK) IABD (OABD) Rch LSB MSB Audio data 16/32 IABCK (OABCK) (b) MSB First Left Justified Mode Lch MSB LSB ≈≈≈ ≈ ≈ ≈ ≈ ≈≈ ≈ IALRCK (OALRCK) IABCK (OABCK) IABD (OABD) MSB Rch LSB Audio data 16/32 IABCK (OABCK) (c) I2S Mode MSB LSB MSB Audio data 32 IABCK (OABCK) 20 Data Sheet S15082EJ4V0DS ≈ ≈ ≈≈ ≈ Lch ≈≈≈ ≈ ≈ IALRCK (OALRCK) IABCK (OABCK) IABD (OABD) Rch LSB µPD61051, 61052 Figure 2-3. Audio Output (a) MSB First Right Justified Mode OABD MSB Lch MSB MSB LSB ≈≈≈ ≈ ≈ OABCK ≈ ≈ ≈≈ ≈ OALRCK Rch MSB LSB Audio data 16/32 OABCK (b) MSB First Left Justified Mode OABD MSB LSB ≈≈≈ ≈ ≈ Lch OABCK ≈ ≈ ≈≈ ≈ OALRCK MSB Rch LSB Audio data 16/32 OABCK (c) I2S Mode OABD MSB LSB MSB ≈ ≈ ≈≈ ≈ OABCK ≈≈≈ ≈ ≈ Lch OALRCK Rch LSB Audio data 32 OABCK Data Sheet S15082EJ4V0DS 21 µPD61051, 61052 2.3 MPEG System Processing This LSI multiplexes and/or de-multiplexes Audio and video streams based on MPEG2-TS/PS and MPEG1. By combining the multiplexer and de-multiplexer, it does the transcode which is accompanied by MPEG2-TS⇔MPEG2 PS conversion. 2.3.1 System time clock (1) Encoding system When the encoding system operates, it uses the clock input to STCLK that is generated with the 27 MHz oscillator. Audio master clock is made with 27 MHz of STCLK, and then Audio synchronizes to STC. Figure 2-4. System Time Clock Input (Encoding System) IVIN7 to IVIN0 Video Decoder 27 MHz IVCLK Audio in Audio ADC AMCLK XTAL 27 MHz 27 MHz SCLK PLL 27 MHz STCLK PWM µPD61051/61052 22 Data Sheet S15082EJ4V0DS µPD61051, 61052 (2) Encoding and Transcoding system It can output the signal, which generates the pulse wide modulation (PWM) with comparing PCR/SCR of the stream and system time clock value, for making the reference clock of the system. Figure 2-5. System Time Clock Input (Encoding and Transcoding System) IS OS IVIN7 to IVIN0 Video Decoder 27 MHz IVCLK Audio in Audio ADC AMCLK 27 MHz 27 MHz XTAL SCLK PLL VCO 27 MHz STCLK Filter PWM µPD61051/61052 2.3.2 Multiplex It stamps SCR, PCR, DTS and PTS after multiplexing streams that are from the video encoder and the audio encoder based on MPEG2-TS/PS. Partial TS can be made by forming SIT packet from PSI and SI data of base on DVB. It is possible to multiplex the packet that inputted from the host CPU interface. 2.3.3 De-multiplex (1) MPEG2-TS Using the PID filter corresponding to 16 PIDs, It separates MPEG2-TS to one video stream, two audio streams, and two user data streams. Internal CPU extracts section data in PSI and SI of base on DVB. (2) MPEG2-PS With the stream ID filter, it separates MPEG2-PS to one video stream, one audio stream, and two user data streams. Data Sheet S15082EJ4V0DS 23 µPD61051, 61052 (3) VBI data The user data stream, the wide screen signal, the closed caption, VBID and format of the video and the audio can be read from the host CPU interface. 2.3.4 Transcode The transcode is a combined multiplexer and de-multiplexer. MPEG2-TS/PS separates into a video stream, two audio streams, and two user data streams. The video stream and the audio stream are multiplexed to MPEG2-TS/PS after transcode on the elementary. PCR, SCR, PTS and DTS are corrected when multiplexing. In the transcode of MPEG2-TS, it can generate partial TS using the data detected by the PID filter and the section filter. Figure 2-6. Transcode MPEG2 Video Bit Rate Conversion Stream MPEG2-TS/PS De-multiplexer MPEG2-TS/PS Multiplexer Audio ES Stream Buffer Audio ES Stream Buffer The change of the MPEG system layer is shown below. MPEG2-TS ⇒ MPEG2-TS MPEG2-TS ⇒ MPEG2-PS MPEG2-PS ⇒ MPEG2-TS MPEG2-PS ⇒ MPEG2-PS MPEG1 ⇒ MPEG1 24 Data Sheet S15082EJ4V0DS Stream µPD61051, 61052 2.4 Stream Interface When it inputs MPEG2-TS, it is able to connect parallel data or serial data with the µPD61051/61052. When it inputs MPEG2-PS, it should connect parallel data with the µPD61051/61052. 2.4.1 Parallel steam data interface This LSI connects to external device by the master mode or the slave mode. When parallel interface, the maximum stream input rate is 100 Mbps, the maximum stream output rate is 30 Mbps. The stream of MPEG encoding and transcode is limited to 15 Mbps on MPEG MP@ML. (1) Stream Input It is possible to receive 4 bytes data after invalid of ISREQ of the stream input. Remark ISSTB and ISCLK are identical pins. Figure 2-7. Parallel Stream Receiving Mode (1/2) (a) Example for Receiving of MPEG2-TS 1 packet (188 bytes) ISVLD ISCLK IS7 to IS0 No received data ISSYNC 1st Valid data Valid data Valid data Valid data Valid data Valid data Valid data Valid data Valid data Valid data No received data Release in a TS packet ISCLK shall be under 13.5 MHz. Data Sheet S15082EJ4V0DS 25 µPD61051, 61052 Figure 2-7. Parallel Stream Receiving Mode (2/2) (b) Example of Receiving MPEG2-PS, ES with Valid and Clock ISREQ It is possible to receive till 4 bytes ISVLD ISCLK IS7 to IS0 No received data Valid data Valid data Valid data Valid data Valid data Valid data No received data No received data Valid data Valid data No No recei- received ved data data Don't care ISSYNC (c) Example of Receiving MPEG2-PS, MPEG2-ES with a Strobe ISREQ It is possible to receive till 4 bytes ISSTB IS7 to IS0 ISSYNC No received data Valid data Valid data Valid data Valid data Valid data Valid data No received data No received data Valid data Valid data No No recei- received ved data data Don't care (2) Stream output There are two modes: valid operation master mode and strobe operation byte transfer mode. The appropriate transfer mode for the system can be selected by setting the two stream output mode and transfer rate. Remark OSSTB and OSRDY are the same pins as OSCLK and OSVLD, respectively. Operation can be selected using combinations of OSSTB and OSRDY or OSCLK and OSVLD. 26 Data Sheet S15082EJ4V0DS µPD61051, 61052 (a) Master Mode Valid This is the MPEG2-TS dedicated output mode. The period of OSCLK can be selected from n times 37 ns (1/27 MHz) (3 ≤ n ≤ 255, n is an integer). If using local decode or input video display, the period is 4 ≤ n ≤ 255 (n is an integer). Figure 2-8. Parallel Stream Transmission Mode ; Transmission of MPEG2-TS (Packet Length is 188 Bytes) (a) Master Mode, Valid 1 packet (188 bytes) OSVLD OSCLK OS7 to OS0 Invalid 1st Valid data Valid data Valid data Valid data Valid data Valid data Valid data Valid data Valid data Valid data Invalid Invalid OSSYNC (b) The Transfer Condition from Reset RESET OSVLD Unsettled OSCLK Unsettled OS7 to OS0 OSSYNC Unsettled (Data does not change) Unsettled The setting of an interface mode The stream preparation completion Data Sheet S15082EJ4V0DS 27 µPD61051, 61052 (b) Bytes Transfer Mode, Strobe In byte transfer mode, the transfer rate is determined by the handshake of OSREQ and OSSTB. Figure 2-9. Parallel Stream Transmission Mode (Transmission of MPEG2-PS, MPEG2-ES) (a) Example for Transmission of Strobe Mode One Byte Transfer OSRDY OSREQ OSSTB OS7 to OS0 OSSYNC (b) The Transfer Condition from Reset RESET OSRDY Unsettiled OSREQ OSSTB OS7 to OS0 OSSYNC Unsettiled Unsettled (Data does not change) Unsettiled The setting of an interface mode The stream preparation completion 28 Data Sheet S15082EJ4V0DS µPD61051, 61052 2.4.2 Serial stream data interface This LSI is able to input a serial stream. Bit rate of serial input is limited less than parallel interface. Serial Stream Interface can transfer only MPEG2-TS stream. Maximum bit rate of stream input is less then 64 Mbps. Bit rate of stream out is 27 Mbps. Additionally, encoding and transcoding bit rate is limited to 15 Mbps on MPEG2 MP@ML. (1) Stream input ISCLK is input by less than 64 MHz clock. Data is MSB first. ISSYNC should active while first byte each packet. If packet error occurred, ISERR should active from ISSYNC of the packet. ISVLD should valid while each byte. ISVLD shall invalid while 8 bits between each packets. Data Sheet S15082EJ4V0DS 29 µPD61051, 61052 Figure 2-10. Serial Stream Input First Byte of TS packet One packet More than 8 ISCLK ISVLD ISCLK MSB Bit6 IS0 Bit1 Bit0 MSB Bit0 Invalid MSB ISSYNC IS1/ISERR ISVLD ISCLK MSB LSB MSB LSB MSB LSB MSB IS0 ISSYNC IS1/ISERR Remark "L" Example for ISVLD, ISSYNC, ISERR active high, ISCLK active high edge 30 Data Sheet S15082EJ4V0DS µPD61051, 61052 (2) Stream Output OSCLK is fixed 27 MHz OSSYNC active at first byte in each packet. OSVLD is active of 1 packet continuously. Data is the MSB first outputs. ISSYNC becomes active among 1 byte at the head of the packet. Figure 2-11. Serial Stream Output First Byte of TS packet One packet More than 8 ISCLK OSVLD OSCLK MSB Bit6 OS0 Bit1 Bit0 MSB Bit0 Invalid MSB OSSYNC OSVLD OSCLK MSB LSB MSB LSB MSB LSB MSB OS0 OSSYNC Remark Example for OSVLD, OSSYNC, OSERR active high Data Sheet S15082EJ4V0DS 31 µPD61051, 61052 2.5 Host CPU Interface The connection of the host CPU can select the eight bits parallel data interface and serial interface (SPI). Internal CPU sends and receives command status through the System Interface Register, which is in the host CPU interface unit. In addition, to control an internal DMA controller through the system interface register, it loads an instruction for internal CPU to the instruction RAM and the transfer of the large-volume data can be sent to the data area on SDRAM. Figure 2-12. Host CPU Interface Instruction RAM of Internal CPU Host CPU Internal CPU System Interface Register DMA Controller SDRAM Interface SDRAM µPD61051/61052 The following describes loading of internal CPU instruction. (1) Parallel interface When parallel interface is selected, host interface has 6-bit address, 8-bit data bus and control ports. CWAIT is selected with CMODE1 to wait on ready signal mode, CMODE1 selects active polarity of CWAIT. (2) Serial interface The µPD61051/61052 communicates with the host CPU using the SPI (serial peripheral interface) serial bus. The host CPU becomes a bus master. The low edge of the chip selection is communication beginning. Its high edge is communication ending. An address and the reading / writing mode are shown at the first byte after the chip selection becomes low. It is the MSB first of six bits of addresses, eight bits of data. Fix CSCLK to high level during CCS is disabled (high level). The µPD61051/61052 becomes a master and downloads the instruction of the internal CPU from external ROM. 32 CSCLK: The serial clock CSDI: The data input CSDO: The data output CCS: The chip selection Data Sheet S15082EJ4V0DS µPD61051, 61052 Figure 2-13. Serial Interface [Data Write] CCS CSCLK CSDI CSDO xx A5 A4 A3 A2 A1 A0 W x D7 D6 D5 D4 D3 D2 D1 D0 x xx [Data Read] CCS CSCLK CSDI CSDO 2.6 xx A5 A4 A3 A2 A1 A0 R x xx x x x x x x x x x D7 D6 D5 D4 D3 D2 D1 D0 SDRAM Interface External memory is SDRAM. It is possible to use the following. Table 2-6. Use Memory Memory Data bus width Quantity Use memory capacity 16 Mbit SDRAM 16 bits 2 32 Mbits 64 Mbit SDRAM 32 bits 1 64 Mbits 64 Mbit SDRAM 16 bits 2 128 Mbits 128 Mbit SDRAM 16 bits 2 128 Mbits 128 Mbit SDRAM 32 bits 1 128 Mbits The µPD61051/61052 preserves the part of the parameter that is necessary to generate the stream, entry video image, a video stream, an audio stream, a stream header, user data, and the instruction of the firmware at this memory. This system uses only CAS latency = 3, burst length = 4. When encode using time base corrector and/or displays local decoding picture, it needs equal to or more than 64 Mbits SDRAM. When PAL encoding, it needs equal to or more than 64 Mbit SDRAM. When transcoding, it needs equal to or more than 64 Mbit SDRAM. Data Sheet S15082EJ4V0DS 33 µPD61051, 61052 2.7 Memory Connection Diagram Each memory connection is as follows. Figure 2-14. Memory Connection Diagram (1/2) (a) 16 Mbit SDRAM by 2 A11 1 Mbits×16 SDRAM A10 to A0 D15 to D0 µPD61051/61052 MA13 MA12 MA11 MA10 to MA0 A11 1 Mbits×16 SDRAM A10 to A0 MD31 to MD16 MD15 to MD0 D15 to D0 Bank A: SDRAM address = 0x xxxx xxxx xxxxB Bank B: SDRAM address = 1x xxxx xxxx xxxxB (b) 64 Mbit SDRAM by 1 µPD61051/61052 MA13 MA12 MA11 MA10 to MA0 A12 A11 2 Mbits×32 SDRAM A10 to A0 MD31 to MD16 D31 to D16 MD15 to MD0 D15 to D0 Bank A: SDRAM address = 00 xxxx xxxx xxxxB Bank B: SDRAM address = 10 xxxx xxxx xxxxB Bank C: SDRAM address = 01 xxxx xxxx xxxxB Bank D: SDRAM address = 11 xxxx xxxx xxxxB 34 Data Sheet S15082EJ4V0DS µPD61051, 61052 Figure 2-14. Memory Connection Diagram (2/2) (c) 64 Mbit SDRAM by 2 or 128 Mbit SDRAM by 2 MA13 4 Mbits×16 SDRAM MA12 MA11 MA10 to MA0 D15 to D0 µPD61051/61052 MA13 MA12 MA11 MA10 to MA0 A13 4 Mbits×16 SDRAM A12 A11 A10 to A0 MD31 to MD16 MD15 to MD0 D15 to D0 Bank A: SDRAM address = 00 xxxx xxxx xxxxB Bank B: SDRAM address = 10 xxxx xxxx xxxxB Bank C: SDRAM address = 01 xxxx xxxx xxxxB Bank D: SDRAM address = 11 xxxx xxxx xxxxB Data Sheet S15082EJ4V0DS 35 µPD61051, 61052 2.8 Memory Map Firmware sets memory map such as video image area and usable work area. Firmware cabinet (temporal buffered area) is the area which firmware does not use. Video Image area size is changed NTSC or PAL. Each area are changed by the firmware. Figure 2-15. Memory Map (1/2) (a) 16 Mbit SDRAM by 2 Firmware Firmware Firmware 00000H Bank A Video Stream Bank B Video Stream Audio Stream User Data 0 Video Image Area Header 7FFFFH (b) Example for 64 Mbit SDRAM by 1 Firmware Firmware Firmware Bank A 00000H Video Stream 0 Bank B Video Stream 0 Bank C Video Stream 1 Audio stream 1 Bank D Video Stream 1 00000H User data 1 Unused Audio stream 0 Video Image Area User data 0 Video Image Area Header Firmware Instruction Pool Instruction Pool Firmware 7FFFFH 36 Usable Work Area Data Sheet S15082EJ4V0DS Usable Work Area 7FFFFH µPD61051, 61052 Figure 2-15. Memory Map (2/2) (c) Example for 64 Mbit SDRAM by 2 or 128 Mbit SDRAM by 2 Firmware 00000H Bank A Bank B Bank C Bank D Video Stream Video Stream Unused Unused 00000H Unused Header Video Image Area Firmware Unused Instruction Pool Video Image Area 80000H Unused Video Stream Video Stream Audio Stream Audio Stream Instruction Pool Firmware Firmware Usable Work Area Usable Work Area User data 0 FFFFFH User data 1 FFFFFH Data Sheet S15082EJ4V0DS 37 µPD61051, 61052 3. SYSTEM INTERFACE REGISTER This LSI corresponds to the various operation modes in exchange instruction of internal CPU from SDRAM to instruction RAM (iRAM). This has 64 byte Registers. They are defined to common registers, interrupt registers and interrupt mask registers. When there is access in the same address from both of the internal CPU and the host CPU, the later data is left at the register. Also, when the writing occurs to the same address at the same time about the common register, the data of the host CPU is left at the register Figure 3-1. System Interface Register Instruction RAM of Internal CPU Host CPU System Interface Register DMA Controller µPD61051/61052 38 Internal CPU Data Sheet S15082EJ4V0DS SDRAM Interface SDRAM µPD61051, 61052 3.1 Register Mapping (General Mapping) Address Bit7 Bit6 Bit5 00H to 1FH 20H Bit4 Bit3 Bit2 Bit1 Bit0 Defined by firmware SI SSD SDI MSD R/W MI 21H R/W SDW SDR SA19 to SA16 R/W Download mode R/W Source address 22H SA15 to SA8 R/W Source address 23H SA7 to SA0 R/W Source address R/W Destination address 24H DA16 25H DA15 to DA8 R/W Destination address 26H DA7 to DA0 R/W Destination address R/W Transfer data count 27H TC18 to TC16 28H TC15 to TC8 R/W Transfer data count 29H TC7 to TC0 R/W Transfer data count iCPU-INT R/W Int. to internal CPU R/W Interrupt mask0 2AH 2BH DMA- DMA- DMA- ERR-M RDY-M DONE-M 2CH Defined by firmware R/W Interrupt mask1 2DH Defined by firmware R/W Interrupt mask2 2EH Defined by firmware R/W Interrupt mask3 2FH Defined by firmware R/W Interrupt mask4 R/W Interrupt0 30H DMA-ERR DMA-RDY DMADONE 31H Defined by firmware R/W Interrupt1 32H Defined by firmware R/W Interrupt2 33H Defined by firmware R/W Interrupt3 34H Defined by firmware R/W Interrupt4 R/W Mask ROM cycle OSVLD R/W Port setup ALL R/W Reset R/W Transfer data 35H iROM2 to iROM0 36H ISREQ 37H to 3DH 3EH NBR RESET 3FH TD7 to TD0 Data Sheet S15082EJ4V0DS 39 µPD61051, 61052 3.2 Register Functions 3.2.1 Common register Address Bit7 Bit6 Bit5 00H to 1FH Bit4 Bit3 Bit2 Bit1 Bit0 Defined by firmware R/W R/W Each firmware defines these registers. These registers are used to communicate with host CPU and internal CPU. For the details of the register, refer to the application notebook. The reset of the RESET pin or ALL RESET of the reset register initializes addresses 00H and 01H addresses to 0H. The original value of the other register is unsettled. It keeps a setting value before reset. 3.2.2 Data transfer register These registers are defined data transfer such as host CPU → SDRAM, SDRAM → host CPU, host CPU → iRAM of internal CPU, SDRAM → iRAM of internal CPU and instruction ROM → iRAM of internal CPU. The host CPU transfers with SDRAM via had a transfer buffer of 128 bytes on this LSI. The transfer with the instruction RAM becomes 4 bytes. A transfer error occurs if the transfer mode register, source address register, destination address register, or transfer counter register is changed before releasing the transfer mode register following transfer completion after setting the transfer mode register and starting the transfer. When transferring data as follows: host CPU → instruction RAM of internal CPU, host CPU → SDRAM, SDRAM → instruction RAM of internal CPU, instruction ROM → SDRAM, instruction ROM → instruction RAM of internal CPU, execute a software reset of the internal CPU (address 3EH ← 02H) before transfer and release the reset after transfer. 40 Data Sheet S15082EJ4V0DS µPD61051, 61052 (1) Data transfer register Address 20H Bit7 Bit6 Bit5 Bit4 Bit3 SI SSD SDI MSD MI Bit 7 Field SI Bit2 SSD SDI MSD MI 1 SDW R/W Download mode Initial value 0 Note 0 Note 0 Note Instruction ROM→SDRAM 0 Note Instruction ROM→instruction RAM of internal CPU 0: Releasing of transfer, 1: Transfer 2 SDR SDRAM→instruction RAM of internal CPU 0: Releasing of transfer, 1: Transfer 3 SDW Host CPU→SDRAM 0: Releasing of transfer, 1: Transfer 4 R/W Host CPU→instruction RAM of internal CPU 0: Releasing of transfer, 1: Transfer 5 Bit0 Function 0: Releasing of transfer, 1: Transfer 6 Bit1 0 Note Reserved (set only 0) 0 Host CPU→SDRAM 0 0: Releasing of transfer,1: Transfer 0 SDR SDRAM→host CPU 0 0: Releasing of transfer, 1: Transfer Note Set internal CPU reset (with Register 3EH←02H) More than one bit cannot be set to 1 at the same time. It becomes a transfer error when writing at the transfer mode register while transferring. When canceling a transfer while transferring, it stops a transfer. At this time, the data in the transfer buffer becomes invalid. The transfer of SDR with once is to a maximum of 128 bytes. If host CPU stops the transfer, host CPU should operate transfer error handling. Data Sheet S15082EJ4V0DS 41 µPD61051, 61052 (2) Source address register Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 21H Bit1 Bit0 SA19 to SA16 R/W R/W Source address 22H SA15 to SA8 R/W Source address 23H SA7 to SA0 R/W Source address It sets the address of the data to transfer. It becomes effective in case of transfer from SDRAM or instruction ROM. Until it releases a transfer mode after setting a transfer mode register, it isn't possible to change. The transfer error occurs when rewriting this register before releasing a transfer mode. The relation with the address of SDRAM, external instruction ROM is shown in Figure 3-2 and 3-3. The addressing of SDRAM becomes a 32 address by 4-word unit (128 bytes). The relation with the SDRAM bank and address is shown in Table 3-1. SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 Host CPU interface register 21H to 23H A21 A20 A19 A18 A17 A16 Figure 3-2. Relation of Source Address and SDRAM Address 0 0 0 0 SDRAM address 0 0 0 0 0 The µPD61051/61052 adds 0 automatically Bank select SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 FA7 FA6 FA5 FA4 FA3 FA2 FA1 FA0 Extemal instruction ROM address FA15 FA14 FA13 FA12 FA11 FA10 FA9 FA8 0 0 0 0 SA19 SA18 SA17 SA16 Host CPU interface register 21H to 23H FA19 FA18 FA17 FA16 Figure 3-3. Relation of Source Address and External Instruction ROM Address Table 3-1. Relation of SDRAM Bank and Address Memory Bank A Bank B Bank C Bank D 16 Mbit SDRAM by 2 000000H to 07FFFFH 200000H to 27FFFFH - - 16 Mbit SDRAM by 1 000000H to 07FFFFH 200000H to 27FFFFH 100000H to 17FFFFH 300000H to 37FFFFH 64 Mbit SDRAM by 2 000000H to 0FFFFFH 200000H to 2FFFFFH 100000H to 1FFFFFH 300000H to 3FFFFFH 000000H to 0FFFFFH 200000H to 2FFFFFH 100000H to 1FFFFFH 300000H to 3FFFFFH 128 Mbit SDRAM by 1 128 Mbit SDRAM by 2 128 Mbit SDRAM by 1 42 Data Sheet S15082EJ4V0DS µPD61051, 61052 (3) Destination address register Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 24H Bit0 R/W DA16 R/W Destination address 25H DA15 to DA8 R/W Destination address 26H DA7 to DA0 R/W Destination address It sets Destination address. It becomes effective in case of transfer to SDRAM or instruction RAM of internal CPU. It isn't possible to change until it cancels a transfer mode after setting a transfer mode register. It becomes a transfer error when rewriting before canceling a transfer mode. The relation of the address of SDRAM and instruction RAM of internal CPU is as in Figure 3-4 and 3-5. The addressing of SDRAM becomes a 32 address by 4-word unit (128 bytes). DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 SDRAM address DA16 Host CPU interface register 24H to 26H A21 A20 A19 A18 A17 A16 Figure 3-4. Relation of Destination Address and SDRAM Address 0 0 0 0 0 0 0 Bank select 0 0 0 0 0 The µPD61051/61052 adds 0 automatically DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Instruction RAM address of intemal CPU 0 0 0 0 0 0 0 DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8 Host CPU interface register 24H to 26H DA16 Figure 3-5. Relation of Destination Address and Instruction ROM Address of Internal CPU Data Sheet S15082EJ4V0DS 43 µPD61051, 61052 (4) Transfer data counter register Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 27H Bit1 Bit0 TC18 to TC16 R/W R/W Transfer data count 28H TC15 to TC8 R/W Transfer data count 29H TC7 to TC0 R/W Transfer data count It sets the transfer data number of the bytes. In case of transfer between host CPU and SDRAM, it sets the number of the transfer bytes by 4 bytes unit. In case of transfer from instructions ROM, SDRAM host CPU to the instruction RAM of internal CPU, it sets the number of the transfer bytes /4 by the 4 byte unit. (5) Transfer data register Address Bit7 Bit6 Bit5 Bit4 3FH Bit3 Bit2 Bit1 Bit0 TD7 to TD0 R/W R/W Transfer data This register is transfer data window. Figure 3-6. SDRAM Write SDRAM address = DA16 to DA0×128 SDRAM address = DA16 to DA0×128+5 Byte2 Byte6 Byte10 Byte14 Byte18 Byte3 Byte7 Byte11 Byte15 Byte19 Transfer buffer (128 bytes) Byte0 Byte1 Byte2 Byte3 Byte4 Byte5 Byte6 Byte7 Byte8 Byte1 Byte5 Byte9 Byte13 Byte17 Lower byte first TD7 to TD0 Host CPU write 44 Data Sheet S15082EJ4V0DS Byte0 Byte4 Byte8 Byte12 Byte16 SDRAM µPD61051, 61052 SDRAM read <1> Interrupt mask Host CPU sets mask bit to interrupt mask register (2CH to 2FH) for the interrupt that needs a data transfer. <2> Set source address Host CPU sets the address of SDRAM to the source address register (21H to 23H) of the µPD61051/61052. <3> Set the number (equal to or less than 128 bytes) of the data to read by 4 bytes unit Host CPU sets the data number of the bytes to the transfer data counter register (27H to 29H) of the µPD61051/61052. <4> Set the transfer of SDRAM → host CPU. Host CPU sets 01H to the transfer mode register (20H) of the µPD61051/61052. <5> CINT interrupt (Interrupt pin) <6> Confirms that the interrupt factor and clear interrupt factor Host CPU confirms that the interrupt register 0 (30H) of the µPD61051/61052 becomes 02H or 01H and clears writing a same value of the interrupt register 0 (30H) to the interrupt register 0 (30H) of the µPD61051/61052. <7> Data read Host CPU reads data from the number of times with the set number of bytes, the transfer data register (3FH) of the µPD61051/61052. <8> CINT interrupt (Interrupt pin) <9> Confirm the interrupt factor Host CPU confirms that the interrupt register 0 (30H) of the µPD61051/61052 becomes 01H. (It clears a writing interrupt factor in 01H at the interrupt register 0 (30H) register of the µPD61051/61052.) <10> Release of SDRAM → host CPU mode Host CPU clears a writing interrupt factor in 01H at the interrupt register 0 (30H) register of the µPD61051/61052 after setting 00H to the transfer mode register (20H) of the µPD61051/61052. <11> Release of interrupt mask It releases the limitation on interrupt which set by <1>. Data Sheet S15082EJ4V0DS 45 µPD61051, 61052 SDRAM write <1> Interrupt mask Host CPU sets mask bit to interrupt mask register (2CH to 2FH) for the interrupt that needs a data transfer. <2> Set destination address Host CPU sets the address of SDRAM to the destination address register (24H to 26H) of the µPD61051/61052. <3> Set the number of the data to write by a 4 byte unit Host CPU sets the data number of the bytes by 4 bytes unit to the transfer data counter register (27H to 29H) of the µPD61051/61052. <4> Set the transfer of host CPU → SDRAM Host CPU sets 02H to the transfer mode register (20H) of the µPD61051/61052. <5> Data write Host CPU writes data to the transfer data register (3FH) of the µPD61051/61052 at times with more few 128 bytes or transfer data count register setting value. <6> CINT interrupt (Interrupt pin) <7> Confirm the interrupt factor When the number of the transfer data is less then 128 bytes, host CPU confirms that the interrupt register 0 (30H) of the µPD61051/61052 becomes 01H, and go to <9>. <8> Confirm that next data transfer prepare completed Host CPU confirms that the interrupt register 0 (30H) of the µPD61051/61052 becomes 02H or 01H and clears a writing sane value of the interrupt register 0 (30H) to the interrupt register 0 (30H) of the µPD61051/61052. Return to <5> and next data write. <9> Release of SDRAM → host CPU Host CPU clears a writing interrupt factor in 01H at the interrupt register 0 (30H) register of the µPD61051/61052 after setting 00H to the transfer mode register (20H) of the µPD61051/61052. <10> Release of interrupt mask It releases the limitation on interrupt which is set by <1>. <11> In the case of an interrupt to internal CPU, it is necessary Host CPU sets a data bank number and the number of the bytes to the address that defined with the firmware. It sets 01H to the 2AH address of the µPD61051/61052 and it notifies an interrupt to internal CPU. 46 Data Sheet S15082EJ4V0DS µPD61051, 61052 3.2.3 Internal CPU interrupt register Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 2AH Bit0 R/W iCPU-INT R/W Int. to internal CPU Host CPU set interrupt to internal CPU. Internal CPU clears this bit after interrupt operation. The reset of the RESET pin or ALL RESET of the reset register initializes this address to 0H. 3.2.4 Interrupt mask register Address Bit7 Bit6 Bit5 Bit4 Bit3 2BH Bit2 Bit1 Bit0 R/W DMA-ERR DMA-RDY DMA-DON -M -M R/W Interrupt mask0 E-M 2CH Defined by firmware R/W Interrupt mask1 2DH Defined by firmware R/W Interrupt mask2 2EH Defined by firmware R/W Interrupt mask3 2FH Defined by firmware R/W Interrupt mask4 These registers are interrupt masks for next interrupt. Interrupt mask can be set bit by bit. When setting an interrupt mask, CINT does not become high even if the interrupt register becomes 1. The reset of the RESET pin or ALL RESET of the reset register initializes this address to 0H. 3.2.5 Download interrupt register Address Bit7 Bit6 Bit5 Bit4 Bit3 30H Bit2 Bit1 Bit0 R/W DMA-ERR DMA-RDY DMA-DON R/W Interrupt0 E It is set for 1 when the interrupt factor occurs. The interrupt bit clears when host CPU writes to this register after the interrupt processing. The reset of the RESET pin or ALL RESET of the reset register initializes this address to 0H. Clear processing continues until interrupt registers is cleared. Bit Field 7 to 3 2 Function Initial value Reserved (set 0) DMA-ERR Data transfer error 0 0: Normal, 1: Error 1 DMA-RDY Data transfer prepared 0 0: Normal, 1: Transfer 0 DMA-DONE Data transfer ended 0 0: Normal, 1: Transfer ended It outputs DMA-RDY or DMA-DONE every 128-byte transfer. DMA-DONE is output when the transfer ends. Data Sheet S15082EJ4V0DS 47 µPD61051, 61052 3.2.6 Interrupt register Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 R/W 31H Defined by firmware R/W Interrupt1 32H Defined by firmware R/W Interrupt2 33H Defined by firmware R/W Interrupt3 34H Defined by firmware R/W Interrupt4 It is set for 1 when the interrupt factor occurs. The interrupt bit clears when host CPU writes 1 in the bit of the interrupt after the interrupt processing. When the other interrupt (which isn't masked) is set to 1 when clearing a interrupt, CINT becomes high 1 µs later. The reset of the RESET pin or ALL RESET of the reset register initializes this address to 0H. Clear processing continues until interrupt registers is cleared. Address Bit 31H to Field 7 to 0 Initial value Firmware define 34H 3.2.7 Function 0H 0: Normal, 1: Interrupt Reset register Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 3EH Bit1 NBR Bit0 R/W ALL R/W Reset RESET When the host CPU sets 1 to ALL RESET, it resets the inside and it returns to 0 automatically. The reset of the RESET pin or ALL RESET of the reset register initializes this address to 0H. Bit Field 7 to 2 1 Function Initial value Reserved (Set 0) NBR Internal CPU reset 0 0: Normal, 1: Reset 0 ALL RESET Same hardware reset 0: Normal, 1: Reset 48 Data Sheet S15082EJ4V0DS 0 µPD61051, 61052 3.2.8 ROM access cycle register Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 35H Bit1 Bit0 iROM2 to iROM0 R/W R/W Mask ROM cycle It specifies the access cycle of the instruction ROM of internal CPU when connecting host CPU interface with the serial bus. The reset of the RESET pin or ALL RESET of the reset register initializes this address to 7H. Bit Field Function 7 to 3 2 to 0 Reserved (Set 0) iROM2 to Access cycle of instruction ROM iROM0 3.2.9 Initial value 7H 0: Reserved, 1 to 7: (Setting value+2) by 24.6 MHz Port setup register Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 36H Bit1 Bit0 R/W ISREQ OSVLD R/W Port setup This register sets the active polarity of ISREQ and OSVLD. The reset of the RESET pin or ALL RESET of the reset register initializes this address to 0H. Bit Field 7 to 2 1 Function Initial value Reserved (Set 0) ISREQ Active polarity of ISREQ 0 0: Low active of request, 1: High active of request 0 OSVLD Active polarity of OSVLD/OSRDY 0 0: Low active of valid/ready 1: High active of valid/ready Data Sheet S15082EJ4V0DS 49 µPD61051, 61052 4. SYSTEM INTERFACE PROCEDURE The host CPU transfers the firmware of each operation mode to the instruction RAM of the internal CPU and works it. This LSI stores up firmware in SDRAM. Host CPU sets to load the firmware of each operation mode in the instruction RAM of internal CPU from SDRAM. When using a parallel bus interface for the host CPU interface, the host CPU sets a data transfer register after hardware reset and transfers the initialization program of SDRAM to instruction RAM of internal CPU and executing. Host CPU writes firmware to SDRAM. When using a serial bus interface for the host CPU interface, the host CPU sets a data transfer register after hardware ware reset and transfers the initialization program of SDRAM to instruction RAM of internal CPU from external instruction ROM and executing. Host CPU loads firmware in SDRAM from instruction ROM outside. It stores the firmware of the encoding and the transcode to SDRAM from ROM in case of start-up of the system, and then it can do the changing of a feature at short time by the high-speed transfer of SDRAM. The host CPU sets the mode of the terminal of the µPD61051/61052 and the access cycle of ROM to the system interface register after hardware reset and sets the transfer of the instruction of the internal CPU after SDRAM is initialized. 50 Data Sheet S15082EJ4V0DS µPD61051, 61052 4.1 Outline An overview from the reset of the hardware to the setting of an operation mode is shown. Initialization Hardware reset SDRAM initialization Note Software reset of internal CPU Reset address (3EH)← 02H Instruction download Internal CPU software reset Mode setting Software reset of internal CPU Reset address (3EH) ←02H Internal CPU start-up Reset address (3EH) ←00H Y Mode change N Operation continuation Note This is not necessary in case that the SDRAM initialization firmware is not separated. Data Sheet S15082EJ4V0DS 51 µPD61051, 61052 4.2 Firmware Download The host CPU downloads the firmware at the instruction RAM for the internal CPU. When a host CPU is connected with the serial bus, the firmware can be downloaded from the external ROM for the download processing to speed up. In addition, it stores more than one piece of firmware in the instruction pool area of SDRAM and it can be replaced depending on the need, too. When transferring to the instruction RAM of the internal CPU, the transfer counter register setting value (number of the transfer bytes / 4) is (program size +3)/ 4. 4.2.1 Host CPU to instruction RAM of internal CPU Host CPU transmits the firmware to instruction RAM of the internal CPU. When transferring data continuously, transfer during resetting an internal CPU, If reset of internal CPU is can canceled on the way, the internal CPU sometime malfunction. Host CPU to instruction RAM of internal CPU Internal CPU reset Reset register (3EH) ← 02H setting Destination address register (24H to 26H) setting (Program size + 3)/4 Transfer counter register (27H to 29H) setting Host CPU→iRAM transfer Transfer mode register (20H)←80H setting Transfer data register (3FH) ←Instruction All instruction written ? N Y Transfer ending (refer to 4.7) Internal CPU reset is canceled Reset register (3EH)←00H setting Return 52 Data Sheet S15082EJ4V0DS µPD61051, 61052 4.2.2 External ROM to instruction RAM of internal CPU When the host CPU is a serial bus type, CPU transmits the instruction of a mode from external ROM to instruction RAM of Internal CPU. When transferring data continuously, transfer during resetting an internal CPU, If reset of internal CPU is can canceled on the way, the internal CPU sometime malfunction. External ROM to instruction RAM of internal CPU Internal CPU reset Reset register (3EH) ←02H setting ROM access cycle register (35H) setting Source address register (21H to 23H) setting Destination address register (24H to 26H) setting (Program size + 3)/4 Transfer counter register (27H to 29H) setting iROM→iRAM transfer Transfer mode register (20H)←80H setting Transfer ending (refer to 4.7) Internal CPU reset is canceled Reset register (3EH)←00H setting Return Data Sheet S15082EJ4V0DS 53 µPD61051, 61052 4.2.3 Host CPU to SDRAM The host CPU can store firmware in the instruction pool area of SDRAM for the internal CPU. It stores more than one piece of firmware and it can be replaced depending on the need, too. When transferring data continuously, transfer during resetting an internal CPU, If reset of internal CPU is can canceled on the way, the internal CPU sometime malfunction. The number of the transfer bytes is a 4-byte unit. Instruction download Internal CPU reset Reset register (3EH) ←02H setting Destination address register (24H to 26H) setting Number of transefer bytes Transfer counter register (27H to 29H) setting Host CPU→SDRAM transfer Transfer mode register (20H) ← 40H setting Transfer data register (3FH) ← Instruction Y All instruction writing ending? Transfer ending (refer to 4.7) N Internal CPU reset is canceled Reset register (3EH)←00H setting N 128 bytes writing ending? Return Y N CINT? Y Interrupt register 0 (30H): (02H or 01H) N N Interrupt register 0 (30H): 04H Y Y Interrupt register 0 clear Interrupt register 0 (30H)← Interrupt register 0 (30H) Transfer error handling (refer to 4.8) Return 54 Data Sheet S15082EJ4V0DS µPD61051, 61052 4.2.4 External ROM to SDRAM The firmware for the internal CPU can be stored in the firmware cabinet of SDRAM from the external ROM. It stores more than one piece of firmware beforehand and it can be replaced according to need, too. When transferring data continuously, transfer during resetting an internal CPU, If reset of internal CPU is can canceled on the way, the internal CPU sometime malfunction. When transferring data below the 1k-byte, transfer, dividing every 128 bytes. The number of the transfer bytes is a 4-byte unit. (a) Transfer over 1 Kbytes (b) Transfer below 128 bytes Instruction download (Serial bus) Instruction download (Serial bus) Internal CPU reset Reset register (3EH) ← 02H setting Internal CPU reset Reset register (3EH) ← 02H setting Source address register (21H to 23H) setting Source address register (21H to 23H) setting Destination address register (24H to 26H) setting Destination address register (24H to 26H) setting Number of transfer bytes /4 Transfer counter register (27H to 29H) setting Number of transfer bytes /4 Transfer counter register (27H to 29H) setting Interrupt mask0 (2BH) ← 03H setting iROM → SDRAM transfer Transfer mode register (20H) ←10H setting iROM→SDRAM transfer Transfer mode register (20H) ← 10H setting After 70 µsec Clear mask transfer interrupt Interrupt mask0 (2BH) ← 00H Transfer ending (refer to 4.7) Internal CPU reset is canceled Reset register (3EH)←00H setting Return Transfer ending (refer to 4.7) Internal CPU reset is canceled Reset register (3EH)←00H setting Return Data Sheet S15082EJ4V0DS 55 µPD61051, 61052 4.3 SDRAM Write during Executing While encoding, the host CPU can transfer parameters to the internal CPU through SDRAM. The number of the transfer bytes is a 4-byte unit. SDRAM writing, during executing Mask Interrupt which requests data transfer Interrupt mask register (2CH to 2FH) setting Destination address register (24H to 26H) setting Number of transfer bytes Transfer counter register (27H to 29H) setting Host CPU → SDRAM transfer Transfer mode register (20H) ← 02H setting Transfer data register (3FH) ← Data All data writing ending? Y N N Transfer ending (refer to 4.7) 128 bytes writing ending? Clear mask Interrupt which requests data transfer Interrupt mask register (2CH to 2FH) setting Y Return CINT? N Y Interrupt register 0 (30H): (02H or 01H) N N Interrupt register 0 (30H): 04H Y Y Interrupt register 0 clear Interrupt register 0 (30H)← Interrupt register 0 (30H) Transfer error handling (refer to 4.8) Clear mask Interrupt which requests data transfer Interrupt mask register (2CH to 2FH) setting Return 56 Data Sheet S15082EJ4V0DS µPD61051, 61052 4.4 SDRAM Read during Executing While encoding, the host CPU reads parameters of usable work area of SDRAM. The maximum data of the reading once is 128 bytes. When reading is equal to or more than 128 byte data, execute reading processing repeatedly. The number of the transfer bytes is a 4 bytes unit. SDRAM reading, during executing Mask Interrupt which requests data transfer Interrupt mask register (2CH to 2FH) settin Source address register (21H to 23H) setting Number of transfer bytes Transfer counter register (27H to 29H) setting SDRAM → host CPU transfer Transfer mode register (20H) ← 01H setting N CINT? Interrupt register 0 clear Interrupt register 0 (30H)← Interrupt register 0 (30H) Y Interrupt register 0 (30H): (02H or 01H) Y Transfer data register (3FH)→Read data N N Interrupt register 0 (30H): 04H All instructions reading ending? Y N Y Transfer error handling (refer to 4.8) Transfer ending (refer to 4.7) Clear mask Interrupt which requests data transfer Interrupt mask register (2CH to 2FH) setting Clear mask Interrupt which requests data transfer Interrupt mask register (2CH to 2FH) setting Return Return Data Sheet S15082EJ4V0DS 57 µPD61051, 61052 4.5 SDRAM Initialization The host CPU transfers the firmware which makes SDRAM a standby condition to the instruction RAM of the internal CPU and executes it. SDRAM initialization SDRAM initialize firmware to instruction RAM of internal CPU 100 µs wait Release of software reset of internal CPU Reset register (3EH)← 00H N CINT? Y Interrupt register x initialization ending N Y Interrupt register x Initialization ending interrupt release Return 58 Data Sheet S15082EJ4V0DS µPD61051, 61052 4.6 Operation Mode Setting by Changing Firmware When changing a mode, host CPU transfers the instruction of each mode from SDRAM to the instruction RAM of the internal CPU and restarts. Parameter setting Mode setting System interface register setting Software reset of internal CPU Reset register (3EH) ← 02H Mode setting A Source address register (21H to 23H) setting Destination address register (24H to 26H) setting Destination address register (24H to 26H) setting Number of transfer bytes Transfer counter register (27H to 29H) setting Number of transfer bytes/4 Transfer counter register (27H to 29H) setting Host CPU → SDRAM transfer Transfer mode register (20H) ← 40H setting SDRAM → iRAM transfer Transfer mode register (20H) ← 20H setting Transfer ending (refer to 4.7) Transfer data register (3FH) ← Parameter Internal CPU reset is canceled Reset register (3EH)←00H setting All parameters writing ending? Y N Transfer ending (refer to 4.7) Parameter setting Return N All parameters in SDRAM writing ending? 128 bytes writing ending? Y N Y Return Mode setting A CINT? N Y Interrupt register 0 (30H): (02H or 01H) N Y Interrupt register 0 clear Interrupt register 0 (30H)← Interrupt register 0 (30H) Interrupt register 0 (30H): 04H N Y Transfer error handling (refer to 4.8) Return Data Sheet S15082EJ4V0DS 59 µPD61051, 61052 4.7 Transfer Ending The host CPU confirms a transfer error when the instruction or data transfer ends. The host CPU clears transfer mode and interrupt registers. Transfer ending N CINT? Y N Interrupt register 0 (30H): 01H Y N Transfer mode register (20H) ← 00H setting Interrupt register 0 (30H): 04H Y Interrupt register 0 clear Interrupt register 0 (30H) ← 01H Transfer error handling (refer to 4.8) Return 60 Data Sheet S15082EJ4V0DS µPD61051, 61052 4.8 Transfer Error Handling 4.8.1 Transfer error handling 1 It is the error handling of DMA-ERR which occurs when interrupting the transfers (the host CPU → the instruction RAM of internal CPU transfer, the host CPU → SDRAM transfer (SSD, SDW), the external ROM → SDRAM transfer and the external ROM → the instruction RAM of internal CPU transfer) Transfer error handling 1 Set destination address register (24H to 26H) to unused area of SDRAM Transfer counter register (27H to 29H) ← 04H setting Host CPU → SDRAM transfer Transfer mode register (20H) ← 02H setting Clear the transfer error Interrupt register 0 (30H) ← 04H setting Transfer data register (3FH) ← Dummy data All data writing ending? N Y CINT? N Y Interrupt register 0 (30H): 01H N Y Host CPU → SDRAM transfer release Transfer mode register (20H) ← 00H setting Interrupt register 0 (30H) ← 01H setting Return Data Sheet S15082EJ4V0DS 61 µPD61051, 61052 4.8.2 Transfer error handling 2 This is a error handling of DMA-ERR which occurs when interrupting the transfers (SDRAM read during executing and SDRAM → instruction RAM of internal CPU transfer) Transfer error handling 2 Destination address register (24H to 26H) ← Unusing area setting SDRAM→ host CPU transfer Transfer mode register (20H) ← 01H setting Transfer counter register (27H to 29H) ← 04H setting CINT? Host CPU → SDRAM transfer Transfer mode register (20H) ← 02H setting Destination address register (24H to 26H) ← Unusing area setting Y Interrupt register 0 (30H): 02 H Clear transfer error Interrupt register 0 (30H) ← 04H setting N Transfer counter register (27H to 29H) ← 04H setting Y Transfer data register (3FH) ← Dummy data All data writing ending? N N Clear Interrupt register 0 Interrupt register 0 (30H)← Interrupt register 0 (30H) setting Host CPU → SDRAM transfer Transfer mode register (20H) ← 02H setting Transfer data register (3FH) → Data read Transfer data register (3FH) ← Dummy data Y Host CPU → SDRAM transfer release Transfer mode register (20H) ← 00H setting All data reading ending? N Y Transfer counter register (27H to 29H) ← 04H setting CINT? N CINT? N Y N Y Interrupt register 0 (30H): 01H Y Interrupt register 0 (30H) ← 01H setting Interrupt register 0 (30H) ← 01H setting SDRAM → host CPU transfer release Transfer mode register (20H) ← 00H setting Host CPU → SDRAM transfer release Transfer mode register (20H) ← 00H setting Return 62 N Y Y Interrupt register 0 (30H): 01H All data writing ending? Data Sheet S15082EJ4V0DS N µPD61051, 61052 4.8.3 Transfer error handling 3 It is the error handling of DMA-ERR which occurs when transfer operation in case of host CPU serial connection with SPI. Transfer error handling 3 SDRAM → host CPU transfer Transfer mode register (20H) ← 01H setting Transfer counter register (27H to 29H) ← 01H setting SDRAM → host CPU transfer Transfer mode register (20H) ← 01H setting CINT? Transfer data register (3FH) → Data read N Y SDRAM → host CPU transfer release Transfer mode register (20H) ← 00H setting Interrupt register 0 (30H): 02H Y N CINT? N Interrupt register 0 (30H) ← 02H setting Transfer data register (3FH) → Data read Y N Interrupt register 0 (30H): 01H Transfer data register (3FH) → Data read Y Transfer data register (3FH) → Data read Interrupt register 0 (30H) ← 01H setting Source address register (21H to 23H) setting CINT? N Y Transfer counter register (27H to 29H) → 03H setting Interrupt register 0 (30H): 01H N Y SDRAM → host CPU transfer release Transfer mode register (20H) ← 00H setting Interrupt register 0 (30H) ← 01H Return Data Sheet S15082EJ4V0DS 63 µPD61051, 61052 5. EXAMPLE FOR COMMON REGISTER USAGE The µPD61051, 61052 operates while the “command code register” is in “start”. When “command code register” becomes “start”, internal CPU reads parameter registers, then starts the operation. Additionally, internal register sets “status register”. Register map for system interface register is defined by firmware. With each application, parameter registers are changed by the firmware. Figure 5-1. Host Interface Register Instruction RAM of Internal CPU Host CPU System Interface Register DMA Controller µPD61051/61052 64 Internal CPU Data Sheet S15082EJ4V0DS SDRAM Interface SDRAM µPD61051, 61052 5.1 Register Map Example Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 00H COMCODE 01H ESTS 02H to 1FH 20H Bit0 Parameters (Defined by each firmware) SI SSD SDI MSD MI SDW 21H SDR SA19 to SA16 22H SA15 to SA8 23H SA7 to SA0 24H DA16 25H DA15 to DA8 26H DA7 to DA0 27H TC18 to TC16 28H TC15 to TC8 29H TC7 to TC0 2AH iCPU-INT 2BH 2CH to 2FH DMA- DMA- DMA- ERR-M RDY-M DONE-M Interrupt Mask (Defined by each firmware) 30H DMA-ERR DMA-RDY DMADONE 31H to 34H Interrupt (Defined by each firmware) 35H iROM2 to iROM0 36H ISREQ OSVLD 37H to 3DH 3EH NBR ALL RESET 3FH TD7 to TD0 : Reserved Data Sheet S15082EJ4V0DS 65 µPD61051, 61052 5.2 Example of the Common Register Which A Firmware Defines 5.2.1 Address COMCODE: Command code register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 00H Bit1 Bit0 COMCODE The host CPU can change the state of operation to the command code register. The µPD61051/61052 accepts commands to operate in three states as shown in the table below. Command Code Standby / Stop 001 Start 011 Reserved Others The command which it is possible to set depend on the internal state. In case of the command whose state transfer is possible, the state transfers according to the command. 5.2.2 Address ESTS: Status register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 01H Bit1 Bit0 ESTS This register shows processing state, when command is illegal, the state doesn’t transfer. ESTS 66 Code Initial State 000 Standby State 001 Encoding State 011 Data Sheet S15082EJ4V0DS µPD61051, 61052 Figure 5-2. Command Status Transition Hardware reset Initial State (000) 001 : Standby Standby State (001) 001 : Stop 011 : Start Encoding State (011) Valid Command in Initial State: Standby Valid Command in Standby State: Start Valid Command in Operation State: Stop Data Sheet S15082EJ4V0DS 67 µPD61051, 61052 6. ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (TA = 25°C) Parameter Supply Voltage Symbol Conditions Rating Unit VDD3 VDD3, vs GND 4.6 V VDD2 VDD2, vs GND 3.6 V PVDD2, vs PGND Input Voltage VIN Vs GND3 −0.5 to +4.6 V Output Voltage VOUT Vs GND3 −0.5 to +4.6 V Output Current IOUT 20 mA Permissible Loss PD 2 W Operating Ambient TA 0 to +70 °C Tstg −55 to +125 °C Temperature Storage Temperature Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. The absolute maximum ratings are values that may physically damage the products. Be sure to use the products within the ratings. DC Characteristics (TA = 0 to +70°C, VDD3 = 3.3±0.165 V, VDD2 = 2.5±0.2 V) Parameter Supply voltage Symbol Condition Min. Typ. Max. Unit VDD3 VDD3, vs GND 3.135 3.3 3.465 V VDD2 VDD2, vs GND 2.3 2.5 2.7 V 2.2 VDD3+0.5 V SCLK −0.5 +0.6 V Except SCLK −0.5 +0.7 V PVDD2, vs PGND High-level input voltage VIH Low-level input voltage VIL High-level output voltage VOH Low-level output voltage VOL Input leakage current ILI 2.4 Except MD31 to MD0 and V 0.4 V ±10 µA CMODE1 Operating current IDD3 3.3 V power supply 70 mA IPDD 2.5 V PLL power supply 15 mA Internal logic power supply of 510 mA IDD2 2.5 V 68 Data Sheet S15082EJ4V0DS µPD61051, 61052 Pin Capacitance (TA = 25°C) Parameter Symbol Conditions Min. Typ. Max. Unit Input capacitance CI 20 pF Output capacitance CO 20 pF I/O capacitance CIO 20 pF AC Characteristics (TA = 0 to +70°C, VDD3 = 3.3±0.165 V, VDD2 = 2.5±0.2 V, CL = 15 pF, tR = tF = 1 ns) (1) System Parameter Symbol Conditions Min. Typ. Max. 27.0 Unit SCLK frequency fSCK MHz SCLK high-level width tSCKH Duty 40:60 13.2 ns SCLK low-level width tSCKL Duty 40:60 13.2 ns PSTOP release time1 tSTP1 Vs VDD3 1 µs PSTOP release time2 tSTP2 Vs VDD2 1 µs PSTOP release time3 tSTP3 Vs PVDD2 1 µs PSTOP release time4 tSTP4 Vs SCLK 1 µs PSTOP pulse width tWSTP 1 µs RESET release time tRES Vs falling edge of PSTOP 100 µs Video input reset time tlVRES After stable IVCLK 600 ns Audio reset time tAURES After stable AMCLK 600 ns STC reset time tSTRES After stable STCLK 600 ns Reset pulse width tRESW After stable all clock 600 ns Input rising time tIR Vs AMCLK, STCLK, SCLK, 3 ns Vs IVCLK 5 ns Vs AMCLK, STCLK, SCLK, 3 ns 5 ns ISCLK Input falling time tIF ISCLK Vs IVCLK Output rising time tOR 3 ns Output falling time tOF 3 ns High level, low level Clock input VIH VIH tIR, tOR VIL tSCKH tIF, tOF VIL tSCKL tSCK = 1/fSCK Data Sheet S15082EJ4V0DS 69 µPD61051, 61052 Reset input VDD3 tSTP1 VDD2 tSTP2 PVDD2 tSTP3 Frequency stabilization (±10% max. ) SCLK tSTP4 PSTOP tWSTP tRES RESET Caution Notes on power on/off • Apply power to VDD3, and VDD2 and PVDD2 at the same time. • If it is difficult to apply the power to these pins at the same time, apply the power to VDD2 and PVDD2 first. • Cut the power of VDD3, and VDD2 and PVDD2 at the same time. • If it is difficult to cut the power of these pins at the same time, cut the power of VDD2 and PVDD2 last. 70 Data Sheet S15082EJ4V0DS µPD61051, 61052 IVCLK tIVRES AMCLK tAURES STCLK tSTRES SCLK tSTP4 PSTOP tWSTP tRES RESET Data Sheet S15082EJ4V0DS 71 µPD61051, 61052 IVCLK tIVRES AMCLK tAURES STCLK tSTRES SCLK PSTOP ''L'' tRESW RESET 72 Data Sheet S15082EJ4V0DS µPD61051, 61052 (2) Video input interface Parameter Symbol Conditions Min. Typ. 27 Max. Unit IVCLK frequency fIVCKS MHz IVCLK high-level width tVCKH 10 ns IVCLK low-level width tVCKL 10 ns IVIN7 to IVIN0 setup time tIVDS Vs rising edge of IVCLK 5 ns IVIN7 to IVIN0 hold time tIVDH Vs rising edge of IVCLK 4 ns IVVSYNC-input setup time tIVVS Vs rising edge of IVCLK 5 ns IVVSYNC-input hold time tIVVH Vs rising edge of IVCLK 4 ns IVHSYNC-input setup time tIVHS Vs rising edge of IVCLK 5 ns IVHSYNC-input hold time tIVHH Vs rising edge of IVCLK 4 ns IVFLD-input setup time tIVFS Vs rising edge of IVCLK 5 ns IVFLD-input hold time tIVFH Vs rising edge of IVCLK 4 ns tIVCKH fIVCKS IVCLK tIVDS IVIN7 to IVIN0 Cr Y tIVVH tIVHH tIVFH IVHSYNC IVVSYNC IVFLD tIVCKL tIVDH Cb Y Cr tIVVS tIVHS tIVFS Data Sheet S15082EJ4V0DS 73 µPD61051, 61052 (3) Video output interface Parameter Symbol Conditions Min. Typ. Max. 27 Unit OVCLK frequency fOVCKS MHz OVCLK high-level width tOVCKH 8 ns OVCLK low-level width tOVCKL 8 ns OVOUT7 to OVOUT0 hold tOVHO Vs rising edge of OVCLK 7 ns tOVDO Vs rising edge of OVCLK OVVSYNC hold time tOVVHO Vs rising edge of OVCLK OVVSYNC delay time tOVVD Vs rising edge of OVCLK OVHSYNC hold time tOVHHO Vs rising edge of OVCLK OVHSYNC delay time tOVHD Vs rising edge of OVCLK time OVOUT7 to OVOUT0 delay 28 ns time 7 28 7 OVCLK tOVDO tOVCKL tOVHO OVOUT7 to OVOUT0 Y Cb Y tOVVD tOVHD tOVVHO tOVHHO OVHSYNC OVVSYNC 74 Data Sheet S15082EJ4V0DS Cr ns ns 28 tOVCKH fOVCKS ns ns µPD61051, 61052 (4) Audio input interface Parameter Symbol Conditions Min. Typ. Max. Unit Bit data-in setup time tACDS Vs IABCK 37 ns Bit data-in hold time tACDH Vs IABCK 37 ns LRCK-in setup time tACLS Vs IABCK 100 ns LRCK-in hold time tACLH Vs IABCK 37 ns IABCK tACDS tACDH IABD tACLH tACLS IALRCK Data Sheet S15082EJ4V0DS 75 µPD61051, 61052 (5) Audio output interface Parameter Symbol Conditions Min. Typ. Max. −5 Unit Bit data-out hold time tACDHO Vs OABCK Bit data-out delay time tACDD Vs OABCK LRCK-out hold time tACLHO Vs OABCK LRCK-out delay tACLD Vs OABCK BCK-out duty ratio dBCK 50 % AMCLK duty ratio dAMCLK 50 % AMCLK frequency fAMCLK 25 −5 tACDHO tACDD OABD tACLHO tACLD OALRCK Data Sheet S15082EJ4V0DS ns ns 25 18.432 OABCK 76 ns ns MHz µPD61051, 61052 (6) Stream input interface (a) Parallel stream input Valid mode Parameter Symbol Conditions Min. Typ. Max. Unit ISCLK cycle tISCcyc 80 ns ISCLK low-level width tISCLW 37 ns ISCLK high-level width tISCHW 37 ns ISREQ output hold time tISRQHO Vs active edge of ISCLK 0 ns ISVLD setup time tISVS Vs active edge of ISCLK 7 ns ISVLD hold time tISVH Vs active edge of ISCLK 3 ns ISSYNC setup time tISSS Vs active edge of ISCLK 7 ns ISSYNC hold time tISSH Vs active edge of ISCLK 3 ns IS7 to IS0 setup time tISDS Vs active edge of ISCLK 7 ns IS7 to IS0 hold time tISDH Vs active edge of ISCLK 3 ns Data cycle time tDCYC 80 ns Remark ISREQ is effective only when it works by the master mode. ISREQ becomes invalid asynchronously to ISCLK. ISREQ output delay time doesn't prescribe to ISCLK. ISCLK (I) tISCHW tISCLW tISCYC ISREQ (O) tISRQHO tISVS ISVLD (I) tDCYC tISVH IS7 to IS0 (I) No received data Valid data 1st of packet Valid data Valid data Valid data tISSH tISDH Valid data Valid data Valid data Valid data tISDS ISSYNC (I) tISSS Remark ISSYNC is active high, SREQ is active high and ISCLK is active high edge. Data Sheet S15082EJ4V0DS 77 µPD61051, 61052 Strobe mode Parameter Symbol Conditions Min. Typ. Max. Unit ISSTB low-level width tISSTLW 37 ns ISSTB high-level width tISSTHW 37 ns ISREQ output hold time tISRQHO Vs active edge of ISSTB 0 ns ISSYNC setup time tISSS Vs active edge of ISSTB 7 ns ISSYNC hold time tISSH Vs active edge of ISSTB 3 ns IS7 to IS0 setup time tISDS Vs active edge of ISSTB 7 ns IS7 to IS0 hold time tISDH Vs active edge of ISSTB 3 ns Data cycle time tDCYC 80 ns Remark ISREQ becomes invalid asynchronously to ISSTB. ISREQ output delay time doesn't prescribe to ISSTB. ISREQ (O) tISRQHO tISSTHW ISSTB (I) tDCYC tISSTLW IS7 to IS0 (I) No received data Valid data 1st of packet Valid data Valid data Valid data tISSH tISDH Valid data Valid data Valid data tISDS ISSYNC (I) tISSS Remark 78 ISSYNC is active high, ISREQ is active low and ISSTB is active high edge. Data Sheet S15082EJ4V0DS Valid data µPD61051, 61052 (b) Serial stream input Parameter Symbol Conditions Min. Typ. Max. Unit ISCLK period tISSCW 15.6 ns ISCLK low-level width tISSCLW 5.0 ns ISCLK high-level width tISSCHW 5.0 ns ISVLD setup time tISSVS Vs active edge of ISCLK 2.5 ns ISVLD hold time tISSVH Vs active edge of ISCLK 2.5 ns ISSYNC setup time tISSSS Vs active edge of ISCLK 2.5 ns ISSYNC hold time tISSSH Vs active edge of ISCLK 2.5 ns ISERR setup time tISSES Vs active edge of ISCLK 2.5 ns ISERR hold time tISSEH Vs active edge of ISCLK 2.5 ns IS0 setup time tISSDS Vs active edge of ISCLK 2.5 ns IS0 hold time tISSDH Vs active edge of ISCLK 2.5 ns Remark Setup and hold time provide to the activist edge of ISCLK. tISSCW tISSCLW tISSCHW ISCLK tISSDS tISSDH tISSVS tISSVH tISSSS tISSSH tISSES tISSEH IS0 ISVLD ISSYNC ISERR Remark ISCLK is active high edge. Data Sheet S15082EJ4V0DS 79 µPD61051, 61052 (7) Stream output interface (a) Parallel stream data output Valid and master mode Parameter Symbol OSCLK low-level width OSCLK high-level width tOSCLW tOSCHW Conditions Min. Max. Unit Active rising edge 30 ns Active falling edge 70 ns Active rising edge 70 ns Active falling edge 30 ns ns OSVLD hold time tOSVHO Vs active edge of OSCLK 30 OSVLD delay time tOSVD Vs non active edge of OSCLK −5 OSSYNC hold time tOSSHO Vs active edge of OSCLK 30 OSSYNC delay time tOSSD Vs non active edge of OSCLK −5 OS7 to OS0 hold time tOSDHO Vs active edge of OSCLK 30 OS7 to OS0 delay time tOSDD Vs non active edge of OSCLK −5 Data cycle time tDCYC2 Remark Typ. +5 ns ns +5 ns ns +5 105 ns ns OSVLD is active high, OSSYNC is active high and OSCLK is active high edge. OSCLK tOSVD tOSCHW tOSCLW OSVLD 188 bytes tDCYC2 tOSVHO OS7 to OS0 Invalid data Valid data Valid data Valid data 1st of packet tOSSD Valid data Valid data tOSDD tOSSHO OSSYNC 80 Data Sheet S15082EJ4V0DS Valid data Valid data Invalid data tOSDHO µPD61051, 61052 Strobe and byte mode Parameter Symbol OSREQ high-level time tOSRHW OSSTB high-level width tOSSTHW OSSTB low-level width tOSSTLW Conditions Min. Typ. Max. Unit 2 STCLK Active rising edge 100 ns Active falling edge 70 ns Active rising edge 70 ns Active falling edge 100 ns OSREQ hold time tOSRRD Vs active edge of OSRDY 0 ns OSREQ hold time tOSTRQ1 Vs active edge of OSSTB 0 ns tOSTRQ2 Vs non active edge of OSSTB 0 ns tOSRSTD1 Vs active edge of OSREQ 2 tOSRSTD2 Vs non active edge of OSREQ 3 OSRDY delay time tOSSTRD1 Vs non active edge of OSSTB OSSYNC-out delay time tOSSD Vs non active edge of OSSTB −5 OSSYNC-out hold time tOSSHO Vs active edge of OSSTB 70 OS7 to OS0 out delay time tOSDD Vs non active edge of OSSTB −5 OS7 to OS0 out hold time tOSDHO Vs active edge of OSSTB 70 OSSTB delay time 3 STCLK STCLK 3 STCLK +5 ns ns +5 ns ns OSRDY tOSRRD tOSRHW tOSSTRD1 tOSTRQ1 OSREQ tOSRSTD2 tOSTRQ2 tOSRSTD1 OSSTB tOSSTLW tOSSTHW tOSDD OS7-OS0 tOSDHO tOSSD OSSYNC Remark tOSSHO OSSYNC is active high, OSRDY is active low and OSSTB is active high edge. Data Sheet S15082EJ4V0DS 81 µPD61051, 61052 (b) Serial stream data output Parameter Symbol Conditions Min. Typ. Max. 37 Unit OSCLK period tOSSCW OSCLK low-level width tOSSCLW 10 ns OSCLK high-level width tOSSCHW 10 ns OS0 delay time tOSSDD Vs active edge of OSCLK OS0 hold time tOSSDHO Vs active edge of OSCLK OSVLD delay time tOSSVD Vs active edge of OSCLK OSVLD hold time tOSSVHO Vs active edge of OSCLK OSSYNC delay time tOSSSD Vs active edge of OSCLK OSSYNC hold time tOSSSHO Vs active edge of OSCLK 27 5.0 5.0 2. Period of the OSCLK is provided by STCLK. tOSSCW tOSSCLW tOSSCHW OSCLK tOSSD OS0 tOSSDHO tOSSVD OSVLD tOSSHO tOSSSD OSSYNC tOSSSHO 82 OSCLK is active high edge. Data Sheet S15082EJ4V0DS ns ns 27 5.0 ns ns 27 Remarks 1. Active edge of OSCLK is able to change according to the following circuit. Remark ns ns ns µPD61051, 61052 (8) SDRAM interface Parameter Symbol Conditions Min. Typ. Max. 12.3 Unit MCLK cycle time tCK ns MCLK high-level width tCH 3.5 ns MCLK low-level width tCL 3.5 ns MD31 to MD0-out hold time tOH Vs MCLK 1.5 ns MD31 to MD0-out delay time tOD Vs MCLK MD31 to MD0 low-Z output time tLZ Vs MCLK MD31 to MD0 high-Z output time tHZ Vs MCLK MD31 to MD0-in setup time tDS Vs MCLK 6 ns MD31 to MD0-in hold time tDH Vs MCLK 2 ns MA13 to MA0 delay time tAD Vs MCLK MA13 to MA0 hold time tAH Vs MCLK MCLKE delay time tCKS Vs MCLK MCLKE hold time tCKH Vs MCLK Command delay time tCMD Vs MCLK Command hold time tCMH Vs MCLK ACT → REF/ACT command period 9 0 ns ns 9 9 1.5 ns ns ns 9 1.5 ns ns 9 ns 1.5 ns tRC 12 MCLK REF → REF/ACT command period tRC1 12 MCLK ACT → PRE command period tRAS 12 MCLK PRE → ACT command period tRP 12 MCLK ACT → R/W command delay time tRCD 3 MCLK ACT (0) → ACT (1) command tRRD 4 MCLK Data-in to PRE command period tDPL 2 MCLK Data-in to ACT (REF) command tDAL 6 MCLK Mode register set cycle period tRSC 2 MCLK Refresh Time (4096 refresh cycle) tREF period period (Auto pre-charge) Remark 50 ms REF: Refresh, ACT: Active, PRE: Pre-charge Data Sheet S15082EJ4V0DS 83 84 Data Sheet S15082EJ4V0DS MD31 to MD0 MDQM MA9 to MA0 MA10 MA12 MA13 MWE MCAS MRAS MCS MCLKE MCLK tCL tAH tCMH T1 Active command for bank A Hi-Z tAD Low tCMD tCH tCK T0 tRCD T2 tCK tRAS T4 Read command for bank A T3 tRC T5 tDH T7 T8 Precharge command for bank A tDS T6 tRP T9 Hi-Z T11 T12 Active command for bank A tCKH T10 T13 µPD61051, 61052 Read timing (Manual pre-charge, burst length = 4, CAS latency = 3) Data Sheet S15082EJ4V0DS MD31 to MD0 MDQM MA9 to MA0 MA10 MA12 MA13 MWE MCAS MRAS MCS MCLKE MCLK tCL tAH tCMH T1 tRCD T2 Active command for bank A Hi-Z tAD Low tCMD tCH tCK T0 tCK tRAS tRRD T4 tRC T5 Read with Auto Precharge command for bank A T3 tDS T6 T8 T9 Active command for bank B tDH T7 Hi-Z T11 T12 Active command for bank A tCKH T10 T13 µPD61051, 61052 Read timing (Auto pre-charge, burst length = 4, CAS latency = 3) 85 86 Data Sheet S15082EJ4V0DS MD31 to MD0 MDQM MA9 to MA0 MA10 MA12 MA13 MWE MCAS MRAS MCS MCLKE MCLK Hi-Z tAD Low tCMD tCKD tCK T0 tCL tAH tCMH T2 DAa1 T4 tRAS tDAL tHZ tRC tDPL Hi-Z T13 tRP tCKH T14 T15 T16 T17 T18 T19 Active command for bank A Precharge command for bank B T12 DBa4 T11 DBa3 T10 DBa2 T9 Active command of bank B Write with Auto Precharge command for bank B DBa1 T8 tOD DAa4 T7 tRC tRCD DAa3 T6 Active command for bank B DAa2 tOH T5 Write with Auto Precharge command for bank A tRRD tRCD tLZ T3 Active command for bank A tCH T1 T20 T21 µPD61051, 61052 Write timing (Burst length = 4, CAS latency = 3) µPD61051, 61052 (9) Host CPU interface (a) Parallel bus interface: Wait mode (1/2) Parameter CCS↓ → CA5 to CA0 delay time Symbol tCAD Conditions Vs falling edge of CCS Min. Typ. Max. Unit - - - ns 15 ns 175 ns Do not care CCS↓ → CWAIT delay time tCWAD1 Vs falling edge of CCS CCS later than CRE/CWE CCS↓→ CWAIT release time tCRDY Vs falling edge of CCS CCS later than CRE/CWE CA5 to CA0 → CRE↓ delay time tARD Vs CA5 to CA0 −20 ns CCS↓ → CRE↓ delay time tCRD Vs falling edge of CCS −20 ns CRE↓ → CWAIT delay time tRWD1 Vs falling edge of CRE 15 ns CRE↓ → CWAIT release time tRRD Vs falling edge of CRE 175 ns CCS↓ → CD7 to CD0 low-Z time tCDLD Vs falling edge of CCS 0 ns 0 ns Data not fixed CRE↓ → CD7 to CD0 low-Z time tRDLD Vs falling edge of CRE Data not fixed CCS↓→ CD7 to CD0 delay time tCDD Vs falling edge of CCS 150 ns 150 ns Data fixed CRE↓ → CD7 to CD0 delay time tRDD Vs falling edge of CRE Data fixed CRE↑ → CD7 to CD0 hold time tRDH Vs rising edge of CRE 0 ns Earlier than rising edge of CCS CRE↑ → CA5 to CA0 hold time tRAH Vs rising edge of CRE −27 ns CRE↑ → CCS↑ hold time tRCH Vs rising edge of CRE −27 ns CCS↑ → CD7 to CD0 hold time tCDRH Vs rising edge of CCS 0 ns 10 ns Earlier than rising edge of CRE CD7 to CD0 → CWAIT release tCDW Vs CD7 to CD0 fixed CD7 to CD0 Hi-Z delay time tCDZD Vs rising edge of CRE or CCS CA5 to CA0 → CWE↓ delay time tAWD Vs CA5 to CA0 −28 ns CCS↓ → CWE↓ delay time tCWD Vs falling edge of CCS −20 ns CWE↓ → CWAIT delay time tWWD1 Vs falling edge of CWE 15 ns CWE↓ → CWAIT release time tWRD Vs falling edge of CWE 150 ns CWE↓ → CD7 to CD0 delay time tWDD Vs falling edge of CWE 30 ns time 12 ns Until data fixed CWE↑ → CD7 to CD0 hold time tWDH Vs rising edge of CWE Data Sheet S15082EJ4V0DS −7 ns 87 µPD61051, 61052 (2/2) Parameter Symbol Conditions Min. Typ. Max. Unit CWE↑ → CA5 to CA0 hold time tWAH Vs rising edge of CWE −27 ns CWE↑ → CCS↑ hold time tWCH Vs rising edge of CWE −27 ns CCS↑ → CD7 to CD0 hold time tCDWH Vs rising edge of CCS 0 ns CCS↑ → CWAIT release time tCWAD2 Vs rising edge of CCS 0 CWAIT release → CWE/CRE hold time tCWR Vs CWAIT release 0 ns CWAIT release → CD5 to CD0 hold time tCWA Vs CWAIT release 0 ns CWAIT release → CSS↑ hold time tCWC Vs CWAIT release 0 ns CRE/CWE recovery time tCAC 25 ns Access cycle after other device tCCYC 200 ns Remark ns If CCS change to "H" in wait cycle, it cancels CWAIT. In access time, don't make CCS "H" until wait released. 88 15 Data Sheet S15082EJ4V0DS µPD61051, 61052 Wait mode (Wait active low, read cycle) tCWA CA5 to CA0 tARD tRAH CCS tRCH tCAD tCRD tCDZD tCWC tCDZD CD7 to CD0 tCDRH tCDLD tCDD CRE tRDH tRDLD tRDD tCAC tCWR tCAC tCDW CWE tCRDY tRRD CWAIT tCWAD1 tRWD1 Wait mode (Wait active low, write cycle) tCWA CA5 to CA0 tAWD tWAH CCS tWCH tCWD tCAD tCWC tCDWH CD7 to CD0 tWDH CRE tWDD CWE tWDD tCWR tCAC tCRDY tCAC tWRD CWAIT tCWAD1 Data Sheet S15082EJ4V0DS tWWD1 89 µPD61051, 61052 Wait mode (Wait active high, read cycle) tCWA CA5 to CA0 tARD tRAH CCS tRCH tCAD tCRD tCDZD tCWC tCDZD CD7 to CD0 tCDRH tCDLD tCDD CRE tRDH tRDLD tRDD tCAC tCWR tCAC tCDW CWE tCRDY tRRD CWAIT tCWAD1 tRWD1 Wait mode (Wait active high, write cycle) tCWA CA5 to CA0 tAWD tWAH CCS tWCH tCWD tCAD tCWC tCDWH CD7 to CD0 tWDH CRE tWDD CWE tWDD tCWR tCAC tCRDY tCAC tWRD CWAIT tCWAD1 90 Data Sheet S15082EJ4V0DS tWWD1 µPD61051, 61052 CA5 to CA0 CCS tCCYC CD7 to CD0 tCCYC CRE tCCYC CWE CWAIT CA5 to CA0 CCS tCCYC CD7 to CD0 tCCYC CRE tCCYC CWE CWAIT Data Sheet S15082EJ4V0DS 91 µPD61051, 61052 (b) Parallel bus interface: Ready mode (1/2) Parameter CCS↓ → CA5 to CA0 delay time Symbol tCAD Conditions Vs falling edge of CCS Min. Typ. Max. Unit - - - ns Do not care CCS↓ → CWAIT delay time tCWAD1 Vs falling edge of CCS 15 CCS later than CRE/CWE CCS↓ → CWAIT ready time tCRDY Vs falling edge of CCS 175 ns CCS later than CRE/CWE CA5 to CA0 → CRE↓ delay time tARD Vs CA5 to CA0 −20 ns CCS↓ → CRE↓ delay time tCRD Vs falling edge of CCS −20 ns CRE↓ → CWAIT ready time tRRD Vs falling edge of CRE CCS↓ → CD7 to CD0 low-Z time tCDLD Vs falling edge of CCS 175 ns 0 ns 0 ns Data not fixed CRE↓ → CD7 to CD0 low-Z time tRDLD Vs falling edge of CRE Data not fixed CCS↓ → CD7 to CD0 delay time tCDD Vs falling edge of CCS 150 ns 150 ns Data fixed CRE↓ → CD7 to CD0 delay time tRDD Vs falling edge of CRE Data fixed CRE↑ → CD7 to CD0 hold time tRDH Vs rising edge of CRE 0 ns Earlier than rising edge of CCS CRE↑ → CA5 to CA0 hold time tRAH Vs rising edge of CRE −27 ns CRE↑ → CCS↑ hold time tRCH Vs rising edge of CRE −27 ns CCS↑ → CD7 to CD0 hold time tCDRH Vs rising edge of CCS 0 ns 10 ns Earlier than rising edge of CRE CD7 to CD0 → CWAIT ready tCDW Vs CD7 to CD0 fixed CD7 to CD0 high-Z delay time tCDZD Vs rising edge of CRE or CCS CA5 to CA0 → CWE↓ delay time tAWD Vs CA5 to CA0 −28 ns CCS↓ → CWE↓ delay time tCWD Vs falling edge of CCS −20 ns CWE↓ → CWAIT ready time tWRD Vs falling edge of CWE 150 ns CWE↓ → CD7 to CD0 delay time tWDD Vs falling edge of CWE 30 ns time 12 ns Until data fixed CWE↑ → CD7 to CD0 hold time tWDH Vs rising edge of CWE −7 ns CWE↑ → CA5 to CA0 hold time tWAH Vs rising edge of CWE −27 ns CWE↑ → CCS↑ hold time tWCH Vs rising edge of CWE −27 ns CCS↑ → CD7 to CD0 hold time tCDWH Vs rising edge of CCS 0 ns CRE↑ → CWAIT release time tRWD2 Vs rising edge of CRE 0 92 Data Sheet S15082EJ4V0DS 15 ns µPD61051, 61052 (2/2) Parameter Symbol Conditions Min. Typ. Max. Unit CWE↑ → CWAIT release time tWWD2 Vs rising edge of CWE 0 15 ns CCS↑ → CWAIT release time tCWAD2 Vs rising edge of CCS 0 15 ns CWAIT ready → CWE/CRE hold tCWR Vs CWAIT ready 0 ns tCWA Vs CWAIT ready 0 ns CWAIT ready → CCS↑ hold time tCWC Vs CWAIT ready 0 ns CRE/CWE recovery time tCAC 25 ns Access cycle after other device tCCYC 200 ns time CWAIT ready → CA5 to CA0 hold time Remark If CCS change to "H" in wait cycle, it cancels CWAIT. In access time, don't make CCS "H" until wait becomes ready. Data Sheet S15082EJ4V0DS 93 µPD61051, 61052 Ready mode (Ready active high, read cycle) tCWA CA5 to CA0 tARD tRAH CCS tRCH tCAD tCRD tCDZD tCWC tCDZD CD7 to CD0 tCDRH tCDLD tCDD CRE tCAC tRDH tRDLD tRDD tCWR tCAC tCDW CWE tCRDY tRRD CWAIT tCWAD2 tRWD2 Ready mode (Ready active high, write cycle) tCWA CA5 to CA0 tAWD tWAH CCS tWCH tCWD tCAD tCWC tCDWH CD7 to CD0 tWDH CRE tWDD CWE tWDD tCWR tCAC tCRDY tCAC tWRD CWAIT tCWAD2 94 Data Sheet S15082EJ4V0DS tWWD2 µPD61051, 61052 Ready mode (Ready active low, read cycle) tCWA CA5 to CA0 tARD tRAH CCS tRCH tCAD tCRD tCDZD tCWC tCDZD CD7 to CD0 tCDRH tCDLD tCDD CRE tCAC tRDH tRDLD tRDD tCWR tCAC tCDW CWE tCRDY tRRD CWAIT tCWAD2 tRWD2 Ready mode (Ready active low, write cycle) tCWA CA5 to CA0 tAWD tWAH CCS tWCH tCWD tCAD tCWC tCDWH CD7 to CD0 tWDH CRE tWDD CWE tWDD tCWR tCAC tCRDY tCAC tWRD CWAIT tCWAD2 Data Sheet S15082EJ4V0DS tWWD2 95 µPD61051, 61052 CA5 to CA0 CCS tCCYC CD7 to CD0 tCCYC CRE tCCYC CWE CWAIT CA5 to CA0 CCS tCCYC CD7 to CD0 tCCYC CRE tCCYC CWE CWAIT 96 Data Sheet S15082EJ4V0DS µPD61051, 61052 (c) Parallel bus interface: Fixed wait mode Parameter CCS↓ → CA5 to CA0 delay time Symbol tCAD Conditions Vs falling edge of CCS Min. Typ. Max. Unit - - - ns Do not care CRE pulse width tRW 175 ns CA5 to CA0 → CRE↓ delay time tARD Vs CA5 to CA0 −20 ns CCS↓ → CRE↓delay time tCRD Vs falling edge of CCS −20 ns CCS↓ → CD7 to CD0 low-Z time tCDLD Vs falling edge of CCS 0 ns 0 ns Data not fixed CRE↓ → CD7 to CD0 low-Z time tRDLD Vs falling edge of CRE Data not fixed CCS↓ → CD7 to CD0 delay time tCDD Vs falling edge of CCS 150 ns 150 ns Data fixed CRE↓ → CD7 to CD0 delay time tRDD Vs falling edge of CRE Data fixed CRE↑ → CD7 to CD0 hold time tRDH Vs rising edge of CRE 0 ns Earlier than rising edge of CCS CRE↑ → CA5 to CA0 hold time tFRAH Vs rising edge of CRE −27 ns CRE↑ → CCS↑ hold time tFRCH Vs rising edge of CRE −27 ns CCS↑ → CD7 to CD0 hold time tCDRH Vs rising edge of CCS 0 ns CD7 to CD0 high-Z delay time tCDZD Vs rising edge of CRE or CCS CWE pulse width tWW CA5 to CA0 → CWE↓ delay time tAWD CCS↓ → CWE↓ delay time CWE↓ → CD7 to CD0 delay time 12 ns 150 ns Vs CA5 to CA0 −28 ns tCWD Vs falling edge of CCS −20 ns tWDD Vs falling edge of CWE 30 ns Until data fixed CWE↑ → CD7 to CD0 hold time tWDH Vs rising edge of CWE −7 ns CWE↑ → CA5 to CA0 hold time tFWAH Vs rising edge of CWE −27 ns CWE↑ → CCS↑ hold time tFWCH Vs rising edge of CWE −27 ns CCS↑ → CD7 to CD0 hold time tCDWH Vs rising edge of CCS 0 ns CRE/CWE recovery time tCAC 25 ns Access cycle after other device tCCYC 200 ns Data Sheet S15082EJ4V0DS 97 µPD61051, 61052 Fixed wait mode (Read cycle) CA5 to CA0 tARD tFRAH CCS tFRCH tCAD tCRD tCDZD tCDZD CD7 to CD0 tCDRH tCDLD tCDD CRE tCAC tRDH tRDLD tRDD tCAC tRW CWE Fixed wait mode (Write cycle) CA5 to CA0 tAWD tFWAH CCS tFWCH tCWD tCAD tCDWH CD7 to CD0 tWDH CRE tWDD CWE tWDD tCAC tCAC 98 Data Sheet S15082EJ4V0DS tWW µPD61051, 61052 CA5 to CA0 CCS tCCYC CD7 to CD0 tCCYC CRE tCCYC CWE CA5 to CA0 CCS tCCYC CD7 to CD0 tCCYC CRE tCCYC CWE Data Sheet S15082EJ4V0DS 99 µPD61051, 61052 (10) Serial bus interface (a) Serial bus interface Parameter Symbol Conditions Min. Typ. Max. Unit CCS → CSCLK delay time tCSCK Vs falling edge of CCS 10 ns CCS → CSDI delay time tCSDI Vs falling edge of CCS 10 ns CSDI setup time tCSDS Vs rising edge of CSCLK 10 ns CSDI hold time tCSDH Vs rising edge of CSCLK 10 ns CSDO hold time tCSDHO Vs falling edge of CSCLK 0 ns CSDO delay time tCSDD Vs falling edge of CSCLK CSCLK → CCS hold time tCCKS Vs rising edge of CSCLK CCS high-level width 15 ns 75 ns tCSHW 125 ns CSCLK cycle time tCKCYC 100 ns CSCLK high-level width tCSCHW 40 ns CSCLK high-level width tCSCLW 40 ns CCS tCSCHW tCSCK tCKCS CSCLK tCSCLW CSDI tCSDI tCSDS tCSDH CSDO tCSDHO tCSDD 100 Data Sheet S15082EJ4V0DS µPD61051, 61052 [Data Write] tCSHW tCKCS CCS tCSCK tCKCYC CSCLK tCSDI CSDI CSDO xx A5 A4 A3 A2 A1 A0 W x D7 D6 D5 D4 D3 D2 D1 D0 x xx tCSDS tCSDH tCSDS tCSDH [Data Read] tCSHW tCKCS CCS tCSCK tCKCYC CSCLK tCSDI CSDI CSDO xx A5 A4 A3 A2 A1 A0 R x x x x x x x x x x D7 D6 D5 D4 D3 D2 D1 D0 tCSDHO tCSDD xx tCSDS tCSDH (b) Instruction ROM interface Parameter Symbol Conditions Min. Typ. Max. Unit Address setup time tFARS Vs falling edge of FOE 0 ns Address hold time tFARH Vs rising edge of FOE 5 ns FOE low-level width tFRLW 70 FOE high-level width tFRHW 24 ns Data setup time tFDS Vs rising edge of FOE 25 ns Data hold time tFDH Vs rising edge of FOE 0 ns Data high-Z output time tFDHL Vs rising edge of FOE 225 60 ns ns FA19 to FA0 tFARH tFARS tFRHW FOE tFRLW FD7 to FD0 Hi-Z Hi-Z tFDS tFDH Data Sheet S15082EJ4V0DS Hi-Z tFDHL 101 µPD61051, 61052 7. PACKAGE DRAWING 208-PIN PLASTIC QFP (FINE PITCH) (28x28) A B 156 157 105 104 detail of lead end S C D Q 208 1 R 53 52 F G H I J M P K N S S L NOTE M ITEM Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A 30.6±0.2 B 28.0±0.2 C 28.0±0.2 D 30.6±0.2 F 1.25 G 1.25 H 0.22 +0.05 −0.04 I 0.10 J K 0.5 (T.P.) 1.3±0.2 L 0.5±0.2 0.17 +0.03 −0.07 M N 0.10 P Q 3.2±0.1 0.4±0.1 R 5°±5° S 3.8 MAX. P208GD-50-LML,MML,SML,WML-7 102 Data Sheet S15082EJ4V0DS µPD61051, 61052 8. RECOMMENDED SOLDERING CONDITIONS The µPD61051, 61052 should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Table 8-1. Surface-Mounted Soldering Conditions µPD61051GD-LML: Note1 µPD61051GD-LML-A : µPD61052GD-LML: Note1 µPD61052GD-LML-A : 208-pin plastic QFP (Fine pitch) (28×28) 208-pin plastic QFP (Fine pitch) (28×28) 208-pin plastic QFP (Fine pitch) (28×28) 208-pin plastic QFP (Fine pitch) (28×28) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235°C IR35-207-3 Time: 30 sec. max. (at 210°C or higher) Count: Three times or fewer Exposure limit: 7 days VPS Note2 (After that, prebake at 125°C for 20 to 72 hours) Package peak temperature: 215°C VP15-207-3 Time: 40 sec. max. (at 200°C or higher) Count: Three times or fewer Exposure limit: 7 days Partial heating Note2 (After that, prebake at 125°C for 20 to 72 hours) Pin temperature: 300°C max. Time: 3 sec. max. (per pin row) Notes 1. Lead-free product 2. After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. Caution Do not use two or more soldering methods in combination (except for partial heating method). Data Sheet S15082EJ4V0DS 103 µPD61051, 61052 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 104 Data Sheet S15082EJ4V0DS µPD61051, 61052 [MEMO] Data Sheet S15082EJ4V0DS 105 µPD61051, 61052 Dolby is a trademark of Dolby Laboratories. • The information in this document is current as of November, 2003. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. 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