NEC UPD75238GJ

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD75238
ELECTRON DEVICE
4 BIT SINGLE-CHIP MICROCOMPUTER
The µPD75238 is a single-chip microcomputer which contains a CPU capable of 1-, 4-, and 8-bit data
processing, ROM, RAM, and I/O ports. In addition, it contains a fluorescent display tube (FIP;) controller/driver,
A/D converter, clock timer, timer/pulse generator capable of 14-bit PWM output, serial interface, and vectored
interrupt function.
In comparison with the µ PD75217, the µPD75238 has larger ROM and RAM capacity and has been enhanced
in such peripheral facilities as the display function of the FIP controller/driver, I/O ports, A/D converter, serial
interface.
The µPD75238 finds best use in such applications as timer/tuner of VCRs from advanced type to common
type, configuration of one-chip system control microcomputer, advanced CD player, advanced microwave
ovens, etc.
With the µ PD75238, the µPD75P238, which is a PROM product, and various development tools including
IE-75001-R and assemblers are available. They can be used for evaluation during system development and
small-volume production.
FEATURES
• Mass-storage built-in ROM and RAM
• Program memory (ROM) : 32K × 8
: 1K × 4
• Data memory (RAM)
• I/O port: 64 lines (excluding pins dedicated
to FIP)
•
•
•
•
•
8-bit A/D converter: 8 channels
Enhanced timer/counter function: 5 channels
8-bit serial interface: 2 channels
Application-oriented interrupt functions
PROM version device: µPD75P238
• Minimum instruction execution time:
0.67 µs (at 6.0 MHz)
• Instruction execution time specification function to allow a wide range of operating
voltages
• Programmable FIP controller/driver contained
• Number of segments : 9 to 24 segments
• Number of digits
: 9 to 16 digits
ORDERING INFORMATION
Part number
Package
Quality grade
µPD75238GJ-×××-5BG
94-pin plastic QFP (20 × 20 mm)
Standard
Please refer to “Quality Grade on NEC Semiconductor Devices” (Document number IEI-1209) published by NEC
Corporation to know the specification of quality grade on the devices and its recommended applications.
The information in this document is subject to change without notice.
Document No.
(O.D. No.
Date Published
Printed in Japan
IC-2777A
IC-8177A)
February 1993 P
Major changes in this revision are indicated by stars (★) in the margins.
© NEC Corporation 1992
µPD75238
FUNCTIONS
Item
Function
On-chip memory
ROM: 32640 × 8 bits, RAM: 1024 × 4 bits
I/O lines
(Excluding pins dedicated to FIP)
•
64 lines •
•
Instruction cycle
•
•
•
0.67 µs/1.33 µs/2.67 µs/10.7 µs (at 6.0 MHz)
0.95 µs/1.91 µs/3.82 µs/15.3 µs (at 4.19 MHz)
122 µs (at 32.768 kHz)
Fluorescent display tube (FIP)
controller/driver
•
•
•
•
•
Number of segments : 9 to 24 segments
Number of digits
: 9 to 16 digits
Dimmer function
: 8 levels
Pull-down resistors provided by mask option
Key scan interrupt generator
Input : 16 lines
I/O
: 24 lines
Output : 24 lines
Timer/counter
5 channels
Serial interface
2 channels
Interrupt
•
•
•
•
•
2
•
Basic interval timer
•
•
•
•
Timer/event counter
Clock timer
: With buzzer output function
Timer/pulse generator : With 14-bit PWM output function
Event counter
: Usable as watchdog timer
•
•
SBI or 3-wire mode
3-wire mode
Allows multiple hardware interrupts.
• Detection of both edges
External interrupts : 3
• Detection edge programmable (with noise
elimination)
• Detection edge programmable
External test input : 1
• Rising edge detection
• Timer/pulse generator
• Timer/event counter
Internal interrupts : 5
• Basic interval timer
• Serial interface #0
• For key scanning
Internal test inputs: 2
• Clock timer
• Serial interface #1
System clock oscillator
•
•
Main system clock : 6.0 MHz, 4.19 MHz
Subsystem clock : 32.768 kHz, standard
Mask option
•
•
•
High-voltage port : Pull-down resistor or open-drain output
Ports 4 and 5
: Pull-up resistor
Port 7
: Pull-down resistor
Operating temperature
-40 to +85 °C
Operating voltage
2.7 to 6.0 V (Data held in standby mode: 2.0 to 6.0 V)
Package
94-pin plastic QFP (20 × 20 mm)
µPD75238
AN1
AN2
AN3
AN4/P90
AN5/P91
AN6/P92
AN7/P93
AVSS
RESET
P00/INT4
P01/SCK0
P02/SO0/SB0
P03/SI0/SB1
P10/INT0
P11/INT1
P12/INT2
P13/TI0
P20/PTO0
P21
P22/PCL
P23/BUZ
P30
P31
PIN CONFIGURATION
P32
P33
P40
P41
P42
P43
VSS
P50
P51
P52
P53
P60
P61
P62
P63
P70
P71
P72
P73
P80/PPO
P81/SCK1
P82/SO1
P83/SI1
VDD
S4/P130
S5/P131
S6/P132
S7/P133
S8/P140
S9/P141
VDD
V LOAD
T15/S10/P142
T14/S11/P143
PH0/T13/S12/P150
PH1/T12/S13/P151
PH2/T11/S14/P152
PH3/T10/S15/P153
T9
T8
T7
T6
T5
T4
T3
T2
T1
T0
µ PD75238GJ-×××-5BG
AN0
AVREF
AVDD
VDD
VDD
X2
X1
IC
XT2
XT1
VSS
S16/P100
S17/P101
S18/P102
S19/P103
S20/P110
S21/P111
S22/P112
S23/P113
S0/P120
S1/P121
S2/P122
S3/P123
94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72
71
1
70
2
69
3
68
4
67
66
5
65
6
64
7
63
8
62
9
61
10
60
11
59
12
58
13
57
14
56
15
55
16
54
17
53
18
52
19
51
20
50
21
49
22
48
23
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Caution Be sure to supply power to the AVDD, VDD, VSS, and AVSS pins (pins 3, 4, 5, 11, 30, 48, 65, and 87).
Remark IC: Internally connected pin (to be grounded)
3
TI0
4
P00-P03
Port 1
4
P10-P13
SP (8)
Port 2
4
P20-P23
SBS (2)
Port 3
4
P30-P33
Bank
Port 4
4
P40-P43Note
Port 5
4
P50-P53Note
Port 6
4
P60-P63
Port 7
4
P70-P73
Port 8
4
P80-P83
Port 9
4
P90-P93
INTBT
Timer/event
counter
#0
TI0/P13
PTO0/P20
Port 0
CY
Program
counter (15)
ALU
INTT0
Watch
timer
BUZ/P23
INTW
Timer/pulse
generator
PPO/P80
INTTPG
SI0/SB1/P03
SO0/SB0/P02
SCK0/P01
Serial
interface 0
General register
ROM
program
memory
32640 × 8
Decode
and control
RAM data
memory
1024 × 4
10
T0-T9
4
T10/S15/PH3/P153T13/S12/PH0/P150
2
T14/S11/P143 and
T15/S10/P142
10
S0/P120-S9/P141
8
S16/P100-S23/P113
INTCSI0
SI1/P83
SO1/P82
SCK1/P81
Serial
interface 1
FIP
controller/
driver
fX /2
INT0/P10
INT1/P11
INT2/P12
INT4/P00
Interrupt
control
Clock
output
control
BLOCK DIAGRAM
4
Basic
interval
timer
N
Clock
divider
Clock
generator
Sub
Stand by
control
CPU clock
Φ
VLOAD
Main
Port 10-15 24
P100-P153
TI0
Event
counter
XT1XT2 X1 X2
RESET
8
VDD
VSS
VDD
A/D
converter
Bit sequential
buffer (16)
Note Port 4 and port 5 are N-ch open-drain I/O ports with a
medium withstand voltage of 10 V.
µPD75238
AN0-AN3
AN4/P90-AN7/P93
AVDD
AVREF
AVSS
PCL/P22
µPD75238
CONTENTS
1.
2.
3.
4.
5.
PIN FUNCTIONS ........................................................................................................................
7
1.1
PORT PINS ......................................................................................................................................
7
1.2
NON-PORT PINS ............................................................................................................................
9
1.3
PIN INPUT/OUTPUT CIRCUITS ....................................................................................................
11
1.4
CONNECTION OF UNUSED µPD75238 PINS ..............................................................................
15
ARCHITECTURE AND MEMORY MAP OF THE µPD75238 ...................................................
16
2.1
DATA MEMORY BANK CONFIGURATION AND ADDRESSING MODES ................................
16
2.2
GENERAL REGISTER BANK CONFIGURATION ..........................................................................
19
2.3
MEMORY-MAPPED I/O .................................................................................................................
22
INTERNAL CPU FUNCTIONS ....................................................................................................
27
3.1
PROGRAM COUNTER (PC) ...........................................................................................................
27
3.2
PROGRAM MEMORY (ROM) ........................................................................................................
27
3.3
DATA MEMORY (RAM) .................................................................................................................
29
3.4
GENERAL REGISTERS ...................................................................................................................
31
3.5
ACCUMULATORS ..........................................................................................................................
32
3.6
STACK POINTER (SP) AND STACK BANK SELECT REGISTER (SBS) .....................................
32
3.7
PROGRAM STATUS WORD (PSW) ..............................................................................................
35
3.8
BANK SELECT REGISTER (BS) .....................................................................................................
39
PERIPHERAL HARDWARE FUNCTIONS ..................................................................................
40
4.1
DIGITAL I/O PORTS .......................................................................................................................
40
4.2
CLOCK GENERATOR ......................................................................................................................
49
4.3
CLOCK OUTPUT CIRCUIT .............................................................................................................
58
4.4
BASIC INTERVAL TIMER ...............................................................................................................
61
4.5
TIMER/EVENT COUNTER .............................................................................................................
63
4.6
CLOCK TIMER .................................................................................................................................
69
4.7
TIMER/PULSE GENERATOR .........................................................................................................
71
4.8
EVENT COUNTER ..........................................................................................................................
77
4.9
SERIAL INTERFACE .......................................................................................................................
79
4.10
A/D CONVERTER ...........................................................................................................................
113
4.11
BIT SEQUENTIAL BUFFER ............................................................................................................
119
4.12
FIP CONTROLLER/DRIVER ............................................................................................................
119
INTERRUPT FUNCTION ............................................................................................................ 131
5.1
CONFIGURATION OF THE INTERRUPT CONTROL CIRCUIT ....................................................
131
5.2
HARDWARE OF THE INTERRUPT CONTROL CIRCUIT ..............................................................
133
5.3
INTERRUPT SEQUENCE ................................................................................................................ 138
5.4
MULTIPLE INTERRUPT PROCESSING CONTROL ......................................................................
139
5.5
VECTOR ADDRESS SHARE INTERRUPT PROCESSING ............................................................
141
5
µPD75238
6.
STANDBY FUNCTION ............................................................................................................... 142
6.1
SETTING OF STANDBY MODES AND OPERATION STATUSES .............................................
6.2
RELEASE OF THE STANDBY MODES ......................................................................................... 144
142
6.3
OPERATION AFTER A STANDBY MODE IS RELEASED ............................................................
146
7.
RESET FUNCTION ..................................................................................................................... 147
8.
INSTRUCTION SET .................................................................................................................... 150
9.
8.1
µPD75238 INSTRUCTIONS ............................................................................................................ 150
8.2
INSTRUCTION SET AND ITS OPERATION .................................................................................. 153
8.3
INSTRUCTION CODES OF EACH INSTRUCTION .......................................................................
162
SPECIFICATION OF MASK OPTIONS ...................................................................................... 168
10. APPLICATION BLOCK DIAGRAM ............................................................................................. 169
11. ELECTRICAL CHARACTERISTICS ............................................................................................. 170
★
12. CHARACTERISTIC CURVES (FOR REFERENCE) ..................................................................... 181
13. PACKAGE DIMENSIONS ........................................................................................................... 183
14. RECOMMENDED SOLDERING CONDITIONS ......................................................................... 184
APPENDIX A
µPD75238 SERIES PRODUCT FUNCTION LIST .................................................. 185
APPENDIX B
DEVELOPMENT TOOLS ......................................................................................... 186
6
µPD75238
1. PIN FUNCTIONS
1.1
PORT PINS (1/2)
Pin name
I/O
Also
used as
P00
I
INT4
P01
SCK0
P02
SO0/SB0
P03
SI0/SB1
P10
I
INT1
P12
INT2
P13
TI0
I/O
PTO0
P21
–
P22
PCL
P23
BUZ
P30Note 2
I/O
–
P31Note 2
–
P32Note 2
–
P33Note 2
–
4-bit I/O port (port 2).
Pull-up resistors can be provided by software
in units of 4 bits.
Programmable 4-bit I/O port (port 3).
Input/output can be specified bit by bit.
Pull-up resistors can be provided by software
in units of 4 bits.
N-ch open-drain 4-bit I/O port (port 4).
A pull-up resistor can be provided bit by bit
(mask option).
Withstand voltage is 10 V in open-drain mode.
P50-P53Note 2
I/O
–
N-ch open-drain 4-bit I/O port (port 5).
A pull-up resistor can be provided bit by bit
(mask option).
Withstand voltage is 10 V in open-drain mode.
P60
I/O
–
Programmable 4-bit I/O port (port 6).
Input/output can be specified bit by bit.
Pull-up resistors can be provided by software
in units of 4 bits.
–
P63
–
P70
I/O
–
P71
–
P72
–
P73
–
B
F-A
×
Input
B-C
×
Input
E-B
×
Input
E-C
4-bit input port (port 1).
Pull-up resistors can be provided by software
in units of 4 bits.
–
P62
Input
I/ONote 1
circuit
type
M-C
With noise elimination function
I/O
–
×
When reset
F-B
P40-P43Note 2
P61
8-bit I/O
4-bit input port (port 0).
For P01 to P03, pull-up resistors can be
provided by software in units of 3 bits.
INT0
P11
P20
Function
4-bit I/O port (port 7).
A pull-down resistor can be provided bit by bit
(mask option).
❍
❍
High level
(when a pull-up
resistor is
provided) or
high impedance
M
High level
(when a pull-up
resistor is
provided) or
high impedance
M
Input
VSS level (when
a pull-down
resistor is
provided) or
high impedance
E-C
V
Notes 1. The circuits enclosed in circles have a Schmitt-triggered input.
2. An LED can be driven directly.
7
µPD75238
1.1
PORT PINS (2/2)
I/O
Also
used as
P80
I/O
PPO
P81
I/O
SCK1
F
P82
I/O
SO1
E
P83
I
SI1
P90
I
AN4
P91
AN5
P92
AN6
P93
AN7
P100
O
S16
P101
S17
P102
S18
P103
S19
P110
O
S20
P111
S21
P112
S22
P113
S23
P120
O
S0
P121
S1
P122
S2
P123
S3
P130
O
S4
P131
S5
P132
S6
P133
S7
P140
O
S8
P141
S9
P142
S10/T15
P143
S11/T14
P150
O
Function
4-bit input port (port 8).
Y-A
P-ch open-drain, 4-bit high-voltage output port.
Pull-down resistors can be provided (mask
option).
❍
VLOAD level
I-F
(when pulldown resistor
to VLOAD is
provided), VSS
level (when pull-
P-ch open-drain, 4-bit high-voltage output port.
Pull-down resistors can be provided (mask
option).
down resistor to
VSS is pro-
vided), or highimpedance
P-ch open-drain, 4-bit high-voltage output port.
Pull-down resistors can be provided (mask
option).
❍
P-ch open-drain, 4-bit high-voltage output port.
Pull-down resistors can be provided (mask
option).
P-ch open-drain, 4-bit high-voltage output port.
Pull-down resistors can be provided (mask
option).
P142 and P143 can drive LED directly.
❍
S12/T13/PH0 P-ch open-drain, 4-bit high-voltage output port.
P153
S15/T10/PH3
PH3
A
B
S14/T11/PH2
PH2
Input
Input
P152
PH1
×
When reset
×
S13/T12/PH1 Pull-down resistors can be provided (mask
O
8-bit I/O
4-bit input port (port 9)
P151
PH0
option).
LED can be driven directly.
S12/T13/P150 P-ch open-drain, 4-bit high-voltage output port.
S13/T12/P151 Pull-down resistors can be provided (mask
option).
S14/T11/P152
S15/T10/P153
Note The circuits enclosed in circles have a Schmitt-triggered input.
8
I/ONote
circuit
type
Pin name
×
VLOAD level
(when pulldown resistor
to VLOAD is
provided) or
highimpedance
I-C
µPD75238
1.2
NON-PORT PINS (1/2)
Pin name
I/O
T0-T9
O
Also
used as
Function
Output pins
for FIP
controller/
PH3/P153driver.
PH0/P150
Allows pulldown
resistor to
P143
be provided
(mask
P142
option).
High-voltage, large-current output for digit
output
S0-S3
P120-P123
S4-S7
P130-P133
High-voltage output for segment output.
Usable for port 12 to port 14 in static mode.
S8
P140
S9
P141
S16-S19
P100-P103
S20-S23
P110-P113
T10/S15T13/S12
T14/S11
T15/S10
–
High-voltage, large-current output usable
for digit/segment output as well.
Any unused pins can be used for port H.
Usable for port 15 in static mode.
High-voltage, large-current output usable
for digit/segment output as well.
Usable for port 14 in static mode.
High-voltage output for segment output.
Usable for port 10 and port 11 in static
mode.
When reset
I/O
circuit
type
VLOAD level
(when
pull-down
resistor to
VLOAD is
provided)
or highimpedance
I-C
VLOAD level
(when
pull-down
resistor to
VLOAD is
provided),
VSS level
(when
pull-down
resistor to
VSS is
provided),
or highimpedance
I-F
9
µPD75238
1.2
NON-PORT PINS (2/2)
I/O
Also
used as
TI0
I
P13
External event pulse input for timer/event counter #0 and
event counter #1.
PTO0
O
P20
PCL
O
BUZ
Function
–
B-C
Timer/event counter output
Input
E-B
P22
Clock output
Input
E-B
O
P23
Fixed frequency output (for buzzer or system clock trimming)
Input
E-B
SCK0
I/O
P01
Serial clock I/O
Input
F-A
SO0/SB0
I/O
P02
Serial data output or serial bus I/O
Input
F-B
SI0/SB1
I/O
P03
Serial data input or serial bus I/O
Input
M-C
INT4
I
P00
Edge detection vectored interrupt input (Either a rising or
falling edge is detected.)
–
B
INT0
I
P10
Edge detection vectored interrupt input
(The edge to be detected is selectable.)
Synchronous
–
B-C
Asynchronous
–
B-C
INT1
P11
Asynchronous
INT2
I
P12
Edge detection testable input
(An rising edge is detected.)
SCK1
I/O
P81
Serial clock I/O
Input
F
SO1
O
P82
Serial data output
Input
E
SI1
I
P83
Serial data input
Input
B
AN0-AN3
I
–
–
Y
AN4-AN7
Analog input to A/D converter
Y-A
P90-P93
AVDD
–
–
Power supply for A/D converter
–
–
AVREF
I
–
A/D converter reference voltage input
–
Z
AVSS
–
–
A/D converter reference GND
–
–
X1, X2
I
–
Connection to a crystal/ceramic resonator for main system
clock generation. When external clock is used, it is input to
X1, and its inverted signal is input to X2.
–
–
XT1
I
–
–
–
XT2
–
Connection to a crystal resonator for subsystem clock
generation. When external clock is used, it is input to XT1,
and XT2 is left open.
RESET
I
–
System reset input
–
B
PPO
O
P80
Input
–
VDD (3 pins)
–
–
Positive power supply
–
–
VSS (2 pins)
–
–
GND potential
–
–
VLOAD
–
–
Pull-down resistor connection for the FIP controller/driver,
or power supply
–
–
Note
10
I/ONote
When reset circuit
type
Pin name
Timer/pulse generator pulse output
The circuits enclosed in circles have a Schmitt-triggered input.
µPD75238
1.3
PIN INPUT/OUTPUT CIRCUITS (1/4)
Type A
Type D
VDD
VDD
Data
P-ch
P-ch
OUT
IN
Output
disable
N-ch
N-ch
Push-pull output which can be set to high-impedance output
(off for both P-ch and N-ch)
CMOS input buffer
Type B
Type E
Data
IN/OUT
Type D
Output
disable
IN
Type A
I/O circuit consisting of a push-pull output
of type D and an input buffer of type A
Schmitt trigger input with hysteresis
Type B - C
Type E - B
VDD
P.U.R.
VDD
Output
disable
P.U.R.
P-ch
P.U.R.
enable
P-ch
Data
IN/OUT
Type D
Output
disable
IN
Type A
P.U.R.: Pull-Up Resistor
Schmitt trigger input with hysteresis
P.U.R.: Pull-Up Resistor
11
µPD75238
1.3
PIN INPUT/OUTPUT CIRCUITS (2/4)
Type E - C
VDD
Type F - B
P.U.R.
VDD
P.U.R.
P.U.R.
enable
P.U.R.
enable
Output
disable
(P-ch)
P-ch
Data
P-ch
VDD
P-ch
IN/OUT
Type D
IN/OUT
Data
Output
disable
Output
disable
N-ch
Output
disable
(N-ch)
Type A
Type B
P.U.R.: Pull-Up Resistor
P.U.R.: Pull-Up Resistor
Type F
VDD
Type F - C
P.U.R.
P.U.R.
enable
Data
IN/OUT
P-ch
Data
IN/OUT
Type D
Type D
Output
disable
Output
disable
Type B
Type B
P.U.R.: Pull-Up Resistor
I/O circuit consisting of a push-pull output of type D
and a Schmitt-triggered input of type B
Type F - A
Type I - C
VDD
P.U.R.
VDD
P.U.R.
enable
VDD
P-ch
Data
IN/OUT
Data
P-ch
P-ch
Type D
Output
disable
OUT
N-ch
P.D.R.
(Mask option)
Type B
P.U.R.: Pull-Up Resistor
12
VLOAD
P.D.R.: Pull-Down Resistor
µPD75238
1.3
PIN INPUT/OUTPUT CIRCUITS (3/4)
Type I - F
Type V
VDD
VDD
Data
IN/OUT
Type D
Data
P-ch
Output
disable
P-ch
OUT
P.D.R.
(Mask option)
N-ch
Type A
P.D.R.
(Mask option)
VLOAD
P.D.R.: Pull-Down Resistor
P.D.R.: Pull-Down Resistor
Type M
Type Y
VDD
AVDD
P.U.R.
(Mask option)
IN/OUT
P-ch
IN
Data
+
Sampling C
N-ch
AVDD
N-ch
Output
disable
–
AVSS
AVSS
AVSS
Reference voltage
(from voltage tap of
serial resistor string)
Middle-voltage input buffer
P.U.R.: Pull-Up Resistor
Type M - C
Type Y - A
VDD
P.U.R.
P.U.R.
enable
AVDD
P-ch
P-ch
IN
IN/OUT
Data
N-ch
+
AVDD
N-ch
Output
disable
Sampling C
–
AVSS
AVSS
Type B
AVSS
Reference voltage
(from voltage tap of
serial resistor string)
P.U.R.: Pull-Up Resistor
13
µPD75238
1.3
PIN INPUT/OUTPUT CIRCUITS (4/4)
Type Z
AVSS
14
µPD75238
1.4
CONNECTION OF UNUSED µPD75238 PINS
Pin name
Recommended connection
P00/INT4
To be connected to VSS
P01/SCK0
To be connected to VSS or VDD
P02/SO0/SB0
P03/SI1/SB1
P10/INT0-P12/INT2
To be connected to VSS
P13/TI0
P20/PTO0
P21
Input state : To be connected to VSS or VDD
Output state : To be left open
P22/PCL
P23/BUZ
P30-P33
P40-P43
P50-P53
P60-P63
P70-P73
P80/PPO
To be connected to VSS
P81/SCK1
P82/SO1
P83/SI1
P90/AN4-P93/AN7
P100/S16-P103/S19
To be left open
P110/S20-P113/S23
P120-P123
P130-P133
P140-P143
P150-P153
AN0-AN3
To be connected to VSS
AVREF
AVDD
To be connected to VDD
AVSS
To be connected to VSS
XT1
To be connected to VSS or VDD
XT2
To be left open
VLOAD
To be connected to VSS
15
µPD75238
2. ARCHITECTURE AND MEMORY MAP OF THE µPD75238
The µPD75238 has three architectural features:
(a) Data memory bank configuration
(b) General register bank configuration
(c) Memory-mapped I/O
Each of these features is explained below.
2.1
DATA MEMORY BANK CONFIGURATION AND ADDRESSING MODES
As shown in Fig. 2-1, the data memory space of the µPD75238 contains a static RAM (928 words × 4 bits)
at addresses 000H to 19FH and 200H to 3FFH, a display data memory (96 words × 4 bits) at addresses 1A0H
to 1FFH, and peripheral hardware (such as I/O ports and timers) at addresses F80H to FFFH. To address a 12bit address in this data memory space, the µPD75238 uses such a memory bank configuration that the loworder eight bits are specified with an instruction directly or indirectly, and the high-order four bits are used
to specify a memory bank (MB).
To specify a memory bank (MB), a memory bank enable flag (MBE) and memory bank select register (MBS)
are contained, allowing the addressing indicated in Fig. 2-1 and Table 2-1. (The MBS is a register used to select
a memory bank, and can be set to 0, 1, 2, 3, or 15. The MBE is a flag used to determine whether a memory
bank selected using the MBS register is to be enabled. The MBE is automatically saved or restored at the time
of interrupt processing or subroutine processing, so that it can be freely set in interrupt processing and
subroutine processing.)
In addressing data memory space, the MBE is usually set to 1 (MBE = 1), and the static RAM in the memory
bank specified by the MBS is operated. However, the MBE = 0 mode or the MBE = 1 mode can be selected
for each step of program processing for more efficient programming.
Applicable program processing
16
MBE = 0 mode
• Interrupt processing
• Processing that repeats internal hardware and static RAM operations
• Subroutine processing
MBE = 1 mode
• Usual program processing
µPD75238
Fig. 2-1
Data Memory Organization and Addressing Range of Each Addressing Mode
Addressing mode
Memory bank enable flag
MBE
=0
MBE
=1
@HL
@H + mem.bit
MBE
=0
MBE
=1
@DE
@DL
–
Stack
pmem.
address- fmem.bit
@L
ing
–
–
–
General
resister
area
000H
01FH
020H
07FH
mem
mem.bit
MBS
=0
MBS
=0
SBS
=0
MBS
=1
MBS
=1
SBS
=1
Data area
Static RAM
(memory bank 2)
MBS
=2
MBS
=2
SBS
=2
Data area
Static RAM
(memory bank 3)
MBS
=3
MBS
=3
SBS
=3
MBS
= 15
MBS
= 15
Data area
Static RAM
(memory bank 0)
0FFH
100H
Data area
Static RAM
(memory bank 1)
19FH
1A0H
Display data
memory area
1FFH
200H
Stack area
2FFH
300H
3FFH
Not contained
F80H
Peripheral hardware area
(memory bank 15)
FC0H
FFFH
Remark — : Don’t care
17
µPD75238
Table 2-1
Addressing mode
Representation
format
1-bit direct addressing
mem.bit
4-bit direct addressing
mem
Addressing Modes
Specified address
Bit specified by bit at the address specified by MB and mem. In this case:
When MBE = 0 and mem = 00H-7FH, MB = 0
When MBE = 0 and mem = 80H-FFH, MB = 15
When MBE = 1, MB = MBS
Address specified by MB and mem. In this case:
When MBE = 0 and mem = 00H-7FH, MB = 0
When MBE = 0 and mem = 80H-FFH, MB = 15
When MBE = 1, MB = MBS
Address specified by MB and mem (mem: even address). In this case:
When MBE = 0 and mem = 00H-7FH, MB = 0
When MBE = 0 and mem = 80H-FFH, MB = 15
8-bit direct addressing
When MBE = 1, MB = MBS
4-bit register indirect
addressing
8-bit register indirect
addressing
Bit manipulation
addressing
@HL
Address specified by MB and HL. In this case, MB = MBE• MBS
@HL+
@HL–
Address specified by MB and HL. In this case, MB = MBE• MBS.
HL+ automatically increments the L register after addressing.
HL- automatically decrements the L register after addressing.
@DE
Address specified by DE in memory bank 0
@DL
Address specified by DL in memory bank 0
@HL
Address specified by MB and HL.
In this case, MB = MBE• MBS. Bit 0 of the L resister is ignored.
fmem.bit
pmem.@L
Bit specified by bit at the address specified by fmem. In this case:
fmem = FB0H-FBFH (interrupt-related hardware)
fmem = FF0H-FFFH (I/O port)
Bit specified by the low-order 2 bits of the L register at the address specified
by the high-order 10 bits of pmem and the high-order 2 bits of the L register.
In this case, pmem = FC0H-FFFH
@H+mem.bit Bit specified by bit at the address specified by MB, H, and the low-order 4 bits
of mem.
In this case, MB = MBE• MBS
Stack addressing
–
Address specified by SP in memory bank 0, 1, 2, and 3 selected by SBS
As summarized in Table 2-1, the µPD75238 allows both direct and indirect addressing in data memory
manipulation for 1-bit data, 4-bit data, and 8-bit data, so that very efficient and simple programming can be
performed.
18
µPD75238
2.2
GENERAL REGISTER BANK CONFIGURATION
The µPD75238 contains four register banks, each consisting of eight general registers: X, A, B, C, D, E, H,
and L. These registers are mapped to addresses 00H to 1FH in memory bank 0 of the data memory. (See Fig.
2-2.) To specify a general register bank, a register bank enable flag (RBE) and a register bank select register
(RBS) are contained. The RBS is a register used to select a register bank, and the RBE is a flag used to determine
whether a register bank selected using the RBS is to be enabled. The register bank (RB) enabled at instruction
execution is determined as RB = RBE• RBS
As indicated in Table 2-2, the µPD75238 enables the user to create programs in a very efficient manner by
selecting a register bank from the four register banks, depending on whether the processing is normal
processing or interrupt processing. (The RBE is automatically saved and set at the time of interrupt processing,
and is automatically restored upon completion of interrupt processing.)
Table 2-2
Recommended Use of Register Banks with Normal Routines and Interrupt Routines
Normal processing
Use register banks 2 and 3 with RBE = 1.
Single interrupt processing
Use register bank 0 with RBE = 0.
Dual interrupt processing
Use register bank 1 with RBE = 1.
(In this case, the RBS needs to be saved and restored.)
Multiple (triple or more) interrupt processing
Save and restore the registers with PUSH or POP.
The general registers allow transfers, comparisons, arithmetic/logical operations, and increments and
decrements not only on a 4-bit basis, but also on an 8-bit basis with the XA, HL, DE, and BC register pairs.
In this case, the register pairs of the register bank that has the inverted value of bit 0 of a register bank specified
by RBE• RBS can be specified as XA’, HL’, DE’, and BC’, thus providing eight 8-bit registers. (See Fig. 2-3.)
19
µPD75238
Fig. 2-2
General Register Configuration (4-Bit Processing)
X
A
01H
H
00H
L
03H
D
02H
E
05H
B
04H
C
07H
X
06H
A
09H
H
08H
L
0BH
D
0AH
Register bank 1
(RBE•RBS = 1)
E
0DH
B
0CH
C
0FH
X
0EH
A
11H
H
10H
L
13H
D
12H
Register bank 2
(RBE•RBS = 2)
E
15H
B
14H
C
17H
X
16H
A
19H
H
18H
L
1BH
D
1AH
E
1DH
B
1CH
C
1FH
20
Register bank 0
(RBE•RBS = 0)
1EH
Register bank 3
(RBE•RBS = 3)
µPD75238
Fig. 2-3
General Register Configuration (8-Bit Processing)
XA’
XA
00H
00H
HL’
HL
02H
02H
DE’
DE
04H
04H
BC’
BC
06H
06H
When RBE•RBS
=0
When RBE•RBS
=1
XA
XA’
08H
08H
HL
HL’
0AH
0AH
DE
DE’
0CH
0CH
BC
BC’
0EH
0EH
XA’
XA
10H
10H
HL’
HL
12H
12H
DE’
DE
14H
14H
BC’
BC
16H
16H
When RBE•RBS
=2
When RBE•RBS
=3
XA
XA’
18H
18H
HL
HL’
1AH
1AH
DE
DE’
1CH
1CH
BC
BC’
1EH
1EH
21
µPD75238
2.3
MEMORY-MAPPED I/O
The µPD75238 employs memory-mapped I/O, which maps peripheral hardware such as timers and I/O ports
to addresses F80H to FFFH in the data memory space as shown in Fig. 2-1. This means that there is no particular
instruction to control peripheral hardware, but all peripheral hardware is controlled using memory manipulation instructions. (Some mnemonics for hardware control are available to make programs readable.)
To manipulate peripheral hardware, the addressing modes listed in Table 2-3 can be used.
The display data memory, key scan registers, and port H mapped to addresses 1A0H to 1FFH are to be
manipulated by specifying memory bank 1.
Table 2-3
Addressing Modes Applicable to Peripheral Hardware Mapped to Addresses F80H to FFFH
Applicable hardware
Applicable addressing mode
Bit manipulation
Direct addressing mode specifying mem.bit with MBE = 0 or
(MBE = 1, MBS = 15)
All hardware allowing bit
manipulation
Direct addressing mode specifying fmem.bit regardless of MBE
and MBS setting
IST0, IST1, MBE, RBE,
IE×××, IRQ×××, PORTn.0-3
Indirect addressing mode specifying pmem.@L regardless of
MBE and MBS setting
PORTn.
4-bit manipulation Direct addressing mode specifying mem with MBE = 0 or (MBE
= 1, MBS = 15)
All hardware allowing 4-bit
manipulation
Register indirect addressing mode specifying @HL with (MBE
= 1, MBS = 15)
8-bit manipulation Direct addressing mode specifying mem (even address) with
MBE = 0 or (MBE = 1, MBS = 15)
All hardware allowing 8-bit
manipulation addressing
Register indirect addressing mode specifying @HL (with the L
register containing an even number) with (MBE = 1, MBS = 15)
Table 2-4 summarizes the I/O map of the µPD75238.
The items in Table 2-4 have the following meanings:
• Symbol:
Name representing the address of incorporated hardware, which can be coded in the operand
field of an instruction
• R/W
:
Indicates whether the hardware allows read/write operation.
R/W: Both read and write operations possible
R
: Read only
W
: Write only
• Number of manipulatable bits:
Indicates the number of bits that can be processed in hardware manipulation
• Bit manipulation addressing:
Bit manipulation addressing applicable in hardware bit manipulation
22
µPD75238
µPD75238 I/O Map (1/4)
Table 2-4
Hardware name (symbol)
Address
b3
b2
b1
F80H
Stack pointer (SP)
F82H
Resister bank select register (RBS)
F83H
Memory bank select register (MBS)
F84H
Stack bank select register (SBS)
F85H
R/W
b0
Number of manipulatable bits
Bit manipulation ad1 bit 4 bits 8 bits dressing
R/W
–
RNote 1
–
Remarks
Bit 0 is always set to
0.
–
★
Note 2
–
R/W
–
–
Basic interval timer mode register (BTM)
W
∆
–
F86H
Basic interval timer (BT)
R
–
F88H
Display mode register (DSPM)
W
–
–
F89H
Dimmer select register (DIMS)
W
–
–
R/W
∆
–
W
∆
∆
R/W
–
–
R/W
–
–
F8AH
KSF
Digit select register (DIGS)
F90H
Timer pulse generator mode register (TPGM)
F94H
Timer pulse generator modulo register L
(MODL)
F96H
Bits 2 and 3 are
always set to 0.
mem.bit
Only bit 3 allows bit
manipulation.
mem.bit
Only bit 3 allows a
bit test.
mem.bit
Only bit 3 allows bit
manipulation.
–
Timer pulse generator modulo register H (MODH)
F98H
Clock mode register (WM)
W
–
–
FA0H
Timer/event counter 0 mode register (TM0)
W
∆
–
–
–
FA2H
TOE0
W
–
FA4H
Timer/event counter 0 count register (T0)
R
–
–
FA6H
Timer/event counter 0 modulo register (TMOD0)
W
–
–
FA8H
Event counter mode register (TM1)
W
∆
–
–
–
FABH
FACH
Gate control register (GATEC)
Count register (T1)
Notes 1.
2.
W
R
–
–
Only bit 3 allows bit
manipulation.
–
Only bit 3 allows bit
manipulation.
–
–
For the SEL instruction, these registers are both readable and writable.
Can be operated separately as the RBS and MBS during 4-bit manipulation.
Can also be operated as the BS during 8-bit manipulation.
23
µPD75238
Table 2-4
Hardware name (symbol)
Address
FB0H
µPD75238 I/O Map (2/4)
R/W
b3
b2
b1
b0
IST1
IST0
MBE
RBE
★
W
FB3H
Processor clock control register (PCC)
W
FB4H
INT0 mode register (IM0)
W
–
FB5H
INT1 mode register (IM1)
W
–
FB7H
System clock control register (SCC)
W
IRQ4
IEBT
IRQBT
R/W
EOT
R/W
IEW
IRQW
R/W
IRQKS
IETPG
IRQTPG
R/W
IRQT1
IET0
IRQT0
R/W
IECSI0
IRQCSI0
R/W
IE0
IRQ0
R/W
FBFH
IE2
IRQ2
R/W
FC0H
Bit sequential buffer 0 (BSB0)
R/W
FC1H
Bit sequential buffer 1 (BSB1)
R/W
FC2H
Bit sequential buffer 2 (BSB2)
R/W
FC3H
Bit sequential buffer 3 (BSB3)
R/W
FB9H
FBAH
FBBH
IEKS
FBCH
FBDH
FBEH
IE1
FC8H
FC9H
FCCH
24
–
Interrupt priority select register (IPS)
IE4
IRQ1
CSIM11
CSIE1
Serial I/O shift register 1 (SIO1)
CSIM10
W
–
–
Bits 1, 2, and 3 are
always set to 0.
–
–
–
–
–
–
–
–
–
Bit 2 is always set to
0.
–
–
W
R/W
Remarks
fmem.bit
FB2H
FB8H
★
Bit manipulation ad1 bit 4 bits 8 bits dressing
R/W
Program status word (PSW)
★
Number of manipulatable bits
–
Only bits 0 and 3
allow bit manipulation.
fmem.bit
µPD75238
µ PD75238 I/O Map (3/4)
Table 2-4
Hardware name (symbol)
Address
b3
b2
R/W
b1
b0
Number of manipulatable bits
Bit manipulation ad1 bit 4 bits 8 bits dressing
FD0H
Clock output mode register (CLOM)
W
–
FD4H
Static mode register B (STATB)
W
–
–
FD6H
Static mode register A (STATA)
W
–
–
R/W
∆
–
–
–
FD8H
SOC
EOC
A/D conversion mode register (ADM)
–
FDAH
SA register (SA)
R
–
–
FDCH
Pull-up resistor specification register group
A (POGA)
W
–
–
FE0H
Serial operation mode register (CSIM0)
W
–
–
FE2H
CSIE0
COI
WUP
CMDD
RELD
CMDT
ADM is write only
during 8-bit manipulation.
R/W
RELT
mem.bit
R/W
Remarks
–
–
CSIM0 is write only
during 8-bit manipulation.
mem.bit
SBI control register (SBIC)
BSYE
ACKD
ACKE
FE4H
Serial I/O shift register 0 (SIO0)
FE6H
Slave address register (SVA)
FE8H
PM33
PM32
PM31
ACKT
PM30
R/W
–
–
W
–
–
W
–
–
W
–
–
Port mode register group A (PMGA)
FECH
PM63
PM62
PM61
PM60
–
PM2
–
–
Port mode register group B (PMGB)
PM7
–
PM5
PM4
25
★
µPD75238
Table 2-4
µPD75238 I/O Map (4/4)
Hardware name (symbol)
Address
b3
b2
b1
R/W
b0
FF0H
Port 0 (PORT0)
FF1H
Port 1 (PORT1)
R
FF2H
Port 2 (PORT2)
R/W
FF3H
Port 3 (PORT3)
R/W
FF4H
Port 4 (PORT4)
R/W
FF5H
Port 5 (PORT5)
R/W
FF6H
Port 6 (PORT6)
R/W
FF7H
Port 7 (PORT7)
R/W
FF8H
Port 8 (PORT8)
R
FF9H
Port 9 (PORT9)
R
FFAH
Port 10 (PORT10)
W
FFBH
Port 11 (PORT11)
W
FFCH
Port 12 (PORT12)
W
FFDH
Port 13 (PORT13)
W
FFEH
Port 14 (PORT14)
W
FFFH
Port 15 (PORT15)
W
R
1A0H+4n Display data memory: S16-S23 (n = 0 to 15)
R/W
1A1H+4n
R/W
1BEH
Key scan register (KS2)
1BFH
R/W
R/W
1C0H+4n Display data memory: S0-S7 (n = 0 to 15)
R/W
1C1H+4n
R/W
1C2H+4n Display data memory: S8-S15 (n = 0 to 15)
R/W
1C3H+4n
R/W
1FCH
Key scan register (KS0)
1FDH
26
R/W
R/W
1FEH
Key scan register (KS1)
R/W
1FFH
Port H (PORTH)
R/W
Number of manipulatable bits
Bit manipulation ad1 bit 4 bits 8 bits dressing
–
fmem.bit
pmem.@L
–
–
mem.bit
Remarks
µPD75238
3. INTERNAL CPU FUNCTIONS
3.1
PROGRAM COUNTER (PC): 15 BITS
The program counter is a 15-bit binary counter for holding program memory address information.
Fig. 3-1 Program Counter Format
PC14 PC13 PC12 PC11 PC10
PC9
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Note that the reset start address must be set within a space of 16K bytes (0000H to 3FFFH). This is because
a RESET input sets the low-order six bits of program memory address 0000H in PC13 to PC8, and the contents
of address 0001H in PC7 to PC0 for initialization.
3.2
PROGRAM MEMORY (ROM): 32640 WORDS × 8 BITS
The program memory is a mask-programmable ROM with a configuration of 32640 words × 8 bits for storing
programs, table data, and so forth.
Program memory is addressed by the program counter. Table data can be referenced using the table
reference instruction (MOVT).
Fig. 3-2 shows the allowable branch address ranges for the branch instructions and subroutine call
instructions. The whole-space branch instruction (BRA !addr1) and the whole-space call instruction (CALLA
!addr1) allow a direct branch throughout the whole space 0000H to 7F7FH. The relative branch instruction
(BR $addr) allows a branch to addresses (PC - 15 to PC - 1 and PC + 2 to PC + 16) regardless of block boundaries.
The program memory is located at addresses 0000H to 7F7FH containing the following specially assigned
addresses. (All areas excluding 0000H and 0001H can be used as normal program memory.)
• 0000H to 0001H
Vector table for holding the RBE and MBE setting values and program start address at the time of a RESET
input. A reset start can be performed at an arbitrary address within a 16K-byte space (0000H to 3FFFH).
• 0002H to 000FH
Vector address table for holding the RBE and MBE setting values and program start address at the time
of each vectored interrupt occurrence. Interrupt processing can be started at an arbitrary address within
a 16K-byte space (0000H to 3FFFH).
• 0020H to 007FH
Table area referenced by the GETI instructionNote
Note The GETI instruction can represent an arbitrary 2-byte or 3-byte instruction or two 1-byte instructions
in 1 byte, thus reducing the number of program bytes. (See Section 8.1.)
27
µPD75238
Fig. 3-2
Program Memory Map
0000H MBE RBE Internal reset start address (high-order 6 bits)
Internal reset start address (low-order 8 bits)
0002H MBE RBE INTBT/INT4 start address
(high-order 6 bits)
INTBT/INT4 start address
(low-order 8 bits)
0004H MBE RBE INT0 start address
(high-order 6 bits)
INT0 start address
(low-order 8 bits)
0006H MBE RBE INT1 start address
(high-order 6 bits)
INT1 start address
(low-order 8 bits)
0008H MBE RBE INTSO start address
(high-order 6 bits)
INTSO start address
(low-order 8 bits)
000AH MBE RBE INTT0 start address
(high-order 6 bits)
INTT0 start address
(low-order 8 bits)
000CH MBE RBE INTTPG start address
(high-order 6 bits)
INTTPG start address
(low-order 8 bits)
000EH MBE RBE INTKS start address
(high-order 6 bits)
INTKS start address
(low-order 8 bits)
CALLF !faddr
instruction
entry address
BRA !addr
instruction
branch address
BRCB !caddr
instruction
branch address
CALLA !addr
instruction
branch address
BR $addr1 instruction
relative branch
address (–15 to –1,
+2 to +16)
BR !addr
instruction
branch address
0020H
GETI instruction reference table
007FH
0080H
07FFH
0800H
0FFFH
1000H
1FFFH
2000H
2FFFH
3000H
3FFFH
4000H
4FFFH
5000H
5FFFH
6000H
6FFFH
7000H
7F7FH
CALL !addr
instruction
branch address
Branch/call
address specified
in GETI instruction
BRCB !caddr
instruction
branch address
BRCB !caddr
instruction
branch address
BRCB !caddr
instruction
branch address
BRCB !caddr
instruction
branch address
BRCB !caddr
instruction
branch address
BRCB !caddr
instruction
branch address
BRCB !caddr
instruction
branch address
Caution The start address of an interrupt vector shown above consists of 14 bits. So, the start address
must be set within a 16K-byte space (0000H to 3FFFH).
Remark In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an address
with only the low-order 8 bits of the PC changed.
28
µPD75238
3.3
DATA MEMORY (RAM)
The data memory consists of a static RAM and peripheral hardware.
The static RAM consists of an area of 768 words × 4 bits in memory banks 0, 2, and 3, an area of 160 words
× 4 bits in memory bank 1, and an area of 96 words × 4 bits in memory bank 1, which is used also as display
data memory. The RAM is used for storing processing data, and is also used as stack memory for subroutine
and interrupt execution.
To particular memory addresses, general registers, display data memory, and peripheral hardware (various
registers) are mapped. Data in these areas are manipulated using general register manipulation instructions
and memory manipulation instructions (See Fig. 2-1).
As a stack area, all addresses in memory banks 0, 1, 2, and 3 (000H to 3FFH) can be used.
The data memory has a configuration of 4 bits per address, but allows 8-bit memory manipulation
instructions to be used for 8-bit oriented manipulation, and also allows bit manipulation instructions to be
used for bit-by-bit manipulation. Even addresses are to be specified for 8-bit manipulation instructions.
Fig. 3-4 shows the organization of the display data memory area (1A0H to 1FFH).
Fig. 3-3
Data Memory Map
Data memory
General
register
area
Memory bank
000H
(32 × 4)
01FH
0
020H
256 × 4
0FFH
100H
Stack
area
Data area
Static RAM
(1024 × 4)
256 × 4
Display
data
memory,
etc.
19FH
1A0H
1
(96 × 4)
1FFH
200H
256 × 4
2
256 × 4
3
2FFH
300H
3 FFH
Not contained
F80H
Peripheral
hardware area
128 × 4
15
FFFH
29
µPD75238
Number of
manipulatable bits
Fig. 3-4
Display Data Memory Configuration
1 A 1 H
1 A 0 H
1 C 3 H
1 C 2 H
1 C 1 H
1 C 0 H
1 A 3 H
1 A 2 H
1 C 7 H
1 C 6 H
1 C 5 H
1 C 4 H
1 A 5 H
1 A 4 H
1 C B H
1 C A H
1 C 9 H
1 C 8 H
1 A 7 H
1 A 6 H
1 C F H
1 C E H
1 C D H
1 C C H
1 A 9 H
1 A 8 H
1 D 3 H
1 D 2 H
1 D 1 H
1 D 0 H
1 A B H
1 A A H
1 D 7 H
1 D 6 H
1 D 5 H
1 D 4 H
1 A D H
1 A C H
1 D B H
1 D A H
1 D 9 H
1 D 8 H
1 A F H
1 A E H
1 D F H
1 D E H
1 D D H
1 D C H
1 B 1 H
1 B 0 H
1 E 3 H
1 E 2 H
1 E 1 H
1 E 0 H
1 B 3 H
1 B 2 H
1 E 7 H
1 E 6 H
1 E 5 H
1 E 4 H
1 B 5 H
1 B 4 H
1 E B H
1 E A H
1 E 9 H
1 E 8 H
1 B 7 H
1 B 6 H
1 E F H
1 E E H
1 E D H
1 E C H
1 B 9 H
1 B 8 H
1 F 3 H
1 F 2 H
1 F 1 H
1 F 0 H
1 B B H
1 B A H
1 F 7 H
1 F 6 H
1 F 5 H
1 F 4 H
1 B D H
1 B C H
1 F B H
1 F A H
1 F 9 H
1 F 8 H
1 B F H
1BEH(KS2)
1FFH(PORTH)
1FEH(KS1)
1 F D H
1FCH(KS0)
1
bit
4
bits
8
bits
Remarks 1. KS0, KS1, and KS2 are key scan registers.
2. PORTH is the high-voltage, high-current output port, and is also used for digit output.
30
µPD75238
3.4
GENERAL REGISTERS: 8 × 4 BITS × 4 BANKS
The general registers are mapped to particular addresses in data memory. Four banks of registers are
provided, with each bank consisting of eight 4-bit registers (B, C, D, E, H, L, X, A).
The register bank (RB) to be enabled at the time of instruction execution is determined by RB = RBE• RBS:
(RBS = 0 to 3)
Each general register allows 4-bit manipulation. In addition, BC, DE, HL, or XA serves as a register pair
for 8-bit manipulation. DL also makes a register pair as well as DE and HL; these three register pairs can be
used as data pointers.
A general register area can be addressed and accessed as normal RAM, regardless of whether it is used
as a register.
Address
3
General Register Format
Data memory
000H
A register
001H
X register
002H
L register
003H
H register
Fig. 3-6
3
0
E register
005H
D register
006H
C register
007H
B register
0
3
B
3
0
3
3
3
H
0
L
0
X
0
E
0
3
0
C
D
Register bank 0
004H
Register Pair Format
1 bank
Fig. 3-5
3
0
A
···········
008H
Same as bank 0
Register bank 1
Same as bank 0
Register bank 2
Same as bank 0
Register bank 3
00FH
···········
010H
017H
···········
018H
01FH
31
µPD75238
3.5 ACCUMULATORS
In the µPD75238, the A register and the XA register pair function as accumulators. The A register is mainly
used for 4-bit data processing instructions, and the XA register pair is mainly used for 8-bit data processing
instructions.
For a bit manipulation instruction, the carry flag (CY) functions as a bit accumulator.
Fig. 3-7
Accumulators
CY
X
3.6
Bit accumulator
A
4-bit accumulator
A
8-bit accumulator
STACK POINTER (SP) AND STACK BANK SELECT REGISTER (SBS)
The µPD75238 uses static RAM as stack memory (LIFO scheme), and the 8-bit register holding the start
address of the stack area is the stack pointer (SP).
The stack area is located at addresses 000H to 3FFH in memory banks 0, 1, 2, and 3. Either of the memory
banks is selected according to the value of the 4-bit SBS.
The SP is decremented before a write (save) operation to stack memory, and is incremented after a read
(restoration) operation from stack memory. The SBS is set with a 4-bit memory manipulation instruction. Note
that the high-order two bits are always set to 00.
Fig. 3-9 and 3-10 show data saved to and restored from stack memory in these stack operations.
To place the stack area at a given location, the SP can be initialized with an 8-bit memory manipulation
instruction, and the SBS can be initialized with a 4-bit memory manipulation instruction. Both can be read
from as well.
Table 3-1
Stack Area to Be Selected by the SBS
SBS1
0
0
1
1
--------------------
SBS
SBS2
Stack area
0
Memory bank 0
1
Memory bank 1
0
Memory bank 2
1
Memory bank 3
When the SP is initialized to 00H, a stack operation starts at the high-order address (nFFH) of memory bank
(n: n = 0, 1, 2, or 3) specified with the SBS.
A stack area must be within the memory bank specified with the SBS. If a stack operation exceeds address
n00H, the operation returns to address nFFH of the same bank. Stacking beyond memory bank boundaries
is enabled only by resetting the SBS.
A RESET signal occurrence causes the contents of the SP and the SBS to be undefined, so that the SP must
always be initialized to a desired value at the start of the program.
32
µPD75238
Fig. 3-8
Stack Bank Select Register Format
Address
F80H
Symbol
SP7
SP6
SP5
SP4
SP3
SP2
F84H
SP1
Always 0
SBS1
SBS0
SP
SBS
000H
SBS
Memory bank 0
SP
Memory bank 1
SP
Memory bank 2
SP
Memory bank 3
SP
0FFH
100H
1FFH
200H
2FFH
300H
3FFH
33
µPD75238
Fig. 3-9
Data Saved to Stack Memory
PUSH instruction
CALL, CALLA, or CALLF instruction
Interrupt
Stack
Stack
Stack
SP – 6
SP – 5
0
PC11 - PC8
SP – 6
PC14 PC13 PC12
SP – 5
0
PC14 PC13 PC12
SP – 2
Lower bits of pair register
SP – 4
PC3 - PC0
SP – 4
PC3 - PC0
SP – 1
Upper bits of pair register
SP – 3
PC7 - PC4
SP – 3
PC7 - PC4
SP – 2
IST1 IST0 MBE RBE
PSW
CY SK2 SK1 SK0
SP – 2
SP
*
*
MBE RBE
Note
SP – 1
*
*
*
SP – 1
*
SP
SP
Fig. 3-10
Data Restored from Stack Memory
POP instruction
RET or RETS instruction
RETI instruction
Stack
Stack
Stack
SP
Lower bits of pair register
SP
SP + 1
Upper bits of pair register
SP + 1
SP + 2
0
PC11 - PC8
SP
PC14 PC13 PC12
SP + 1
PC11 - PC8
0
PC14 PC13 PC12
SP + 2
PC3 - PC0
SP + 2
PC3 - PC0
SP + 3
PC7 - PC4
SP + 3
PC7 - PC4
SP + 4
IST1 IST0 MBE RBE
PSW
CY SK2 SK1 SK0
SP + 4
*
*
MBE RBE
Note
SP + 5
*
*
*
*
SP + 6
Note A PSW other than the MBE or RBE is not saved/restored.
Remark Data marked with * is undefined.
34
PC11 - PC8
SP + 5
SP + 6
µPD75238
3.7
PROGRAM STATUS WORD (PSW): 8 BITS
The program status word (PSW) consists of various flags closely associated with processor operations.
The PSW is mapped to addresses FB0H and FB1H in the data memory space. The four bits at address FB0H
can be manipulated with a memory manipulation instruction. Address FB1H cannot be manipulated with a
normal data memory manipulation instruction.
Fig. 3-11
Program Status Word Format
FB1H
Address
CY
SK2
SK1
FB0H
SK0
IST1
Cannot be manipulated
IST0
Symbol
MBE
RBE
PSW
Can be manipulated
Can be manipulated
by an instruction
specifically provided
for controlling this flag
Table 3-2
PSW Flags Saved/Restored in Stack Operation
Saved/restored flag
Save
Restore
When CALL, CALLA, or CALLF instruction is executed
MBE and RBE are saved.
When hardware interrupt occurs
All PSW bits are saved.
When RET or RETS instruction is executed
MBE and RBE are restored.
When RETI is executed
All PSW bits are restored.
35
µPD75238
(1) Carry flag (CY)
The carry flag is a 1-bit flag used to store overflow or underflow occurrence information when an arithmetic
operation with a carry (ADDC, SUBC) is executed.
The carry flag also has the function of a bit accumulator, and therefore can be used to store the result of
a Boolean operation performed on the CY and bit at a specified data memory bit address.
The carry flag is manipulated using special instructions, independently of the other PSW bits.
A RESET signal occurrence causes the carry flag to be undefined.
Table 3-3
Carry Flag Manipulation Instructions
Instruction (mnemonic)
Carry flag operation/processing
Instruction dedicated to
carry flag manipulation
SET1 CY
CLR1 CY
NOT1 CY
SKT CY
Sets CY to 1.
Clears CY to 0.
Inverts the contents of CY.
Skips if CY is set to 1.
Bit transfer instruction
MOV1 mem*.bit CY
MOV1 CY,mem*.bit
Transfers the contents of CY to a specified bit.
Transfers the contents of a specified bit to CY.
Bit Boolean instruction
AND1 CY,mem*.bit
OR1 CY,mem*.bit
XOR1 CY,mem*.bit
ANDs, ORs, or XORs CY with the contents of a specified bit, then
sets the result in CY.
Interrupt handling
Remark
Saves CY and all other PSW bits to stack memory in parallel.
Interrupt execution
------------------------------------------------------------------Restores CY together with the other PSW bits from stack memory.
RETI
mem*.bit represents the following three addressing modes:
• fmem.bit
• pmem.@L
• @H+mem.bit
(2) Skip flags (SK2, SK1, SK0)
The skip flags are used to store skip status, and are automatically set or reset when the CPU executes an
instruction.
The user cannot directly manipulate these flags as operands.
36
µPD75238
(3) Interrupt status flag (IST1, IST0)
The interrupt status flag is a 2-bit flag used to store the status of processing being performed. (For detailed
information, see Table 5-3.)
Table 3-4
Information Indicated by the Interrupt Status Flag
IST1
IST0
Status of processing
being performed
0
0
Status 0
Normal program processing is being performed.
Any interrupts are acceptable.
0
1
Status 1
A lower- or higher-priority interrupt is being serviced.
Higher-priority interrupts are acceptable.
1
0
Status 2
A higher-priority interrupt is being serviced.
No interrupts are acceptable.
1
1
—
Processing and interrupt control
Not to be set
The interrupt priority control circuit (see Fig. 5-1) checks this flag to control multiple interrupts.
The contents of the IST1 and IST0 are saved as part of the PSW to stack memory if an interrupt is accepted,
then are automatically set to a one-step higher status. The RETI instruction restores the contents present
before an interrupt occurs.
The interrupt status flag can be manipulated using a memory manipulation instruction, and the status of
processing being performed can be changed by program control.
Caution The user must always disable interrupts with the DI instruction before manipulating this flag,
and must enable interrupts with the EI instruction after manipulating this flag.
37
µPD75238
(4) Memory bank enable flag (MBE)
The memory bank enable flag is a 1-bit flag used to specify the address information generation mode for
the high-order four bits of a 12-bit data memory address.
When the MBE is set to 1, the data memory address space is expanded, allowing all data memory space
to be addressed.
When the MBE is reset to 0, the data memory address space is fixed, regardless of MBS setting. (See Fig.
2-1.)
A RESET input automatically initializes the MBE by setting the MBE to the content of bit 7 at program
memory address 0.
In vectored interrupt processing, the MBE is automatically set to the content of bit 7 in the vector address
table for servicing the interrupt.
Usually, the MBE is set to 0 in interrupt processing, and static RAM in memory bank 0 is used.
(5) Register bank enable flag (RBE)
The register bank enable flag is a 1-bit flag used to determine whether to expand the general register bank
configuration.
When the RBE is set to 1, a set of general registers can be selected from register banks 0 to 3, depending
on the setting of the register bank select register (RBS).
When the RBE is reset to 0, register bank 0 is always selected as general registers, regardless of the setting
of the RBS.
A RESET input automatically initializes the RBE by setting the RBE to the content of bit 6 at program
memory address 0.
When a vectored interrupt occurs, the RBE is automatically set to the content of bit 6 in the vector address
table for servicing the interrupt. Usually, the RBE is set to 0 in interrupt processing. Register bank 0 is
used for 4-bit processing, and register banks 0 and 1 are used for 8-bit processing.
38
µPD75238
3.8
BANK SELECT REGISTER (BS)
The bank select register consists of a register bank select register (RBS) and memory bank select register
(MBS), which specify a register bank and memory bank to be used, respectively.
The RBS and MBS are set using the SEL RBn instruction and SEL MBn instruction, respectively.
The contents of BS can be saved to or restored from a stack area eight bits at a time by using the PUSH
BS/POP BS instruction.
Fig. 3-12
Address
F82H
Bank Select Register Format
MBS
RBS
MBS3 MBS2 MBS1 MBS0
0
0
RBS1
Symbol
RBS0
BS
(1) Memory bank select register (MBS)
The memory bank select register is a 4-bit register used to store the high-order four bits of a 12-bit data
memory address. The contents of this register specify a memory bank to be accessed. Memory banks
0, 1, 2, 3, and 15 can be specified.
The MBS is set with the SEL MBn instruction (n = 0, 1, 2, 3, 15)
Fig. 2-1 shows the range of addressing using MBE and MBS settings.
A RESET input initializes the MBS to 0.
(2) Register bank select register (RBS)
The register bank select register specifies a register bank to be used as general registers; a register bank
can be selected from register banks 0 to 3.
The RBS is set with the SEL RBn instruction (n = 0 to 3).
A RESET input initializes the RBS to 0.
Table 3-5
Register Bank to Be Selected with the RBE and RBS
RBS
RBE
0
1
Register bank
3
2
1
0
0
0
×
×
Bank 0 is always selected.
0
0
Bank 0 is selected.
0
1
Bank 1 is selected.
1
0
Bank 2 is selected.
1
1
Bank 3 is selected.
0
0
Always 0
Remark
×: Don’t care
39
µPD75238
4. PERIPHERAL HARDWARE FUNCTIONS
4.1
DIGITAL I/O PORTS
The µPD75238 employs memory-mapped I/O, enabling all I/O ports to be mapped to data memory space.
Fig. 4-1
Address
40
Data Memory Address Assigned to Digital Port
3
2
1
0
Symbol
FF0H
P03
P02
P01
P00
PORT 0
FF1H
P13
P12
P11
P10
PORT 1
FF2H
P23
P22
P21
P20
PORT 2
FF3H
P33
P32
P31
P30
PORT 3
FF4H
P43
P42
P41
P40
PORT 4
FF5H
P53
P52
P51
P50
PORT 5
FF6H
P63
P62
P61
P60
PORT 6
FF7H
P73
P72
P71
P70
PORT 7
FF8H
P83
P82
P81
P80
PORT 8
FF9H
P93
P92
P91
P90
PORT 9
FFAH
P103
P102
P101
P100
PORT 10
FFBH
P113
P112
P111
P110
PORT 11
FFCH
P123
P122
P121
P120
PORT 12
FFDH
P133
P132
P131
P130
PORT 13
FFEH
P143
P142
P141
P140
PORT 14
FFFH
P153
P152
P151
P150
PORT 15
µPD75238
(1) Configurations of digital I/O ports
Fig. 4-2 to Fig. 4-11 show the configurations of the ports.
(2) I/O mode setting
The I/O mode of each I/O port is set by the port mode register as shown in Fig. 4-12.
Each port functions as an input port when the corresponding bit of the port mode register is set to 0, and
functions as an output port when the same corresponding bit is set to 1.
An 8-bit memory manipulation instruction is used to set port mode register group A or B.
A RESET input clears all bits of each port mode register to 0. This means that the output buffers are set
off, and all ports are placed in the input mode.
(3) Operation of digital I/O ports
When an instruction is executed, the operation of the port and pins depends on the I/O mode setting, as
listed in Table 4-1.
Table 4-1
I/O Port Operations by I/O Instructions
Input mode (corresponding bit in the
mode register is 0)
[Output buffer is off]
Output mode (corresponding bit in
the mode register is 1)
[Output buffer is on]
When a 1-bit test instruction, 1-bit input instruction, or 4-/8-bit input instruction is executed
Receives data on certain pins.
Receives the contents of the output
latch.
When a 4-/8-bit output instruction is
executed
Transfers data in the accumulator to
the output latch.
Outputs data in the accumulator to
output pins.
When a 1-bit output instructionNote is
executed
The contents of the output latch are
undefined.
Changes the output pin state according to the instruction.
Note Instructions such as SET1/CLR1/MOV1 PORTn.bit, CY
41
µPD75238
Fig. 4-2
SI0
SCK0
Configuration of Ports 0, 1, and 8
INT4
Internal
SCK0
SO0
P01
output
latch
Selector
8
VDD
Pull-up
resistor
Selector
CSIM0
P-ch
Bit 0 of
POGA
P00/INT4
P01/SCK0
P02/SO0/SB0
P03/SI0/SB1
Output buffer which can
be switched to either
push-pull output or N-ch
open-drain output
Input buffer
VDD
Internal bus
Pull-up
resistor
P-ch
Bit 1 of
POGA
Φ or fX/64
Input buffer
Noise elimination
circuit
P10/INT0
P11/INT1
P12/INT2
P13/ TI0
TI0
INT2 INT1 INT0
SI1
8
SO1 SCK1
Input buffer with hysteresis
Internal SCK1
PPO
CSIM1
P80/PPO
P81/SCK1
P82/SO1
P83/PI1
Input buffer
42
µPD75238
Fig. 4-3
Configuration of Ports 3n and 6n (n = 0 to 3)
VDD
Input buffer
PMmn = 0
Pull-up
resistor
MPX
PMmn = 1
Bit m of
POGA
P-ch
Internal bus
Output buffer
Output latch
Pmn
PMmn
Bit of port mode register
group A
m = 3, 6
n = 0 to 3
Fig. 4-4
Configuration of Port 2
VDD
Pull-up
resistor
P-ch
Bit m of
POGA
Input buffer
PMm = 0
Internal bus
MPX
PMm = 1
Pm0
Pm1
Output
latch
Pm2
Pm3
Output
buffer
PMm
Bit of port mode
register group B (m = 2)
43
µPD75238
Fig. 4-5
Configuration of Ports 4 and 5
VDD
Pull-up resistor
Mask option
Input buffer
PMm = 0
PMm = 1
Internal bus
MPX
Pm0
Pm1
Output
latch
Pm2
Pm3
N-ch open-drain
output buffer
PMm
Bit of port mode register
group B (m = 4, 5)
44
µPD75238
Fig. 4-6
Configuration of Port 7
Input buffer
PMm = 0
Internal bus
MPX
PMm = 1
Pm0
Pm1
Output
latch
Pm2
Pm3
Output buffer
Mask option
PMm
Bit of port mode
register group B (m = 7)
Fig. 4-7
Pull-down resistor
Configuration of Port 9
Input instruction
Input buffer
Internal bus
P90/AN4
P91/AN5
P92/AN6
P93/AN7
To A /D converter
45
µPD75238
Fig. 4-8
Configuration of Ports 10 and 11
SK
SK /Pm0
P-ch open-drain
output buffer
SK+1
SK+1/Pm1
SK+2/Pm2
SK+3
SK+3/Pm3
Internal bus
SK+2
Mask option
Pull-down
resistor
4
DSPM
Mask option
VLOAD
(Specified
for S16 to
S23 at a time)
STATB
8
Remarks 1. Port 10: K = 16, m = 10
2. Port 11: K = 20, m = 11
Fig. 4-9
Configuration of Ports 12 and 13
SK
SK /Pm0
P-ch open-drain
output buffer
SK+1
SK+1/Pm1
SK+2/Pm2
SK+3
SK+3/Pm3
Internal bus
SK+2
Mask option
Pull-down
resistor
4
DSPM
8
STATA
Remarks 1. Port 12: K = 0, m = 12
2. Port 13: K = 4, m = 13
46
VLOAD
µPD75238
Fig. 4-10
Configuration of Port 14
Output
buffer
P-ch open-drain
output buffer
S8/P140
M
S8
Internal bus
S9/P141
P
X
S9
S10/T15/P142
Note
S10
S11
4
S11/T14/P143
Note
T15 T14
DSPM. 3
8
Mask option
(each pin)
Pull-down
resistor
STATA
4
DIGS
VLOAD
Note Selector
Fig. 4-11
Configuration of Ports 15 and H
Output
buffer
P-ch open-drain
output buffer
Note
M
Internal bus
S12
X
Note
S14
S13/T12/P151/PH1
P
Note
S13
Note
S12/T13/P150/PH0
S14/T11/P152/PH2
Note
Note
S15
Note
S15/T10/P153/PH3
Note
PH1 PH3
T12 T10
T13 T11
PH0 PH2
4
Mask option
(each pin)
DSPM. 3
Pull-down
resistor
8
STATA
4
DIGS
VLOAD
Note Selector
47
µPD75238
Fig. 4-12
Formats of the Port Mode Registers
Port mode register group A
7
6
5
4
3
2
1
0
Symbol
PM63
PM62
PM61
PM60
PM33
PM32
PM31
PM30
PMGA
0
Symbol
Address
FE8H
Symbol
PM3n, PM6n
PMGA
P3n and P6n pin I/O specification (n = 0-3)
0
Input mode (output buffers set off)
1
Output mode (output buffers set on)
Port mode register group B
7
Address
FECH
6
PM7
5
4
3
PM5
PM4
2
1
PMGB
PM2
Symbol
PMn
PMGB
Remark
Port n I/O specification (n = 2, 4, 5, and 7)
0
Input mode (output buffers set off)
1
Output mode (output buffers set on)
——: Don’t care
(4) Pull-up resistor register group A (POGA)
Pull-up resistor register group A is a register to specify an internal pull-up register to each port pin of ports
0 to 3 and port 6 (excluding P00). Fig. 4-13 shows the format of this register.
When a pull-up resistor is to be contained, set 1 to an associated bit, and when a pull-up resistor is not
to be contained, set 0.
Fig. 4-13
Address
FDCH
Format of the Register Group A Specifying the Use of Pull-Up Resistors
7
6
5
4
3
2
1
0
—
PO6
—
—
PO3
PO2
PO1
PO0
Symbol
POGA
Port 0 (P01 - P03)
Port 1 (P10 - P13)
Port 2 (P20 - P23)
Port 3 (P30 - P33)
Port 6 (P60 - P63)
Caution For mask option, ports 4 and 5 can contain pull-up resistors, and port 7 and ports 10 to 15 can
contain pull-down resistors bit by bit.
Remark ——: Don’t care
48
µPD75238
4.2 CLOCK GENERATOR
(1) Configuration of the clock generator
The clock generator supplies various clock signals to the CPU and peripheral hardware. Fig. 4-14 shows
the configuration of the clock generator.
Fig. 4-14
Block Diagram of the Clock Generator
•
•
•
•
•
•
•
XT1
XT2
Subsystem
clock generator
fXT
Clock timer
Timer/pulse
generator
FIP controller/driver
Basic interval timer (BT)
Timer/event counter
Serial interface
Clock timer
Clock output circuit
INT0 voice eliminator
X1
X2
Main system
clock generator
fX
1/8 to 1/4096
Frequency divider
1/2 1/4 1/16
SCC
Selector
Oscillator
disable
signal
Frequency
divider
SCC3
Selector
• CPU
• INT0 noise
SCC0
Internal bus
Φ
1/4
eliminator
PCC
• Clock output
circuit
PCC0
PCC1
4
HALT F/F
HALT Note
STOP Note
PCC2
S
PCC3
PCC2, PCC3
clear signal
R
STOP F/F
Q
Q
Wait release signal from BT
S
RESET signal
R
Standby release signal from
interrupt control circuit
Note Instruction execution
Remarks 1. fX : Main system clock frequency
2. fXT: Subsystem clock frequency
3. Φ = CPU clock
4. PCC : Processor clock control register
5. SCC: System clock control register
6. One clock cycle (tCY) of the CPU clock (Φ) is equal to one machine cycle of an instruction. See
Chapter 11 for details of t CY.
49
★
µPD75238
(2) Functions of the clock generator
The clock generator generates the clock signals listed below, and controls the standby mode and other
CPU operation modes.
• Main system clock: fX
• Subsystem clock: fXT
• CPU clock: Φ
• Clocks for peripheral hardware
The operation of the clock generator is determined by the processor clock control register (PCC) and
system clock control register (SCC). The clock generator functions and operates as described below.
(a) A RESET input selects the lowest-speed mode (10.7 µs at 6.0 MHz)Note 1 for the main system clock.
(PCC = 0, SCC = 0)
(b) When the main system clock is selected, the PCC can be set to select one of four CPU clocks (0.67
µs, 1.33 µs, 2.67 µs, and 10.7 µ s at 6.0 MHz)Note 2 .
(c) When the main system clock is selected, the two standby modes, STOP mode and HALT mode, are
available.
(d) The SCC can be set to select the subsystem clock for very low-speed, low-current operation (122 µs
at 32.768 kHz).
(e) When the subsystem clock is selected, main system clock generation can be stopped with the SCC.
In addition, the HALT mode can be used, but the STOP mode cannot be used. (Subsystem clock
generation cannot be stopped.)
(f) Clocks for peripheral hardware are produced by dividing the main system clock signal. Only to the
watch timer, the subsystem clock can be directly supplied to continue the clock function.
(g) When the subsystem clock is selected, the watch timer can operate normally, but other hardware
cannot be used because they operate with the main system clock.
Notes 1. 15.3 µs at 4.19 MHz
2. 0.95 µs, 1.91 µs, 3.82 µs, 15.3 µs at 4.19 MHz
50
µPD75238
(3) Processor clock control register (PCC)
The PCC is a 4-bit register for selecting CPU clock Φ with the low-order two bits and for selecting a CPU
operation mode with the high-order two bits. (See Fig. 4-15.)
When bit 3 or bit 2 is set to 1, the standby mode is set. When this is released by the standby release signal,
these bits are automatically cleared to return to the normal operation mode. (See Chapter 6 for detailed
information.)
A 4-bit memory manipulation instruction is used to set the low-order two bits of the PCC. (The high-order
two bits are set to 0.)
Bit 3 and bit 2 are set to 1 using the STOP instruction and HALT instruction, respectively.
The STOP instruction and HALT instruction can be executed regardless of MBE setting.
A CPU clock can be selected only when the main system clock is used for operation. When the subsystem
clock is selected for operation, the low-order two bits of the PCC are invalidated, and fXT/4 is automatically
set. The STOP instruction can be executed only when the main system clock is used for operation.
The generation of a RESET signal clears the PCC to 0.
51
µPD75238
Fig. 4-15
Address
FB3H
3
PCC3
2
1
PCC2 PCC1
Format of the Processor Clock Control Register
Symbol
0
PCC0
PCC
CPU clock selection bit
(Operation with fX = 6.0 MHz)
SCC = 0
( ) indicates fX = 6.0 MHz
SCC = 1
( ) indicates f XT = 32.768 kHz
CPU clock frequency
1 machine cycle
CPU clock frequency
1 machine cycle
Φ = fXT/4 (8.192 kHz)
122 µs
µs
0
0
Φ = fX /64 (93.7 kHz)
µs
10.7 µ
s
0
1
Φ = fX /16 (375 kHz)
2.67 µµs
s
1
0
Φ = fX /8 (750 kHz)
µs
1.33 µ
s
1
1
Φ = fX /4 (1.5 MHz)
0.67 µµs
s
Not to be set
122 µs
µs
Φ = fXT/4 (8.192 kHz)
(Operation with fX = 4.19 MHz)
SCC = 0
( ) indicates fX = 4.19 MHz
CPU clock frequency
1 machine cycle
0
0
Φ = fX /64 (65.5 kHz)
15.3 µ
s
µs
0
1
Φ = fX /16 (262 kHz)
3.82 µs
µs
1
0
Φ = fX /8 (524 kHz)
1.91 µs
µs
1
1
Φ = fX /4 (1.05 MHz)
0.95 µs
µs
SCC = 1
( ) indicates f XT = 32.768 kHz
CPU clock frequency
1 machine cycle
Φ = fXT/4 (8.192 kHz)
122 µs
µs
Not to be set
Φ = fXT/4 (8.192 kHz)
Remarks 1. fX : Output frequency from the main syem clock oscillator
2. fXT: Output frequency from the subsyem clock oscillator
CPU operation mode control bits
52
0
0
Normal operation mode
0
1
HALT mode
1
0
STOP mode
1
1
Not to be set
µs
122 µ
s
µPD75238
(4) System clock control register (SCC)
The SCC is a 4-bit register for selecting CPU clock Φ with the least significant bit and for controlling the
termination of main system clock generation with the most significant bit. (See Fig. 4-16.)
SCC.0 and SCC.3 are located at the same data memory address, but both bits cannot be changed at the
same time. Accordingly, SCC.0 and SCC.3 are set using bit manipulation instructions. SCC.0 and SCC.3
can be manipulated regardless of MBE setting.
Main system clock generation can be terminated by setting SCC.3 only when the subsystem clock is used
for operation. The STOP instruction must be used for generation termination when the main system clock
is used for operation.
A RESET input clears the SCC to 0.
Fig. 4-16
Address
FB7H
Format of the System Clock Control Register
Symbol
SCC3
—
—
SCC0
SCC
SCC3 SCC0
System clock selection
0
0
Main system clock
0
1
Subsystem clock
1
0
1
1
Main system clock operation
Can oscillate
Not to be set
Subsystem clock
Oscillation stopped
Cautions 1. A time period of up to 1/fXT is needed to change the system clock. This means that to
terminate main system clock generation, SCC.3 must be set when the machine cycles
indicated in Table 4-2 or more have elapsed after the clock is switched from the main system
clock to the subsystem clock.
2. When the main system clock is used for operation, setting SCC.3 to stop clock generation
does not enter the normal STOP mode.
3. When SCC.3 is set to 1, the X1 input pin is connected to VSS (GND electric potential) to
prevent leakage in the crystal oscillator. When an external clock is used as the main system
clock, never set SCC.3 to 1.
4. When the four bits of PCC are set to 0001B (Φ = fX/16), do not set SCC.0 to 1. Before switching
the main system clock to the subsystem clock, be sure to manipulate the PCC bits so other
than 0001B is set. When the system operates on the subsystem clock, the PCC bits must
also be other than 0001B.
53
µPD75238
(5) System clock oscillator
The main system clock oscillator operates with a crystal (6.0 MHz standard) or ceramic resonator
connected to the X1 and X2 pins.
An external clock can also be input.
Fig. 4-17
External Circuitry for the Main System Clock Oscillator
(a) Crystal/ceramic oscillation
(b) External clock
µ PD75238
X1
X2
µ PD75238
External
clock
X1
X2
Crystal
oscillator
or ceramic
oscillator
Caution When an external clock is used, the STOP mode cannot be set. This is because the X1 pin is
connected to V SS in the STOP mode.
54
µPD75238
The subsystem clock oscillator operates with a crystal resonator (32.768 kHz standard) connected to the
XT1 and XT2 pins.
An external clock can also be input.
Fig. 4-18
External Circuitry for the Subsystem Clock Oscillator
(a) Crystal oscillation
(b) External clock
µ PD75238
µ PD75238
XT1
External
clock
XT1
32.768 kHz
XT2
Open
XT2
Caution When the main system clock or subsystem clock oscillator is used, conform to the following
guidelines when wiring at the shaded portions of Fig. 4-17 and 4-18 to eliminate the influence
of the wiring capacity.
• The wiring must be as short as possible.
• Other signal lines must not run in these areas. Any line carrying a high fluctuating current
must be kept away as far as possible.
• The grounding point of the capacitor of the oscillator must have the same potential as that
of VSS. It must not be grounded to ground patterns carrying a large current.
• No signal must be taken from the oscillator.
When the subsystem clock is used, pay special attention to its wiring; the subsystem clock
oscillator has low amplification to minimize current consumption and is more likely to malfunction due to noise than the main system clock oscillator.
55
µPD75238
(6) Time required to change the system clock and CPU clock
The system clock and CPU clock can be changed by using the least significant bit of the SCC and the loworder two bits of the PCC. This switching is not performed immediately after the contents of the registers
are rewritten, but the system operates with the previous clock for some machine cycles. Accordingly, after
this time period, the STOP instruction must be executed or SCC.3 must be set to 1 to terminate main system
clock generation.
Table 4-2
Setting before
switching
SCC PCC PCC
0
0
1
Maximum Time Required to Change the System Clock and CPU Clock
Setting after switching
SCC0 PCC1 PCC0
0
0
0
SCC0 PCC1 PCC0
0
0
1
SCC0 PCC1 PCC0
0
1
0
SCC0 PCC1 PCC0
0
1
1
1 machine cycle
1 machine cycle
1 machine cycle
fX /64fXT machine
cycles
(3 machine cycles)
4 machine cycles
4 machine cycles
Not to be set
8 machine cycles
fX/8fXT machine
cycles
(23 machine cycles)
0
0
0
1
4 machine cycles
1
0
8 machine cycles
1
1
16 machine cycles 16 machine cycles 16 machine cycles
×
×
1 machine cycle
SCC0 PCC1 PCC0
1
×
×
0
1
8 machine cycles
Not to be set
1 machine cycle
fX/4fXT machine
cycles
(46 machine cycles)
1 machine cycle
Remarks 1. CPU clock Φ is supplied to the CPU in the µPD75238. The reciprocal of this frequency is a
minimum instruction time (defined as one machine cycle in this manual).
2. Time enclosed in parentheses is required when fX = 6.0 MHz and fXT = 32.768 kHz.
Caution When the four bits of PCC are set to 0001B (Φ = fX/16), do not set SCC.0 to 1. Before switching
the main system clock to the subsystem clock, be sure to manipulate the PCC bits so other than
0001B is set. When the system operates on the subsystem clock, the PCC bits must also be
other than 0001B.
56
µPD75238
(7) Procedure for changing the system clock and CPU clock
The procedure for changing the system clock and CPU clock is explained using Fig. 4-19.
Fig. 4-19
Commercial
power
line voltage
Changing the System Clock and CPU Clock
ON
OFF
VDD pin voltage
RESET signal
Wait 21.8 ms [31.3 ms]
System clock
CPU clock
fX
fX
f XT
fX
10.7 µs
[15.3 µs]
0.67 µ s
[0.95 µ s]
122 µ s
0.67 µ s
[0.95 µ s]
Internal reset
operation
Remark The values not enclosed in square brackets are for fX = 6.0 MHz and fXT = 32.768 kHz; the values
enclosed in square brackets for fX = 4.19 MHz.
1
A RESET input starts CPU operation at the lowest speed of the main system clock (10.7 µ s
at 6.0 MHz) Note 1 after a wait time (21.8 ms at 6.0 MHz) Note 2 for stable oscillation.
2
The PCC is rewritten for highest-speed operation after a time elapse which is sufficient for the voltage
3
The removal of commercial power is detected using, for example, an interrupt input (INT4 is useful),
on the VDD pin to be high enough for highest-speed operation.
then SCC.0 is set to operate with the subsystem clock. (In this case, the start of subsystem clock
generation must be confirmed beforehand.) After a time (32 machine cycles) required to switch to
the subsystem clock elapses, SCC.3 is set to terminate main system clock generation.
4
After detecting the input of commercial power by using an interrupt, SCC.3 is cleared to start main
system clock generation. After a time required for stable generation, SCC.0 is cleared to operate at
highest speed.
Notes 1. 15.3 µs at 4.19 MHz
2. 31.3 ms at 4.19 MHz
57
µPD75238
4.3
CLOCK OUTPUT CIRCUIT
(1) Configuration of the clock output circuit
Fig. 4-20 shows the configuration of the clock output circuit.
(2) Functions of the clock output circuit
The clock output circuit outputs a clock pulse signal on the P22/PCL pin for remote control or for supplying
clock pulses to a peripheral LSI device.
The procedure for outputting a clock pulse signal is as follows:
(a) Select a clock output frequency, and disable clock output.
(b) Write a 0 in the P22 output latch.
(c) Set the output mode for port 2.
(d) Enable clock output.
Fig. 4-20
Configuration of the Clock Output Circuit
From the clock
generator
Φ
Output
buffer
f X/23
Selector
f X/24
PCL/P22
6
f X/2
PORT2.2
CLOM3
0
CLOM1 CLOM0 CLOM
P22 output
latch
Bit 2 of PMGB
Port 2 input/
output mode
specification bit
4
Internal bus
Remark The clock output circuit is designed so that pulses with short widths do not appear in enabling
or disabling clock output.
58
µPD75238
(3) Clock output mode register (CLOM)
The CLOM is a 4-bit register to control clock output.
The CLOM is set with a 4-bit memory manipulation instruction. No read operation is allowed on this
register.
Example
CPU clock Φ is output on the PCL/P22 pin.
SEL
MB15
; Or CLR1 MBE
MOV A, #1000B
MOV CLOM, A
A RESET input clears the CLOM to 0, disabling clock output.
Fig. 4-21
Address
FD0H
3
2
CLOM3
0
1
Format of the Clock Output Mode Register
Symbol
0
CLOM1 CLOM0
CLOM
Clock output frequency selection bit
(Frequency when fX = 6.0 MHz)
0
0
Φ Output
Note
(1.50 MHz, 750 kHz, 375 kHz, 93.7 kHz)
3
0
1
Output fX/2 (750 kHz)
1
0
Output fX/24 (375 kHz)
1
1
Output fX/26 (93.7 kHz)
(Frequency when fX = 4.19 MHz)
0
0
Φ Output Note (1.05 MHz, 524 kHz, 262 kHz, 65.5 kHz)
0
1
Output fX/23 (524 kHz)
1
0
Output fX/24 (262 kHz)
1
1
Output fX/2 (65.5 kHz)
6
Note Φ is the CPU clock supply selected by PCC.
Clock output enable/disable bit
Caution
0
Output disable
1
Output enable
Be sure to write a 0 in bit 2 of the CLOM.
59
µPD75238
(4) Application to remote control output
The clock output function of the µPD75238 is applicable to remote control output. The frequency of the
carrier for remote control output is selected by the clock frequency select bit of the clock output mode
register. Pulse output is enabled or disabled by controlling the clock output enable/disable bit by software.
The clock output circuit is designed so that pulses with short widths do not appear in enabling or disabling
clock output.
Fig. 4-22
CLOM. 3
PCL pin
output
60
Application to Remote Control Output
µPD75238
4.4
BASIC INTERVAL TIMER
(1) Configuration of the basic interval timer
Fig. 4-23 shows the configuration of the basic interval timer.
(2) Basic interval timer functions
The basic interval timer provides the following four functions:
(a) Reference time generation (four time intervals)
(b) Application of watchdog timer for detecting program crashes
(c) Selection of a wait time for releasing the standby mode, and counting
(d) Reading the count value
Fig. 4-23
Configuration of the Basic Interval Timer
From the clock
generator
Clear
Clear
fX/25
fX/27
Set
fX/29
fX/212
BT
3
BTM3
SET1 Note
BT interrupt
request flag
Basic interval timer
(8-bit frequency divider circuit)
MPX
BTM2
BTM1
IRQBT
Vector
interrupt
request
signal
Wait release
signal for standby
release
BTM0
BTM
8
4
Internal bus
Note
Instruction execution
61
µPD75238
(3) Basic interval timer mode register (BTM)
BTM is a 4-bit register that controls operation of the basic interval timer.
The BTM contents are set by using a 4-bit memory manipulation instruction.
Bit 3 can be independently set using a bit manipulation instruction.
When bit 3 is set to 1, the contents of the basic interval timer are cleared, and the basic interval timer
interrupt request flag (IRQBT) is also cleared (to start the basic interval timer).
A RESET input clears the contents to 0, and the longest interrupt request signal generation interval time
is set.
Fig. 4-24
Address
F85H
Format of the Basic Interval Timer Mode Register
3
2
1
0
BTM3
BTM2
BTM1
BTM0
Symbol
BTM
(Frequency when fX = 6.0 MHz)
Input clock specification
Interrupt interval time
(wait time for releasing standby)
0
0
0
fX /212 (1.46 kHz)
20
2 /fX (175 ms)
0
1
1
fX /29 (11.7 kHz)
217/fX (21.8 ms)
1
0
1
fX /2 (46.9 kHz)
1
1
1
fX /2 (188 kHz)
Other setting
7
5
15
2 /fX (5.46 ms)
13
2 /fX (1.37 ms)
Not to be set
–
(Frequency when fX = 4.19 MHz)
Input clock specification
12
Interrupt interval time
(wait time for releasing standby)
20
0
0
0
fX /2
0
1
1
9
fX /2 (8.18 kHz)
17
2 /fX (31.3 ms)
1
0
1
fX /27 (32.768 kHz)
215/fX (7.82 ms)
1
1
1
fX /25 (131 kHz)
13
2 /fX (1.95 ms)
Other setting
(1.02 kHz)
Not to be set
2 /fX (250 ms)
–
Basic interval timer start control bit
When “1” is written to this bit, the basic interval timer operation starts (the counter
and the interrupt request flag are cleared).
When the operation starts, this bit is automatically reset to 0.
62
µPD75238
(4) Operation of the basic interval timer
The basic interval timer (BT) is always incremented by the clock supplied from the clock generator, and
when it overflows, the interrupt request flag (IRQBT) is set. The count operation of BT cannot be stopped.
One of four interrupt generation intervals can be selected by setting BTM. (See Fig. 4-24.)
The basic interval timer and the interrupt request flag can be cleared by setting bit 3 of BTM to 1 (instruction
for starting as an interval timer).
The count status can be read by using an 8-bit manipulation instruction. No data can be loaded to the
timer.
Caution
When reading the count value of the basic interval timer, execute a read instruction twice so
that unstable data which has been counted will not be read. If the two read values are
reasonable, use the second one as the result. If the two read values are far apart, retry from
the beginning.
To allow the system clock to stabilize after releasing the STOP mode, a wait function is available which
stops the operation of the CPU until the basic interval timer overflows.
The wait time after a RESET input is fixed. On the other hand, a wait time can be selected by setting BTM
when releasing the STOP mode with an interrupt occurrence. In this case, the wait times are the same
as the interval times shown in Fig. 4-24.
BTM must be set before the STOP mode is set. (For details, see Chapter 6.)
4.5 TIMER/EVENT COUNTER
(1) Functions of the timer/event counter
The timer/event counter has the following functions.
(a) Programmable interval timer operation
(b) Output of a square wave at a given frequency to the PTO0 pin
(c) Event counter operation
(d) Frequency divider operation that divides TI0 pin input by N and outputs the result to the PTO0 pin
(e) Supply of serial shift clock signal to a serial interface circuit
(f) Function of reading the state of counting
63
64
Fig. 4-25
Block Diagram of the Timer/Event Counter
Internal bus
8
SET1
Note 1
TM0
8
8
TM07 TM06 TM05 TM04 TM03 TM02
TO enable
flag
Modulo register (8)
PORT2.0
P20
output
latch
Bit 2 of PGMB
Port 2
input/
output
mode
To serial
interface
8
PORT1.3
Match
Comparator (8)
P13/ TI0Note 2
TOE0
TMOD0
8
Input
buffer
TOUT
F/F
P20/PTO0
Reset
Output
buffer
T0
INTT0

From the 
clock

generator
Event
counter #1

Count register (8)
CP
MPX
Clear
IRQT0
set signal
Timer operation start signal
RESET
IRQT0 clear
signal
(See Fig. 4-26.)
Notes 1. Instruction execution
2. The P13/TI0 pin is an external event pulse input pin shared between timer/event counter and
event counter.
µPD75238
µPD75238
(2) Timer/event counter mode register (TM0) and timer/event counter output enable flag (TOE0)
The timer/event counter mode register (TM0) is an 8-bit register for controlling the timer/event counter.
It is set by an 8-bit memory manipulation instruction.
Fig. 4-27 shows the format of the timer/event counter mode register.
Bit 3 is the timer start bit, and can be set independently of the other bits. Bit 3 is automatically reset to
0 when the timer starts operation.
A RESET input clears all the bits of the TM0 to 0.
The timer/event counter output enable flag (TOE0) enables or disables output of the timer out F/F (TOUT
F/F) status to the PTO0 pin.
Fig. 4-26 shows the format of the timer/event counter output enable flag.
The timer out F/F (TOUT F/F) can be inverted by a match signal sent out from the comparator. The timer
out F/F is reset when an instruction sets bit 3 of the TM0.
A RESET input clears the TOE0 and TOUT F/F to 0.
Fig. 4-26
Address
FA2H
Format of the Timer/Event Counter Output Enable Flag
3
TOE0
Timer/event counter output enable flag
0
Disables
1
Enables
65
µPD75238
Fig. 4-27
Address
FA0H
7
6
—
TM06
5
Format of the Timer/Event Counter Mode Register
4
3
2
TM05 TM04 TM03 TM02
1
0
—
—
Symbol
TM0
Operation mode
Count operation
0
Halts (retains
the contents of
counting)
1
Count
operation
Timer start specification bit
When “1” is written to this bit, the counter and the IRQT0
flag are cleared. Count operation starts if bit 2 has been
set to 1.
Count pulse (CP) select bit
(Frequency when fX = 6.0 MHz)
TM06 TM05
TM04
Count pulse (CP)
0
0
0
TI0 input rising edge
0
0
1
TI0 input falling edge
1
0
0
fX /210 (5.86 kHz)
1
0
1
fX /28 (23.4 kHz)
1
1
0
fX /26 (93.8 kHz)
1
1
1
fX /24 (375 kHz)
Other setting
Not to be set
(Frequency when fX = 4.19 MHz)
TM06 TM05
Count pulse (CP)
0
0
0
TI0 input rising edge
0
0
1
TI0 input falling edge
1
0
0
fX /210 (4.09 kHz)
1
0
1
fX /28 (16.4 kHz)
1
1
0
fX /26 (65.5 kHz)
1
1
1
4
fX /2 (262 kHz)
Other setting
66
TM04
Not to be set
µPD75238
(3) Operation mode of the timer/event counter
The timer/event counter operates in the count operation disable mode or in the count operation mode,
depending on the setting of the mode register.
The following operations are possible, regardless of the setting of the mode register:
(i) P13/TI0 pin signal input and test
(ii) Output of the timer out F/F status to the PTO0
(iii) Setting of the modulo register (TMOD0)
(iv) Reading from the count register (T0)
(v) Setting, clearing, and testing of the interrupt request flag (IRQT0)
(a) Count operation disable mode
This mode is set when bit 2 of TM0 is set to 0. In this mode, count operation is not performed because
count pulse (CP) supply to the count register is stopped.
(b) Count operation mode
This mode is set when bit 2 of TM0 is set to 1. In this mode, a count pulse signal selected with bits
4 to 6 is supplied to the count register for count operation as shown in Fig. 4-28.
Timer operation is usually started in the following steps:
1
A count value is set in the modulo register (TMOD0).
2
An operation mode, count clock, and start instruction are set in the mode register (TM0).
An 8-bit data transfer instruction is used to set the modulo register.
Fig. 4-28
Operation in the Count Operation Mode
INTT0
(IRQT0 set signal)
TI0
Internal
clock





MPX
CP
Count register
(T0)
Comparator
Clear
Match
TOUT
F/F
PTO0
Modulo register
(TMOD0)
To serial interface (channel 0)
67
µPD75238
(4) Time setting in the timer/event counter
[Timer set time] (period) is [value of the modulo register + 1] divided by [count pulse frequency] selected
by the timer mode register.
T(sec) =
(n + 1)
= (n + 1) • (resolution)
fCP
T(sec) : Timer set time (seconds)
fCP (Hz) : Count pulse frequency (Hz)
n
: Value in the modulo register (n = 0)
Once the timer is set, the interrupt request signal (IRQT0) is generated at set time intervals. Table 4-3
indicates the resolution and maximum set time (set when FFH is set in the modulo register) of the timer/
event counter for each count pulse signal.
Table 4-3
Resolution and Maximum Set Time
(When fX = 6.0 MHz)
Mode register
TM06 TM05 TM04
Timer channel 0
Resolution
Maximum set time
1
0
0
171 µs
43.7 ms
1
0
1
42.7 µs
10.9 ms
1
1
0
10.7 µs
2.73 ms
1
1
1
2.67 µs
683 µs
(When fX = 4.19 MHz)
Mode register
TM06 TM05 TM04
68
Timer channel 0
Resolution
Maximum set time
1
0
0
244 µs
62.5 ms
1
0
1
61.1 µs
15.6 ms
1
1
0
15.3 µs
3.91 ms
1
1
1
3.81 µs
977 µs
µPD75238
4.6 CLOCK TIMER
(1) Clock timer
The µPD75238 contains one channel for a clock timer. Fig. 4-29 shows the configuration of the timer.
(2) Clock timer functions
(a) The clock timer sets the test flag (IRQW) every 0.5 seconds.
The standby mode can be released with IRQW.
(b) Either the main system clock (4.19 MHz) or subsystem clock (32.768 kHz) can produce 0.5-second
intervals.
(c) The fast-forward mode produces an interval 128 times faster (3.91 ms), which is useful for program
debugging and testing.
(d) A fixed frequency (2.048, 4.096, or 32.768 kHz) can be output to the P23/BUZ pin, so that it can be used
for sounding the buzzer and system clock frequency trimming.
(e) The frequency divider can be cleared, so the clock can start from zero seconds.
Fig. 4-29
Block Diagram of the Clock Timer
fW
2

From the 
clock

generator


fX
128
(32.768 kHz)
14
Selector
INTW
IRQW
set signal
Selector
2
fW
8
fXT
(32.768 kHz)
(256 Hz: 3.91 ms)
fW
fW
(32.768 kHz)
Selector
7
Frequency divider
fW
16
(4.096 kHz)
2 Hz
0.5 sec
Clear
Output buffer
P23/BUZ
WM
WM7
PORT2.3
0
WM5 WM4
0
WM2 WM1 WM0
P23 output
latch
Bit 2 of PMGB
Port 2 input/
output mode
8
Internal bus
Remark
The values in parentheses are for fX = 4.194304 MHz and fXT = 32.768 kHz
Caution
When the main system clock operates at 6.0 MHz, a time interval of 0.5 s cannot be produced.
Before producing this time interval, the main system clock must be changed to the subsystem
clock.
69
µPD75238
(3) Watch mode register (WM)
The watch mode register (WM) is an 8-bit register that controls the clock timer, and that is set with an
8-bit memory manipulation instruction. Fig. 4-30 shows the format.
An 8-bit memory manipulation instruction is used to set the watch mode register. A RESET input clears
all bits to 0.
Fig. 4-30
Address
F98H
Format of the Clock Mode Register
Symbol
7
6
5
4
3
2
1
0
WM7
0
WM5
WM4
0
WM2
WM1
WM0
WM
Count clock (fW) selection bit
0
Selects divided system clock output:
1
Selects subsystem clock: fXT
fX
128
WM0
Operation mode selection bit
fW
: sets IRQW at 0.5 s)
214
0
Normal clock mode (
1
Advanced clock mode (
WM1
fW
: sets IRQW at 3.91 ms)
7
2
Clock operation enable/disable bit
0
Disables clock operation (clears the frequency dividing circuit)
1
Enables clock operation
WM2
BUZ output frequency selection bit
WM5 WM4
BUZ output frequency
0
0
fW/24 (2.048 kHz)
0
1
fW/23 (4.096 kHz)Note
1
0
Not to be set
1
1
fW (32.768 kHz)Note
Note Not supported by the IE-75000-R.
BUZ output enable/disable bit
0
Disables BUZ output
1
Enables BUZ output
WM7
70
µPD75238
4.7 TIMER/PULSE GENERATOR
(1) Timer/pulse generator functions
The µPD75238 contains one channel for a timer/pulse generator that can be used as a timer or a pulse
generator. It has the following functions:
(a) Functions available when the timer/pulse generator is used in the timer mode
• 8-bit interval timer operation using one of five clock sources (occurrence of IRQTPG)
• Square wave output to the PPO pin
(b) Functions available when the timer/pulse generator is used in the PWM pulse generation mode
• PWM pulse output to the PPO pin with an accuracy of 14 bits (applicable for electronic tuning when
used as an D/A converter)
• Generation of interrupts at regular intervals (215/fX = 5.46 ms at 6.0 MHz)Note
Note 7.81 ms at 4.19 MHz
If pulse output is unnecessary, the PPO pin can be used as a 1-bit output port.
Caution
If the timer/pulse generator is operating when the STOP mode is set, it may malfunction. So
the timer/pulse generator must be disabled with the mode register in advance.
71
µPD75238
(2) Timer/pulse generator mode register (TPGM)
The timer/pulse generator mode register (TPGM) is an 8-bit register that controls operation of the timer/
pulse generator. Fig. 4-31 shows the format of the register.
TPGM is set with an 8-bit memory manipulation instruction.
Bit 3 enables or disables the transfer (reloading) of the timer/pulse generator modulo register (MODH and
MODL) contents to the modulo latch. Bit 3 can be manipulated independently of the other bits.
By setting TPGM1 to 0, timer/pulse generator operation can be stopped to decrease current consumption.
A RESET input clears all bits to 0.
Fig. 4-31
Address
F90H
7
6
TPGM7
—
5
Format of Timer/Pulse Generator Mode Register
4
3
TPGM5 TPGM4 TPGM3
2
0
1
0
TPGM1 TPGM0
Symbol
TPGM
Timer/pulse generator operation mode selection bit
TPGM0
0
Select PWM pulse generation mode
1
Select timer mode
Timer/pulse generator operation enable/disable bit
TPGM1
0
Disable timer/pulse generator operation
1
Enable timer/pulse generator operation
Modulo register reload enable/disable bit
TPGM3
0
Disable reloading of modulo register
1
Enable reloading of modulo register
PPO output latch data
TPGM4
0
Output 0 to PPO output latch
1
Output 1 to PPO output latch
PPO pin output selection bit static/pulse
TPGM5
0
Static output on PPO pin
1
Pulse output (square wave/PWM) on PPO pin
PPO pin output enable/disable bit
TPGM7
72
0
Disable output on PPO pin (high-impedance)
1
Enable output on PPO pin
µPD75238
(3) Configuration and operation when the timer/pulse generator is used in the timer mode
Fig. 4-32 shows the configuration when the timer/pulse generator is used in the timer mode.
The timer mode is selected by setting bit 0 of TPGM to 1. In the timer mode, TPGM3 must be set to 1,
allowing a modulo register to be reloaded at any time.
In the timer mode, a prescaler is selected with the modulo register L (MODL), and a frequency or interrupt
interval value is set in the modulo register H (MODH). The timer starts when the TPGM1 is set to 1.
Fig. 4-33 shows the operation timing for the MODH setting, and Table 4-4 shows the setting of a frequency
or interrupt interval.
The output to the PPO pin can be switched between the square wave output and static output. To output
a square wave, set TPGM5 and TPGM7 to 1.
Fig. 4-32
Block Diagram of the Timer/Pulse Generator (Timer Mode)
Internal bus
8
8
MODL
MODH
Modulo register L (8)
Modulo register H (8)
TPGM3
(Set to 1)
INTTPG
IRQTPG
set signal
Modulo latch H (8)
8
Output
buffer
Match
Comparator (8)
Frequency
divider
fX
1/2
CP
Prescaler select latch (5)
Selector
T F/F
PPO
Set
8
Count register (8)
TPGM4 TPGM5 TPGM7
TPGM1
Clear
Caution
Clear
When the timer operating in the timer operation mode is stopped, IRQTPG may be set because
T F/F is set. So, the timer must be stopped with an interrupt being disabled, then IRQTPG must
be cleared.
73
µPD75238
Fig. 4-33
Timer Mode Operation Timing
CP
N
MODH
Count
register
0
1
2
N–1
N
0
N
0
N
0
T F/F
(PPO)
Set TPGM1.
Generate IRQTPG.
Table 4-4
Modulo Register Settings
(When fX = 6.0 MHz)
MODL bits 2-6
Interrupt generation interval
Square wave output frequency
(fX = 6.0 MHz)
(fX = 6.0 MHz)
6
5
4
3
2
0
0
0
0
1
256 (N+1)/fX = 85.3 µs - 10.9 ms
fX/256 (N+1) = 91.6 Hz - 11.7 kHz
0
0
0
1
0
128 (N+1)/fX = 42.7 µs - 5.45 ms
fX/128 (N+1) = 183 Hz - 23.4 kHz
0
0
1
0
0
64 (N+1)/fX = 21.3 µs - 2.73 ms
fX/64 (N+1) = 366 Hz - 46.9 kHz
0
1
0
0
0
32 (N+1)/fX = 10.7 µs - 1.37 ms
fX/32 (N+1) = 732 Hz - 93.8 kHz
1
0
0
0
0
16 (N+1)/fX = 5.33 µs - 683 µs
fX/16 (N+1) = 1465 Hz - 188 kHz
(When fX = 4.19 MHz)
MODL bits 2-6
Interrupt generation interval
Square wave output frequency
(f X = 4.19 MHz)
(fX = 4.19 MHz)
6
5
4
3
2
0
0
0
0
1
256 (N+1)/fX = 122 µs - 15.6 ms
fX/256 (N+1) =64 Hz - 8 kHz
0
0
0
1
0
128 (N+1)/fX = 61.0 µs - 7.81 ms
fX/128 (N+1) = 128 Hz - 16 kHz
0
0
1
0
0
64 (N+1)/fX = 30.5 µs - 3.91 ms
fX/64 (N+1) = 256 Hz - 32 kHz
0
1
0
0
0
32 (N+1)/fX = 15.3 µs - 1.95 ms
fX/32 (N+1) = 512 Hz - 65 kHz
1
0
0
0
0
16 (N+1)/fX = 7.63 µs - 977 µs
fX/16 (N+1) = 1024 Hz - 131 kHz
Cautions 1. A value other than the above cannot be set in MODL. Bits 0, 1, and 7 must be set to 0.
2. N is the set value of MODH. 0 must not be set for N.
Be sure to set a value from 1 to 255 for N.
74
µPD75238
(4) Configuration and operation when the timer/pulse generator is used in the PWM pulse generation mode
Fig. 4-34 shows the configuration when the timer/pulse generator is used in the PWM pulse generation
mode.
The PWM pulse generation mode is selected by setting TPGM0 to 0. TPGM5 and TPGM7 are set to 1 to
enable pulse output. In the PWM mode, the PWM pulse signal can be output on the PPO pin, and IRQTPG
can be set at intervals of a fixed time period (215 /fX = 5.46 ms at 6.0 MHz)Note 1.
PWM pulses output by the µ PD75238 are active-low and have an accuracy of 14 bits. This pulse signal
is applicable for electronic tuning and control of a DC motor when it is integrated by an external low-pass
filter and is converted to analog voltage. (See Fig. 4-35.)
The PWM pulse signal is generated by combining the basic period determined by 2 10 /f X (171 µ s
at 6.0 MHz) Note 2 and the secondary period by 215 /f X (5.46 ms at 6.0 MHz) Note 1 so that the time
constant of the external low-pass filter can be decreased.
The low-level width of a PWM pulse depends on the 14-bit modulo latch value. The upper 8 bits of the
modulo latch are sent from the 8 bits of MODH, and the lower 6 bits of the latch are sent from the upper
6 bits of MODL.
When the PWM pulse signal is converted to analog form, the voltage level of the analog output is obtained
as follows:
VAN = Vref ×
Value of modulo latch
2 14
Vref: Reference voltage of external switching circuitry
To prevent an incorrect PWM pulse from being output by unstable modulo latch data being rewritten, the
µPD75238 allows correct data to be written in MODH and MODL beforehand with 8-bit manipulation
instructions, then in the 14-bit data which is to be transferred to the modulo latch at one time. This transfer
operation is referred to as reloading, and it is controlled by TPGM3.
Cautions 1. If the modulo register H (MODH) is set to 0, the PWM pulse generator cannot function
normally. So be sure to set MODH to a value from 1 to 255.
2. If the lower 2 bits of the modulo register L (MODL) are read, the read result is unpredictable.
3. If the modulo latch is changed in a shorter period than the PWM pulse basic period
210/fX (171 µs at 6.0 MHz)Note 2, PWM pulses do not change.
Notes 1.
2.
7.81 ms at 4.19 MHz
244 µs at 4.19 MHz
(5) Static output to the PPO pin
When pulse output is unnecessary, the PPO pin can be used as normal static output. In this case, the output
data is set in TPGM4 with TPGM5 being set to 0 and TPGM7 to 1.
75
µPD75238
Fig. 4-34
Block Diagram of the Timer/Pulse Generator (PWM Pulse Generation Mode)
Internal bus
8
8
MODL
MODH
Modulo register H (8)
Modulo
register L (6)
(2)
TPGM3
MODL7-2 (6)
MODH (8)
Modulo latch (14)
TPGM1
fX
Output
buffer
Selector
PWM pulse generator
1/2
PPO
Frequency
divider
INTTPG
(IRQTPG set signal)
TPGM5
TPGM7
(215/fX = 5.46 ms: 6.0 MHz) Note
Note
7.81 ms at 4.19 MHz
Fig. 4-35
Sample Configuration of D/A Conversion Using µPD75238
µ PD75238
PPO
76
Vref
PWM
signal
Switching
circuit
Low-pass
filter
VAN (analog voltage)
µPD75238
4.8
EVENT COUNTER
(1) Configuration of the event counter
The event counter of the µPD75238 has a noise eliminator. Fig. 4-36 shows the configuration of the counter.
Fig. 4-36 Block Diagram of the Event Counter
Selector
TI0/P13
TM1.4
Noise
eliminator
Selector
GATEC.0
Timer/counter #0
fx
4
8-bit
counter
TM1.2
Overflow
flag
T1
IRQT1
Internal bus
Caution The TI0/P13 pin is an external event pulse input pin shared between timer/event counter #0
and event counter #1.
(2) Event counter functions
The event counter provides the following functions:
(a) Event counter operation
(b) Function of reading the state of counting
(c) Count pulse edge specification
(d) Noise elimination function
77
µPD75238
(3) Event counter mode register
The event counter mode register (TM1) is an 8-bit register that controls the event counter. Fig. 4-37 shows
the format of the register.
The TM1 is set with an 8-bit memory manipulation instruction. Bit 3 is an event counter start bit, and can
be set independently of the other bits. Bit 3 is automatically reset to 0 when the timer starts operation.
Fig. 4-37
Format of the Event Counter Mode Register
Address
7
6
5
4
3
2
1
0
Symbol
FA8H
0
0
0
TM14
TM13
TM12
0
0
TM1
Event count operation enable/disable bit
0
Disables count operation (count value retained)
1
Enables count operation
TM12
Event count start instruction bit
TM13
When 1 is written, the counter and the IRQ1 flag are cleared.
IF TM12 is set to 1, count opertaion starts.
Count pulse edge specification
0
TI0 input rising edge
1
TI0 input falling edge
TM14
(4) Overflow flag (IRQT1)
The overflow flag is set to 1 when the event counter (IRQT1) overflows. The flag is cleared to 0 by a count
operation start instruction.
(5) Event counter control register (GATEC)
This register specifies sampling by sampling clock (fX/4). A noise eliminator eliminates pulses narrower
than two sampling clock cycles (8/fX) as noise and accepts pulses wider than as interrupt signals.
Fig. 4-38 shows the format of the GATEC.
Fig. 4-38
78
Format of the Event Counter Control Register
Address
3
2
1
0
Symbol
FABH
0
0
0
GATEC0
GATEC
0
No sampling
1
Sampling at fX/4
µPD75238
4.9
SERIAL INTERFACE
The µPD75238 has two channels of clock synchronous 8-bit serial interface: Channel 0 and channel 1. Table
4-5 lists the differences between channel 0 and channel 1.
Table 4-5
Differences between Channel 0 and Channel 1
Serial transfer mode, function
3-wire serial I/O
2-wire serial I/O
Channel 1
Channel 0
Clock selection
fX/24 , fX/23, TOUT F/F, external clock
fX/24 , fX/23, external clock
Transfer method
Start bit switchable: MSB/LSB
Start bit: MSB
Transfer end flag
Serial transfer end interrupt request
flag (IRQCSI0)
Serial transfer end flag (EOT)
Available
Not available
Serial bus interface
79
µPD75238
(1) Serial interface (channel 0) functions
The serial interface (channel 0) of the µ PD75238 has following four different modes.
The functions of the four modes are outlined below.
• Operation halt mode
This mode is used when serial transfer is not performed. This mode reduces power consumption.
• Three-wire serial I/O mode
In this mode, 8-bit data is transferred through three lines: Serial clock (SCK0), serial output (SO0), and
serial input (SI0).
The three-wire serial I/O mode allows full-duplex transmission, so data transfer can be performed at
higher speed.
The user can choose 8-bit data transfer starting with the MSB or LSB, so devices starting with either
the MSB or LSB can be connected.
The three-wire serial I/O mode enables connections to be made with the 75X series, 78K series, and
many other types of peripheral I/O devices.
• Two-wire serial I/O mode
In this mode, 8-bit data is transferred through two lines: Serial clock (SCK0) and serial data bus (SB0
or SB1). By controlling output levels on the two lines by software, communication with multiple devices
is enabled.
The output levels of SCK0 and SB0 (or SB1) can be controlled by software, so the user can match an
arbitrary transfer format. This means that a line that has been required for handshaking to connect
multiple lines can be eliminated for more efficient I/O port utilization.
• Serial bus interface (SBI) mode
In this mode, communication with multiple devices can be performed using two lines: Serial clock
(SCK0) and serial data bus (SB0 or SB1).
This mode conforms to the NEC serial bus format.
In this mode, the sender can output, on the serial data bus, an address for selecting a device subject
to serial communication, commands directed to the remote device, and data. The receiver can identify
an address, commands, and data from received data by hardware. This function enables more efficient
I/O port utilization as in the case of the two-wire serial I/O mode. In addition, this function can simplify
the serial interface control portion of an application program.
(2) Configuration of serial interface (channel 0)
Fig. 4-39 shows the block diagram of the serial interface (channel 0).
80
Fig. 4-39
Block Diagram of the Serial Interface (Channel 0)
Internal bus
8/4
CSIM0
Bit
test
8
8
Bit manipulation
Bit test
8
Slave address register (SVA) (8)
SBIC
Coincidence
RELT
signal
Address comparator
CMDT
(8)
P03/SI0/SB1
SET CLR SO0 latch
D
Q
BSYE
(8)
ACKE
Shift register (SIO0)
ACKT
Selector
P02/SO0/SB0
Busy/
acknowledge
output circuit
Selector
Bus release/
command/
acknowledge
detection circuit
P01/SCK0
Serial clock
counter
P01 output
latch
RELD
CMDD
ACKD
INTCSI0
RQCSI0
set signal
INTCSI0
control circuit
3
Serial clock
control circuit
Serial clock
selector
External SCK0
81
µPD75238
fX/2
4
fX/2
6
fX/2
TOUT F/F
(from timer/event counter)
µPD75238
(3) Functions of serial interface (channel 0) registers
(a) Serial operation mode register 0 (CSIM0)
Fig. 4-40 shows the format of serial operation mode register 0 (CSIM0).
CSIM0 is an 8-bit register which specifies a serial interface (channel 0) operation mode, serial clock,
wake-up function, and so forth.
CSIM0 is manipulated using an 8-bit memory manipulation instruction. The higher three bits can be
manipulated bit by bit. Each bit can be manipulated using its name.
Each bit may or may not allow read and/or write operation. (See Fig. 4-40.) Bit 6 allows bit test
operation only; any data written to this bit is invalid.
A RESET input clears all bits to 0.
Fig. 4-40
Format of Serial Operation Mode Register 0 (CSIM0) (1/3)
Address
FE0H
Symbol
7
6
5
CSIE0
COI
WUP
4
3
2
1
0
CSIM04 CSIM03 CSIM02 CSIM01 CSIM00
CSIM0
Serial clock selection bit (W)
Serial interface operation mode selection bit (W)
Wake-up function specification bit (W)
Signal from address comparator (R)
Serial interface operation enable/disable specification bit (W)
Remark (R) : Read only
(W) : Write only
82
µPD75238
Fig. 4-40
Format of Serial Operation Mode Register 0 (CSIM0) (2/3)
Serial clock selection bit (W)
Serial clock
CSIM01
CSIM00
SCK0 pin mode
3-wire serial I/O mode
0
0
0
1
1
1
SBI mode
2-wire serial I/O mode
External clock applied to SCK0 pin
Input
Time/event counter output (T0)
Output
0
fX/24
1
fX/23 (524 kHz or 750 kHz)Note
(262 kHz or 375
kHz)Note
fX/26
(65.5 kHz or
93.8 kHz) Note
Note The values in parentheses are for fX = 4.19 MHz or 6.0 MHz.
Serial interface operation mode selection bit (W)
CSIM04
CSIM03
CSIM02
×
0
0
Operation mode
3-wire serial I/O
mode
1
0
1
0
SBI mode
Bit sequence for
shift register 0
SIO07-0 ↔ XA
(Transfer starting
with MSB)
SIO00-7 ↔ XA
(Transfer starting
with LSB)
SIO07-0↔ XA
(Transfer starting
with MSB)
1
1
0
1
2-wire serial I/O
mode
1
SIO07-0 ↔ XA
(Transfer starting
with MSB)
SO0 pin function
SI0 pin function
SO0/P02
(CMOS output)
SI0/P03
(Input)
SB0/P02
(N-ch open-drain
input/output)
P03 input
P02 input
SB1/P03
(N-ch open-drain
input/output)
SB0/P02
(N-ch open-drain
input/output)
P03 input
P02 input
SB1/P03
(N-ch open-drain
input/output)
Remark ×: Don’t care
Wake-up function specification bit (W)
WUP
0
Sets IRQCSI0 each time serial transfer is completed in each mode.
1
Used in the SBI mode only to set IRQCSI0 only when an address received after bus release matches
the data in the slave address register (wake-up state). SB0/SB1 goes to high-impedance state.
Caution When WUP = 1 is set during BUSY signal output, BUSY is not released. In the SBI mode, the
BUSY signal is output until the next falling edge of the serial clock (SCK0) appears after release
of BUSY is directed. Before setting WUP = 1, be sure to confirm that the SB0 (or SB1) pin is high
after releasing BUSY.
83
µPD75238
Fig. 4-40
Format of Serial Operation Mode Register 0 (CSIM0) (3/3)
Signal from address comparator (R)
COINote
Condition for being set (COI = 1)
Condition for being cleared (COI = 0)
When the slave address register (SVA) does not match
the data of the shift register
When the slave address register (SVA) matches the
data of the shift register
Note COI can be read only before serial transfer is started or after serial transfer is completed. An
undefined value may be read during transfer.
COI data written by an 8-bit manipulation instruction is ignored.
Serial interface operation enable/disable specification bit (W)
Shift register 0 operation
CSIE0
Serial clock counter
IRQCSI0 flag
SO0/SB0, SI0/SB1 pin
0
Shift operation disabled
Cleared
Held
Used only for port 0
1
Shift operation enabled
Count operation
Can be set.
Used in each mode as
well as for port 0
Remarks 1. Each mode can be selected by setting CSIE0, CSIM03, and CSIM02.
CSIE0
CSIM03 CSIM02
Operation mode
0
×
×
Operation halt mode
1
0
×
Three-wire serial I/O mode
1
1
0
SBI mode
1
1
1
Two-wire serial I/O mode
2. The P01/SCK0 pin assumes the following state according to the setting of CSIE0, CSIM01, and
CSIM00:
CSIE0
84
CSIM01 CSIM00
P01/SCK0 pin state
0
0
0
Input port
1
0
0
High impedance
0
0
1
High level output
0
1
0
0
1
1
1
0
1
1
1
0
1
1
1
Serial clock output (High level output)
µPD75238
Remarks 3. When clearing CSIE0 during serial transfer, use the following procedure:
1
Disable interrupts by clearing the interrupt enable flag.
2
Clear CSIE0.
3
Clear the interrupt request flag.
Examples 1. fX/2 4 is selected as the serial clock, serial interrupt IRQCSI0, is generated each time serial
transfer is completed, and serial transfer is performed in the SBI mode with the SB0 pin used
as the serial data bus.
2.
SEL
MB15
MOV
XA, #10001010B
MOV
CSIM0, XA
; or CLR1 MBE
; CSIM0 ← 10001010B
Serial transfer dependent on the contents of CSIM0 is enabled.
SEL
MB15
SET1
CSIE0
; or CLR1 MBE
85
µPD75238
(b) Serial bus interface control register (SBIC)
Fig. 4-41 shows the format of the serial bus interface control register (SBIC).
SBIC is an 8-bit register consisting of bits for controlling the serial bus and flags for indicating the
states of input data from the serial bus. SBIC is used mainly in the SBI mode.
SBIC is manipulated using a bit manipulation instruction. SBIC cannot be manipulated using a 4-bit
or 8-bit memory manipulation instruction.
Each bit may or may not allow read and/or write operation. (See Fig. 4-41.)
A RESET input clears all bits to 0.
Caution Only the following bits can be used in the three-wire and two-wire serial I/O modes:
• Bus release trigger bit (RELT): Sets the SO0 latch.
• Command trigger bit (CMDT): Clears the SO0 latch.
Fig. 4-41
Format of Serial Bus Interface Control Register (SBIC) (1/3)
Address
FE2H
Symbol
7
6
5
4
3
2
1
0
BSYE
ACKD
ACKE
ACKT
CMDD
RELD
CMDT
RELT
SBIC
Bus release trigger bit (W)
Command trigger bit (W)
Bus release detection flag (R)
Command detection flag (R)
Acknowledge trigger bit (W)
Acknowledge enable bit (R/ W)
Acknowledge detection flag (R)
Busy enable bit (R/ W)
Remarks 1.
86
(R)
: Read only
2.
(W) : Write only
3.
(R/W): Read/write
µPD75238
Fig. 4-41
Format of Serial Bus Interface Control Register (SBIC) (2/3)
Bus release trigger bit (W)
RELT
Control bit for bus release signal (REL) trigger output.
By setting RELT = 1, the SO0 latch is set to 1. Then the RELT bit is automatically cleared to 0.
Caution Never clear SB0 (or SB1) during serial transfer. Be sure to clear SB0 (or SB1) before or after serial
transfer.
Command trigger bit (W)
CMDT
Control bit for command signal (CMD) trigger output.
By setting CMDT = 1, the SO0 latch is cleared to 0. Then the CMDT bit is automatically cleared to 0.
Caution Never clear SB0 (or SB1) during serial transfer. Be sure to clear SB0 (or SB1) before or after serial
transfer.
Bus release detection flag (R)
RELD
Condition for being cleared (RELD = 0)
Condition for being set (RELD = 1)
The transfer start instruction is executed.
The RESET signal is entered.
CSIE0 = 0 (See Fig. 4-40.)
SVA does not match SIO0 when an address is
received.
1
2
3
4
The bus release signal (REL) is detected.
Command detection flag (R)
CMDD
Condition for being cleared (CMDD = 0)
Condition for being set (CMDD = 1)
The transfer start instruction is executed.
The bus release signal (REL) is detected.
The RESET signal is entered.
CSIE0 = 0 (See Fig. 4-40.)
1
2
3
4
The command signal (CMD) is detected.
Acknowledge trigger bit (W)
ACKT
When set after transfer, ACK is output in phase with the next SCK0. After ACK signal output, this bit is automatically cleared to 0.
Cautions 1.
Never set ACKT before or during serial transfer.
2.
ACKT cannot be cleared by software.
3.
Before setting ACKT, set ACKE = 0.
Acknowledge enable bit (R/W)
ACKE
0
Disables automatic output of the acknowledge signal (ACK). (Output by ACKT is possible.)
1
When set before transfer
ACK is output in phase with the 9th clock of SCK0.
When set after transfer
ACK is output in phase with SCK0 immediately following set
instruction execution.
87
µPD75238
Fig. 4-41
Format of Serial Bus Interface Control Register (SBIC) (3/3)
Acknowledge detection flag (R)
ACKD
Condition for being cleared (ACKD = 0)
The transfer start instruction is executed.
The RESET signal is entered.
1
2
Condition for being set (ACKD = 1)
The acknowledge signal (ACK) is detected (in phase
with the rising edge of SCK0).
Busy enable bit (R/W)
BSYE
The busy signal is automatically disabled.
Busy signal output is stopped in phase with the falling edge of SCK0 immediately after clear
instruction execution.
0
1
2
1
The busy signal is output after the acknowledge signal in phase with the falling edge of SCK0.
Examples 1. A command signal is output.
SEL
MB15
SET1
CMDT
; or CLR1 MBE
2. RELD and CMDD are tested to identify the types of received data and the types of processing
accordingly.
By setting WUP = 1, this interrupt routine is processed only when an address match is found.
88
SEL
MB15
SKF
RELD
BR
!ADRS
SKT
CMDD
BR
!DATA
; RELD test
; CMDD test
CMD :
••••••••••••••••
; Command analysis
DATA :
••••••••••••••••
; Data processing
ADRS :
••••••••••••••••
; Address decode
µPD75238
(c) Shift register (SIO0)
Fig. 4-42 shows the configuration of peripheral hardware of shift register 0. SIO0 is an 8-bit register
which performs parallel-serial conversion and serial transfer (shift) operation in phase with the serial
clock.
Serial transfer is started by writing data to SIO0.
In send operation, data written to SIO0 is output on the serial output (SO0) or serial data bus (SB0/
SB1). In receive operation, data is read from the serial input (SI0) or SB0/SB1 into SIO0.
Data can be read from or written to SIO0 by using an 8-bit manipulation instruction.
When the RESET signal is entered during operation, the value of SIO0 is undefined. When the RESET
signal is entered in the standby mode, the value of SIO0 is preserved.
Shift operation is stopped after 8-bit send or receive operation is completed.
Fig. 4-42
Peripheral Hardware of Shift Register 0
Internal bus
Address
comparator
RELT
CMDT
Shift register 0
SO0 latch
SET
CLR
D
Q
CLK
CSIM0
Shift clock
BUSY/ACK
N-ch open-drain output
The timing for reading SIO0 and start of serial transfer (writing to SIO0) is as follows:
• When the serial interface operation enable/disable bit (CSIE0) = 1. However, the case where CSIE0
is set to 1 after data is written to the shift register is excluded.
• When the serial clock is masked after 8-bit serial transfer
• SCK0 is high.
When reading from or writing to SIO0, make sure that SCK0 is high.
In the two-wire serial I/O mode and SBI mode, the pins specified for the data bus are used for both
input and output. Because the configuration of output pins is N-ch open-drain, write FFH in SIO0 for
devices that are to receive data.
89
µPD75238
(d) Slave address register (SVA)
The slave address register (SVA) has the two functions described below.
SVA is manipulated using an 8-bit manipulation instruction. SVA allows only write operation.
When a RESET is entered, the value of SVA is undefined. However, the value of SVA is preserved
when the RESET is entered in the standby mode.
• Slave address detection
[In the SBI mode]
SVA is used when the µPD75238 is connected as a slave device to the serial bus. SVA is an 8-bit
register for a slave to set its slave address (number assigned to it). The master outputs a slave
address to the connected slaves to select a particular slave. Two data values (a slave address output
from the master and the value of SVA) are compared with each other by the address comparator.
If a match is found, the slave is selected.
At this time, bit 6 (COI) of serial operation mode register 0 (CSIM0) is set to 1.
Cautions 1. Slave selection or nonselection state is detected by detecting a match for a slave
address received after bus release (in the state of RELD = 1).
For this match detection, an address match interrupt (IRQCSI0) generated when
WUP is set to 1 is usually used. So detect selection/nonselection state by slave
address when WUP is set to 1.
2. When detecting selection/nonselection state without using an interrupt when WUP
is 0, do not use the address match detection method. Instead, use transfer of
commands set in advance in a program.
• Error detection
[In the two-wire serial I/O mode or SBI mode]
SVA detects an error in either of the following cases:
• When addresses, commands, or data is transferred with the µPD75238 operating as the master
• When data is transferred with the µPD75238 operating as a slave
(4) Signals
Table 4-6 lists signals. Fig. 4-43 to 4-48 show operations of signals and flags.
90
Table 4-6
Signal name
Bus release signal
(REL)
Output
device
Master
Various Signals Used in the SBI Mode (1/2)
Rising edge of SB0/SB1
when SCK0 = 1
Condition for
output
Timing chart
Definition
SCK0
Flag
operation
Meaning
of signal
• RELT is set.
• RELD is set.
• CMDD is cleared.
Indicates that CMD
signal follows and
data sent is address
data.
• CMDT is set.
• CMDD is set.
i) Data sent after
REL signal output
is address.
ii) Data sent, with
REL signal not
being output, is
command.
# ACKE = 1
$ ACKT is set.
• ACKD is set.
Indicates completion
of receive operation.
“H”
SB0/SB1
Command signal
(CMD)
Master
Falling edge of SB0/SB1
when SCK0 = 1
SCK0
“H”
SB0/SB1
Acknowledge
signal
(ACK)
Busy signal
(BUSY)
Ready signal
(READY)
Master/
slave
Slave
Slave
Low level signal
output on SB0/SB1
during one SCK0 clock
cycle after serial
receive operation is
completed
[Synchronous busy
signal]
Low level signal output
on SB0/SB1 after
acknowledge signal
• BSYE = 1
SCK0
9
SB0/
SB1
D0 ACK
SB0/
SB1
D0
–
BUSY
READY
BUSY
ACK
READY
# BSYE = 0
$ Execution of
instruction to
write data to
SIO0 (direction
to start transfer)
–
Indicates that serial
receive operation is
disabled because
processing is in
progress.
Indicates that serial
receive operation is
enabled.
91
µPD75238
High level signal
output on SB0/SB1
before serial transfer
is started or after
serial transfer is
completed
[Synchronous busy signal output]
92
Table 4-6
Signal name
Serial clock
Output
device
Master
(SCK0)
Various Signals Used in the SBI Mode (2/2)
Timing chart
Definition
Synchronous clock for
outputting address/
command/data, ACK
SCK0
signal, synchronous
BUSY signal, and so on. SB0/
Address/command/data SB1
is output during first 8
1
2
7
8
9
10
Condition for
output
Flag
operation
Meaning
of signal
Execution of
instruction to
write data to SIO0
IRQCSI0 is set (on
rising edge of
Note 1
ninth clock)
Timing of signal
output on serial data
bus
when CSIE0 = 1
(direction to
start serial
transfer)Note 2
clock cycles.
Master
Address
(A7 - A0)
8-bit data transferred in
phase with SCK0 after
REL signal and CMD
signal output
1
SCK0
Data
(D7 - D0)
Master
Master/
slave
8-bit data transferred in
phase with SCK0 after
only CMD signal is
output, with REL signal
not being output
7
8
2
7
8
Address of slave
device on serial bus
SB0/
SB1
REL
Command
(C7 - C0)
2
CMD
Directions and
1
SCK0
messages to slave
device
SB0/
SB1
CMD
8-bit data transferred in
phase with SCK0, with
SCK0
neither REL signal nor
CMD signal being
output
SB0/
SB1
1
2
7
8
Value processed by
slave or master
device
Notes 1. When WUP = 0, IRQCSI0 is always set on the ninth rising edge of SCK0.
When WUP = 1, IRQCSI0 is set on the ninth rising edge of SCK0 only if a received address matches the value of the slave address register (SVA).
µPD75238
2. If the BUSY state is present, data transfer is started after the READY state is set.
µPD75238
Fig. 4-43
Operations of RELT, CMDT, RELD, and CMDD (Master)
Transfer operation start specification
SIO0
SCK0
"H"
SO0 latch
RELT
CMDT
RELD
CMDD
Fig. 4-44
Operations of RELT, CMDT, RELD, and CMDD (Slave)
Transfer operation start specification
Write to SIO0
SIO0
SCK0
1
2
SO0 latch
D7
D6
7
D1
8
D0
RELT
(Master)
CMDT
(Master)
When address match is found
RELD
When address mismatch is found
CMDD
Fig. 4-45
Operation of ACKT
Set after transfer completion.
SCK0
SB0/SB1
6
7
D2
8
D1
9
D0
ACK
ACK signal is output during first clock
cycle immediately after ACKT is set.
ACKT
When set during this period
Caution Do not set the ACKT until the transfer is completed.
93
µPD75238
Fig. 4-46 Operation of ACKE
(a) When ACKE = 1 at time of transfer operation completion
SCK0
1
SB0/SB1
2
D7
7
D6
D2
9
8
D1
D0
ACK
The ACK signal is output
during the ninth clock
cycle
ACKE
When ACKE = 1 at this point
(b) When ACKE is set after transfer operation completion
SCK0
SB0/SB1
6
7
D2
8
D1
9
D0
ACK
The ACK signal is output
during the first clock cycle
immediately after ACKT is set.
ACKE
When ACKE is set during this period and ACKE = 1 at
the falling edge of the next SCK0
(c) When ACKE = 0 at time of transfer operation completion
SCK0
SB0/SB1
1
2
D7
7
D6
D2
9
8
D1
D0
The ACK signal is not
output
ACKE
When ACKE = 0 at this point
(d) When ACKE = 1 period is too short
SCK0
SB0/SB1
The ACK signal is not
output
ACKE
When ACKE is set or cleared during this period,
and ACKE = 0 at the falling edge of SCK0
94
µPD75238
Fig. 4-47
Operation of ACKD
(a) When ACK signal is output during ninth SCK0 clock
Transfer operation start specification
SIO0
Transfer operation start
SCK0
6
SB0/SB1
7
D2
8
D1
9
D0
ACK
ACKD
(b) When ACK signal is output after ninth SCK0 clock
Transfer operation start specification
SIO0
Transfer operation start
SCK0
6
SB0/SB1
7
D2
8
D1
9
D0
ACK
ACKD
(c) Clear timing for case where start of transfer is directed during BUSY
Transfer operation start specification
SIO0
SCK0
6
SB0/SB1
7
D2
8
D1
9
D0
ACK
BUSY
D7
D6
ACKD
Fig. 4-48
SCK0
SB0/SB1
6
7
8
Operation of BSYE
9
ACK
BUSY
BSYE
When BSYE = 1 at this point
When reset operation is executed during
this period and BSYE = 0 at the falling edge
of SCK0.
95
µPD75238
(5) Serial interface (channel 0) operation
(a) Operation halt mode
The operation halt mode is used when serial transfer is not performed. This mode reduces power
consumption.
The shift register 0 does not perform shift operation in this mode, so the shift register can be used
as a normal 8-bit register.
A RESET input sets the operation halt mode. The P02/SO0/SB0 pin and P03/SI0/SB1 pin function as
input-only port pins. The P01/SCK0 pin can be used as an input port pin by setting the serial operation
mode register 0.
(b) Three-wire serial I/O mode operations
The three-wire serial I/O mode is compatible with other modes used in the 75X series and 78K series.
Communication is performed using three lines: Serial clock (SCK0), serial output (SO0), and serial
input (SI0).
(i)
Communication operation
The three-wire serial I/O mode transfers data, with eight bits as one block. Data is transferred
bit by bit in phase with the serial clock.
The shift register performs shift operation on the falling edge of the serial clock (SCK0). Send
data is latched on the SO0 latch, and is output on the SO0 pin. Receive data applied to the SI0
pin is latched in the shift register 0 on the rising edge of SCK0.
When eight bits have been transferred, shift register 0 operation automatically terminates setting
the interrupt request flag (IRQCSI0).
Fig. 4-49
SCK0
1
Timing of Three-Wire Serial I/O Mode
2
3
4
5
6
7
8
SI0
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO0
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
IRQCSI0
Completion of transfer
Transfer operation is started in phase with falling edge of SCK0.
Execution of instruction that writes data to SIO0 (Transfer operation start specification)
96
µPD75238
The SO0 pin becomes a CMOS output and outputs the state of the SO0 latch. So the output state
of the SO0 pin can be manipulated by setting the RELT bit and CMDT bit.
However, this manipulation must not be performed during serial transfer operation.
The output state of the SCK0 pin can be controlled by manipulating the P01 output latch in the
output mode (internal system clock mode). (See (7) in Section 4.9.)
(ii)
Switching between MSB and LSB as the first transfer bit
The three-wire serial I/O mode has a function that can switch between the MSB and LSB as the
first bit of transfer.
Fig. 4-50 shows the configuration of shift register 0 (SIO0) and internal bus. As shown in Fig.
4-50, read or write operation can be performed by switching between the MSB and LSB.
This switching can be specified using bit 2 of serial operation mode register 0 (CSIM0).
Fig. 4-50
Transfer Bit Switching Circuit
7
6
Internal bus
1
0
LSB first
MSB first
Read/write gate
Read/write gate
SO0 latch
SI0
Shift resister 0 (SIO0)
D
Q
SO0
SCK0
The first bit is switched by changing the order of data bits written to shift register 0 (SIO0). The
shift operation order of SIO0 is always the same.
Accordingly, the first bit must be switched between the MSB and LSB before writing data to the
shift register 0.
97
µPD75238
(c) Two-wire serial I/O mode
The two-wire serial I/O mode can be made compatible with any communication format by programming.
In this mode, communication is basically performed using two lines: Serial clock (SCK0) and serial
data input/output (SB0 or SB1).
(i)
Communication operation
The two-wire serial I/O mode transfers data, with eight bits as one block. Data is transferred bit
by bit in phase with the serial clock.
The shift register 0 performs shift operation on the falling edge of the serial clock (SCK0). Send
data is latched on the SO0 latch, and is output on the SB0/P02 pin or SB1/P03 pin starting with
the MSB. Receive data applied to the SB0 pin or SB1 pin is latched in the shift register 0 on the
rising edge of SCK0.
When eight bits have been transferred, shift register 0 operation automatically terminates setting
the interrupt request flag (IRQCSI0).
Fig. 4-51
SCK0
SB0/SB1
Timing of Two-Wire Serial I/O Mode
1
2
D7
3
D6
4
D5
5
D4
6
D3
7
D2
8
D1
D0
IRQCSI0
Completion of transfer
Transfer operation is started in phase with falling edge of SCK0.
Execution of instruction that writes date to SIO0 (Transfer operation start spcification)
The SB0 or SB1 pin becomes an N-ch open-drain I/O when specified as the serial data bus, so
the voltage level on that pin must be pulled up externally.
The state of the SO0 latch is output on the SB0 or SB1 pin, so the SB0 or SB1 pin output states
can be controlled by setting the RELT or CMDT bit.
However, this operation must not be performed during serial transfer operation.
The output state of the SCK0 pin can be controlled by manipulating the P01 output latch in the
output mode (internal system clock mode). (See (7) in Section 4.9.)
98
µPD75238
(d) SBI mode operation
The SBI (serial bus interface) is a high-speed serial interface that conforms to the NEC serial bus
format.
To allow communication with multiple devices on a single-master and high-speed serial bus using
two signal lines, the SBI has a bus configuration function added to the clock synchronous serial I/O
method. So the SBI can reduce ports and wires on boards when multiple microcomputers and
peripheral ICs are used to configure a serial bus.
Fig. 4-52 is an example of the SBI system configuration.
Fig. 4-52
Example of SBI System Configuration
Master CPU
µ PD75238
SB0 (SB1)
Slave CPU
µ PD75238
SB0 (SB1)
Address 1
SCK0
SCK0
Slave CPU
SB0 (SB1)
Address 2
SCK0
Slave IC
SB0 (SB1)
Address N
SCK0
Cautions 1. In the SBI mode, the serial data bus pin SB0 (or SB1) is an open-drain output. So the
serial data bus line is placed in the wired OR state. A pull-up resistor is required for
the serial data bus line.
2. To switch between the master and slave, a pull-up resistor is required also for the serial
clock line (SCK0), because SCK0 input/output switching is performed between the
master and slave asynchronously.
99
µPD75238
(i)
SBI functions
• Address/command/data identification function
Serial data is classified into three types: Address, command, and data.
• Address-based chip select function
The master selects a chip by address transfer.
• Wake-up function
A slave can easily check address reception (for chip select identification) with the wake-up
function. This function can be set or released by software.
When the wake-up function is set, an interrupt (IRQCSI0) is generated when a match address
is received. For this reason, in communication with multiple devices, a CPU other than a
selected slave can operate independently of serial communication.
• Acknowledge signal (ACK) control function
The acknowledge signal, which is used to confirm the reception of serial data, can be
controlled.
• Busy signal (BUSY) control function
The busy signal, which is used to post the busy state of a slave, can be controlled.
Fig. 4-53
Timing of SBI Transfer
Address transfer
SCK0
8
SB0/SB1
A7
9
A0
ACK
BUSY
Bus release signal
Command transfer
Command signal
SCK0
SB0/SB1
9
C7
C0 ACK
BUSY
READY
BUSY
READY
Data transfer
SCK0
SB0/SB1
100
8
D7
9
D0 ACK
µPD75238
(ii)
Communication operation
In the SBI mode, the master usually selects a slave device to communicate with from multiple
devices by outputting the address of the slave in the serial bus.
After selecting a device to communicate with, the master exchanges commands and data with
the slave device, thus establishing serial communication.
Fig. 4-54 to 4-57 show the timing charts of data communication operations.
In the SBI mode, the shift register 0 performs shift operation on the falling edge of the serial clock
(SCK0). Send data is held on the SO0 latch, and is output on the SB0/P02 or SB1/P03 pin starting
with the MSB. Receive data applied to the SB0 (or SB1) pin is latched in the shift register 0 on
the rising edge of SCK0.
101
102
Fig. 4-54
Address Transfer Operation from Master Device to Slave Device (WUP = 1)
Master device processing (transmitter)
Program processing
Set
CMDT
Set
Set
RELT CMDT
Write
to SIO0
Interrupt handling (preparation for next serial transfer)
Stop
SCK0
Set
ACKD
Generate
IRQCSI0
Serial send operation
Hardware operation
Transfer line
SCK0 pin
1
SB0 pin
2
A7
3
A6
4
A5
5
A4
6
A3
7
A2
8
A1
9
A0
ACK
BUSY
READY
Address
Slave device processing (receiver)
Program processing
Hardware operation
WUP←0
Set
Clear Set
CMDD CMDD CMDD
Set
RELD
Serial receive operation
Generate
IRQCSI0
Set
ACKT
Clear
BUSY
Output Output
ACK BUSY
Clear
BUSY
(When SVA = SIO0)
µPD75238
Fig. 4-55
Command Transfer Operation from Master Device to Slave Device
Master device processing (transmitter)
Program processing
Set
CMDT
Write
to SIO0
Interrupt handling (preparation for next serial transfer)
Hardware operation
Stop
SCK0
Set
ACKD
Generate
IRQCSI0
Serial send operation
Transfer line
SCK0 pin
1
2
C7
SB0 pin
3
C6
4
C5
5
C4
6
C3
7
C2
8
C1
9
C0
ACK
BUSY
READY
Command
Slave device processing (receiver)
Read
SIO0
Program processing
Hardware operation
Set
CMDD
Serial receive operation
Generate
IRQCSI0
Analyze
command
Set
ACKT
Clear
BUSY
Output Output
BUSY
ACK
Clear
BUSY
µPD75238
103
104
Fig. 4-56
Data Transfer Operation from Master Device to Slave Device
Master device processing (transmitter)
Program processing
Write
to SIO0
Interrupt handling (preparation for next serial transfer)
Hardware operation
Set
ACKD
Generate
IRQCSI0
Serial send operation
Stop
SCK0
Transfer line
SCK0 pin
SB0 pin
1
2
D7
3
D6
4
D5
5
D4
6
D3
7
D2
8
D1
9
D0
ACK
BUSY
READY
Data
Slave device processing (receiver)
Read
SIO0
Program processing
Hardware operation
Serial receive operation
Generate
IRQCSI0
Set
ACKT
Clear
BUSY
Output Output
BUSY
ACK
Clear
BUSY
µPD75238
Fig. 4-57
Data Transfer Operation from Master Device to Slave Device ★
Master device processing (receiver)
Read
SIO0
Write FFH
to SIO0
Program processing
Stop
SCK0
Hardware operation
Generate
IRQCSI0
Serial receive operation
Set
Write FFH
ACKT to SIO0
Receive data processing
Output
ACK
Serial reception
Transfer line
SCK0 pin
SB0 pin
1
BUSY
READY
D7
2
3
D6
4
D5
5
D4
6
D3
7
D2
8
D1
9
1
D0
ACK
BUSY
2
D7
D6
READY
Data
Slave device processing (transmitter)
Program processing
Write
to SIO0
Hardware operation
Clear
BUSY
Write
to SIO0
Serial send operation
Generate
IRQCSI0
Set
ACKD
Output
BUSY
Clear
BUSY
µPD75238
105
µPD75238
(6) Transfer start in each mode
In each of the three-wire serial I/O, two-wire serial I/O, and SBI modes, serial transfer is started by writing
transfer data in shift register 0 (SIO0).
However, the following two conditions must be satisfied:
• The serial interface operation enable/disable bit (CSIE0) is set to 1.
• The internal serial clock is not operating after 8-bit serial transfer, or SCK0 is high.
Caution
Transfer operation cannot be started by setting CSIE0 to 1 after writing data to the shift register
0.
When eight bits have been transferred, serial transfer automatically terminates setting the interrupt
request flag (IRQCSI0).
[In the two-wire serial I/O mode]
Caution
The N-ch transistor needs to be turned off when data is received. So FFH must be written to
SIO0 beforehand.
[In the SBI mode]
Cautions 1. The N-ch transistor needs to be turned off when data is received. So FFH must be written
to SIO0 beforehand.
However, when the wake-up function specification bit (WUP) is set to 1, the N-ch transistor
is always off. So FFH need not be written to SIO0 beforehand for reception.
2. If data is written to SIO0 when the slave is busy, the data is not lost.
Transfer operation is started when the busy state is released and input to SB0 (or SB1) goes
high.
Example When RAM data specified by the HL register is transferred to SIO0, SIO0 data is loaded into the
accumulator at the same time, and serial transfer is started.
MOV
106
XA, @HL
; Extracts send data from RAM
SEL
MB15
; Or CLR1 MBE
XCH
XA, SIO0
; Exchanges send data with receive data and starts transfer
µPD75238
(7) Manipulation of SCK0 pin output
The SCK0/P01 pin has a built-in output latch, so that this pin allows static output by software manipulation
in addition to normal serial clock output.
The number of SCK0s can be software-set arbitrarily by manipulating the P01 output latch. (The SO0/
SB0/SB1 pin is controlled by manipulating the RELT and CMDT bits of SBIC.)
The procedure for manipulating SCK0/P01 pin output is explained below.
1
Set serial operation mode register 0 (CSIM0) (SCK0 pin: output mode, serial operation: enabled).
When serial transfer operation is halted, SCK0 from the serial clock control circuit is set to 1.
2
Manipulate the P01 output latch by using a bit manipulation instruction.
Example
To output one clock cycle on the SCK0/P01 pin by software
SEL
MB15
; or CLR1 MBE
MOV
XA, #10000011B ; SCK0 (fX/2 3), output mode
MOV
CSIM0, XA
CLR1
0FF0H.1
; SCK0/P01 ← 0
SET1
0FF0H.1
; SCK0/P01 ← 1
Fig. 4-58
SCK0/P01 Pin Circuit Configuration
P01/SCK0
To internal circuit
Address
FF0H.1
P01
output
latch
SCK0
From the serial clock
control circuit
When CSIE0=1 and CSIM01
and CSIM00 are not 00
The P01 output latch is mapped to bit 1 of address FF0H. A RESET signal sets the P01 output latch to 1.
Cautions 1.
2.
During normal serial transfer operation, the P01 output latch must be set to 1.
The P01 output latch cannot be addressed by specifying PORT0.1 (as described below). The
address of the latch (0FF0H.1) must be coded in the operand of an instruction directly.
However, MBE = 0 (or MBE = 1, MBS = 15) must be specified before the instruction is
executed.
CLR1 PORT0.1
Not allowed
SET1 PORT0.1
CLR1 0FF0H.1
SET1 0FF0H.1
Allowed
107
µPD75238
(8) Serial interface (channel 1) functions
The serial interface (channel 1) of the µ PD75238 has following two modes.
The functions of the two modes are outlined below.
• Operation halt mode
This mode is used when serial transfer is not performed. This mode reduces power consumption.
• Three-wire serial I/O mode
8-bit data transfer is performed using three lines: Serial clock (SCK1), serial output (SO1), and serial
input (SI1).
The three-wire serial I/O mode allows full-duplex transmission, so data transfer can be performed at
higher speed.
★
Eight-bit data transfer always starts the MSB.
The three-wire serial I/O mode enables connections to be made with the 75X series, 78K series, and many
other types of peripheral I/O devices.
(9) Serial interface (channel 1) configuration
Fig. 4-59 shows the block diagram of the serial interface (channel 1).
108
Fig. 4-59
Block Diagram of the Serial Interface (Channel 1)
Internal bus
Bit
manipulation
8
SIO1 write signal (serial start signal)
bit 0
P83/SI1
7
bit 7
SIO1
Shift register 1 (8)
Bit manipulation
8
0
CSIM1
Serial operation mode register (8)
P82/SO1
Clear
Serial clock
counter (3)
Serial transfer
end flag (EOT)
Overflow
Set
Clear
P81/SCK1
R
Q
S
fX/23
fX/24
109
µPD75238
Serial clock
selector
µPD75238
(10)
Functions of serial interface (channel 1) registers
(a) Serial operation mode register 1 (CSIM1)
Fig. 4-60 shows the format of serial operation mode register 1 (CSIM1).
CSIM1 is an 8-bit register which specifies a serial interface (channel 1) operation mode and serial
clock.
CSIM1 is manipulated using an 8-bit memory manipulation instruction. Only the high-order one
bit can be manipulated independently. Each bit can be manipulated using its name.
A RESET input clears all bits to 0.
Fig. 4-60
Address
FC8H
Format of Serial Operation Mode Register 1
7
6
5
4
3
2
CSIE1
0
0
0
0
0
1
0
CSIM11 CSIM10
Symbol
CSIM1
Serial clock selection bit (W)
CSIM11
CSIM10
0
0
External clock applied to SCK1 pin
0
1
Not to be set
1
0
fX/24 (262 kHz or 375 kHz)Note
1
fX/23
1
Serial clock (3-wire serial I/O mode)
(524 kHz or 750
SCK1 pin mode
Input
Output
kHz)Note
Note The values in parentheses are for fX = 4.19 MHz or 6.0 MHz.
Serial interface operation enable/disable specification bit (W)
Shift register 1
★
CSIE1
★
Serial clock counter
IRQCSI flag
0
Shift operation disabled
Cleared
Held
Used only for port 8
1
Shift operation enabled
Count operation
Can be set.
Port 8 is shared with
serial function
Caution Be sure to write 0 in bits 2 to 6 of the serial operation mode register.
110
SO1, SI1 pin
µPD75238
(b) Shift register 1 (SIO1)
SIO1 is an 8-bit register which performs parallel-serial conversion and serial transfer (shift)
operation in phase with the serial clock.
Serial transfer is started by writing data to SIO1.
In send operation, data written to SIO1 is output on the serial output (SO1). In receive operation,
data is read from the serial input (SI1) into SIO1.
Data can be read from or written to SIO1 using an 8-bit manipulation instruction.
When the RESET signal is entered during operation, the value of SIO1 is undefined. When the RESET
signal is entered in the standby mode, the value of SIO1 is preserved.
Shift operation is stopped after 8-bit send or receive operation is completed.
The timing for reading SIO1 and start of serial transfer (writing to SIO1) is as follows:
• When the serial interface operation enable/disable bit (CSIE1) is set to 1. However, the case where
CSIE1 is set to 1 after data is written to the shift register is excluded.
• When the serial clock is masked after 8-bit serial transfer
• When SCK1 is high
111
µPD75238
(11)
Serial interface (channel 1) operation
(a) Operation halt mode
The operation halt mode is used when serial transfer is not performed. This mode reduces power
consumption.
Shift register 1 does not perform shift operation in this mode, so the shift register can be used as
a normal 8-bit register.
A RESET input sets the operation halt mode.
The P82/SO1 pin and P83/SI1 pin are fixed to function for input ports. The P81/SCK1 pin can be used
as an input port pin by setting serial operation mode register 1.
(b) Three-wire serial I/O mode operations
The three-wire serial I/O mode is compatible with other modes used in the 75X series and 78K series.
Communication is performed using three lines: Serial clock (SCK1), serial output (SO1), and serial
input (SI1).
The three-wire serial I/O mode transfers data with eight bits as one block. Data is transferred bit
by bit in phase with the serial clock.
Shift register 1 performs shift operation on the falling edge of the serial clock (SCK1). Send data
is latched on the SO1 latch, and is output on the SO1 pin.
Receive data applied to the SI1 pin is latched in the shift register 1 on the rising edge of SCK1.
When eight bits have been transferred, operation of shift register 1 automatically terminates setting
the serial transfer end flag (EOT).
Fig. 4-61
SCK1
1
Timing of the Three-Wire Serial I/O Mode
2
3
4
5
6
7
8
SI1
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SO1
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
EOT
Completion of transfer
Transfer operation is started in phase with falling edge of SCK1.
Execution of instruction that writes data to SIO1 (Transfer operation start specification)
112
µPD75238
4.10
A/D CONVERTER
The µPD75238 contains an 8-bit analog/digital (A/D) converter that has eight analog input channels (AN0
to AN7).
The A/D converter employs the successive-approximation method.
(1) Configuration of the A/D converter
Fig. 4-62 shows the configuration of the A/D converter.
Fig. 4-62
Block Diagram of the A/D Converter
Internal bus
8
0
ADM6 ADM5 ADM4
SOC
EOC
0
0
8
AN0
Control circuit
AN1
Sample and hold circuit
AN2
+
AN3
Multiplexer
SA register (8)
–
AN4
Comparator
AN5
AN6
8
AN7
Tap decoder
AVREF
R/2
R
R
R
R/2
AVSS
113
µPD75238
(2) Pins of the A/D converter
(a) AN0 to AN7
AN0 to AN7 are the input pins for eight analog signal channels. Analog signals subject to A/D
conversion are applied to these pins.
The A/D converter contains a sample-and-hold circuit, and analog input voltages are internally
maintained during A/D conversion.
(b) AVREF, AVSS
A reference voltage for the A/D converter is applied to these pins.
By using an applied voltage across AVREF and AVSS, signals applied to AN0 to AN7 are converted to
digital signals.
AVSS must be always VSS.
★
(c) AVDD
This is the supply voltage pin for the A/D converter. When the A/D converter is not used or is in the
standby mode, the potential of the AVDD pin must be equal to that of the VDD pin.
(3) A/D conversion mode register
The A/D conversion mode register (ADM) is an 8-bit register used to select analog input channels, direct
the start of conversion, and detect the completion of conversion. (See Fig. 4-63.)
ADM is set with an 8-bit manipulation instruction. The conversion completion detection flag (EOC) in bit
2 and the conversion start direction bit (SOC) in bit 3 can be manipulated individually.
A RESET input initializes ADM to 04H. That is, only EOC is set to 1, with all bits cleared to 0.
114
µPD75238
Fig. 4-63
Format of the A/D Conversion Mode Register
Address
FD8H
Symbol
7
6
5
4
3
2
1
0
0
ADM6
ADM5
ADM4
SOC
EOC
0
0
ADM
End of conversion flag
0
Conversion under way
1
Conversion completed
EOC
Start of conversion bit
SOC
Setting this bit starts conversion.
After conversion is started, the bit is reset
automatically.
Analog channel selection bit
ADM6
ADM5
ADM4
Analog channel
0
0
0
AN0
0
0
1
AN1
0
1
0
AN2
0
1
1
AN3
1
0
0
AN4
1
0
1
AN5
1
1
0
AN6
1
1
1
AN7
Caution A/D conversion is started a maximum of 24/f X seconds (2.67 µs at 6.0 MHz)Note after SOC is set.
(See (5) in Section 4.10.)
Note 3.81 µs at 4.19 MHz
115
µPD75238
(4) SA register (SA)
The SA register (successive approximation register) is an 8-bit register to hold the result of A/D conversion
in successive approximation.
SA is read with an 8-bit manipulation instruction. No data can be written to SA by software.
A RESET input sets SA to 7FH.
(5) A/D converter operation
Analog input signals subject to A/D conversion are specified by setting bits 6, 5, and 4 in the A/D conversion
mode register (ADM6, ADM5, and ADM4).
A/D conversion is started by setting bit 3 (SOC) of ADM to 1. After that, SOC is automatically cleared to
0. A/D conversion is performed by hardware using the successive-approximation method. The resultant
8-bit data is loaded into the SA register. Upon completion of A/D conversion, bit 2 (EOC) of ADM is set
to 1.
Fig. 4-64 shows the timing chart of A/D conversion.
The A/D converter is used as follows:
1
Select analog input channels (by setting ADM6, ADM5 and ADM4).
2
Direct the start of A/D conversion (by setting SOC)3
3
Wait for the completion of A4D conversion (wait for EOC to be set or wait using a software timer).
4
Read the result of A/D conversion (read the SA register).
Cautions 1. 1 and 2 above can be performed at the same time.
2. There is a delay of up to 24/fX seconds (2.67 µs at 6.0 MHz)Note from the setting of SOC to
the clearing of EOC after A/D conversion is started. EOC must be tested when a time
indicated in Table 4-7 has elapsed after the setting of SOC. Table 4-7 also indicates A/D
conversion times.
Note 3.81 µs at 4.19 MHz
Table 4-7
Setting of SCC and PCC
Setting values of SCC, PCC
A/D conversion time
SCC3 SCC0 PCC1 PCC0
0
0
0
1
0
1
Waiting not required
3 machine cycles
2 machine cycles
21 machine cycles
1
4 machine cycles
42 machine cycles
Waiting not required
Waiting not required
168/fX
(28.0 µs at 6.0 MHz)Note
0
1
×
×
1
×
×
×
Note
40.1 µs at 4.19 MHz
Remark
116
0
Wait time from SOC setting Wait time from SOC setting
to A/D conversion completo EOC test
tion
×: Don’t care
Conversion stopped
—
—
µPD75238
Fig. 4-64
Timing Chart of A/D Conversion
SOC
EOC
SA register
Previous data
Undefined
Time elapsed before
A/D conversion starts
(Maximum of 24/fX s)
Result of conversion
Sampling time
A/D conversion
168/fX s (28 µ s at 6.0 MHz) Note
Note
40.1 µs at 4.19 MHz
(6) Notes on the standby mode
The A/D converter operates with the main system clock. So its operation stops in the STOP mode, or when
the subsystem clock is used, in the HALT mode. A current flows through the AVREF pin even when the
A/D converter is stopped, so that the current must be stopped to reduce overall system power consumption. Since the P21 pin has a higher drive capability than the other ports, it can supply voltage to the AVREF
pin directly.
In this case, however, the actual AVREF voltage does not provide precision. This means that the value
resulting from conversion does not provide precision and can be used only for relative comparison. In
the standby mode, outputting a low on the P21 can reduce power consumption.
In the standby mode, the potential of the AVDD pin must be equal to that of the VDD pin.
Fig. 4-65
Reducing Power Consumption in the Standby Mode
VDD
P-ch Note
P21
AVREF
.. VDD
AVREF =
µ PD75238
AVSS
Note
The drive capability of P-ch is higher than that of other ports.
117
µPD75238
(7) Other notes on use
(a) AN0 to AN7 input range
Specified voltages must be applied to AN0 to AN7 inputs. If a voltage higher than VDD or lower than
VSS is applied even when the maximum absolute rating is not exceeded, the conversion result for an
associated channel becomes unpredictable. In addition, the conversion results for other channels
may be affected.
(b) Noise protection
★
To maintain 8-bit resolution, the user should pay attention to noise that may be applied to the AVREF,
and AN0 to AN7 pins. Noise adversely affects operation to a greater extent when the analog input
source has a higher output impedance. As shown in Fig. 4-66, a capacitor should be externally
connected.
Fig. 4-66
VDD
Analog Input Pin Connection
If it is anticipated that noise voltages do not fall in the
range of VDD to VSS, clamp this point using a diode with
a low VF (not higher than 0.3 V).
AVREF, AN0 to AN7
C = 100 – 1000 pF
C
µ PD75238
VDD
VDD
AVDD
AVSS
VSS
(c) AN4/P90 to AN7/P93 pins
The analog input pins (AN4 to AN7) are also used for an input port (port 9).
When any of AN4 to AN7 is selected for A/D conversion, no input instruction must be executed for
port 9 during A/D conversion. Otherwise, the accuracy of conversion may deteriorate.
If a digital pulse signal is applied to a pin adjacent to a pin being used for A/D conversion, an expected
A/D conversion value may not be obtained because of coupling noise.
So no digital pulse signal should be applied to the adjacent pin being used for A/D conversion.
★
(d) AVDD pins
When the A/D converter is not used or is in the standby mode, the potential of the AVDD pin must be
equal to that of the VDD pin.
118
µPD75238
4.11
BIT SEQUENTIAL BUFFER: 16 BITS
The bit sequential buffer (BSB0 to BSB3) is special data memory for bit manipulations.
The buffer allows bit manipulations to be performed very easily by sequentially changing address and bit
specifications. So the buffer is particularly useful in processing long data bit by bit.
This data memory consists of 16 bits, and allows pmem.@L addressing with a bit manipulation instruction
and also allows indirect bit specification using the L register.
In this case, only by incrementing or
decrementing the L register in a program loop, the bit to be manipulated can be sequentially shifted for
continued processing.
Fig. 4-67
FC3H
Address
3
Bit
2
1
FC2H
0
3
BSB3
Symbol
L register
Format of the Bit Sequential Buffer
L=F
2
1
FC1H
0
3
BSB2
L=C L=B
2
FC0H
1
0
3
BSB1
L=8 L=7
2
1
0
BSB0
L=4 L=3
L=0
DECS L
INCS L
Remark In pmem.@L addressing, bit specification is shifted according to the L register. With pmem.@L
addressing, bit sequential buffer can be manipulated at any time regardless of MBE/MBS
specification.
Data can also be manipulated using direct addressing. The buffer can be used for applications such as
continuous 1-bit data input or output operations by combining direct 1-bit, 4-bit, and 8-bit addressing with
pmem.@L addressing. In 8-bit manipulation, the higher eight bits or lower eight bits can be manipulated by
specifying BSB0 or BSB2.
4.12
FIP CONTROLLER/DRIVER
(1) Configuration of the FIP controller/driver
The µPD75238 contains a display controller that reads the contents of display data memory by DMA
operation and generates digit and segment signals automatically. It also contains a high-voltage output
buffer that can directly drive a fluorescent indicator lamp (FIP). Fig. 4-68 shows the configuration of the
FIP controller/driver.
Caution
The FIP controller/driver can operate only when the high-speed or medium-speed (PCC = 0011B
or 0010B) is set for the main system clock (SCC.0 = 0). With the other clocks or in the standby
mode, the FIP controller/driver may malfunction. Disable FIP controller operation (DSPM.3 =
0) before entering into the standby mode.
119
120
Fig. 4-68
Block Diagram of the FIP Controller/Driver
Internal bus
8
Static
mode
register B
4/8
Display data
memory
(32 × 4 bits)
Key scan register (KS2)
Display data memory
(64 × 4 bits)
Key scan registers
(KS0 and KS1)
8
Segment data
latch (8)
4
4
4
Display
mode
register
Digit
select
register
Dimmer
select
register
4/8
Key scan
flag (KSF)
8
Static
mode
register A
Key scan flag
(KSF)
Port H
4
12
INTKS
IRQKS
set signal
Digit signal
generator
Segment data latch (16)
4
4
Selector
8
10
2
2
4
4
Selector
2
High-voltage
output buffer
4
10
Hige-voltage output buffer
8
10
S16/P100S23/P113
S0/P120S9/P141
2
4
S10/T15/P142
S12/T13/P150/PH0and S11/T14/P143 S15/T10/P153/PH3
10
T0-T9
VLOAD
µPD75238
µPD75238
(2) FIP controller/driver functions
The FIP controller/driver contained in the µPD75238 has the following functions:
(a) The FIP controller/driver automatically reads display data and generates a segment signal (DMA
operation) and a digit signal.
(b) An FIP having 9 to 24 segments and 9 to 16 digits can be controlled with the display mode register
(DSPM), digit select register (DIGS), static mode register A (STATA), and static mode register B
(STATB). (Up to 34 display outputs are allowed.)
(c) Any outputs not used for dynamic display can be used as static outputs or output ports.
(d) The dimmer function provides eight levels of intensity.
(e) Hardware that makes key scan application possible
• An interrupt (IRQKS) is caused for key scanning (detection of key scan timing).
• Key scan data can be output on a segment output with key scan buffers (KS0, KS1, and KS2).
(f) A high-voltage output pin (40 V) is provided which can directly drive the FIP.
• Segment output pins (S0 to S9, S16 to S23): VOD = 40 V, IOD = 3 mA
• Digit output pins (T0 to T15): VOD = 40 V, IOD = 15 mA
(g) Mask options for display output pins
• A pull-down resistor to VLOAD can be incorporated bit by bit for T0 to T9 and S0 to S15.
• A pull-down resistor to VLOAD or VSS can be incorporated bit by bit for S16 to S23. VLOAD or VSS must
be selected in 8-bit units.
(3) Difference of the display output function between the µPD75238, µPD75216A, and µPD75217
Table 4-8 shows the difference of the display output function between the µPD75238, µPD75216A, and
µPD75217.
Table 4-8
Difference of the Display Output Function between the µPD75238, µ PD75216A, and µPD75217
µPD75238
µPD75216A, µPD75217
High-voltage output display
FIP output total : 34
Segment output : 9 - 24
Digit output
: 9 - 16
FIP output total : 26
Segment output : 9 - 16
Digit output
: 9 - 16
Display data area
1A0H-1FFH
1C0H-1FFH
Output dual-function pin
S0-S23 (Port 10-port 15)
S12-S15 (Port H)
Key scan register
KS0-KS2
KS0, KS1
121
µPD75238
Fig. 4-69
FIP Controller Operation Timing
TCYT
TDSP
TKS
T0
T1
T2
TDIG
TN
Key scan
flag (KSF)
Changeable
at any time
Segment
data
1 display
cycle
Key scan timing
IRQKS generation
N
: Value set in the digit select register
TDSP : One display cycle (1024/fX: 171 µs at 6.0 MHzNote 1 or 2048/fX: 341 µs at 6.0 MHzNote 2)
TCYT : Display cycle (TCYT = T DSP × (N + 2))
TDIG : Digit signal pulse width, which can be selected from eight levels with the dimmer select register
Notes 1. 244 µs at 4.19 MHz
2. 489 µs at 4.19 MHz
122
µPD75238
(4) Display mode register (DSPM)
The display mode register (DSPM) is a 4-bit register for enable/disable setting for the display operation
and for specifying the number of display segments. Fig. 4-70 shows the format of the register.
The display mode register is set with a 4-bit memory manipulation instruction.
Before a standby mode (STOP mode or HALT mode) can be set or the subsystem clock (fXT) can be used
for operation, display must be disabled by setting DSPM.3 to 0.
A RESET input clears all bits to 0.
Fig. 4-70
Address
F88H
Display Mode Register Format
3
2
1
0
Symbol
DSPM3
DSPM2
DSPM1
DSPM0
DSPM
Bit for specifying the number of display segments
DSPM2
DSPM1
DSPM0
Number of display segments
0
0
0
9 segments (+ 8 segments)
0
0
1
10 segments (+ 8 segments)
0
1
0
11 segments (+ 8 segments)
0
1
1
12 segments (+ 8 segments)
1
0
0
13 segments (+ 8 segments)
1
0
1
14 segments (+ 8 segments)
1
1
0
15 segments (+ 8 segments)
1
1
1
16 segments (+ 8 segments)
Remark Segments in parentheses are added when pins S16 to S23 are specified as dynamic mode
in STATB.
Display operation enable/disable bit
0
Display disabled
1
Display enabled
DSPM3
(5) Digit select register (DIGS)
The digit select register (DIGS) is a 4-bit register that specifies the number of display digits. Fig. 4-71 shows
the format of the register.
DIGS is set with a 4-bit memory manipulation instruction. This register enables the number of display
digits to be selected from 9 to 16 digits. No other values can be selected.
A RESET input initializes the register to 1000B so that 9-digit display is selected.
Fig. 4-71 Digit Select Register Format
Address
F8AH
3
2
1
0
DIGS3
DIGS2
DIGS1
DIGS0
Symbol
DIGS
Caution Do not set a value from 0 to 7 for N.
DIGS0-3 set value
Number of display digits
N (= 8 to 15)
N+1
123
µPD75238
(6) Dimmer select register (DIMS)
The dimmer select register (DIMS) is a 4-bit register for specifying a digit signal cut width to prevent display
light leakage and to use the dimmer function (for intensity control). In addition, the register is used to
select a display cycle (TDSP).
Fig. 4-72 shows the format of DIMS.
DIMS is set with a 4-bit memory manipulation instruction.
A display cycle of 341 µs at 6.0 MHzNote 1 is usually selected by setting 1 in DIMS.0 for reduced light leakage.
However, as the number of display digits increases, the display cycle becomes closer to the frequency
of commercial power, causing the display to fricker. In this case, a display cycle of 171 µs at 6.0 MHzNote
2 should
be selected. If light leakage occurs in this case, adjust cutting width of the digit single by setting
DIMS.1, DIMS.2, and DIMS.3.
A RESET input clears all bits to 0.
Notes 1. 489 µs at 4.19 MHz
2. 244 µs at 4.19 MHz
Fig. 4-72
Dimmer Select Register Format
Address
F89H
Symbol
DIMS3
DIMS2
DIMS1
DIMS0
DIMS
Display cycle specification bit
0
A display cycle is 1024 . (One cycle = 171µ s/6.0 MHz) Note 1
fX
1
A display cycle is 2048 . (One cycle = 341µ s/6.0 MHz) Note 2
fX
DIMS0
Digit signal cut width specification bit
DIMS3
DIMS2
DIMS1
0
0
0
1/16
0
0
1
2/16
0
1
0
4/16
0
1
1
6/16
1
0
0
8/16
1
0
1
10/16
1
1
0
12/16
1
1
1
14/16
Notes 1. 244 µs at 4.19 MHz
2. 489 µs at 4.19 MHz
124
Digit signal cut width
µPD75238
(7) Static mode registers
A static mode registers are registers used to specify static output/dynamic output of the segment output
pins.
There are two static mode registers: static mode register A and static mode register B. Fig. 4-73 and Fig.
4-74 show their formats.
These registers are set with an 8-bit manipulation instruction. A RESET input clears all bits to 0.
(a) Static mode register A (STATA)
Static mode register A (STATA) is a register to specify static output/dynamic output of the S0/P120
to S15/P153/T10/PH3 pins.
Fig. 4-73 Static Mode Register A (STATA)
Address
7
6
5
4
FD6H
0
0
0
0
3
2
1
0
STATA3 STATA2 STATA1 STATA0
Symbol
STATA
S0 to S15 pins Static output/dynamic output selection bit
STATA3 STATA2 STATA1 STATA0
Output status of S0 to S15 pins
0
0
0
0
S0 to S15 become dynamic outputs. The
number of segments and the number of digits
are set by DSPM and DIGS.
1
1
1
1
S0 to S15 become static outputs. Static data is
output by issuing an output instruction for ports
12 to 15. The outputs are independent of the
value of DSPM.3.
Caution Part of the S0 to S15 pins cannot be set as dynamic outputs while the other pins are set
as static outputs.
125
µPD75238
(b) Static mode register B (STATB)
Static mode register B (STATB) is a register to specify static output/dynamic output of the S16/P100
to S23/P113 pins.
Fig. 4-74 Static Mode Register B (STATB)
Address
7
6
FD4H
0
0
5
4
STATB5 STATB4
3
2
1
0
Symbol
0
0
0
0
STATB
S16 to S23 pins Static output/dynamic output selection bit
STATB5
STATB4
Output status of S16 to S23 pins
0
0
S16 to S23 become dynamic outputs. Output depends on
the contents of 1A0H to 1BDH.
1
1
S16 to S23 become static outputs. Static data is output
by issuing an output instruction for ports 10 and 11.
The outputs are independent of the value of DSPM.3.
Caution Part of the S16 to S23 pins cannot be set as dynamic outputs while the other pins are set
as static outputs.
126
µPD75238
(8) Selection of display mode
The number of segments and number of digits which can be displayed by the internal FIP controller/driver
are determined by display modes.
Fig. 4-75 shows the selection of display mode.
Fig. 4-75
Selection of Display Mode
Number of digits
0
9
10
11
12
13
14
15
16
9-segment mode
9
10-segment mode
10
11-segment mode
11
12-segment mode
12
13-segment mode
13
14-segment mode
14
Number of segments
15-segment mode
15
16-segment mode
16
17-segment mode
17
18-segment mode
18
19-segment mode
19
20-segment mode
20
21-segment mode
21
22-segment mode
22
23-segment mode
23
24-segment mode
24
Remark The shaded circles indicate extended modes derived from the µPD75216A and µPD75217.
127
µPD75238
(9) Display data memory
Display data memory stores segment data for display. It is mapped to addresses 1A0H to 1FFH in data
memory. The display controller automatically reads display data (DMA operation). Area not used for
display can be used as normal data memory.
Display data is manipulated with data memory manipulation instructions in 1-, 4-, and 8-bit units. With
8-bit manipulation instructions, only even-numbered addresses can be specified.
Display data memory locations at 1FCH to 1FFH, 1BEH, and 1BFH are also used as key scan registers KS0,
KS1, and KS2.
Table 4-9
Data Memory Locations Also Used as Key Scan Registers
Key scan register
Data memory locations
KS0
1FCH, 1FDH
KS1
1FEH, 1FFH
KS2
1BEH, 1BFH
Caution Special care must be paid when a program developed for the µPD75238 is transported to the
µPD75216A or the µPD75217. This is because the µPD75216A and the µPD75217 allow up to
16 display segments, and do not contain data memory at the addresses (1A0H + 4n, 1A1H +
4n).
128
µPD75238
Fig. 4-76
Correspondence between Display Data Memory and Segment Output
24-segment mode
23-segment mode
22-segment mode
21-segment mode
20-segment mode
19-segment mode
18-segment mode
17-segment mode
16-segment mode
15-segment mode
14-segment mode
13-segment mode
12-segment mode
11-segment mode
10-segment mode
9-segment mode
Display data memory
Key
scan
data
03
03
03
03
03
0
1A1H
1A0H
1C3H
1C2H
1C1H
1C0H
T0
1A3H
1A2H
1C7H
1C6H
1C5H
1C4H
T1
1A5H
1A4H
1CBH
1CAH
1C9H
1C8H
T2
1A7H
1A6H
1CFH
1CEH
1CDH
1CCH
T3
1A9H
1A8H
1D3H
1D2H
1D1H
1D0H
T4
1ABH
1AAH
1D7H
1D6H
1D5H
1D4H
T5
1ADH
1ACH
1DBH
1DAH
1D9H
1D8H
T6
1AFH
1AEH
1DFH
1DEH
1DDH
1DCH
T7
1B1H
1B0H
1E3H
1E2H
1E1H
1E0H
T8
1B3H
1B2H
1E7H
1E6H
1E5H
1E4H
T9
1B5H
1B4H
1EBH
1EAH
1E9H
1E8H
T10
1B7H
1B6H
1EFH
1EEH
1EDH
1ECH
T11
1B9H
1B8H
1F3H
1F2H
1F1H
1F0H
T12
1BBH
1BAH
1F7H
1F6H
1F5H
1F4H
T13
1BDH
1BCH
1FBH
1FAH
1F9H
1F8H
T14
1BFH
1BEH(KS2)
1FFH
1FEH(KS1)
1FDH
1FCH(KS0)
T15
KS2
KS1
KS0
Timing output
Bit 3
Tks
Segment
S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
output
Timing
output
T10 T11 T12 T13 T14 T15 (When specified by digit select register)
Port H
output
PH3 PH2 PH1 PH0 (When neither segment output nor timing output is required)
129
µPD75238
(10) Key scan registers (KS0, KS1, and KS2)
The key scan registers (KS0, KS1, and KS2) set segment output data on the key scan timing that is mapped
to display data memory locations (1FCH, 1FDH, 1FEH, 1FFH, 1BEH, and 1BFH).
KS0, KS1, and KS2 are 8-bit registers, which are usually manipulated with an 8-bit manipulation
instruction. (One-bit or 4-bit manipulation is also possible for the lower 4 bits.)
The data set in KS0, KS1, and KS2 is output on the segment output pins on the key scan timing. During
the key scan timing, the rewriting of KS0, KS1, and KS2 is immediately reflected in segment output data,
which can be used for key scanning.
(11) Key scan flag (KSF)
The key scan flag (KSF) is set to 1 on the key scan timing, and is automatically reset to 0 on any other
timing. KSF is mapped to bit 3 at address F8AH, and can be tested on a single-bit basis. KSF cannot
be written to. Testing this flag can determine whether the key scan timing is present, so that the validity
of key input data can be determined.
130
µPD75238
5. INTERRUPT FUNCTION
The µPD75238 has eight interrupt sources and can handle multiple interrupts with a priority.
The µPD75238 is also provided with two test sources. One test source, INT2, is set by edge detection testable
input.
Table 5-1
Interrupt Sources
Interrupt source
In/out
PriorityNote 1
Vector interrupt request
signal (vector table
address)
In
1
VRQ1 (0002H)
INTBT
(Reference time interval signal from basic
interval timer)
INT4
(Detection of rising or falling edge)
Out
INT0
(Rising/falling edge detection specification)
Out
2
VRQ2 (0004H)
Out
3
VRQ3 (0006H)
INT1
INTCSI0
(Serial data transfer completion signal)
In
4
VRQ4 (0008H)
INTT0
(Match signal from timer enter/counter 0)
In
5
VRQ5 (000AH)
INTTPG
(Match signal from timer/pulse generator)
In
6
VRQ6 (000CH)
INTKS
(Key scan timing signal from display controller)
In
7
VRQ7 (000EH)
INT2Note 2
(Detection of rising edge )
INTWNote 2
(Signal from clock timer)
Out
Testable input signal (Sets IRQ2 and IRQW.)
In
Notes 1. The priority is used when two or more interrupt requests are issued at a time.
2. INT2 and INTW are test sources. Like interrupt sources, these test sources are controlled by an
interrupt enable flag. But, they do not cause vector interrupts.
The following functions are provided for the interrupt control circuit of the µPD75238.
(a) Vector interrupt function under hardware control which can determine whether to accept an interrupt by
an interrupt enable flag (IE×××) and the interrupt master enable flag (IME)
(b) Any interrupt start address can be set.
(c) Multiple interrupt function which can specify the priority by the interrupt priority specification register
(IPS)
(d) Test function of an interrupt request flag (IRQ×××)
(The software can confirm that an interrupt occurred.)
(e) Release of the standby mode (Interrupts released by an interrupt enable flag can be selected.)
5.1
CONFIGURATION OF THE INTERRUPT CONTROL CIRCUIT
The interrupt control circuit of the µPD75238 is configured as shown in Fig. 5-1. Each hardware item is
mapped in the data memory space.
131
132
Fig. 5-1 Block Diagram of Interrupt Control Circuit
Internal bus
2
2
IM1
IM0
4
(IME)
2
IPS
IST
Interrupt enable flag (IE×××)
INT
BT
Noise
eliminator
INT4
/P00
INT0
/P10
INT1
/P11
Both-edge
detection
circuit
Edge
detection
circuit
Edge
detection
circuit
INTCSI0
INTT0
INTTPG
INT2
/P12
IRQ4
VRQn
IRQ0
IRQ1
Priority control circuit
IRQCSI0
Vector table
address
generator
IRQT0
IRQTPG
INTKS
IPQKS
INTW
IRQW
Rising edge
detection
circuit
Decoder
IRQBT
Standby release signal
IRQ2
µPD75238
µPD75238
5.2
HARDWARE OF THE INTERRUPT CONTROL CIRCUIT
(1) Interrupt request flag and interrupt enable flag
There are ten interrupt request flags (IRQ×××), listed below, each corresponding to a particular interrupt
★
or test source; there are 8 interrupt and 2 test sources.
INT0 interrupt request flag (IRQ0)
Serial interface interrupt request flag (IRQCSI0)
INT1 interrupt request flag (IRQ1)
Timer/event counter interrupt request flag (IRQT0)
INT2 interrupt request flag (IRQ2)
Timer/pulse generator interrupt request flag (IRQTPG)
INT4 interrupt request flag (IRQ4)
Key scan interrupt request flag (IRQKS)
BT interrupt request flag (IRQBT)
Clock timer interrupt request flag (IRQW)
The interrupt request flag is set to 1 when an interrupt request is issued, and is automatically cleared to
0 when the CPU is interrupted. Since the IRQBT and IRQ4 share the vector address, the clear operation
varies. (See Section 5.5.)
There are ten interrupt enable flags (IE×××), listed below, each corresponding to a particular interrupt
request flag.
INT0 interrupt enable flag (IE0)
Serial interface interrupt enable flag (IECSI0)
INT1 interrupt enable flag (IE1)
Timer/event counter interrupt enable flag (IET0)
INT2 interrupt enable flag (IE2)
Timer/pulse generator interrupt enable flag (IETPG)
INT4 interrupt enable flag (IE4)
Key scan interrupt enable flag (IEKS)
BT interrupt enable flag (IEBT)
Clock timer interrupt enable flag (IEW)
When an interrupt request flag is set, the interrupt enable flag corresponding to that interrupt request flag
enables the request interrupt. When an interrupt request flag is cleared, the interrupt enable flag
corresponding to that interrupt request flag disables the interrupt.
When an interrupt request flag is set and its corresponding interrupt enable flag enables the requested
interrupt, a vector interrupt request (VRQn) is issued. This signal is also used for releasing the standby
mode.
The interrupt request flags and interrupt enable flags are manipulated with bit manipulating instructions
and 4-bit memory manipulation instructions. When a bit manipulation instruction is used, the flags can
always be manipulated directly irrespective of the MBE setting. The interrupt enable flags are manipulated
with EI IE××× and DI IE××× instructions. An SKTCLR instruction is normally used to test an interrupt request
flag.
When an interrupt request flag is set with an instruction, a vector interrupt is executed irrespective of
whether an interrupt occurs.
A RESET input clears an interrupt request flag and its corresponding interrupt enable flag to 0 and all
interrupts are disabled.
133
★
µPD75238
Table 5-2 Set Signals of Interrupt Request Flags
Interrupt
request flag
★
Set signal of interrupt request flag
Interrupt
enable flag
IRQBT
Set by a reference time interval signal from the basic interval timer.
IEBT
IRQ4
Set by a detected rising or falling edge of an INT4/P00 pin input signal.
IE4
IRQ0
Set by a detected edge of an INT0/P10 pin input signal. The detection edge is specified
by the INT0 mode register (IM0).
IE0
IRQ1
Set by a detected edge of an INT1/P11 pin input signal.
by the INT1 mode register (IM1).
IE1
IRQCSI0
Set by a serial data transfer completion signal for the serial interface.
IECSI0
IRQT0
Set by a match signal from timer/event counter 0.
IET0
IRQTPG
Set by a match signal from the timer/pulse generator.
IETPG
IRQKS
Set by a key scan timing signal from the display controller.
IEKS
IRQW
Set by a signal from the clock timer.
IEW
IRQ2
Set by a detected rising edge of an INT2/P12 pin input signal.
IE2
The detection edge is specified
(2) Noise eliminator and edge detection mode register
As shown in Fig. 5-2 and Fig. 5-3, the INT0, INT1, and INT2 pins are configured as external interrupt input
pins that enable detection edge selection.
In addition, INT0 is provided with a noise elimination function based on a sampling clock. Basically, the
noise eliminator eliminates pulses narrower than two sampling clock cyclesNote as noise. However, it may
accept pulses wider than one sampling clock cycle as interrupt signals depending on the sampling timing.
It surely accepts pulses wider than two sampling clock cycles as interrupt signals.
INT0 has two sampling clocks Φ and fX/64, either of which can be selected according to bit 3 (IM03) of the
edge detection mode register (see Fig. 5-4).
The IRQ2 is set by detecting a rising edge of the INT2 pin input.
The edge detection mode registers (IM0 and IM1) used to select a detection edge have the format shown
in Fig. 5-4. A 4-bit memory manipulation instruction is used to set IM0 or IM1. A RESET input clears all
bits to 0, and a rising edge is selected for INT0, INT1, and INT2.
Note When a sampling clock is Φ, two sampling clock cycles are 2tCY.
When a sampling clock is fX/64, two sampling clock cycles are 128/fX.
Cautions 1. Since the INT0 pin input is sampled with a clock, INT0 does not operate in a standby mode.
2. When INT0/P10 is used as a port, pulses input from INT0/P10 go through the noise
eliminator. So the input pulses must be wider than two sampling clock cycles.
134
µPD75238
Fig. 5-2
Configuration of INT0 and INT1
INT0
IRQ0 set
signal
Edge detection
circuit
Noise
eliminator
INT0/P10
IM01, IM00
Φ
Selector
IM03
2
fX
64
Φ
INT1
IRQ1 set
signal
Edge detection
circuit
INT1/P11
IM10
Input buffer
IM1
IM0
4
4
Internal bus
Fig. 5-3
Configuration of INT2
Rising edge
detection
circuit
INT2/P12
INT2
IRQ2 set
signal
Input buffer
Internal bus
135
µPD75238
Fig. 5-4
Address
FB4H
Format of Edge Detection Mode Registers
3
2
1
0
IM03
0
IM01
IM00
Symbol
IM0
Detection edge specification
★
0
0
Specifies rising edge.
0
1
Specifies falling edge.
1
0
Specifies both rising and falling edges.
1
1
Ignored (interrupt request flag is not set.)
Sampling clock
FB5
0
0
0
IM10
0
Φ (0.67µs, 1.33µs, 2.67µ s, or 10.7µ s at 6.0 MHz) Note 1
1
fX /64 (10.7µ s at 6.0 MHz) Note 2
IM1
0
Specifies rising edge.
1
Specifies falling edge.
Notes 1. 0.95 µs, 1.91 µ s, 3.82 µs, or 15.3 µs at 4.19 MHz
2. 15.3 µs at 4.19 MHz
Caution Since changing the edge detection mode register may set an interrupt request flag, disable the
interrupts before changing the edge detection mode register. Then clear the interrupt request
flag with a CLR1 instruction and enable the interrupts. When fX/64 is selected as a sampling
clock pulse in changing IM0, wait for 16 machine cycles after changing the mode register and
clear the interrupt request flag.
136
µPD75238
(3) Interrupt priority specification register (IPS)
The interrupt priority specification register specifies an interrupt with a higher priority from multiple
interrupts using the low-order three bits.
Bit 3, interrupt master enable flag (IME), specifies whether to disable all interrupts.
The IPS is set with a 4-bit memory manipulation instruction. Bit 3 is set with an EI instruction and reset
with a DI instruction.
When changing the low-order three bits of the IPS, interrupts must be disabled (IME = 0) beforehand.
A RESET input clears all bits to 0.
Fig. 5-5
Interrupt Priority Specification Register
Address
FB2H
Symbol
3
2
1
0
IPS3
IPS2
IPS1
IPS0
IPS
High-order interrupt selection
0
0
0
All low-order interrupt
0
0
1
VRQ1 (INTBT/INT4)
0
1
0
VRQ2 (INT0)
0
1
1
VRQ3 (INT1)
1
0
0
VRQ4 (INTCSI0)
1
0
1
VRQ5 (INTT0)
1
1
0
VRQ6 (INTTPG)
1
1
1
VRQ7 (INTKS)
The listed vector
interrupts are treated
as high-order interrupts.
Interrupt master enable flag (IME)
0
All interrupts are disabled and no vector interrupt is
activated.
1
The interrupt enable flag corresponding to an interrupt
request flag controls interrupt enabling/disabling.
137
µPD75238
5.3
INTERRUPT SEQUENCE
The following flowchart shows the sequence of an interrupt.
Interrupt (INT×××) occurrence
IRQ××× setting
NO
IE××× set?
Hold until IE××× is set.
YES
Corresponding VRQn occurrence
IME = 1
NO
Hold until IME
is set.
YES
Depending on the
instrucrtion being
executed when
IRQn is set
Is VRQn
high-order
interrupt?
Hold until processing being executed
is finished
NO
YES
Note 1
NO
IST1, 0 = 00 or 01
NO
Note 1
IST1, 0 = 00
YES
YES
If two or more VRQns occur,
select one VRQn according to
Table 5-1.
Selected
VRQn
Remaining
VRQns
Save contents of PC and PSW in stack memory and set dataNote 2 in vector table
corresponding to activated VRQn to PC, RBE, and MBE.
Change contents of IST0 and IST1 from 00 to 01
or from 01 to 10.
2 machine
cycles
Reset accepted IRQ×××.
See Section 5.5 when those interrupt
sources share vector address.
Start processing the interrupt service program.
Notes 1. IST1 and IST0: Interrupt status flags (Bits 3 and 2 of PSW. See Table 5-3.)
2. Each vector table must store the start address of the interrupt service program and the set values
of the MBE and RBE at the start of an interrupt.
138
µPD75238
5.4
MULTIPLE INTERRUPT PROCESSING CONTROL
The µPD75238 can handle multiple interrupts by either of the following methods.
(1) Multiple interrupt processing by a high-order interrupt
In this method, the µPD75238 selects an interrupt source among multiple interrupt sources, enabling
double interrupt processing.
That is, the high-order interrupt specified by the interrupt priority specification register (IPS) is enabled
when the processing status is 0 or 1. Other interrupts (interrupts lower than the specified high-order
interrupt) are enabled only when the status is 0. (See Fig. 5-6 and Table 5-3.)
Fig. 5-6
Multiple Interrupt Processing by a High-Order Interrupt
Low- or high-order
interrupt processing
(Status 1)
Normal
processing
(Status 0)
High-order
interrupt
processing
(Status 2)
Interrupt is disabled.
IPS setting
Interrupt is enabled.
High-order
interrupt
occurrence
Low- or high-order
interrupt occurrence
Table 5-3
IST1
IST0
Interrupt Processing Statuses of IST1 and IST0
After acceptance
Processing
status
CPU operation
Interrupts that can be accepted
IST1
IST0
0
0
Status 0
Is processing the normal
program.
All
0
1
0
1
Status 1
Is processing a low- or highorder interrupt.
Only high-order interrupts
1
0
1
0
Status 2
Is processing a high-order
interrupt.
None
–
–
1
1
This status is disabled.
IST1 and IST0 are saved with the remaining PSW in the stack memory when an interrupt is accepted and
the status of IST0 and IST1 changes to a status one level higher. When an RETI instruction is executed,
the former values of IST0 and IST1 are returned.
139
µPD75238
(2) Multiple interrupt processing by changing the interrupt status flags
As shown in Table 5-3, changing the interrupt status flags with the program causes multiple interrupts
to be enabled. That is, when the interrupt processing program changes both IST1 and IST0 to 0 (status
0), multiple interrupt processing is enabled.
This method is used when two or more interrupts are to be enabled at a time or when the processing of
three or more interrupts is to be performed.
When changing IST1 and IST0, interrupts must be disabled beforehand with a DI instruction.
Fig. 5-7
Multiple Interrupt Processing by Changing the Interrupt Status Flags
Normal processing
(status 0)
Single interrupt
Interrupt is disabled.
IPS setting
Interrupt is enabled.
Low- or high-order
interrupt occurrence
Dual interrupts
Status 1
Interrupt is
disabled.
Modification
of IST
Interrupt is
enabled.
Status 0
Status 1
Low- or high-order
interrupt occurrence
High-order
interrupt
occurrence
Status 0
140
Triple interrupts
Status 2
µPD75238
5.5
VECTOR ADDRESS SHARE INTERRUPT PROCESSING
Since interrupt sources INTBT and INT4 share the vector table, the following two cases must be considered.
(1) When using only one interrupt source
The interrupt enable flag corresponding to the required interrupt source of the two interrupt sources
sharing the vector table is set and the other interrupt enable flag is cleared. In this case, the enabled
interrupt source (IE××× = 1) issues an interrupt request. If this request is accepted, the corresponding
interrupt request flag is reset. (The same operation as that of interrupts not sharing a vector address)
(2) When using both interrupt sources
The interrupt enable flags corresponding to the two interrupt sources are set. In this case, the logical and
of the interrupt request flags corresponding to the two interrupt sources is an interrupt request.
Even if one or both of the interrupt request flags are set and an interrupt request is accepted, neither of
the interrupt request flags is reset.
The interrupt service routine must therefore judge which interrupt source caused an interrupt. This is done
by executing a DI instruction at the beginning of the interrupt service routine and checking the interrupt
request flags with an SKTCLR instruction.
141
µPD75238
6. STANDBY FUNCTION
To reduce the power consumption when the program is in the wait state, the µPD75238 has two standby
modes, STOP and HALT.
6.1
SETTING OF STANDBY MODES AND OPERATION STATUSES
Table 6-1
Operation Statuses in the Standby Mode
STOP mode
HALT mode
Instruction for setting
STOP instruction
HALT instruction
System clock at setting
This mode can be set only when the main
system clock is used.
This mode can be set when either the main
system clock or the subsystem clock is
used.
Only the main system clock is stopped.
Only CPU clock (Φ) is stopped (with oscil-
Operation
status
Clock generator
lation continued).
Serial interface
(Channel 0)
Operation is possible only when external
SCK0 input is selected for the serial clock.
Operation is possible only when the main
system clock operates or external SCK0 is
used.
Serial interface
(Channel 1)
Operation is possible only when external
SCK1 input is selected for the serial clock.
Operation is possible only when the main
system clock operates.
Basic interval
timer
Operation is stopped.
Operation is continued (to set IRQBT at
reference time intervals).
Timer/event
counter
Operation is possible only when TI0 pin
input is selected for the count clock.
Operation is possible.
Watch timer
Operation is possible only when fXT is selected for the count clock.
Operation is possible.
Timer/pulse
generator
Operation is stopped.
Operation is possible only when the main
system clock operates.
Event counter
Operation is stopped.
Operation is possible only when the main
system clock operates.
A/D converter
Operation is stopped.
Operation is possible only when the main
system clock operates.
FIP controller/
driver
Operation is disabled. (The display off mode is selected before setting.)
External interrupt
INT0 is disabled. INT1, INT2, and INT4 are enabled.
CPU
Operation is stopped.
Release signal
142
Interrupt request signals sent out from hardware, which are enabled by interrupt
enable flags, or RESET input.
µPD75238
A STOP instruction is used to set the STOP mode, and a HALT instruction is used to set the HALT mode.
(A STOP instruction sets bit 3 of PCC, and a HALT instruction sets bit 2 of PCC.)
When changing a CPU operation clock pulse with the low-order two bits of PCC, a time lag may occur from
the time when PCC is rewritten to the time when the CPU clock signal is changed as indicated in Table 4-1.
When changing an operation clock pulse before the standby mode or a CPU clock signal after the standby mode
is released, it is necessary to rewrite PCC and set the standby mode after the number of machine cycles
required to change the CPU clock pulse elapses.
In a standby mode, the contents of all registers and data memory that are stopped during the standby mode,
including general registers, flags, mode registers, and output latches, are retained.
Cautions 1. When the STOP mode is set, the X1 input is internally connected to VSS (GND potential) to
suppress leakage at the crystal oscillator circuitry. This means that the STOP mode cannot
be used with a system that uses an external clock.
2. An interrupt request signal is used to release a standby mode.
This means that if an interrupt source whose interrupt request flag and interrupt enable flag
are both set exists, the initiated standby mode is released immediately after it is set. When
the STOP mode is set, therefore, the µPD75238 enters the HALT mode immediately after the
STOP instruction is executed, then returns to the operation mode after the wait time specified
by the BTM register has elapsed.
143
µPD75238
6.2
RELEASE OF THE STANDBY MODES
The STOP mode and HALT mode are released by a RESET input or the generation of an interrupt request
signalNote that is enabled with the interrupt enable flag. Fig. 6-1 shows how the STOP and HALT modes are
released.
Note INT0 to INT2 are excluded.
Fig. 6-1
Standby Mode Release Operation
(a) Release of the STOP mode by RESET input
Wait
approximately
21.8 ms/6.0 MHz
STOP instruction
Note
RESET
signal
Clock
Operating
mode
STOP mode
HALT mode
Oscillation
No oscillation
Oscillation
Operating
mode
(b) Release of the STOP mode by the occurrence of an interrupt
Wait
(Time set by BTM)
STOP instruction
Standby
release
signal
Clock
Operating
mode
STOP mode
HALT mode
Oscillation
No oscillation
Oscillation
Operating
mode
Remark The dashed line indicates the case where the interrupt request that releases the standby
mode is accepted (IME = 1).
(c) Release of the HALT mode by RESET input
Wait
approximately
21.8 ms/6.0 MHz
Note
HALT instruction
RESET
signal
Operating
mode
Clock
Note
144
31.3 ms at 4.19 MHz.
HALT mode
Oscillation
Operating
mode
µPD75238
(d) Release of the HALT mode by the occurrence of an interrupt
HALT instruction
Standby
release
signal
Operating mode
HALT mode
Operating mode
Oscillation
Clock
Remark The dashed line indicates the case where the interrupt request that releases the standby
mode is accepted (IME = 1).
The wait times used when the STOP mode is released do not include a time (a in the figure below) required
before clock generation is started following the release of the STOP mode, regardless of whether the STOP
mode is released by RESET signal input or the generation of an interrupt.
STOP mode release
Wave-form
at the X1 pin
a
VSS
When the STOP mode is released by the occurrence of an interrupt, a wait time is determined by BTM. (See
Table 6-2.)
Table 6-2
Selection of a Wait Time with BTM
(When fX = 6.0 MHz)
BTM0 Wait timeNote. ( ) indicates the value for fX = 6.0 MHz
BTM3
BTM2
BTM1
–
0
0
0
Approx. 220/fX (Approx. 175 ms)
–
0
1
1
Approx. 217/fX (Approx. 21.8 ms)
–
1
0
1
Approx. 215/fX (Approx. 5.46 ms)
–
1
1
1
Approx. 213/f X (Approx. 1.37 ms)
Other than above
Use prohibited
(When fX = 4.19 MHz)
Wait timeNote. ( ) indicates the value for fX = 4.19 MHz
BTM3
BTM2
BTM1
BTM0
–
0
0
0
Approx. 220/fX (Approx. 250 ms)
–
0
1
1
Approx. 217/fX (Approx. 31.3 ms)
–
1
0
1
Approx. 215/fX (Approx. 7.82 ms)
–
1
1
1
Approx. 213/fX (Approx. 1.95 ms)
Other than above
Use prohibited
Note This time does not include the time from the release of the STOP mode to the start of oscillation.
145
µPD75238
6.3
OPERATION AFTER A STANDBY MODE IS RELEASED
(1) If a standby mode is released by a RESET input, normal reset operation is performed.
(2) If a standby mode is released by the occurrence of an interrupt request, bit 3 of the IPS (IME) determines
whether to perform a vectored interrupt when the CPU resumes instruction execution.
(a) When IME = 0
After the standby mode is released, execution of an instruction (NOP instruction) is restarted
immediately after the instruction which set the standby mode.
The interrupt request flag is held.
(b) When IME = 1
After the standby mode is released, two instructions are executed, then a vector interrupt is caused.
However, when the standby mode is released by INTW or INT2 (input of a testable signal), no vector
interrupt is caused and the same processing as (a) above is performed.
146
µPD75238
7. RESET FUNCTION
Fig. 7-1 shows the configuration of the reset (RES) signal generator.
Fig. 7-1 Reset Signal Generator
Internal reset signal
(RES)
RESET
Fig. 7-2 shows reset operation.
The output buffer is set to off at the time of a RESET input.
After a reset, the hardware is initialized as indicated in Table 7-1.
Fig. 7-2 Reset Operation by RESET Input
Wait
(approximately 21.8 ms/6.0 MHz)Note
RESET input
Operation mode or
standby mode
HALT mode
Operation mode
Internal reset operation
Note
31.3 ms at 4.19 MHz.
After a reset, the hardware is initialized as indicated in Table 7-1.
147
µPD75238
Table 7-1
Statuses of the Hardware after a Reset (1/2)
Hardware
RESET input in a standby mode
RESET input during operation
Low-order 6 bits at address 0000H
Low-order 6 bits at address 0000H
in program memory are set in PC
in program memory are set in PC
bits 13 to 8, and the data at address
bits 13 to 8, and the data at address
0001H are set in PC bits 7 to 0.
0001H are set in PC bits 7 to 0.
Carry flag (CY)
Held
Undefined
Skip flags (SK0 to SK2)
0
0
Interrupt status flags (IST1, IST2)
0
0
Bank enable flags (MBE, RBE)
Bit 6 at address 0000H in program memory is set in RBE, and
bit 7 is set in MBE.
Bit 6 at address 0000H in program memory is set in RBE, and
bit 7 is set in MBE.
Data memory (RAM)
Held
Undefined
General registers (X, A, H, L, D, E, B, C)
Held
Undefined
Bank select register (MBS, RBS)
0, 0
0, 0
Stack pointer (SP)
Undefined
Undefined
Stack bank select register (SBS)
Undefined
Undefined
Basic interval
timer
Counter (BT)
Undefined
Undefined
Mode register (BTM)
0
0
Timer/event
counter
Counter (T0)
0
0
Modulo register (TMOD0)
FFH
FFH
Mode register (TM0)
0
0
TOE0, TOUT F/F
0, 0
0, 0
Watch timer
Mode register (WM)
0
0
Timer/pulse
generator
Modulo registers (MODH, MODL)
Held
Held
Mode register (TPGM)
0
0
Event counter
Counter (T1)
0
0
Mode register (TM1)
0
0
Gate control register (GATEC)
0
0
Held
Undefined
0
0
SBI control register (SBIC)
0
0
Slave address register (SVA)
Held
Undefined
P01/SCK0 output latch
1
1
Held
Undefined
0
0
0
0
Program counter (PC)
PSW
Serial interface Shift register (SIO0)
(Channel 0)
Operation mode register
(CSIM0)
Serial interface Shift register (SIO1)
(Channel 1)
Operation mode register
(CSIM1)
Serial transfer end flag (EOT)
148
µPD75238
Table 7-1
Statuses of the Hardware after a Reset (2/2)
Hardware
A/D converter
RESET input in a standby mode
RESET input during operation
Mode register (ADM), EOC
04H (EOC = 1)
04H (EOC = 1)
SA register
Undefined
Undefined
Bit sequential buffers (BSB0 to BSB3)
Held
Undefined
FIP controller/ Mode register (DSPM)
driver
Dimmer select register (DIMS)
0
0
0
0
Digit select register (DIGS)
8H
8H
Display data memory
Held
Held
Output buffer
Off
Off
Static mode registers
(STATA, STATB)
0, 0
0, 0
Clock genera- Processor clock control register
tor, clock out- (PCC)
put circuit
System clock control register (SCC)
0
0
0
0
Clock output mode register (CLOM)
0
0
Interrupt request flag (IRQ×××)
Reset
Reset
Interrupt enable flag (IE×××)
0
0
Interrupt master enable flag (IME)
0
0
INT0 and INT1 mode registers
(IM0, IM1)
0, 0
0, 0
Output buffer (Ports 2 to 7)
Off
Off
Output latch
Clear
Clear
I/O mode registers (PMGA, PMGB)
0
0
Pull-up resistor specification register (POGA)
0
0
Output buffer
Off
Off
Output latch
0
0
Output latch
Held
Undefined
Interrupt
Digital ports
Ports 10 to 15
Port H
(Ports 2 to 7)
149
µPD75238
8. INSTRUCTION SET
8.1
µPD75238 INSTRUCTIONS
(1) GETI instruction
The GETI instruction references a two-byte table in the program memory and performs the following
three types of operations. This single-byte instruction is very useful in reducing the number of program
steps.
(a) A subroutine call is made to a 16-KB space (0000H to 3FFFH), regarding data in a table as the call
address of a call instruction.
(b) A branch is made to a 16-KB space (0000H to 3FFFH), regarding data in a table as the branch address
of a branch instruction.
(c) Data in a table is executed as a double-byte instruction excluding BRCB and the CALLF instructions.
(d) Data in a table is executed as the instruction code of two single-byte instructions.
As shown in Fig. 3-2, the tables to be referenced by a GETI instruction are located at addresses 0020H
to 007FH in the program memory. That is, data can be set in up to 48 tables.
When describing a table address as an operand, describe an even address.
Cautions 1. A two-byte instruction which can be referenced by a GETI instruction must be a twomachine-cycle instruction.
2. When referencing two single-byte instructions with a GETI instruction, only the combinations listed in the table below are valid.
Instruction of first byte
MOV A,@HL
MOV @HL,A
XCH A,@HL
MOV A,@DE
XCH A,@DE
MOV A,@DL
XCH A,@DL
Instruction of second byte
INCS
DECS
INCS
DECS
INCS
L
L
H
H
HL
INCS
DECS
INCS
DECS
INCS
E
E
D
D
DE
INCS
DECS
INCS
DECS
L
L
D
D
3. Branch and subroutine instructions can be referenced by the GETI instruction only when
the addresses of the destination and subroutine call are in the 16K-byte space (0000H to
3FFFH). A branch or subroutine instruction to an address from 4000H to 7F7FH cannot be
referenced by the GETI instruction.
150
µPD75238
Since PC does not increment the counter during execution of a GETI instruction, control returns to the
address next to the GETI instruction after the execution of the GETI instruction.
When the instruction before a GETI instruction has the skip function, the GETI instruction is skipped in
the same way as for other single-byte instructions. When the instruction referenced by a GETI instruction
has the skip function, the instructions after the GETI instruction are skipped.
When a string effect instruction is referenced by a GETI instruction, the following results are obtained.
• When the group of the string effect instruction before the GETI instruction is the same as that of the
instruction referenced by the GETI instruction, the effect of the string effect instruction is canceled and
the referenced instruction is not skipped.
• When the group of the instruction after the GETI instruction is the same as that of the instruction
referenced by the GETI instruction, the effect of the string effect instruction caused by the referenced
instruction is valid and the instructions after the referenced instruction are skipped.
(2) Bit manipulation instructions
The µPD75238 is provided with bit test instructions, bit transfer instructions, and bit Boolean instructions
(AND, OR, and XOR) in addition to normal bit manipulation instructions (set instruction and clear
instruction). Manipulation bits are specified by bit manipulation addressing.
There are three types of bit manipulation addressing. The table below lists the bits manipulated by each
addressing.
Addressing
Specifiable peripheral hardware
Specifiable bit address range
RBE/MBE/IST1, IST0/IE×××/IRQ×××
FB0H to FBFH
Port 0 to port 6
FF0H to FFFH
pmem.@L
Port 0 and port 4
FC0H to FFFH
@H+mem.bit
All the peripheral hardware (bitmanipulatable)
All the bits of the memory bank specified by
MB (bit-manipulatable)
fmem.bit
×××: 0, 1, 2, 4, BT, T0, TPG, CSI0, KS, W
MB = MBE• MBS
151
µPD75238
(3) String effect instructions
When two or more instructions in the same group (group A or B) are placed at two or more string effect
addresses, the instruction placed at the start point of the string effect instructions is executed. After that,
each string effect instruction is executed as an NOP instruction.
Group A: MOV A, #n4,
MOV XA, #n8
Group B: MOV HL, #n8
(4) Base conversion instruction
The µPD75238 is provided with base conversion instructions to convert the results of addition and
subtraction of 4-bit data to a base-n number.
When a base-m number is to be obtained, the following combinations of instructions are used for
adjustment.
• For addition
ADDS A, #16-m
ADDC A, @HL
ADDS A, #m
• For subtraction SUBC A, @HL
ADDS A, #m
The result of adding or subtracting the contents of the accumulator and the memory addressed by the
HL register pair is converted to a base-m number. However, for subtraction, the complement of the
obtained result (base-m number) is set in the accumulator. An overflow or underflow is reflected in the
carry flag. (In the above combinations, the skip function of the ADDS A, #m instruction is prohibited.)
152
µPD75238
8.2
INSTRUCTION SET AND ITS OPERATION
(1) Representation format and description method of operands
An operand is described in the operand field of each instruction according to the description method
corresponding to the operand representation format of the instruction. Refer to the assembler specifications for details. When two or more elements are described in the description method field, select one
of them. Uppercase letters, a plus sign (+), and a minus sign (-) are keywords, so they can be used without
alteration.
Specify an appropriate numeric value or label for immediate data.
The symbols shown in format diagrams in Chapters 3 to 5 can be used as a label instead of mem, fmem,
pmem, and bit. However, there are some restrictions on usable labels for fmem and pmem. (See (2) in
Section 8.1.)
Representation format
Description method
reg
X, A, B, C, D, E, H, L
reg1
X, B, C, D, E, H, L
rp
XA, BC, DE, HL
rp1
BC, DE, HL
rp2
BC, DE
rp’
XA, BC, DE, HL, XA’, BC’, DE’, HL’
rp’1
BC, DE, HL, XA’, BC’, DE’, HL’
rpa
HL, HL+, HL-, DE, DL
rpa1
DE, DL
n4
4-bit immediate data or label
n8
8-bit immediate data or label
mem
8-bit immediate data or labelNote
bit
2-bit immediate data or label
fmem
FB0H-FBFH/FF0H-FFFH immediate data or label
pmem
FC0H-FFFH immediate data or label
addr1
0000H-7F7FH immediate data or label
addr
0000H-3F7FH immediate data or label
caddr
12-bit immediate data or label
faddr
11-bit immediate data or label
taddr
20H-7FH immediate data (bit 0 = 0) or label
PORTn
PORT0-PORT15
IE×××
IEBT, IECSI0, IET0, IETPG, IE0, IE1, IE2, IEKS, IEW, IE4
RBn
RB0-RB3
MBn
MB0, MB1, MB2, MB3, MB15
Note Only even addresses can be specified for 8-bit data processing.
153
µPD75238
(2) Legend
154
A
:
A register, 4-bit accumulator
B
:
B register, 4-bit accumulator
C
:
C register, 4-bit accumulator
D
:
D register, 4-bit accumulator
E
:
E register, 4-bit accumulator
H
:
H register, 4-bit accumulator
L
:
L register, 4-bit accumulator
X
:
X register, 4-bit accumulator
XA
:
Register pair (XA), 8-bit accumulator
BC
:
Register pair (BC), 8-bit accumulator
DE
:
Register pair (DE), 8-bit accumulator
HL
:
Register pair (HL), 8-bit accumulator
XA’
:
Extended register pair (XA’)
BC’
:
Extended register pair (BC’)
DE’
:
Extended register pair (DE’)
HL’
:
Extended register pair (HL’)
PC
:
Program counter
SP
:
Stack pointer
SBS
:
Stack bank select register
CY
:
Carry flag, bit accumulator
PSW
:
Program status word
MBE
:
Memory bank enable flag
RBE
:
Register bank enable flag
PORTn:
Port n (n = 0 to 15)
IME
:
Interrupt master enable flag
IPS
:
Interrupt priority specification register
IE××× :
Interrupt enable flag
RBS
:
Register bank select register
MBS
:
Memory bank select register
PCC
:
Processor clock control register
.
:
Address/bit delimiter
(××)
:
Contents addressed by ××
××H
:
Hexadecimal data
µPD75238
(3) Explanation of the symbols in the addressing area field
*1
MB = MBE•MBS
(MBS = 0, 1, 2, 3, or 15)
*2
MB = 0
*3
MBE = 0: MB = 0 (00H-7FH)
MB = 15 (80H-FFH)
MBE = 1: MB = MBS (MBS = 0, 1, 2, 3, or 15)
*4
MB = 15, fmem = FB0H-FBFH or
FF0H-FFFH
*5
MB = 15, pmem = FC0H-FFFH
*6
addr = 0000H-3FFFH
*7
addr = (Current PC) -15 to (Current PC) -1 or
(Current PC) +2 to (Current PC) +16
*8
*9
caddr = 0000H-0FFFH
1000H-1FFFH
2000H-2FFFH
3000H-3FFFH
4000H-4FFFH
5000H-5FFFH
6000H-6FFFH
7000H-7F7FH
faddr = 0000H-07FFH
*10
taddr = 0020H-007FH
*11
addr1 = 0000H-7F7FH
Remarks 1.
Data memory
addressing
(PC14,13,12 = 00B) or
(PC14,13,12 = 01B) or
(PC14,13,12 = 10B) or
(PC14,13,12 = 11B) or
(PC14,13,12 = 100B) or
(PC14,13,12 = 101B) or
(PC14,13,12 = 110B) or
(PC14,13,12 = 111B)
Program
memory
addressing
MB indicates an accessible memory bank.
2.
For *2, MB is always 0 irrespective of MBE and MBS.
3.
For *4 and *5, MB is always 15 irrespective of MBE and MBS.
4.
*6 to *11 indicate each addressable area.
(4) Explanation of the machine cycle column
S represents the number of machine cycles required when a skip instruction with the skip function
performs a skip operation. S assumes one of the following values:
• When no skip operation is performed
: S=0
• When a 1-byte instruction or 2-byte instruction is skipped: S = 1
• When a 3-byte instruction is skipped
Caution
: S=2
The GETI instruction is skipped in one machine cycle.
One machine cycle is equal to one cycle (= tCY) of the CPU clock (Φ), and five types of times are available
for selection according to the PCC and SCC settings. (See (3) in Section 4.2.)
155
µPD75238
Instruction Mnemonic
Transfer
MOV
XCH
Table
reference
156
MOVT
Operand
Number Machine
Operation
of bytes cycle
Addressing area
Skip
condition
A,#n4
1
1
A ← n4
reg1,#n4
2
2
reg1 ← n4
XA,#n8
2
2
XA ← n8
String effect A
HL,#n8
2
2
HL ← n8
String effect B
rp2,#n8
2
2
rp2 ← n8
A,@HL
1
1
A ← (HL)
*1
A,@HL+
1
2+S
A ← (HL), then L ← L + 1
*1
L=0
A,@HL-
1
2+S
A ← (HL), then L ← L - 1
*1
L = FH
A,@rpa1
1
1
A ← (rpa1)
*2
XA,@HL
2
2
XA ← (HL)
*1
@HL,A
1
1
(HL) ← A
*1
@HL,XA
2
2
(HL) ← XA
*1
A,mem
2
2
A ← (mem)
*3
XA,mem
2
2
XA ← (mem)
*3
mem,A
2
2
(mem) ← A
*3
mem,XA
2
2
(mem) ← XA
*3
A,reg
2
2
A ← reg
XA,rp’
2
2
XA ← rp’
reg1,A
2
2
reg1 ← A
rp’1,XA
2
2
rp’1 ← XA
A,@HL
1
1
A ↔ (HL)
*1
A,@HL+
1
2+S
A ↔ (HL), then L ← L + 1
*1
L=0
A,@HL-
1
2+S
A ↔ (HL), then L ← L - 1
*1
L = FH
A,@rpa1
1
1
A ↔ (rpa1)
*2
XA,@HL
2
2
XA ↔ (HL)
*1
A,mem
2
2
A ↔ (mem)
*3
XA,mem
2
2
XA ↔ (mem)
*3
A,reg1
1
1
A ↔ reg1
XA,rp’
2
2
XA ↔ rp’
XA,@PCDE
1
3
XA ← (PC14-8+DE)ROM
XA,@PCXA
1
3
XA ← (PC14-8+XA)ROM
XA, @BCDE
1
3
XA ← (BCDE)ROM
*11
XA, @BCXA
1
3
XA ← (BCXA)ROM
*11
String effect A
µPD75238
Operand
Instruction Mnemonic
Bit
transfer
Arithmetic/logical
MOV1
ADDS
ADDC
SUBS
SUBC
AND
OR
XOR
Accumula- RORC
tor manipulation
NOT
Number Machine
Operation
of bytes cycle
Addressing area
Skip
condition
CY,fmem.bit
2
2
CY ← (fmem.bit)
*4
CY,pmem.@L
2
2
CY ← (pmem 7-2+L3-2.bit(L1-0))
*5
CY,@H+mem.bit
2
2
CY ← (H+mem3-0 .bit)
*1
fmem.bit,CY
2
2
(fmem.bit) ← CY
*4
pmem.@L,CY
2
2
(pmem7-2+L3-2.bit(L1-0)) ← CY
*5
@H+mem.bit,CY
2
2
(H+mem3-0.bit) ← CY
*1
A,#n4
1
1+S
A ← A + n4
carry
XA,#n8
2
2+S
XA ← XA + n8
carry
A,@HL
1
1+S
A ← A + (HL)
XA,rp’
2
2+S
XA ← XA + rp’
carry
rp’1,XA
2
2+S
rp’1 ← rp’1 + XA
carry
A,@HL
1
1
A,CY ← A + (HL) + CY
XA,rp’
2
2
XA,CY ← XA + rp’ + CY
rp’1,XA
2
2
rp’1,CY ← rp’1 + XA + CY
A,@HL
1
1+S
A ← A - (HL)
XA,rp’
2
2+S
XA ← XA - rp’
borrow
rp’1,XA
2
2+S
rp’1 ← rp’1 - XA
borrow
A,@HL
1
1
A,CY ← A - (HL) - CY
XA,rp’
2
2
XA,CY ← XA - rp’ - CY
rp’1,XA
2
2
rp’1,CY ← rp’1 - XA - CY
A,#n4
2
2
A←A
A,@HL
1
1
XA,rp’
2
2
rp’1,XA
2
2
A,#n4
2
2
A,@HL
1
1
XA,rp’
2
2
rp’1,XA
2
2
A,#n4
2
2
A,@HL
1
1
XA,rp’
2
2
rp’1,XA
2
2
∧ n4
A ← A ∧ (HL)
XA ← XA ∧ rp’
rp’1 ← rp’1 ∧ XA
A ← A ∨ n4
A ← A ∨ (HL)
XA ← XA ∨ rp’
rp’1 ← rp’1 ∨ XA
A ← A ∨ n4
A ← A ∨ (HL)
XA ← XA ∨ rp’
rp’1 ← rp’1 ∨ XA
A
1
1
CY ← A0,A 3 ← CY, An-1 ← An
A
2
2
A←A
*1
carry
*1
*1
borrow
*1
*1
*1
*1
157
µPD75238
Operand
Instruction Mnemonic
158
Addressing area
Skip
condition
1
1+S
reg ← reg + 1
reg = 0
rp1
1
1+S
rp1 ← rp1 + 1
rp1 = 00H
@HL
2
2+S
(HL) ← (HL) + 1
*1
(HL) = 0
mem
2
2+S
(mem) ← (mem) + 1
*3
(mem) = 0
reg
1
1+S
reg ← reg - 1
reg = FH
rp’
2
2+S
rp’ ← rp’ - 1
rp’ = FFH
reg,#n4
2
2+S
Skip if reg = n4
reg = n4
@HL,#n4
2
2+S
Skip if (HL) = n4
*1
(HL) = n4
A,@HL
1
1+S
Skip if A = (HL)
*1
A = (HL)
XA,@HL
2
2+S
Skip if XA = (HL)
*1
XA = (HL)
A,reg
2
2+S
Skip if A = reg
A = reg
XA,rp’
2
2+S
Skip if XA = rp’
XA = rp’
SET1
CY
1
1
CY ← 1
CLR1
CY
1
1
CY ← 0
SKT
CY
1
1+S
NOT1
CY
1
1
DECS
Carry flag
manipulation
Operation
of bytes cycle
reg
Increment/ INCS
decrement
Comparison
Number Machine
SKE
Skip if CY = 1
CY ← CY
CY = 1
µPD75238
Instruction Mnemonic
SET1
Memory
bit
manipulation
CLR1
SKT
SKF
SKTCLR
AND1
OR1
XOR1
Branch
BR
Operand
Number Machine
Operation
of bytes cycle
Addressing area
Skip
condition
mem.bit
2
2
(mem.bit) ← 1
*3
fmem.bit
2
2
(fmem.bit) ← 1
*4
pmem.@L
2
2
(pmem7-2+L3-2.bit(L1-0)) ← 1
*5
@H+mem.bit
2
2
(H+mem3-0.bit) ← 1
*1
mem.bit
2
2
(mem.bit) ← 0
*3
fmem.bit
2
2
(fmem.bit) ← 0
*4
pmem.@L
2
2
(pmem7-2+L3-2.bit(L1-0)) ← 0
*5
@H+mem.bit
2
2
(H+mem3-0.bit) ← 0
*1
mem.bit
2
2+S
Skip if (mem.bit) = 1
*3
(mem.bit) = 1
fmem.bit
2
2+S
Skip if (fmem.bit) = 1
*4
(fmem.bit) = 1
pmem.@L
2
2+S
Skip if (pmem7-2+L3-2.bit(L1-0)) = 1
*5
(pmem.@L) = 1
@H+mem.bit
2
2+S
Skip if (H+mem3-0.bit) = 1
*1
(@H+mem.bit) = 1
mem.bit
2
2+S
Skip if (mem.bit) = 0
*3
(mem.bit) = 0
fmem.bit
2
2+S
Skip if (fmem.bit) = 0
*4
(fmem.bit) = 0
pmem.@L
2
2+S
Skip if (pmem7-2+L3-2.bit(L1-0)) = 0
*5
(pmem.@L) = 0
@H+mem.bit
2
2+S
Skip if (H+mem3-0.bit) = 0
*1
(@H+mem.bit) = 0
fmem.bit
2
2+S
Skip if (fmem.bit) = 1 and clear
*4
(fmem.bit) = 1
pmem.@L
2
2+S
Skip if (pmem7-2 + L3-2.bit(L1-0)) = 1 and clear
*5
(pmem.@L) = 1
@H+mem.bit
2
2+S
Skip if (H+mem3-0.bit) = 1 and clear
*1
(@H+mem.bit) = 1
CY,fmem.bit
2
2
CY,pmem.@L
2
2
CY,@H+mem.bit
2
2
CY,fmem.bit
2
2
CY,pmem.@L
2
2
CY,@H+mem.bit
2
2
CY,fmem.bit
2
2
CY,pmem.@L
2
2
CY,@H+mem.bit
2
2
∧ (fmem.bit)
CY ← CY ∧ (pmem7-2+L3-2.bit(L 1-0))
CY ← CY ∧ (H+mem3-0.bit)
CY ← CY ∨ (fmem.bit)
CY ← CY ∨ (pmem7-2+L3-2.bit(L 1-0))
CY ← CY ∨ (H+mem3-0.bit)
CY ← CY ∨ (fmem.bit)
CY ← CY ∨ (pmem 7-2+L3-2.bit(L 1-0))
CY ← CY ∨ (H+mem3-0.bit)
addr
—
—
PC14-0 ← addr1
CY ← CY
*4
*5
*1
*4
*5
*1
*4
*5
*1
*11
(The assembler selects an appropriate
instruction from the BR !addr, BRA
!addr1, BRCB !caddr, and BR $addr1
instructions.)
★
$addr 1
1
2
PC14-0 ← addr1
*7
!addr
3
3
PC14 ← 0, PC13-0 ← !addr
*6
PCDE
2
3
PC14-0 ← PC14-8 + DE
PCXA
2
3
PC14-0 ← PC14-8 + XA
BCDE
2
3
PC14-0 ← BCDE
BCXA
2
3
PC14-0 ← BCXA
BRA
!addr1
3
3
PC14-0 ← !addr1
*11
BRCB
!caddr
2
2
PC14-0 ← PC14,13,12 + caddr11-0
*8
159
µPD75238
Operand
Instruction Mnemonic
Subroutine stack
control
CALL
!addr
Number Machine
Operation
of bytes cycle
3
4
(SP-5)(SP-6)(SP-3)(SP-4) ← PC14-0
CALLF
!addr1
!faddr
3
2
3
3
(SP-5)(SP-6)(SP-3)(SP-4) ← PC14-0
(SP-2) ← ×, ×, MBE, RBE
PC14-0 ← addr1, SP ← SP-6
RETS
1
RETI
1
3
×, PC 14,13,12 ← (SP+1)
PC11-0 ← (SP)(SP+3)(SP+2)
PSW ← (SP+4)(SP+5), SP ← SP+6
rp
1
1
(SP-1)(SP-2) ← rp, SP ← SP-2
BS
2
2
(SP-1) ← MBS, (SP-2) ← RBS, SP ←
SP-2
rp
1
1
rp ← (SP+1)(SP), SP ← SP+2
BS
2
2
MBS ← (SP+1), RBS ← (SP), SP ←
SP+2
2
2
IME(IPS.3) ← 1
2
2
IE××× ← 1
2
2
IME(IPS.3) ← 0
IE×××
2
2
IE××× ← 0
A,PORTn
2
2
A ← PORTn
XA,PORTn
2
2
XA ← PORTn+1, PORTn
PORTn,A
2
2
PORTn ← A
PORTn,XA
2
2
PORTn+1, PORTn ← XA
HALT
2
2
Set HALT Mode (PCC.2 ← 1)
STOP
2
2
Set STOP Mode (PCC.3 ← 1)
NOP
1
1
No Operation
EI
IE×××
DI
INNote
OUTNote
160
*6
3+S
*11
*9
×, ×, MBE, RBE ← (SP+4)
PC14-0 ← (SP+1)(SP)(SP+3)(SP+2)
SP ← SP+6
1
POP
Note
3
RET
PUSH
CPU
control
Skip
condition
(SP-5)(SP-6)(SP-3)(SP-4) ← PC14-0
(SP-2) ← ×, ×, MBE, RBE
PC14-0 ← 0000, faddr, SP ← SP-6
I/O
ing area
(SP-2) ← ×, ×, MBE, RBE
PC14 ← 0, PC13-0 ← addr, SP ← SP-6
CALLA
Interrupt
control
Address-
×, ×, MBE, RBE ← (SP+4)
PC14-0 ← (SP+1) (SP)(SP+3)(SP+2)
SP ← SP+6
then skip unconditionally
Unconditionally
MBE = 0, or MBE = 1 and MBS = 15 must be set when an IN/OUT instruction is executed.
µPD75238
Instruction Mnemonic
Special
SEL
GETINote
Operand
Number Machine
Operation
of bytes cycle
RBn
2
2
RBS ← n (n=0-3)
MBn
2
2
MBS ← n (n=0,1,2,3,15)
taddr
1
3
• For a TBR instruction
PC13-0 ← (taddr)5-0 + (taddr+1)
Addressing area
Skip
condition
*10
★
PC14 ← 0
Note
4
• For a TCALL instruction
(SP-5)(SP-6)(SP-3)(SP-4) ← PC14-0
(SP-2) ← ×, ×, MBE, RBE
PC13-0 ← (taddr)5-0 + (taddr+1)
SP ← SP-6 PC14 ← 0
3
• For an instruction other than TBR
and TCALL
Executes the instruction in
(taddr)(taddr+1).
Depends
upon the
referenced
instruction.
The TBR and TCALL instructions are table definition assembler pseudo instructions of the GETI
instructions.
161
µPD75238
8.3
INSTRUCTION CODES OF EACH INSTRUCTION
(1) Explanations of the symbols for the instruction codes
R2
R1
R0
reg
P2
P1
P0
reg-pair
0
0
0
A
0
0
0
XA
0
0
1
X
0
0
1
XA'
0
1
0
L
0
1
0
HL
0
1
1
H
0
1
1
HL'
1
0
0
DE
reg
reg1
1
0
0
E
1
0
1
D
1
0
1
DE'
1
1
0
C
1
1
0
BC
1
1
1
B
1
1
1
BC'
Q2
Q1
Q0
addressing
P2
P1
reg-pair
0
0
1
@HL
0
0
XA
0
1
0
@HL+
0
1
HL
0
1
1
@HL–
1
0
DE
1
0
0
@DE
1
1
BC
1
0
1
@DL
N5
N2
N1
N0
IE×××
0
0
0
0
IEBT
0
0
1
0
IEW
0
0
1
1
IETPG
0
1
0
0
IET0
0
1
0
1
IECSI0
0
1
1
0
IE0
0
1
1
1
IE2
1
0
0
0
IE4
1
0
1
1
IEKS
1
1
1
0
IE1
@rpa
@rpa1
rp'
rp'1
rp1
rp
rp2
In : Immediate data for n4 or n8
Dn: Immediate data for mem
Bn: Immediate data for bit
Nn: Immediate data for n or IE×××
Tn: Immediate data for taddr × 1/2
An: Immediate data for the relative address distance (2 to 16) for the branch destination address minus
one
Sn: Immediate data for the ones complement of the relative address distance (15 to 1) for the branch
destination address
162
µPD75238
(2) Bit manipulation addressing instruction codes
*1 in the operand field indicates that there are three types of bit manipulation addressing, fmem.bit,
pmem.@L, and @H+mem.bit.
The table below lists the second byte *2 of an instruction code corresponding to the above addressing.
*1
Second byte of instruction code
Accessible bits
1
0
B1
B0
F3
F2
F1
F0
FB0H - FBFH manipulatable bits
1
1
B1
B0
F3
F2
F1
F0
FF0H - FFFH manipulatable bits
pmem.@L
0
1
0
0
G3
G2
G1
G0
FC0H-FFFH manipulatable bits
@H+mem.bit
0
0
B1
B0
D3
D2
D1
D0
Manipulatable bits of accessible
memory bank
fmem.bit
Bn: Immediate data for bit
Fn:
Immediate data for fmem (Low-order four bits of address)
Gn: Immediate data for pmem (Bits 2 to 5 of address)
Dn: Immediate data for mem (Low-order four bits of address)
163
µPD75238
Instruction code
Instruction
Mnemonic
Transfer
MOV
XCH
Table
MOVT
reference
Bit
transfer
MOV1
Operand
B2
A, #n4
0 1 1 1 I3 I2 I1 I0
reg1, #n4
1 0 0 1 1 0 1 0
I3 I2 I1 I0 1 R2 R1 R0
rp, #n8
1 0 0 0 1 P2 P1 1
I7 I6 I5 I4 I3 I2 I1 I0
A, @rpa
1 1 1 0 0 Q2 Q1 Q0
XA, @HL
1 0 1 0 1 0 1 0
@HL, A
1 1 1 0 1 0 0 0
@HL, XA
1 0 1 0 1 0 1 0
0 0 0 1 0 0 0 0
A, mem
1 0 1 0 0 0 1 1
D7 D6 D5 D4 D3 D2 D1 D0
XA, mem
1 0 1 0 0 0 1 0
D7 D6 D5 D4 D3 D2 D1 0
mem, A
1 0 0 1 0 0 1 1
D7 D6 D5 D4 D3 D2 D1 D0
mem, XA
1 0 0 1 0 0 1 0
D7 D6 D5 D4 D3 D2 D1 0
A, reg
1 0 0 1 1 0 0 1
0 1 1 1 1 R2 R1 R0
XA, rp'
1 0 1 0 1 0 1 0
0 1 0 1 1 P2 P1 P0
reg1, A
1 0 0 1 1 0 0 1
0 1 1 1 0 R2 R1 R0
rp'1, XA
1 0 1 0 1 0 1 0
0 1 0 1 0 P2 P1 P0
A, @rpa
1 1 1 0 1 Q2 Q1 Q0
XA, @HL
1 0 1 0 1 0 1 0
0 0 0 1 0 0 0 1
A, mem
1 0 1 1 0 0 1 1
D7 D6 D5 D4 D3 D2 D1 D0
XA, mem
1 0 1 1 0 0 1 0
D7 D6 D5 D4 D3 D2 D1 0
A, reg1
1 1 0 1 1 R2 R1 R0
XA, rp'
1 0 1 0 1 0 1 0
XA, @PCDE
1 1 0 1 0 1 0 0
XA, @PCXA
1 1 0 1 0 0 0 0
XA, @BCDE
1 1 0 1 0 1 0 1
XA, @BCXA
1 1 0 1 0 0 0 1
CY, *1
1 0 1 1 1 1 0 1
*2
1 0 0 1 1 0 1 1
*2
*1 , CY
164
B1
0 0 0 1 1 0 0 0
0 1 0 0 0 P2 P1 P0
B3
µPD75238
Instruction
Instruction code
Mnemonic
Operand
B1
Arithme- ADDS
tic/logical
ADDC
SUBS
SUBC
AND
OR
XOR
Accumu- RORC
lator manipulation NOT
B2
A, #n4
0 1 1 0 I3 I2 I1 I0
XA, #n8
1 0 1 1 1 0 0 1
A, @HL
1 1 0 1 0 0 1 0
XA, rp'
1 0 1 0 1 0 1 0
1 1 0 0 1 P2 P1 P0
rp'1, XA
1 0 1 0 1 0 1 0
1 1 0 0 0 P2 P1 P0
A, @HL
1 0 1 0 1 0 0 1
XA, rp'
1 0 1 0 1 0 1 0
1 1 0 1 1 P2 P1 P0
rp'1, XA
1 0 1 0 1 0 1 0
1 1 0 1 0 P2 P1 P0
A, @HL
1 0 1 0 1 0 0 0
XA, rp'
1 0 1 0 1 0 1 0
1 1 1 0 1 P2 P1 P0
rp'1, XA
1 0 1 0 1 0 1 0
1 1 1 0 0 P2 P1 P0
A, @HL
1 0 1 1 1 0 0 0
XA, rp'
1 0 1 0 1 0 1 0
1 1 1 1 1 P2 P1 P0
rp'1, XA
1 0 1 0 1 0 1 0
1 1 1 1 0 P2 P1 P0
A, #n4
1 0 0 1 1 0 0 1
0 0 1 1 I3 I2 I1 I0
A, @HL
1 0 0 1 0 0 0 0
XA, rp'
1 0 1 0 1 0 1 0
1 0 0 1 1 P2 P1 P0
rp'1, XA
1 0 1 0 1 0 1 0
1 0 0 1 0 P2 P1 P0
A, #n4
1 0 0 1 1 0 0 1
0 1 0 0 I3 I2 I1 I0
A, @HL
1 0 1 0 0 0 0 0
XA, rp'
1 0 1 0 1 0 1 0
1 0 1 0 1 P2 P1 P0
rp'1, XA
1 0 1 0 1 0 1 0
1 0 1 0 0 P2 P1 P0
A, #n4
1 0 0 1 1 0 0 1
0 1 0 1 I3 I2 I1 I0
A, @HL
1 0 1 1 0 0 0 0
XA, rp'
1 0 1 0 1 0 1 0
1 0 1 1 1 P2 P1 P0
rp'1, XA
1 0 1 0 1 0 1 0
1 0 1 1 0 P2 P1 P0
A
1 0 0 1 1 0 0 0
A
1 0 0 1 1 0 0 1
B3
I7 I6 I5 I4 I3 I2 I1 I0
0 1 0 1 1 1 1 1
165
µPD75238
Instruction
Increment/
decrement
Mnemonic
Instruction code
Operand
B1
INCS
B2
reg
1 1 0 0 0 R2 R1 R0
rp1
1 0 0 0 1 P2 P1 0
@HL
1 0 0 1 1 0 0 1
0 0 0 0 0 0 1 0
mem
1 0 0 0 0 0 1 0
D7 D6 D5 D4 D3 D2 D1 D0
reg
1 1 0 0 1 R2 R1 R0
rp'
1 0 1 0 1 0 1 0
0 1 1 0 1 P2 P1 P0
reg, #n4
1 0 0 1 1 0 1 0
I3 I2 I1 I0 0 R2 R1 R0
@HL, #n4
1 0 0 1 1 0 0 1
0 1 1 0 I3 I2 I1 I0
A, @HL
1 0 0 0 0 0 0 0
XA, @HL
1 0 1 0 1 0 1 0
0 0 0 1 1 0 0 1
A, reg
1 0 0 1 1 0 0 1
0 0 0 0 1 R2 R1 R0
XA, rp'
1 0 1 0 1 0 1 0
0 1 0 0 1 P2 P1 P0
Carry flag SET1
manipuCLR1
lation
SKT
CY
1 1 1 0 0 1 1 1
CY
1 1 1 0 0 1 1 0
CY
1 1 0 1 0 1 1 1
NOT1
CY
1 1 0 1 0 1 1 0
SET1
mem.bit
1 0 B1 B0 0 1 0 1
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 1 1 1 0 1
*2
1 0 B1 B0 0 1 0 0
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 1 1 1 0 0
*2
1 0 B1 B0 0 1 1 1
D7 D6 D5 D4 D3 D2 D1 D0
1 0 1 1 1 1 1 1
*2
1 0 B1 B0 0 1 1 0
D7 D6 D5 D4 D3 D2 D1 D0
*1
1 0 1 1 1 1 1 0
*2
*1
1 0 0 1 1 1 1 1
*2
DECS
Comparison
Memory
bit
manipulation
SKE
*1
CLR1
mem.bit
*1
SKT
mem.bit
*1
SKF
SKTCLR
166
mem.bit
AND1
CY, *1
1 0 1 0 1 1 0 0
*2
OR1
CY, *1
1 0 1 0 1 1 1 0
*2
XOR1
CY, *1
1 0 1 1 1 1 0 0
*2
B3
µPD75238
Instruction code
Instruction
Mnemonic
Branch
BR
Operand
B1
$addr1
PCXA
1 0 0 1 1 0 0 1
0 0 0 0 0 0 0 0
BCDE
1 0 0 1 1 0 0 1
0 0 0 0 0 1 0 1
BCXA
1 0 0 1 1 0 0 1
0 0 0 0 0 0 0 1
BRA
!addr1
1 0 1 1 1 0 1 0
0
BRCB
!caddr
0 1 0 1
caddr
!addr
1 0 1 0 1 0 1 1
0 1
!addr1
1 0 1 1 1 0 1 1
0
!faddr
0 1 0 0 0
RET
1 1 1 0 1 1 1 0
RETS
1 1 1 0 0 0 0 0
RETI
1 1 1 0 1 1 1 1
addr1
faddr
0 1 0 0 1 P2 P1 1
BS
1 0 0 1 1 0 0 1
rp
0 1 0 0 1 P2 P1 0
BS
1 0 0 1 1 0 0 1
0 0 0 0 0 1 1 0
A, PORTn
1 0 1 0 0 0 1 1
1 1 1 1 N3 N2 N1 N0
XA, PORTn
1 0 1 0 0 0 1 0
1 1 1 1 N3 N2 N1 N0
PORTn, A
1 0 0 1 0 0 1 1
1 1 1 1 N3 N2 N1 N0
PORTn, XA
1 0 0 1 0 0 1 0
1 1 1 1 N3 N2 N1 N0
1 0 0 1 1 1 0 1
1 0 1 1 0 0 1 0
1 0 0 1 1 1 0 1
1 0 N5 1 1 N2 N1 N0
1 0 0 1 1 1 0 0
1 0 1 1 0 0 1 0
1 0 0 1 1 1 0 0
1 0 N5 1 1 N2 N1 N0
HALT
1 0 0 1 1 1 0 1
1 0 1 0 0 0 1 1
STOP
1 0 0 1 1 1 0 1
1 0 1 1 0 0 1 1
NOP
0 1 1 0 0 0 0 0
IN
EI
IE×××
DI
IE×××
SEL
GETI
addr
addr1
rp
OUT
Special
1 1 1 1 S3 S2 S1 S0
addr
★
0 0 0 0 0 1 0 0
POP
CPU
control
0 0 0 0 A3 A2 A1 A0
(-1) to (-15)
0 0
1 0 0 1 1 0 0 1
PUSH
Interrupt
control
(+16) to (+2)
PCDE
Subrou- CALL
tine stack
CALLA
control
CALLF
I/O
1 0 1 0 1 0 1 1
!addr
B3
B2
0 0 0 0 0 1 1 1
RBn
1 0 0 1 1 0 0 1
0 0 1 0 0 0 N1 N0
MBn
1 0 0 1 1 0 0 1
0 0 0 1 N3 N2 N1 N0
taddr
0 0 T5 T4 T3 T2 T1 T0
167
µPD75238
9. SPECIFICATION OF MASK OPTIONS
The µ PD75238 provides the following mask options, which enable specifying whether to incorporate the
elements below:
Pin
Mask option
Allows pull-up resistor to be contained bit by bit.
P40-P43
P50-P53
P70-P73
Allows pull-down resistor to be contained bit by bit.
S0/P120-S3/P123
Allows pull-down resistor to be contained to VLOAD bit by bit.
S4/P130-S7/P133
S8/P140, S9/P141
S10/T15/P142, S11/T14/P143
S12/T13/P150/PH0-S15/T10/P153/PH3
S16/P100-S19/P103
S20/P110-S23/P113
XT1, XT2
Allows pull-down resistorNote to be contained to VLOAD or VSS
bit by bit.
Allows feed-back resistor of the subsystem clock oscillator
to be deleted.
Note Select whether to incorporate the pull-down resistors in VLOAD or VSS in unit of eight bits.
Caution In systems without using subsystem clock, power consumption in STOP mode can be more
reduced by deleting feed-back resistor of the oscillator.
168
µPD75238
10. APPLICATION BLOCK DIAGRAM
Power
failure
detection
INT4
LPF
Electronic
tuner
T0-T15
S0-S17
Fluorescent indicator
panel (FIP)
18 segments × 16 digits
PORT7
Key matrix
(18 × 4)
PPO
ANn
Hsync pulse
µ PD75238
L
Voice level
Timer
Tuner
System computer
Remote-control reception
Hsync detection
ANn
R
LED
PORTn
µ PC1490
INT0
SCK0
OSD
SCK1
SO0
PORTn
SO1
Servo IC
Remote
controller
signal
Mechanical
components
BUZ
X1
4.19/6.0 MHz
Remark LPF
X2
XT1
XT2
BZ Piezo-electric
buzzer
32.768 kHz
: Low pass filter
OSD : On screen display
Hsync : Horizontal synchronous
169
µPD75238
11. ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS (Ta = 25 °C)
Parameter
Supply voltage
Input voltage
Conditions
Rating
Unit
VDD
-0.3 to +7.0
V
VLOAD
VDD - 40 to VDD + 0.3
V
Symbol
VI1
Ports other than ports 4 and 5
-0.3 to VDD + 0.3
V
VI2
Ports 4 and 5 Built-in pull-up resistor
-0.3 to VDD + 0.3
V
-0.3 to +11
V
-0.3 to VDD + 0.3
V
VDD - 40 to VDD + 0.3
V
Open drain
Output voltage
High-level output current
Low-level output current
Total power dismission
VO
Pins other than display output pins
VOD
Display output pins
IOH
One of pins other than display output
pins
-15
mA
One pin of S0 to S9 and S16 to S23
-15
mA
One pin of T0 to T15
-30
mA
All pins other than display output pins
-30
mA
All display output pins
-120
mA
Peak value
30
mA
rms
15
mA
Total of all pins of Peak value
ports 0, 2, 3, and 4
rms
100
mA
60
mA
Total of all pins of
ports 5 to 8
Peak value
100
mA
rms
60
mA
Plastic QFP
(Ta = -40 to +70 °C)
700
mW
(Ta = -40 to +85 °C)
510
mW
IOL
PT
Each pin
Operating temperature
Topt
-40 to +85
°C
Storage temperature
Tstg
-65 to +150
°C
RANGE OF SUPPLY VOLTAGE (Ta = -40 to +85 °C)
Min.
Max.
Unit
Note 2
6.0
V
Display controller
4.5
6.0
V
Timer/pulse generator
4.5
6.0
V
Hardware other than the
aboveNote 1
2.7
6.0
V
Parameter
CPUNote 1
Notes 1.
Conditions
The CPU does not include the system clock oscillator, the display controller, and the timer/pulse
generator.
2.
The range of the supply voltage at which the CPU can operate varies according to the cycle time.
See the item of AC characteristics.
170
µPD75238
CHARACTERISTICS OF THE MAIN SYSTEM CLOCK OSCILLATOR (Ta = -40 to +85 °C, VDD = 2.7 to 6.0 V)
Recommended
constant
Resonator
Ceramic
resonator
X1
C2
X1
C2
X1
X2
µ PD74HCU04
Notes 1.
2.
Typ.
2.0
Oscillation
stability
timeNote 2
2.0
Oscillator
frequency
(fX)Note 1
X2
C1
External
clock
Min.
Oscillator
frequency
(fX)Note 1
X2
C1
Crystal
resonator
Parameter
4.19
Oscillation
stability
timeNote 2
Max.
Unit
Conditions
6.2
MHz
VDD = oscillation
voltage range
4
ms
6.2
MHz
10
ms
30
ms
X1 input
frequency
(fX)Note 1
2.0
6.2
MHz
X1 input
high/low
level width
(tXH, tXL)
81
250
ns
After VDD reaches
Min. of the oscillation voltage range
VDD = 4.5 to 6.0 V
The oscillator frequency and input frequency indicate only the oscillator characteristics. See the
item of AC characteristics for the instruction execution time.
The oscillation stability time means the time required for the oscillation to stabilize after VDD is
applied or after the STOP mode is released.
CHARACTERISTICS OF THE SUBSYSTEM CLOCK OSCILLATOR (Ta = -40 to +85 °C, VDD = 2.7 to 6.0 V)
Recommended
constant
Resonator
Crystal
resonator
XT1
XT2
R
C3
External
clock
C4
XT1
Notes 1.
2.
XT2
Parameter
Oscillator
frequency
(fXT)Note 1
Min.
Typ.
Max.
Unit
32
32.768
35
kHz
1.0
2
s
10
s
Oscillation
stability
timeNote 2
XT1 input
frequency
(fXT)Note 1
32
100
kHz
XT1 input
high/low
level width
(tXTH, tXTL)
5
15
µs
Conditions
VDD = 4.5 to 6.0 V
The oscillator frequency and input frequency indicate only the oscillator characteristics. See the
item of AC characteristics for the instruction execution time.
The oscillation stability time means the time required for the oscillation to stabilize after VDD is
applied or after the STOP mode is released.
CAPACITANCE (Ta = 25 °C, VDD = 0 V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Input capacitance
CI
15
pF
Output capacitance (Other than display output)
CO
15
pF
I/O capacitance
CIO
15
pF
Output capacitance (Display output)
CO
35
pF
Conditions
f = 1 MHz
0 V for pins other than
pins to be measured
171
µPD75238
DC CHARACTERISTICS (Ta = -40 to +85 °C, VDD = 2.7 to 6.0 V)
Parameter
High-level input
voltage
Symbol
Min.
VIH1
Max.
Unit
Conditions
0.7VDD
VDD
V
Other than ports 0, 1, 4, 5, and 7, RESET, P81, P83,
X1, X2, and XT1
VIH2
0.8VDD
VDD
V
Ports 0 and 1, RESET, P81, and P83
VIH3
VDD - 0.4
VDD
V
X1, X2, and XT1
VIH4
0.65VDD
VDD
V
Port 7
VDD = 4.5 to 6.0 V
0.7VDD
VDD
V
0.7VDD
VDD
V
Ports 4 and 5
Built-in pull-up resistor
0.7VDD
10
V
VIL1
0
0.3VDD
V
Other than ports 0 and 1, RESET, P81, P83, X1, X2,
and XT1
VIL2
0
0.2VDD
V
Ports 0 and 1, RESET, P81, and P83
VIL3
0
0.4
V
X1, X2, and XT1
VOH
VDD - 1.0
V
IOH = -1 mA
VDD - 0.5
V
All output pins VDD = 4.5 to 6.0 V
(excl. ports 4
and 5, and P03) VDD = 2.7 to 6.0 V
VIH5
Low-level input
voltage
High-level output
voltage
Typ.
Open drain
IOH = -100 µA
2.0
V
Ports 3, 4, and
5
VDD = 4.5 to 6.0 V
IOL = 15 mA
0.4
V
All output pins VDD = 4.5 to 6.0 V
IOL = 1.6 mA
0.5
V
VDD = 2.7 to 6.0 V
IOL = 400 µA
0.2VDD
V
ILIH1
3
µA
Other than X1, X2, XT1,
Ports 4 and 5
ILIH2
20
µA
X1, X2, and XT1
ILIH3
20
µA
Ports 4 and 5
VIN = 10 V (open drain)
ILIL1
-3
µA
Other than X1, X2, and
XT1
VIN = 0 V
ILIL2
-20
µA
X1, X2, and XT1
High-level output
leakage current
ILOH1
3
µA
Other than ports 4 and 5
VOUT = VDD
ILOH2
20
µA
Ports 4 and 5
VOUT = 10 V (open drain)
Low-level output
leakage current
ILOL1
-3
µA
Other than display output VOUT = 0 V
ILOL2
-10
µA
Display output
VOUT = VLOAD
= VDD - 35 V
Low-level output
voltage
High-level input
leakage current
Low-level input
leakage current
VOL
Display output
current
IOD
Built-in pull-down
resistor (mask
option)
RP7
Built-in pull-up
resistor
0.4
Open drain
pull-up resistor: 1 kΩ or more
VIN = VDD
-3
-5.5
mA
S0 to S9, S16 to S23
VDD = 4.5 to 6.0 V
-15
-22
mA
T0 to T15
VOD = VDD - 2 V
20
80
200
kΩ
Port 7
VDD = 4.5 to 6.0 V
1000
kΩ
VIN = VDD
20
RL
25
50
135
kΩ
Display output
VOD - VLOAD = 35 V
RV1
15
40
80
kΩ
VDD = 5 V ±10 %
300
kΩ
Ports 0, 1, 2, 3, and 6
(excl. P00)
VIN = 0 V
70
kΩ
VDD = 5 V ±10 %
60
kΩ
Ports 4 and 5
VOUT = VDD - 2.0 V
30
RV2
15
10
172
SB0 and SB1
40
VDD = 3 V ±10 %
VDD = 3 V ±10 %
µPD75238
DC CHARACTERISTICS (Ta = -40 to +85 °C, VDD = 2.7 to 6.0 V)
Parameter
Min.
Symbol
Power supply
current Note 1
IDD1
IDD2
IDD1
IDD2
Typ.
Max.
Unit
4.5
13.5
mA
0.6
1.8
mA
600
1800
µA
200
600
µA
3
9
mA
0.5
1.5
mA
600
1800
µA
200
600
µA
IDD3
40
120
µA
IDD4
5
15
µA
IDD5
0.5
20
µA
0.3
10
µA
5
µA
Conditions
6.0 MHz
crystal
resonance
C1 = C2
= 22 pFNote 4
Operation VDD = 5 V ±10 %Note 2
mode
VDD = 3 V ±10 %Note 3
4.19 MHz
crystal
resonance
C1 = C2
= 22 pFNote 4
Operation VDD = 5 V ±10 %Note 2
mode
VDD = 3 V ±10 %Note 3
kHzNote 5
32
crystal
resonance
HALT
mode
HALT
mode
VDD = 5 V ±10 %
VDD = 3 V ±10 %
VDD = 5 V ±10 %
VDD = 3 V ±10 %
Operation VDD = 3 V ±10 %
mode
HALT
mode
VDD = 3 V ±10 %
VDD = 5 V ±10 %
XT1 = 0 V
STOP mode
VDD =
3 V ±10 %
Ta = 25 ˚C
Notes 1.
This current excludes the current which flows through the built-in pull-down or pull-up resistors.
2.
Value when the processor clock control register (PCC) is set to 0011 and the µPD75238 is operated
in the high-speed mode
3.
Value when the PCC is set to 0000 and the µPD75238 is operated in the low-speed mode
4.
This value applies also when the subsystem clock oscillates.
5.
This value applies when the system clock control resistor (SCC) is set to 1001 to stop the main
system clock pulse and to start the subsystem clock pulse.
A/D CONVERTER CHARACTERISTICS (Ta = -40 to +85 °C, VDD = 2.7 to 6.0 V, AVSS = VSS = 0 V, AVDD = VDD)
Parameter
Symbol
Resolution
Min.
Typ.
Max.
Unit
8
8
8
bit
±1.5
LSB
Absolute accuracyNote 1
Conditions
2.5 V ≤ AVREF ≤ AVDD
±2.0
tCONV
168/f X
µs
Note 2
Sampling time
tSAMP
44/fX
µs
Note 3
Analog input voltage
VIAN
AVREF
V
Analog input impedance
RAN
1000
AVREF current
IAREF
1.0
Notes 1.
★
-40 ≤ T a < -10 °C
Conversion time
AVSS
-10 ≤ T a ≤ +85 °C
MΩ
2.0
mA
Absolute accuracy excluding quantization error (±1/2 LSB)
2.
Time from the execution of a conversion start instruction till EOC = 1
3.
Time from the execution of a conversion start instruction till the end of sampling
(28.0 µs at fX = 6.0 MHz, 40.1 µs at fX = 4.19 MHz)
(7.33 µs at fX = 6.0 MHz, 10.5 µs at fX = 4.19 MHz)
173
µPD75238
AC CHARACTERISTICS (Ta = -40 to +85 °C, VDD = 2.7 to 6.0 V)
(1) Basic operation
Parameter
Symbol
Min.
CPU clock cycle time
(minimum instruction
execution time)Note 1
tCY
Max.
Unit
0.67
64
µs
2.6
64
µs
Operated by main
system clock
pulse
125
µs
Operated by subsystem clock pulse
1
MHz
275
kHz
114
TI0 input frequency
fTI
Typ.
122
0
0
Conditions
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
TI0 input high/low level
width
tTIH,
tTIL
0.48
µs
1.8
µs
Interrupt input high/low
level width
tINTH,
tINTL
Note 2
µs
INT0
10
µs
INT1, INT2, and INT4
tRSL
10
µs
RESET low level width
Notes 1. The cycle time of CPU clock (Φ) de-
VDD = 4.5 to 6.0 V
tCY vs VDD
(When the main system clock is operating)
pends on the connected resonator
70
frequency, the system clock control
64
60
register (SCC), and the processor clock
control register (PCC). The figure on
6
the next page shows the cycle time
5
tCY characteristics for the supply voltage VDD during main system clock
2. This value becomes 2tCY or 128/fX according to the setting of the interrupt
mode register (IM0).
4
Cycle time tCY [ µs]
operation.
Guaranteed operating
range
3
2
1
0.5
0
1
2
3
4
5
Supply voltage VDD [V]
174
6
µPD75238
(2) Serial transfer operation
(a) Two-wire and three-wire serial I/O modes (SCK ... Internal clock output):
Parameter
Symbol
Min.
tKCY1
1340
ns
1600
ns
fX = 4.19 MHz
2680
ns
fX = 6.0 MHz
3800
ns
fX = 4.19 MHz
tKL1
(tKCY/2) – 50
ns
tKH1
(tKCY/2) – 150
ns
SI setup time
(referred to SCK↑)
tSIK1
150
ns
SI hold time
(referred to SCK↑)
tKSI1
400
ns
SCK↓ → SO output
delay time
tKSO1
SCK cycle time
SCK high/low level
width
Typ.
Max.
Unit
250
ns
1000
ns
Conditions
VDD = 4.5 to 6.0 V
fX = 6.0 MHz
VDD = 4.5 to 6.0 V
RL = 1 kΩ,
CL = 100 pFNote
VDD = 4.5 to 6.0 V
Note RL and CL are the resistance and capacitance of the SO output line load respectively.
(b) Two-wire and three-wire serial I/O modes (SCK ... External clock input):
Symbol
Min.
tKCY2
800
ns
3200
ns
tKL2
400
ns
tKH2
1600
ns
SI setup time
(referred to SCK↑)
tSIK2
100
ns
SI hold time
(referred to SCK↑)
tKSI2
400
ns
SCK↓ → SO output
delay time
tKSO2
Parameter
SCK cycle time
SCK high/low level
width
Typ.
Max.
Unit
300
ns
1000
ns
Conditions
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
RL = 1 kΩ,
CL = 100 pFNote
VDD = 4.5 to 6.0 V
Note RL and CL are the resistance and capacitance of the SO output line load respectively.
175
µPD75238
(c) SBI mode (SCK ... Internal clock output (master)):
Parameter
Min.
tKCY3
1340
ns
1600
ns
fX = 4.19 MHz
2680
ns
fX = 6.0 MHz
3800
ns
tKL3
tKCY/2 - 50
ns
tKH3
tKCY/2 - 150
ns
SB0/SB1 setup time
(referred to SCK↑)
tSIK3
150
ns
SB0/SB1 hold time
(referred to SCK↑)
tKSI3
tKCY/2
ns
SCK↓ → SB0/SB1
output delay time
tKSO3
0
250
ns
0
1000
ns
SCK↑ → SB0/SB1↓
tKSB
tKCY
ns
SB0/SB1↓ → SCK
tSBK
tKCY
ns
SB0/SB1 low level
width
tSBL
tKCY
ns
SB0/SB1 high level
width
tSBH
tKCY
ns
SCK cycle time
SCK high/low level
width
Typ.
Max.
Unit
Symbol
Conditions
VDD = 4.5 to 6.0 V
fX = 6.0 MHz
fX = 4.19 MHz
VDD = 4.5 to 6.0 V
RL = 1 kΩ ,
CL = 100 pFNote
VDD = 4.5 to 6.0 V
Note RL and CL are the resistance and capacitance of the SO output line load respectively.
(d) SBI mode (SCK ... External clock input (slave)):
Parameter
Min.
tKCY4
800
ns
3200
ns
tKL4
400
ns
tKH4
1600
ns
SB0/SB1 setup time
(referred to SCK↑)
tSIK4
100
ns
SB0/SB1 hold time
(referred to SCK↑)
tKSI4
tKCY/2
ns
SCK↓ → SB0/SB1
output delay time
tKSO4
0
300
ns
0
1000
ns
SCK↑ → SB0/SB1↓
tKSB
tKCY
ns
SB0/SB1↓ → SCK ↓
tSBK
tKCY
ns
SB0/SB1 low level
width
tSBL
tKCY
ns
SB0/SB1 high level
width
tSBH
tKCY
ns
SCK cycle time
SCK high/low level
width
Typ.
Max.
Unit
Symbol
Conditions
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
RL = 1 kΩ ,
CL = 100 pFNote
VDD = 4.5 to 6.0 V
Note RL and CL are the resistance and capacitance of the SO output line load respectively.
176
µPD75238
AC Timing Measurement Points (Excluding X1 and XT1 Inputs)
0.8VDD
0.8VDD
Measurement
point
0.2VDD
0.2VDD
Clock Timing
1/fX
tXL
tXH
VDD – 0.5 V
X1 input
0.4 V
1/fXT
tXTL
tXTH
VDD – 0.5 V
XT1 input
0.4 V
TI0 Timing
1/fTI
tTIL
tTIH
TI0
177
µPD75238
Serial Transfer Timing
Three-wire serial I/O mode:
tKCY1
tKL1
tKH1
SCK
tSIK1
tKSI1
Input data
SI
tKSO1
Output data
SO
Two-wire serial I/O mode:
tKCY2
tKL2
tKH2
SCK
tKSO2
SB0 and SB1
178
tSIK2
tKSI2
µPD75238
Serial Transfer Timing
Bus release signal transfer:
tKCY3
tKCY4
tKL3
tKL4
tKH3
tKH4
SCK
tKSB
tSBL
tSBH
tSIK3
tSIK4
tSBK
tKSI3
tKSI4
SB0 and SB1
tKSO3
tKSO4
Command signal transfer:
tKCY3
tKCY4
tKL3
tKL4
tKH3
tKH4
SCK
tKSB
tSIK3
tSIK4
tSBK
tKSI3
tKSI4
SB0 and SB1
tKSO3
tKSO4
Interrupt Input Timing
tINTL
tINTH
INT0, INT1, INT2
and INT4
RESET Input Timing
tRSL
RESET
179
µPD75238
DATA HOLD CHARACTERISTICS BY LOW SUPPLY VOLTAGE IN DATA MEMORY STOP MODE
(Ta = -40 to +85 °C)
Parameter
Symbol
Min.
VDDDR
2.0
Data hold supply voltage
currentNote 1
IDDDR
Release signal setting time
tSREL
Data hold supply
Max.
Unit
6.0
V
10
µA
0.1
Conditions
VDDDR = 2.0 V
µs
0
tWAIT
Oscillation stability wait
timeNote 2
Notes 1.
2.
3.
Typ.
217/fX
ms
Release by RESET
Note 3
ms
Release by interrupt request
Excluding the current which flows through the built-in pull-up or pull-down resistors
CPU operation stop time for preventing unstable operation at the beginning of oscillation
This value depends on the settings of the basic interval timer mode register (BTM) shown below.
BTM3
BTM2
Wait time
BTM1
BTM0
fX = 6.0 MHz
—
—
—
—
0
0
1
1
0
1
0
1
0
220/fX
1
217/fX
1
215/fX
1
213/fX
fX = 4.19 MHz
(approx. 175 ms)
220/fX
(approx. 250 ms)
(approx. 21.8 ms)
217/fX
(approx. 31.3 ms)
(approx. 5.46 ms)
215/fX
(approx. 7.82 ms)
(approx. 1.37 ms)
213/fX
(approx. 1.95 ms)
Data Hold Timing (STOP Mode Release by RESET)
Internal reset operation
HALT mode
Operation
mode
STOP mode
Data hold mode
VDD
VDDDR
tSREL
STOP instruction execution
RESET
tWAIT
Data Hold Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT mode
Operation
mode
STOP mode
Data hold mode
VDD
VDDDR
tSREL
STOP instruction execution
Standby release signal
(interrupt request)
tWAIT
180
µPD75238
★
12. CHARACTERISTIC CURVES (FOR REFERENCE)
IDD vs V DD (Main System Clock: 6.0 MHz)
(Ta = 25 ˚C)
PCC = 0011
5000
PCC = 0010
PCC = 0001
PCC = 0000
Main system clock
HALT mode + 32 kHz
oscillation
1000
Supply current IDD ( µA)
500
Subsystem clock
operation mode
100
50
Main system clock
STOP mode + 32 kHz
oscillation, and subsystem clock
HALT mode
10
X1
X2
Crystal
resonator
6.0 MHz
5
22 pF
22 pF
XT1
XT2
Crystal
resonator
32.768 kHz 330 kΩ
22 pF
22 pF
1
0
1
2
3
4
5
6
7
Supply voltage VDD (V)
181
µPD75238
IDD vs V DD (Main System Clock: 4.19 MHz)
(Ta = 25 ˚C)
5000
PCC = 0011
PCC = 0010
PCC = 0001
PCC = 0000
Main system clock
HALT mode + 32 kHz
oscillation
1000
Supply current IDD ( µA)
500
Subsystem clock
operation mode
100
50
Main system clock
STOP mode + 32 kHz
oscillation, and subsystem clock
HALT mode
10
X1
X2
Crystal
resonator
4.19 MHz
5
30 pF
30 pF
XT1
XT2
Crystal
resonator
32.768 kHz 330 kΩ
22 pF
1
0
1
2
3
4
Supply voltage VDD (V)
182
5
6
7
22 pF
µPD75238
13. PACKAGE DIMENSIONS
94 PIN PLASTIC QFP (
20)
F2
A
B
71
72
48
47
F1
Q
R
S
C
D
detail of lead end
94
1
G1
24
23
G2
H
I
M
J
M
P
K
N
L
NOTE
Each lead centerline is located within 0.15 mm (0.006 inch) of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
INCHES
A
23.2±0.4
0.913 +0.017
–0.016
B
20.0±0.2
0.787+0.009
–0.008
C
20.0±0.2
0.787 +0.009
–0.008
D
23.2±0.4
0.913 +0.017
–0.016
F1
1.6
0.063
F2
0.8
0.031
G1
1.6
0.063
G2
0.8
H
0.35±0.10
0.031
0.014 +0.004
–0.005
0.006
I
0.15
J
0.8 (T.P.)
0.031 (T.P.)
K
1.6±0.2
L
0.8±0.2
0.063±0.008
0.031 +0.009
–0.008
M
0.15 +0.10
–0.05
0.006 +0.004
–0.003
N
0.10
0.004
P
Q
3.7
0.146
R
0.1±0.1
5 °±5°
0.004±0.004
5°±5°
S
4.0 MAX.
0.158 MAX.
S94GJ-80-5BG-3
183
µPD75238
★
14. RECOMMENDED SOLDERING CONDITIONS
The following conditions must be met when soldering the µPD75238.
Please consult with our sales offices in case other soldering process is used, or in case soldering is done
under different conditions.
Table 14-1 Recommended Soldering Conditions
Part number
Package
µPD75238GJ-×××-5BG
94-pin plastic QFP
Symbol
WS60-107-1
IR30-107-1
VP15-107-1
Partial heating method
Table 14-2 Soldering Conditions
Symbol
Soldering process
Soldering conditions
WS60-107-1
Wave soldering
Temperature in the soldering vessel: 260 ˚C or below
Soldering time: 10 seconds or less
Number of soldering processes: 1
Exposure limit: 7 daysNote
(10 hours of pre-baking is required at 125 ˚C afterward.)
Pre-heating temperature: 120 ˚C max.
(package surface temperature)
IR30-107-1
Infrared ray reflow
Peak package’s surface temperature: 230 ˚C
Reflow time: 30 seconds or less (at 210 ˚C or higher)
Number of reflow processes: 1
Exposure limit: 7 daysNote
(10 hours of pre-baking is required at 125 ˚C afterward.)
VP15-107-1
VPS
Peak package’s surface temperature: 215 ˚C
Reflow time: 40 seconds or less (at 200 ˚C or higher)
Number of reflow processes: 1
Exposure limit: 7 daysNote
(10 hours of pre-baking is required at 125 ˚C afterward.)
Partial heating
method
Partial heating method
Terminal temperature: 300 ˚C or below
Flow time: 3 seconds or less (one side per device)
Note Exposure limit before soldering after dry-pack package is opened. Storage conditions: 25 °C and
relative humidity at 65 % or less.
Caution Do not apply more than a single process at a time, except for “Partial heating method.”
Remark For more details, refer to our document “SMT MANUAL” (IEI-1207).
184
µPD75238
APPENDIX A
Item
µPD75238 SERIES PRODUCT FUNCTION LIST
Product
ROM
µPD75217
µPD75236
µPD75237
24448 × 8
16256 × 8
24448 × 8
When main
system clock
is selected
0.95 µs/1.91 µs/
15.3 µs
(at 4.19 MHz)
When subsystem clock
is selected
I/O lines
(including FIP
dual-function
pins and
excluding
FIP-exclusive
pins)
0.95 µs/1.91 µs/
3.82 µs/15.3 µs
(at 4.19 MHz)
64
Number of
input lines
8
16
Number of I/O 20: Eight lines
for driving
lines
LED
5
None
High-voltage
output
Number of
segments
0.67 µs/1.33 µs/2.67 µs/10.7 µs (at 6.0 MHz)
122 µs (at 32.768 kHz)
33
A/D converter
FIP controller/driver
1024 × 4
Total number
of I/O lines
Number of
output lines
µPD75P238
32640 × 8
768 × 4
RAM
Instruction
cycle
µPD75238
26: 40 V (max.)
9 to 16
Number of
digits
24 : 12 lines for driving LED
24
8 : 8-bit resolution
34 : 40 V (max.)
9 to 24
9 to 16
Timer
Four channels
Serial interface
One channel:
Five channels
SBI/3-wire system
Two channels
3-wire system
3-wire system
Number of interrupt sources
10
11
Range of operating temperature
-40 to +85 °C
Operating power voltage
2.7 to 6.0 V
Package
64-pin plastic
shrink DIP
64-pin plastic
QFP
94-pin plastic QFP
-40 to +70 °C
94-pin plastic
QFP
94-pin ceramic
LCC with a
window
185
★
µPD75238
★
APPENDIX B DEVELOPMENT TOOLS
The following development tools are provided for developing a system which employs the µPD75238.
Language processor
RA75X relocatable assembler
Host machine
PC-9800 series
IBM PC series
Part number
OS
Distribution media
MS-DOSTM
Ver. 3.10
to
Ver. 3.30C
3.5-inch 2HD
µS5A13RA75X
5-inch 2HD
µS5A10RA75X
PC DOS TM
(Ver. 3.1)
5-inch 2HC
µS7B10RA75X
PROM programming tools
Hardware
PG-1500
PA-75P238GJ
A PROM programmer with which programs can be written into PROMs
through keyboards or by remote control, when connected with the
accessory board and optional programmer adapter. Products programmable with the PG-1500 are commonly-used PROMs (256K-bit to 1M-bit)
and single chip microcomputers containing a PROM.
A PROM programmer adapter for the µPD75P238. This adapter is
connected to the PG-1500.
Software
PG-1500 controller
This program enables the host machine to control the PG-1500 through
the serial and parallel interfaces.
Host machine
PC-9800 series
IBM PC series
186
OS
Part number
Distribution media
MS-DOS
Ver. 3.10
to
Ver. 3.30C
3.5-inch 2HD
µS5A13PG1500
5-inch 2HD
µS5A10PG1500
PC DOS
(Ver. 3.1)
5-inch 2HC
µS7B10PG1500
µPD75238
Debugging tools
Hardware
IE-75000-RNote
The IE-75000-R is an in-circuit emulator available for the 75X series. This
emulator is used together with the emulation probe to develop application
systems of the µPD75238. For efficient debugging, the emulator is connected to the host machine and PROM programmer.
IE-75000-R-EM
The IE-75000-R-EM is an emulation board for the IE-75000-R and IE-75001R. The IE-75000-R contains the emulation board. The emulation board is
used together with the IE-75000-R or IE-75001-R to evaluate the µPD75238.
IE-75001-R
The IE-75001-R is an in-circuit emulator available for the 75X series. This
emulator is used together with the IE-75000-R-EM emulation board (option)
and emulation probe to develop application systems of the µPD75238. For
efficient debugging, the emulator is connected to the host machine and
PROM programmer.
EP-75238GJ-R
EV-9200G-94
Software
IE control program
The EP-75238GJ-R is an emulation probe for the µPD75238 (94-pin plastic
QFP). The emulation probe is connected to the IE-75000-R or IE-75001-R
when it is used. A 94-pin conversion socket, the EV-9200G-94, attached to
the probe facilitates the connection of the prove with the user system.
This program enables the host machine to control the IE-75000-R or
IE-75001-R through the RS-232-C interface.
Host machine
Part number
OS
PC-9800 series
IBM PC series
Note
Distribution media
3.5-inch 2HD
µS5A13IE75X
to
Ver. 3.30C
5-inch 2HD
µS5A10IE75X
PC DOS
(Ver. 3.1)
5-inch 2HC
µS7B10IE75X
MS-DOS
Ver. 3.10
Maintenance service only
187
188
Development tool configuration
In-circuit emulator
IE-75000-R
IE-75001-R
Centronics interface
Note 1
Emulation probe
EP-75238GJ-R
RS-232-C
IE-75000-R-EM
IE control
program
Host machine
PC-9800 series
IBM PC series
(Symbolic debugging
is possible.)
Note 2
User sysytem
PG-1500
controller
Built-in PROM
PROM programmer
µ PD75P238GJ/KF
PG-1500
Relocatable
assembler
+
Programmer adapter
Notes 1. The IE-75001-R does not contain the
IE-75000-R-EM (to be ordered).
2. EV-9200G-94
PA-75P238GJ
µPD75238
µPD75238
[MEMO]
189
µPD75238
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear
reactor control systems and life support systems. If customers intend to use NEC devices for above applications
or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact
our sales people in advance.
Application examples recommended by NEC Corporation
Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment,
Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.
Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime
systems, etc.
M4 92.6
FIP® is a registered trademark of NEC Corporation.
MS-DOSTM is a trademark of Microsoft Corporation.
PC DOSTM is a trademark of IBM Corporation.