TI CD74HC73

[ /Title
(CD74
HC73,
CD74
HCT73
)
/Subject
(Dual
J-K
FlipFlop
CD74HC73,
CD74HCT73
Data sheet acquired from Harris Semiconductor
SCHS134
Dual J-K Flip-Flop with Reset
Negative-Edge Trigger
February 1998
Features
Description
• Hysteresis on Clock Inputs for Improved Noise
Immunity and Increased Input Rise and Fall Times
The Harris CD74HC73 and CD74HCT73 utilize silicon gate
CMOS technology to achieve operating speeds equivalent to
LSTTL parts. They exhibit the low power consumption of
standard CMOS integrated circuits, together with the ability
to drive 10 LSTTL loads.
• Asynchronous Reset
• Complementary Outputs
These flip-flops have independent J, K, Reset and Clock
inputs and Q and Q outputs. They change state on the
negative-going transition of the clock pulse. Reset is
accomplished asynchronously by a low level input. This
device is functionally identical to the HC/HCT107 but differs
in terminal assignment and in some parametric limits.
• Buffered Inputs
• Typical fMAX = 60MHz at VCC = 5V, CL = 15pF,
TA = 25oC
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
The 74HCT logic family is functionally as well as pin
compatible with the standard 74LS logic family.
• Wide Operating Temperature Range . . . -55oC to 125oC
Ordering Information
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
PART NUMBER
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
TEMP. RANGE
(oC)
PKG.
NO.
PACKAGE
CD74HC73E
-55 to 125
14 Ld PDIP
E14.3
CD74HCT73E
-55 to 125
14 Ld PDIP
E14.3
CD74HC73M
-55 to 125
14 Ld SOIC
M14.15
NOTES:
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
6. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
7. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
Pinout
CD74HC73, CD74HCT73
(PDIP, SOIC)
TOP VIEW
1CP 1
14 1J
1R 2
13 1Q
1K 3
12 1Q
VCC 4
11 GND
2CP 5
10 2K
2R 6
9 2Q
2J 7
8 2Q
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1998
1
File Number
1721.1
CD74HC73, CD74HCT73
Functional Diagram
14
12
1J
1Q
3
1K
FF 1
13
1Q
1
1CP
2
1R
7
9
2J
10
2K
2Q
FF 2
8
5
2Q
6
GND = 11
VCC = 4
2CP
2R
TRUTH TABLE
INPUTS
R
OUTPUTS
CP
J
K
Q
Q
L
X
X
X
L
H
H
↓
L
L
H
↓
H
L
H
L
H
↓
L
H
L
H
H
↓
H
H
Toggle
H
H
X
X
No Change
No Change
NOTE:
H =High Level (Steady State)
L =Low Level (Steady State)
X = Irrelevant
↓ = High-to-Low Transition
Logic Diagram
14 (7)
J
3(10)
K
nA
CL R
2 (6)
R
2
12 (9)
Q
K
CL
1 (5)
CP
J
13 (8)
Q
CD74HC73, CD74HCT73
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, IO
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Resistance (Typical, Note 3)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
175
Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
8. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
SYMBOL
VI (V)
VIH
-
25oC
IO (mA) VCC (V)
-40oC TO 85oC
-55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
VIL
VOH
-
VIH or
VIL
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or
VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
II
VCC or
GND
-
-
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
-
-
-
-
-
-
-
-
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
-
5.34
-
5.2
-
V
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
-
-
-
-
-
-
-
-
-
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
-
6
-
-
±0.1
-
±1
-
±1
µA
3
CD74HC73, CD74HCT73
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
SYMBOL
VI (V)
ICC
VCC or
GND
0
High Level Input
Voltage
VIH
-
Low Level Input
Voltage
VIL
High Level Output
Voltage
CMOS Loads
VOH
PARAMETER
Quiescent Device
Current
25oC
IO (mA) VCC (V)
-40oC TO 85oC
-55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
6
-
-
4
-
40
-
80
µA
-
4.5 to
5.5
2
-
-
2
-
2
-
V
-
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
VIH or
VIL
-
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
4.5
3.98
-
-
3.84
-
3.7
-
V
-4
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.26
-
0.33
-
0.4
V
±0.1
-
±1
-
±1
µA
HCT TYPES
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage CMOS Loads
VOL
VIH or
VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
II
VCC
and
GND
4
5.5
-
ICC
VCC or
GND
0
5.5
-
-
4
-
40
-
80
µA
∆ICC
VCC
- 2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
µA
NOTE:
9. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT
UNIT LOADS
All
0.3
HC TYPES
NOTE: Unit Load is ∆ICC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC.
HCT TYPES
Input Level
VCC
3V
VS
50% VCC
1.3V
NOTE: Transition times and propagation delay times.
Prerequisite For Switching Specifications
PARAMETER
SYMBOL
TEST
CONDITIONS
25oC
-40oC TO 85oC -55oC TO 125oC
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
80
-
-
100
-
120
-
ns
4.5
16
-
-
20
-
24
-
ns
6
14
-
-
17
-
20
-
ns
2
80
-
-
100
-
120
-
ns
4.5
16
-
-
20
-
24
-
ns
6
14
-
-
17
-
20
-
ns
HC TYPES
CP Pulse Width
R Pulse Width
tw
tw
-CL = 50pF
-CL = 50pF
4
CD74HC73, CD74HCT73
Prerequisite For Switching Specifications
PARAMETER
Setup Time, J, K to CP
Hold Time, J, K to CP
Removal Time
CP Frequency
SYMBOL
tSU
tH
(Continued)
TEST
CONDITIONS
CL = 50pF
CL = 50pF
25oC
-40oC TO 85oC -55oC TO 125oC
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
80
-
-
100
-
120
-
ns
4.5
16
-
-
20
-
24
-
ns
6
14
-
-
17
-
20
-
ns
2
3
-
-
3
-
3
-
ns
4.5
3
-
-
3
-
3
-
ns
6
3
-
-
3
-
3
-
ns
2
80
-
-
100
-
120
-
ns
4.5
16
-
-
20
-
24
-
ns
6
14
-
-
17
-
20
-
ns
2
6
-
-
5
-
4
-
MHz
4.5
30
-
-
25
-
20
-
MHz
CL = 15pF
5
-
60
-
-
-
-
-
MHz
CL = 50pF
6
35
-
-
29
-
23
-
MHz
tw
CL = 50pF
4.5
16
-
-
20
-
24
-
ns
tREM
fMAX
-CL = 50pF
CL = 50pF
HCT TYPES
CP Pulse Width
R Pulse Width
tw
CL = 50pF
4.5
18
-
-
23
-
27
-
ns
Setup Time, J, K to CP
tSU
CL = 50pF
4.5
16
-
-
20
-
24
-
ns
Hold Time, J, K to CP
tH
CL = 50pF
4.5
3
-
-
3
-
3
-
ns
Removal Time
tREM
CL = 50pF
4.5
12
-
-
15
-
18
-
ns
CP Frequency
fMAX
CL = 50pF
4.5
30
-
-
25
-
20
-
MHz
CL = 15pF
5
-
60
-
-
-
-
-
MHz
Switching Specifications Input tr, tf = 6ns
PARAMETER
SYMBOL
TEST
CONDITIONS
tPLH, tPHL
CL = 50pF
25oC
-40oC TO 85oC -55oC TO 125oC
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
-
-
160
-
200
-
240
ns
4.5
-
-
32
-
40
-
48
ns
CL = 15pF
5
-
13
-
-
-
-
-
ns
CL = 50pF
6
-
-
28
-
34
-
41
ns
CL = 50pF
2
-
-
160
-
200
-
240
ns
HC TYPES
Propagation Delay,
CP to Q
Propagation Delay,
CP to Q
Propagation Delay,
R to Q, Q
Output Transition Time
tPLH, tPHL
tPLH, tPHL
tTLH, tTHL
4.5
-
-
32
-
40
-
48
ns
CL = 15pF
5
-
13
-
-
-
-
-
ns
CL = 50pF
6
-
-
28
-
34
-
41
ns
CL = 50pF
2
-
-
145
-
180
-
220
ns
4.5
-
-
29
-
36
-
44
ns
CL = 15pF
5
-
12
-
-
-
-
-
ns
CL = 50pF
6
-
-
25
-
31
-
38
ns
CL = 50pF
2
-
-
75
-
95
18
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
5
CD74HC73, CD74HCT73
Switching Specifications Input tr, tf = 6ns
PARAMETER
Input Capacitance
Power Dissipation Capacitance
(Notes 5, 6)
(Continued)
25oC
-40oC TO 85oC -55oC TO 125oC
SYMBOL
TEST
CONDITIONS
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
CI
-
-
-
-
10
-
10
-
10
pF
CPD
-
5
-
28
-
-
-
-
-
pF
HCT TYPES
Propagation Delay,
CP to Q
tPLH, tPHL
CL = 50pF
4.5
-
-
38
-
48
-
57
ns
Propagation Delay,
CP to Q
tPLH, tPHL
CL = 50pF
4.5
-
-
36
-
45
-
54
ns
Propagation Delay,
R to Q, Q
tPLH, tPHL
CL = 50pF
4.5
-
-
34
-
43
-
51
ns
Output Transition Time
tTLH, tTHL
CL = 50pF
4.5
-
-
15
-
19
-
22
ns
Input Capacitance
Power Dissipation Capacitance
(Notes 5, 6)
CI
-
-
-
-
10
-
10
-
10
pF
CPD
-
5
-
28
-
-
-
-
-
pF
NOTES:
10. CPD is used to determine the dynamic power consumption, per flip-flop.
11. PD = CPD VCC2 fi + Σ CL VCC2 fo where fi = input frequency, fo = output frequency, CL = output load capacitance, VCC = supply voltage.
Test Circuits and Waveforms
tfCL
trCL
CLOCK
tWL + tWH =
90%
10%
I
tr = 6ns
FIGURE 3. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
tf = 6ns
tr = 6ns
VCC
GND
tTLH
GND
tTHL
90%
50%
10%
INVERTING
OUTPUT
3V
2.7V
1.3V
0.3V
INPUT
tTHL
GND
tWH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
tf = 6ns
90%
50%
10%
1.3V
1.3V
tWL
FIGURE 2. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
tPHL
1.3V
0.3V
tWH
NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%.
INPUT
2.7V
0.3V
GND
tWL
I
fCL
3V
CLOCK
50%
50%
tfCL = 6ns
fCL
VCC
50%
10%
tWL + tWH =
trCL = 6ns
tTLH
90%
1.3V
10%
INVERTING
OUTPUT
tPHL
tPLH
FIGURE 4. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
tPLH
FIGURE 5. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
6
CD74HC73, CD74HCT73
Test Circuits and Waveforms
trCL
tfCL
trCL
CLOCK
INPUT
(Continued)
VCC
90%
GND
tH(H)
GND
tH(H)
VCC
DATA
INPUT
50%
tH(L)
3V
1.3V
1.3V
1.3V
GND
tSU(H)
tSU(H)
tSU(L)
tTLH
90%
OUTPUT
tTHL
90%
50%
10%
tTLH
90%
1.3V
OUTPUT
tREM
3V
SET, RESET
OR PRESET
GND
tTHL
1.3V
10%
FIGURE 6. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
tPHL
1.3V
GND
IC
CL
50pF
GND
90%
tPLH
50%
IC
tSU(L)
tPHL
tPLH
tREM
VCC
SET, RESET
OR PRESET
1.3V
0.3V
tH(L)
DATA
INPUT
3V
2.7V
CLOCK
INPUT
50%
10%
tfCL
CL
50pF
FIGURE 7. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
7
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