[ /Title (CD74 HC75, CD74 HCT75 ) /Subject (Dual 2-Bit Bistabl e CD74HC75, CD74HCT75 Data sheet acquired from Harris Semiconductor SCHS135 Dual 2-Bit Bistable Transparent Latch March 1998 Features at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH • True and Complementary Outputs • Buffered Inputs and Outputs • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC Description • Balanced Propagation Delay and Transition Times The Harris CD74HC75 and CD74HCT75 are dual 2-bit bistable transparent latches. Each one of the 2-bit latches is controlled by separate Enable inputs (1E and 2E) which are active LOW. When the Enable input is HIGH data enters the latch and appears at the Q output. When the Enable input (1E and 2E) is LOW the output is not affected. • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC Ordering Information Pinout CD74HC75, CD74HCT75 (PDIP, SOIC) TOP VIEW 1Q0 1 16 1Q0 1D0 2 15 1Q1 1D1 3 14 1Q1 13 1E 2E 4 VCC 5 12 GND 2D0 6 11 2Q0 2D1 7 10 2Q0 2Q1 8 9 2Q1 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1998 1 File Number 1666.1 CD74HC75, CD74HCT75 Functional Diagram 16 (10) 2 (6) Q0 1 (11) D0 1 OF 2 LATCHES 3 (7) D1 Q0 14 (8) Q1 15 (9) Q1 13 (4) E TRUTH TABLE INPUTS OUTPUTS D E Q Q L H L H H H H L X L Q0 Q0 NOTE: H = High Level L = Low Level X = Don’t Care Q0 = The level of Q before the transition of E. LATCH 0 16 (10) 2 (6) D0 D Q LE LE Q0 1 (11) Q0 13 (4) E LE 14 (8) Q Q1 LE LE D Q 3 (7) D1 P P N N LE 15 (9) Q1 LE Q LATCH 1 5 12 VCC GND FIGURE 1. LOGIC DIAGRAM FIGURE 2. LATCH DETAIL 2 LE CD74HC75, CD74HCT75 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical, Note 3) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. θJA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications TEST CONDITIONS PARAMETER SYMBOL VI (V) VIH - 25oC IO (mA) VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 2 1.5 - - 1.5 - 1.5 - V 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V HC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads VIL VOH - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current II VCC or GND - - -0.02 2 1.9 - - 1.9 - 1.9 - V 4.5 4.4 - - 4.4 - 4.4 - V 6 5.9 - - 5.9 - 5.9 - V - - - - - - - - - V -4 4.5 3.98 - - 3.84 - 3.7 - V -5.2 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 4.5 - - 0.1 - 0.1 - 0.1 V 6 - - 0.1 - 0.1 - 0.1 V - - - - - - - - - V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.33 - 0.4 V - 6 - - ±0.1 - ±1 - ±1 µA 3 CD74HC75, CD74HCT75 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) ICC VCC or GND 0 High Level Input Voltage VIH - Low Level Input Voltage VIL High Level Output Voltage CMOS Loads VOH PARAMETER Quiescent Device Current 25oC IO (mA) VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 6 - - 4 - 40 - 80 µA - 4.5 to 5.5 2 - - 2 - 2 - V - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V VIH or VIL - 4.5 4.4 - - 4.4 - 4.4 - V -0.02 4.5 3.98 - - 3.84 - 3.7 - V -4 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.26 - 0.33 - 0.4 V ±0.1 - ±1 - ±1 µA HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load II VCC and GND 4 5.5 - ICC VCC or GND 0 5.5 - - 4 - 40 - 80 µA ∆ICC (Note 4) VCC - 2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA NOTE: 4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS D0, D1 0.8 1E, 2E 1.2 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25oC. Prerequisite For Switching Specifications PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tW - 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns 2 60 - - 75 - 90 - ns 4.5 12 - - 15 - 18 - ns 6 10 - - 13 - 15 - ns HC TYPES Pulse Width Enable Input Setup Time D to Enable tSU - 4 CD74HC75, CD74HCT75 Prerequisite For Switching Specifications PARAMETER Hold Time Enable to D (Continued) 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tH - 2 3 - - 3 - 3 - ns 4.5 3 - - 3 - 3 - ns 6 3 - - 3 - 3 - ns HCT TYPES Pulse Width Enable Input tW - 4.5 16 - - 20 - 24 - ns Setup Time D to Enable tSU - 4.5 12 - - 15 - 18 - ns Hold Time Enable to D tH - 4.5 3 - - 3 - 3 - ns SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tPLH, tPHL CL = 50pF 2 - - 110 - 140 - 165 ns CL = 50pF 4.5 - - 22 - 28 - 33 ns CL = 15pF 5 - 9 - - - - - ns CL = 50pF 6 - - 19 - 24 - 28 ns CL = 50pF 2 - - 130 - 165 - 195 ns CL = 50pF 4.5 - - 26 - 33 - 39 ns CL = 15pF 5 - 10 - - - - - ns CL = 50pF 6 - - 22 - 28 - 33 ns CL = 50pF 2 - - 130 - 165 - 195 ns CL = 50pF 4.5 - - 26 - 33 - 39 ns CL = 15pF 5 - 10 - - - - - ns CL = 50pF 6 - - 22 - 28 - 33 ns CL = 50pF 2 - - 130 - 165 - 195 ns CL = 50pF 4.5 - - 26 - 33 - 39 ns CL = 15pF 5 - 11 - - - - - ns CL = 50pF 6 - - 22 - 28 - 33 ns CL = 50pF 2 - - 75 - 95 - 110 ns CL = 50pF 4.5 - - 15 - 19 - 22 ns CL = 50pF 6 - - 13 - 16 - 19 ns Switching Specifications Input tr, tf = 6ns PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC HC TYPES Propagation Delay, Data to Q Propagation Delay, Data to Q Propagation Delay, Enable to Q Propagation Delay, Enable to Q Output Transition Time Input Capacitance Power Dissipation Capacitance (Notes 5, 6) tPLH, tPHL tPLH, tPHL tPLH, tPHL tTLH, tTHL CI - - - - 10 - 10 - 10 pF CPD - 5 - 46 - - - - - pF CL = 50pF 4.5 - - 28 - 35 - 42 ns CL = 15pF 5 - 11 - - - - - ns CL = 50pF 4.5 - - 28 - 35 - 42 ns HCT TYPES Propagation Delay, Data to Q tPLH, tPHL Propagation Delay, Data to Q tPLH, tPHL Propagation Delay, Enable to Q tPLH, tPHL CL = 15pF 5 - 11 - - - - - ns CL = 50pF 4.5 - - 28 - 35 - 42 ns CL = 15pF 5 11 - - - - - ns 5 CD74HC75, CD74HCT75 Switching Specifications Input tr, tf = 6ns (Continued) 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS Propagation Delay, Enable to Q tPLH, tPHL CL = 50pF 4.5 - - 30 - 38 - 45 ns CL = 15pF 5 - 12 - - - - - ns Output Transition Time tTLH, tTHL CL = 50pF 4.5 - - 15 - 19 - 22 ns PARAMETER Input Capacitance Power Dissipation Capacitance (Notes 5, 6) CI - - - - 10 - 10 - 10 pF CPD - 5 - 46 - - - - - pF NOTES: 5. CPD is used to determine the dynamic power consumption, per latch. 6. PD = VCC2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage. Test Circuits and Waveforms tfCL trCL CLOCK tWL + tWH = 90% 10% I tr = 6ns FIGURE 4. HCT CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH tf = 6ns tr = 6ns VCC GND tTLH GND tTHL 90% 50% 10% INVERTING OUTPUT 3V 2.7V 1.3V 0.3V INPUT tTHL GND tWH NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. tf = 6ns 90% 50% 10% 1.3V 1.3V tWL FIGURE 3. HC CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH tPHL 1.3V 0.3V tWH NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. INPUT 2.7V 0.3V GND tWL I fCL 3V CLOCK 50% 50% tfCL = 6ns fCL VCC 50% 10% tWL + tWH = trCL = 6ns tTLH 90% 1.3V 10% INVERTING OUTPUT tPHL tPLH FIGURE 5. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tPLH FIGURE 6. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 6 CD74HC75, CD74HCT75 Test Circuits and Waveforms trCL tfCL trCL CLOCK INPUT (Continued) VCC 90% GND tH(H) GND tH(H) VCC DATA INPUT 50% tH(L) 3V 1.3V 1.3V 1.3V GND tSU(H) tSU(H) tSU(L) tTLH 90% OUTPUT tTHL 90% 50% 10% tTLH 90% 1.3V OUTPUT tREM 3V SET, RESET OR PRESET GND tTHL 1.3V 10% FIGURE 7. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS tPHL 1.3V GND IC CL 50pF GND 90% tPLH 50% IC tSU(L) tPHL tPLH tREM VCC SET, RESET OR PRESET 1.3V 0.3V tH(L) DATA INPUT 3V 2.7V CLOCK INPUT 50% 10% tfCL CL 50pF FIGURE 8. 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