NEC UPD703003GC-25

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD703003
V853TM
32/16-BIT SINGLE-CHIP MICROCONTROLLER
The µPD703003 is a member of the V850 FamilyTM of 32-bit single-chip microcontrollers designed for real-time
control operations. This microcontroller provides on-chip features, including a 32-bit CPU core, ROM, RAM, interrupt
controller, real-time pulse unit, a serial interface, an A/D converter, a D/A converter, and PWM signal units.
See the following manuals for a detailed description of this product’s functions. Be sure to use these
manuals as a reference for design.
V853 USER’S MANUAL, HARDWARE:
U10913E
V850 FAMILY USER’S MANUAL, ARCHITECTURE:
U10243E
FEATURES
• Number of instructions: 74
• Minimum instruction execution time
30 ns (during 33-MHz operation)
• General registers
32 bits × 32 registers
• Instruction set optimized for control applications
• On-chip memory
ROM: 128 Kbytes
RAM:
4 Kbytes
• Advanced on-chip interrupt controller
• Real-time pulse unit suitable for control operations
• Powerful serial interface (on-chip dedicated baud rate generator)
• On-chip clock generator
• 10-bit resolution A/D converter: 8 channels
• 8-bit resolution D/A converter: 2 channels
• 8/9/10/12-bit resolution PWM: 2 channels
• Power saving functions
APPLICATIONS
• AV: Video cameras, VCRs, etc.
• Office equipment: PPCs, LBPs, printers, etc.
• Industrial equipment: motor controllers, NC machine tools, etc.
• Communications equipment: Mobile telephones, etc.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. U12261EJ2V1DS00 (2nd edition)
Date Published April 1999 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1997
µPD703003
ORDERING INFORMATION
Part Number
Package
Maximum operating frequency (MHz)
µPD703003GC-25-xxx-7EA 100-pin plastic QFP (fine pitch) (14 × 14 mm)
25
µPD703003GC-33-xxx-7EA 100-pin plastic QFP (fine pitch) (14 × 14 mm)
33
Remark “xxx” indicates ROM code suffix.
PIN CONFIGURATION
• 100-Pin Plastic QFP (fine pitch) (14 × 14 mm)
µPD703003GC-25-xxx-7EA
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P43/AD3
P42/AD2
VSS
VDD
P41/AD1
P40/AD0
P90/LBEN
P91/UBEN
P92/R/W
P93/DSTB
P94/ASTB
P95/HLDAK
P96/HLDRQ
WAIT
IC
MODE
RESET
CVDD/CKSEL
X2
X1
CVSS
CLKOUT
VSS
VDD
P110/TO140
P31/TO131
P32/TCLR13
P33/TI13
P34/INTP130
P35/INTP131/SO3
P36/INTP132/SI3
P37/INTP133/SCK3
P63/A19
P62/A18
P61/A17
P60/A16
VSS
VDD
P57/AD15
P56/AD14
P55/AD13
P54/AD12
P53/AD11
P52/AD10
P51/AD9
P50/AD8
P47/AD7
P46/AD6
P45/AD5
P44/AD4
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
P30/TO130
P27/SCK1
P26/RXD1/SI1
P25/TXD1/SO1
P24/SCK0
P23/RXD0/SI0
P22/TXD0/SO0
P21/PWM1
P20/PWM0
NMI
VDD
VSS
P17/INTP123/SCK2
P16/INTP122/SI2
P15/INTP121/SO2
P14/INTP120
P13/TI12
P12/TCLR12
P11/TO121
P10/TO120
AVDD
AVSS
AVREF1
P77/ANI7
P76/ANI6
µPD703003GC-33-xxx-7EA
Caution
2
Connect the IC pin directly to VSS.
Data Sheet U12261EJ2V1DS00
P75/ANI5
P74/ANI4
P73/ANI3
P72/ANI2
P71/ANI1
P70/ANI0
ANO0
ANO1
AVREF2
AVREF3
P07/INTP113/ADTRG
P06/INTP112
P05/INTP111
P04/INTP110
P03/TI11
P02/TCLR11
P01/TO111
P00/TO110
P117/INTP143
P116/INTP142
P115/INTP141
P114/INTP140
P113/TI14
P112/TCLR14
P111/TO141
µPD703003
PIN NAMES
A16 to A19
: Address Bus
P30 to P37
: Port3
AD0 to AD15
: Address/Data Bus
P40 to P47
: Port4
ADTRG
: AD Trigger Input
P50 to P57
: Port5
ANI0 to ANI7
: Analog Input
P60 to P63
: Port6
ANO0, ANO1
: Analog Output
P70 to P77
: Port7
ASTB
: Address Strobe
P90 to P96
: Port9
AVDD
: Analog VDD
P110 to P117
: Port11
AVREF1 to AVREF3
: Analog Reference Voltage
PWM0, PWM1
: Pulse Width Modulation
AVSS
: Analog VSS
RESET
: Reset
CVDD
: Power Supply for Clock Generator
R/W
: Read/Write Status
CVSS
: Ground for Clock Generator
RXD0, RXD1
: Receive Data
CKSEL
: Clock Select
SCK0 to SCK3
: Serial Clock
CLKOUT
: Clock Output
SI0 to SI3
: Serial Input
DSTB
: Data Strobe
SO0 to SO3
: Serial Output
HLDAK
: Hold Acknowledge
TO110, TO111,
: Timer Output
HLDRQ
: Hold Request
TO120, TO121,
IC
: Internally Connected
TO130, TO131,
INTP110 to INTP113, : Interrupt Request from Peripherals
TO140, TO141
INTP120 to INTP123,
TCLR11 to TCLR14 : Timer Clear
INTP130 to INTP133,
TI11 to TI14
: Timer Input
INTP140 to INTP143
TXD0, TXD1
: Transmit Data
LBEN
: Lower Byte Enable
UBEN
: Upper Byte Enable
MODE
: Mode
WAIT
: Wait
NMI
: Non-maskable Interrupt Request
X1, X2
: Crystal
P00 to P07
: Port0
VDD
: Power Supply
P10 to P17
: Port1
VSS
: Ground
P20 to P27
: Port2
Data Sheet U12261EJ2V1DS00
3
µPD703003
INTERNAL BLOCK DIAGRAM
Mask ROM
CPU
NMI
INTP110 to INTP113
INTP120 to INTP123
INTP130 to INTP133
INTP140 to INTP143
TO110, TO111
TO120, TO121
TO130, TO131
TO140, TO141
Instruction
queue
PC
INTC
128
Kbytes
32-bit
barrel shifter
Multiplier
16×16→32
BCU
System
register
RPU
TCLR11 to TCLR14
TI11 to TI14
HLDRQ
HLDAK
RAM
4
Kbytes
ASTB
DSTB
R/W
UBEN
LBEN
WAIT
A16 to A19
AD0 to AD15
General
register
32 bits × 32
ALU
SIO
SO0/TXD0
SI0/RXD0
SCK0
UART0/CSI0
A/D
converter
D/A
converter
BRG1
SO2
SI2
SCK2
CSI2
BRG2
4
SO3
SI3
SCK3
CSI3
PWM0, PWM1
PWM
Port
P110 to P117
P90 to P96
P70 to P77
P60 to P63
P50 to P57
P40 to P47
P30 to P37
P20 to P27
P10 to P17
P00 to P07
UART1/CSI1
ANO0, ANO1
AVREF2, AVREF3
SO1/TXD1
SI1/RXD1
SCK1
ANI0 to ANI7
AVREF1
AVSS
AVDD
ADTRG
BRG0
Data Sheet U12261EJ2V1DS00
CG
CKSEL
CLKOUT
X1
X2
MODE
RESET
VDD
VSS
CVDD
CVSS
µPD703003
CONTENTS
1.
DIFFERENCES AMONG PRODUCTS ...........................................................................................
6
2. LIST OF PIN FUNCTIONS ...............................................................................................................
7
2.1
Port Pins ................................................................................................................................................
7
2.2
Non-port Pins ........................................................................................................................................
9
2.3
I/O Circuits of Pins and Processing of Unused Pins .........................................................................
11
3. FUNCTION BLOCKS ....................................................................................................................... 14
3.1
Internal Units .........................................................................................................................................
14
4. CPU FUNCTIONS ............................................................................................................................ 16
5. BUS CONTROL FUNCTIONS ......................................................................................................... 17
6. INTERRUPT/EXCEPTION HANDLING FUNCTIONS ..................................................................... 18
7. CLOCK GENERATION FUNCTIONS .............................................................................................. 21
8. TIMER/COUNTER FUNCTIONS (REAL-TIME PULSE UNIT) ........................................................ 22
9. SERIAL INTERFACE FUNCTIONS (SIO) ....................................................................................... 24
9.1
Asynchronous Serial Interface 0, 1 (UART0, UART1) ........................................................................
24
9.2
Clock-synchronized Serial Interface 0 to 3 (CSI0 to CSI3) ................................................................
26
9.3
Baud Rate Generator 0 to 2 (BRG0 to BRG2) .....................................................................................
28
10. PWM UNIT ....................................................................................................................................... 29
11. A/D CONVERTER ............................................................................................................................ 30
12. D/A CONVERTER ............................................................................................................................ 31
13. PORT FUNCTIONS .......................................................................................................................... 32
14. RESET FUNCTIONS ........................................................................................................................ 45
15. INSTRUCTION SET ......................................................................................................................... 46
16. ELECTRICAL SPECIFICATIONS .................................................................................................... 53
17. PACKAGE DRAWINGS ................................................................................................................... 77
18. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 78
Data Sheet U12261EJ2V1DS00
5
µPD703003
1. DIFFERENCES AMONG PRODUCTS
µPD703003 µPD703003A µPD703004A µPD703025A µPD70F3003 µPD70F3003A µPD70F3025A
Item
Internal ROM
Mask ROM
Flash memory
128 Kbytes
Internal RAM
Operation Normal
mode
operation
mode
4 Kbytes
256 Kbytes 128 Kbytes
256 Kbytes
8 Kbytes
8 Kbytes
4 Kbytes
Single-chip Implemented
mode
ROM-less
mode
Flash memory
programming mode
VPP pin
Implemented Not implemented
Implemented Not implemented
Not implemented
Implemented
Not implemented
Implemented
Value of CKC register when reset 00H
6
96 Kbytes
MODE = 0 : 03H
MODE = 1 : 00H
00H
MODE = 0 : 03H
MODE = 1 : 00H
Electrical specifications
Power consumption levels vary (see specific product’s data sheet).
Others
Noise tolerance and noise emission vary, depending on the circuit scale and mask layout.
Data Sheet U12261EJ2V1DS00
µPD703003
2. LIST OF PIN FUNCTIONS
2.1 Port Pins
(1/2)
Pin Name
P00
I/O
I/O
P01
Function
Port 0
TO110
8-bit I/O port
TO111
Input/output mode can be specified bitwise
P02
Alternate Function Pin
TCLR11
P03
TI11
P04
INTP110
P05
INTP111
P06
INTP112
P07
INTP113/ADTRG
P10
I/O
P11
Port 1
TO120
8-bit I/O port
TO121
Input/output mode can be specified bitwise
P12
TCLR12
P13
TI12
P14
INTP120
P15
INTP121/SO2
P16
INTP122/SI2
P17
INTP123/SCK2
P20
I/O
P21
Port 2
PWM0
8-bit I/O port
PWM1
Input/output mode can be specified bitwise
P22
TXD0/SO0
P23
RXD0/SI0
P24
SCK0
P25
TXD1/SO1
P26
RXD1/SI1
P27
SCK1
P30
I/O
P31
Port 3
TO130
8-bit I/O port
TO131
Input/output mode can be specified bitwise
P32
TCLR13
P33
TI13
P34
INTP130
P35
INTP131/SO3
P36
INTP132/SI3
P37
INTP133/SCK3
P40 to P47
I/O
Port 4
AD0 to AD7
8-bit I/O port
Input/output mode can be specified bitwise
P50 to P57
I/O
Port 5
AD8 to AD15
8-bit I/O port
Input/output mode can be specified bitwise
Data Sheet U12261EJ2V1DS00
7
µPD703003
(2/2)
Pin Name
P60 to P63
I/O
I/O
Function
Port 6
Alternate Function Pin
A16 to A19
4-bit I/O port
Input/output mode can be specified bitwise
P70 to P77
Input
Port 7
ANI0 to ANI7
8-bit input port
P90
I/O
P91
LBEN
UBEN
Input/output mode can be specified bitwise
P92
R/W
P93
DSTB
P94
ASTB
P95
HLDAK
P96
HLDRQ
P110
P111
P112
8
Port 9
7-bit I/O port
I/O
Port 11
TO140
8-bit I/O port
TO141
Input/output mode can be specified bitwise
TCLR14
P113
TI14
P114
INTP140
P115
INTP141
P116
INTP142
P117
INTP143
Data Sheet U12261EJ2V1DS00
µPD703003
2.2 Non-port Pins
(1/2)
Pin Name
TO110
I/O
Output
Function
Pulse signal output from timers 11 to 14
Alternate Function Pin
P00
TO111
P01
TO120
P10
TO121
P11
TO130
P30
TO131
P31
TO140
P110
TO141
P111
TCLR11
Input
External clear signal input for timers 11 to 14
P02
TCLR12
P12
TCLR13
P32
TCLR14
P112
TI11
Input
External count clock input for timers 11 to 14
P03
TI12
P13
TI13
P33
TI14
P113
INTP110
Input
INTP111
External maskable interrupt request input,
P04
shared as external capture trigger input for timer 11
P05
INTP112
P06
INTP113
P07/ADTRG
INTP120
Input
INTP121
External maskable interrupt request input,
P14
shared as external capture trigger input for timer 12
P15/SO2
INTP122
P16/SI2
INTP123
P17/SCK2
INTP130
Input
INTP131
External maskable interrupt request input,
P34
shared as external capture trigger input for timer 13
P35/SO3
INTP132
P36/SI3
INTP133
P37/SCK3
INTP140
Input
INTP141
External maskable interrupt request input,
P114
shared as external capture trigger input for timer 14
P115
INTP142
P116
INTP143
P117
SO0
Output
Serial transmit data output (3-wire) for CSI0 to CSI3
P22/TXD0
SO1
P25/TXD1
SO2
P15/INTP121
SO3
P35/INTP131
SI0
Input
Serial receive data input (3-wire) for CSI0 to CSI3
P23/RXD0
SI1
P26/RXD1
SI2
P16/INTP122
SI3
P36/INTP132
Data Sheet U12261EJ2V1DS00
9
µPD703003
(2/2)
Pin Name
SCK0
I/O
I/O
Function
Serial clock I/O (3-wire) for CSI0 to CSI3
Alternate Function Pin
P24
SCK1
P27
SCK2
P17/INTP123
SCK3
P37/INTP133
TXD0
Output
Serial transmit data output for UART0 and UART1
TXD1
RXD0
P25/SO1
Input
Serial receive data input for UART0 and UART1
RXD1
PWM0
P23/SI0
P26/SI1
Output
PWM pulse signal output
PWM1
AD0 to AD7
P22/SO0
P20
P21
I/O
16-bit multiplexed address/data bus for external memory expansion
A16 to A19
Output
High-order address bus used for external memory expansion
P60 to P63
LBEN
Output
External data bus’s low-order byte enable signal output
P90
External data bus’s high-order byte enable signal output
P91
External read/write status output
P92
DSTB
External data strobe signal output
P93
ASTB
External address strobe signal output
P94
AD8 to AD15
P50 to P57
UBEN
R/W
P40 to P47
Output
HLDAK
Output
Bus hold acknowledge output
P95
HLDRQ
Input
Bus hold request input
P96
ANI0 to ANI7
Input
Analog input to A/D converter
P70 to P77
ANO0, ANO1
Output
Analog output to D/A converter
—
NMI
Input
Nonmaskable interrupt request input
—
CLKOUT
Output
System clock output
—
CKSEL
Input
Input for specifying clock generator’s operation mode
WAIT
Input
Control signal input for inserting wait in bus cycle
—
MODE
Input
Operation mode select
—
RESET
Input
System reset input
—
X1
Input
Oscillator connection for system clock. Input is via X1 when using an
—
external clock.
—
X2
—
CVDD
ADTRG
Input
A/D converter external trigger input
P07/INTP113
AVREF1
Input
Reference voltage input for A/D converter
—
AVREF2
Input
Reference voltage input for D/A converter
—
AVREF3
—
AVDD
—
Positive power supply for A/D converter
—
AVSS
—
Ground potential for A/D converter
—
CVDD
—
Positive power supply for on-chip clock generator
CVSS
—
Ground potential for on-chip clock generator
—
VDD
—
Positive power supply
—
VSS
—
Ground potential
—
IC
—
Internally connected pin (connect directly to VSS)
—
10
Data Sheet U12261EJ2V1DS00
CKSEL
µPD703003
2.3 I/O Circuits of Pins and Processing of Unused Pins
Table 2-1 lists I/O circuit type of respective pins and processing method (recommended connection method) when
not used. Figure 2-1 illustrates the various circuit types using partially abridged diagrams.
When connecting to VDD or VSS via a resistor, a resistance value in the range of 1 to 10 kΩ is recommended.
Table 2-1. I/O Circuits of Pins and Processing of Unused Pins (1/2)
Pin
P00/TO110, P01/TO111
I/O Circuit Type
Recommended Connection Method
5
Input: Connect to VDD or VSS separately via a resistor
P02/TCLR11, P03/TI11,
P04/INTP110 to P07/INTP113/ADTRG
8
Output: Leave open
P10/TO120, P11/TO121
5
P12/TCLR12, P13/TI12
P14/INTP120
P15/INTP121/SO2
P16/INTP122/SI2
P17/INTP123/SCK2
8
P20/PWM0, P21/PWM1
5
P22/TXD0/SO0
P23/RXD0/SI0, P24/SCK0
8
P25/TXD1/SO1
5
P26/RXD1/SI1, P27/SCK1
8
P30/TO130, P31/TO131
5
P32/TCLR13, P33/TI13
8
P34/INTP130
P35/INTP131/SO3
P36/INTP132/SI3
10-A
P37/INTP133/SCK3
P40/AD0 to P47/AD7
5
P50/AD8 to P57/AD15
P60/A16 to P63/A19
P70/ANI0 to P77/ANI7
9
Connect directly to VSS
P90/LBEN
5
Input: Connect to VDD or VSS separately via a resistor
Output: Leave open
P91/UBEN
P92/R/W
P93/DSTB
P94/ASTB
P95/HLDAK
P96/HLDRQ
P110/TO140, P111/TO141
P112/TCLR14, P113/TI14
P114/INTP140 to P117/INTP143
8
ANO0, ANO1
12
Leave open
NMI
2
Connect directly to VSS
Data Sheet U12261EJ2V1DS00
11
µPD703003
Table 2-1. I/O Circuits of Pins and Processing of Unused Pins (2/2)
Pin
I/O Circuit Type
Recommended Connection Method
CLKOUT
3
Leave open
WAIT
1
Connect directly to VDD
MODE
2
—
RESET
CVDD/CKSEL
AVREF1 to AVREF3, AVSS
—
Connect directly to VSS
AVDD
—
Connect directly to VDD
IC
—
Connect directly to VSS
12
Data Sheet U12261EJ2V1DS00
µPD703003
Figure 2-1. I/O Circuits of Pins
Type 1
Type 8
VDD
VDD
Data
P-ch
IN/OUT
P-ch
Output
disable
IN
N-ch
N-ch
Type 2
Type 9
P-ch
IN
+
IN
Comparator
–
N-ch
VREF (threshold voltage)
Input enable
Schmitt trigger input with hysteresis characteristics
Type 10-A
Type 3
VDD
VDD
Pull-up
enable
P-ch
VDD
P-ch
Data
OUT
P-ch
IN/OUT
N-ch
Open-drain
output disable
Type 5
N-ch
Type 12
VDD
Data
P-ch
IN/OUT
Output
disable
N-ch
Analog output voltage
P-ch
N-ch
OUT
Input
enable
Data Sheet U12261EJ2V1DS00
13
µPD703003
3. FUNCTION BLOCKS
3.1 Internal Units
3.1.1 CPU
The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic
operations, data transfers, and almost all other instruction processing.
Other dedicated on-chip hardware, such as the multiplier (16 bits × 16 bits) and the barrel shifter (32 bits) help
accelerate processing of complex instructions.
3.1.2 Bus control unit (BCU)
The BCU starts a required bus cycle based on the physical address obtained by the CPU. When an instruction
is fetched from external memory space and the CPU does not send a bus cycle start request, the BCU generates a
prefetch address and prefetches the instruction code. The prefetched instruction code is stored in a prefetch queue.
3.1.3 ROM
ROM is mapped to the address space starting at 00000000H. The MODE pin can be used to select an access
enable/disable setting. ROM can be accessed by the CPU in one clock cycle when an instruction is fetched.
3.1.4 RAM
RAM is mapped to the address space starting at FFFFE000H. RAM can be accessed by the CPU in one clock
cycle when data accessed.
3.1.5 Ports
In addition to the 75 pins (port 0 to port 11) comprising I/O ports (of which eight pins comprise an input-only port),
various port pin and control pin functions can be selected for these pins.
3.1.6 Interrupt controller (INTC)
This controller handles hardware interrupt requests (NMI, INTP110 to INTP113, INTP120 to INTP123, INTP130
to INTP133, and INTP140 to INTP143) from on-chip peripheral hardware and external hardware. Eight interrupt
priority levels can be specified for these interrupt requests, and multiplexed servicing control can be performed for
interrupt sources.
3.1.7 Clock generator (CG)
An on-chip PLL enables the CPU operating clock to be supplied to resonators connected to pins X1 and X2 at 5×
frequency, 1× frequency, and 1/2× frequency. It can also be connected to an external clock instead of to the resonator.
3.1.8 Real-time pulse unit (RPU)
The RPU includes a four-channel 16-bit timer/event counter and a one-channel 16-bit interval timer, which enables
measurement of pulse intervals and frequency as well as programmable pulse output.
14
Data Sheet U12261EJ2V1DS00
µPD703003
3.1.9 Serial interface (SIO)
Four channels are comprised of two kinds of serial interfaces: an asynchronous serial interface (UART) and a clocksynchronized serial interface (CSI). Two of these four channels are switchable between the UART and CSI and the
other two channels are fixed as CSI.
For UART, data is transferred via the TXD and RXD pins. The baud rate is determined by the on-chip baud rate
generator. For CSI, data is transferred via the SO, SI, and SCK pins. The baud rate can be determined by the onchip baud rate generator or it can be supplied from an external source.
One of the two CSI-fixed channels is used as the serial clock output, and serial output is sent via an N-ch open
drain output.
3.1.10 Pulse width modulation (PWM)
There are two channels of selectable 8/9/10/12-bit resolution PWM signal outputs. When a low pass filter is
externally connected, PWM output can be used as D/A converter output. This is suitable for actuator control
applications, such as in motors.
3.1.11 A/D converter (ADC)
This is a high-speed, high-resolution 10-bit A/D converter that includes eight analog input pins. It converts using
the sequential conversion method.
3.1.12 D/A converter (DAC)
This is an 8-bit resolution D/A converter that includes two channels. It converts using the R-2R conversion method.
Data Sheet U12261EJ2V1DS00
15
µPD703003
4. CPU FUNCTIONS
The CPU employs a RISC-based architecture and uses five-stage pipeline control to enable single-clock execution
of almost all instructions.
The features of the CPU functions are shown below.
• Minimum instruction execution time
30 ns (during internal 33-MHz operation)
• Address space: 16-Mbyte linear
• General registers: 32 bits × 32 registers
• Internal 32-bit architecture
• 5-stage pipeline control
• Multiply/divide instructions
• Saturated operation instructions
• 32-bit shift instruction: 1 clock
• Long/short format
• Four types of bit manipulation instructions
• Set
• Clear
• Not
• Test
16
Data Sheet U12261EJ2V1DS00
µPD703003
5. BUS CONTROL FUNCTIONS
The features of the bus control functions are shown below.
• Shared as port pins, connectable to external device
• Wait functions
• Programmable wait function for up to three states per two blocks
• External wait function using WAIT pin
• Idle state insertion function
• Bus mastering arbitration function
• Bus hold function
Data Sheet U12261EJ2V1DS00
17
µPD703003
6. INTERRUPT/EXCEPTION HANDLING FUNCTIONS
The features of the interrupt/exception handling functions are shown below.
• Interrupts
• Nonmaskable interrupt: 1 source
• Maskable interrupt: 32 sources
• 8-level programmable priority control
• Multiple interrupt control based on priority levels
• Mask specification for each maskable interrupt request
• Noise elimination, edge detection, and valid edge specification for external interrupt requests
• Exceptions
• Software exceptions: 32 sources
• Exception trap: 1 source (invalid instruction code exception)
The configuration of the interrupt/exception handling functions is shown below.
Figure 6-1. Block Diagram of Maskable Interrupt
Internal bus
7
3210321032103210
INTM1
INTM2
INTM3
INTM4
SIO
INTCSI0
INTCSI1
INTCSI2
INTCSI3
INTSER0
INTSR0
INTST0
INTSER1
INTSR1
INTST1
A/D converter
INTAD
OVIF11
OVIF12
OVIF13
OVIF14
P11IF0
P11IF1
P11IF2
P11IF3
P12IF0
P12IF1
P12IF2
P12IF3
P13IF0
P13IF1
P13IF2
P13IF3
P14IF0
P14IF1
P14IF2
P14IF3
CMIF4
CSIF0
CSIF1
CSIF2
CSIF3
SEIF0
SRIF0
STIF0
SEIF1
SRIF1
STIF1
ADIF
XX: Name of peripheral unit (OV, P11 to P14, CM, CS, SE, SR, ST, AD)
n: Peripheral unit number (if none exists, then 0 to 4 or 11 to 14)
18
Data Sheet U12261EJ2V1DS00
Handler
address
generator
XXPRn (priority controller)
INTP110
INTP111
INTP112
INTP113
INTP120
INTP121
INTP122
INTP123
INTP130
INTP131
INTP132
INTP133
INTP140
INTP141
INTP142
INTP143
3210 321032103210
Selector
RPU
3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
XXMKn (interrupt mask flag)
INTOV11
INTOV12
INTOV13
INTOV14
INTP110/INTCC110
INTP111/INTCC111
INTP112/INTCC112
INTP113/INTCC113
INTP120/INTCC120
INTP121/INTCC121
INTP122/INTCC122
INTP123/INTCC123
INTP130/INTCC130
INTP131/INTCC131
INTP132/INTCC132
INTP133/INTCC133
INTP140/INTCC140
INTP141/INTCC141
INTP142/INTCC142
INTP143/INTCC143
INTCM4
0
ISPR
Interrupt
request
Interrupt
request
acknowledge
HALT mode
release signal
CPU
PSW
ID
µPD703003
Interrupt/exception sources are shown in Table 6-1.
Table 6-1. List of Interrupts (1/2)
Interrupt/Exception Source
Type
Reset
Category
Interrupt
Name
Control
Register
Trigger Source
Default
Unit
Priority
Level
Exception
Code
Handler Restored
Address
PC
RESET
—
Reset input
—
—
0000H
00000000H
Undefined
Nonmaskable Interrupt
NMI
—
NMI input
—
—
0010H
00000010H
nextPC
Software
exception
Exception
TRAP0nNote
—
004nHNote
00000040H
nextPC
Exception
TRAP1nNote
—
—
005nHNote
00000050H
nextPC
Exception trap
Exception ILGOP
—
—
0060H
00000060H
nextPC
Maskable
Interrupt
INTOV11
OVIC11 Timer 11 overflow
RPU
0
0080H
00000080H
nextPC
Interrupt
INTOV12
OVIC12 Timer 12 overflow
RPU
1
0090H
00000090H
nextPC
Interrupt
INTOV13
OVIC13 Timer 13 overflow
RPU
2
00A0H
000000A0H nextPC
Interrupt
INTOV14
OVIC14 Timer 14 overflow
RPU
3
00B0H
000000B0H nextPC
Interrupt
INTP110/INTCC110 P11IC0
Match between INTP110 and CC110
Pin/RPU
4
00C0H
000000C0H nextPC
Interrupt
INTP111/INTCC111 P11IC1
Match between INTP111 and CC111
Pin/RPU
5
00D0H
000000D0H nextPC
Interrupt
INTP112/INTCC112 P11IC2
Match between INTP112 and CC112
Pin/RPU
6
00E0H
000000E0H nextPC
Interrupt
INTP113/INTCC113 P11IC3
Match between INTP113 and CC113
Pin/RPU
7
00F0H
000000F0H nextPC
Interrupt
INTP120/INTCC120 P12IC0
Match between INTP120 and CC120
Pin/RPU
8
0100H
00000100H
nextPC
Interrupt
INTP121/INTCC121 P12IC1
Match between INTP121 and CC121
Pin/RPU
9
0110H
00000110H
nextPC
Interrupt
INTP122/INTCC122 P12IC2
Match between INTP122 and CC122
Pin/RPU
10
0120H
00000120H
nextPC
Interrupt
INTP123/INTCC123 P12IC3
Match between INTP123 and CC123
Pin/RPU
11
0130H
00000130H
nextPC
Interrupt
INTP130/INTCC130 P13IC0
Match between INTP130 and CC130
Pin/RPU
12
0140H
00000140H
nextPC
Interrupt
INTP131/INTCC131 P13IC1
Match between INTP131 and CC131
Pin/RPU
13
0150H
00000150H
nextPC
Interrupt
INTP132/INTCC132 P13IC2
Match between INTP132 and CC132
Pin/RPU
14
0160H
00000160H
nextPC
Interrupt
INTP133/INTCC133 P13IC3
Match between INTP133 and CC133
Pin/RPU
15
0170H
00000170H
nextPC
Interrupt
INTP140/INTCC140 P14IC0
Match between INTP140 and CC140
Pin/RPU
16
0180H
00000180H
nextPC
Interrupt
INTP141/INTCC141 P14IC1
Match between INTP141 and CC141
Pin/RPU
17
0190H
00000190H
nextPC
Interrupt
INTP142/INTCC142 P14IC2
Match between INTP142 and CC142
Pin/RPU
18
01A0H
000001A0H nextPC
Interrupt
INTP143/INTCC143 P14IC3
Match between INTP143 and CC143
Pin/RPU
19
01B0H
000001B0H nextPC
Interrupt
INTCM4
CMIC4
Signal matches CM4
RPU
20
01C0H
000001C0H nextPC
Interrupt
INTCSI0
CSIC0
CSI0 send/receive completion
SIO
21
01D0H
000001D0H nextPC
Interrupt
INTCSI1
CSIC1
CSI1 send/receive completion
SIO
22
01E0H
000001E0H nextPC
Interrupt
INTCSI2
CSIC2
CSI2 send/receive completion
SIO
23
01F0H
000001F0H nextPC
—
TRAP instruction
—
TRAP instruction
—
Undefined instruction code
—
Note n represents a value between 0 and FH.
Remarks 1. Default priority: The default priority level is the level that takes precedence when multiple
maskable interrupt requests having the same priority level occur at the same
time. The highest priority level is level 0.
Restored PC: This is the PC value that is saved to EIPC or FEPC when interrupt or exception
handling is activated. However, if an interrupt occurs during execution of the
DIVH (divide) instruction, the recovered PC value is the PC value of the current
instruction (DIVH).
2. The invalid instruction execution address can be obtained (using restored PC-4) when an invalid
instruction code exception occurs.
Data Sheet U12261EJ2V1DS00
19
µPD703003
Table 6-1. List of Interrupts (2/2)
Interrupt/Exception Source
Type
Maskable
Category
Name
Control
Register
Trigger Source
Default
Unit
Priority
Level
Exception
Handler
Restored
Code
Address
PC
Interrupt
INTCSI3
CSIC3
CSI3 transmit/receive completion
SIO
24
0200H
00000200H
nextPC
Interrupt
INTSER0
SEIC0
UART0 receive error
SIO
25
0210H
00000210H
nextPC
Interrupt
INTSR0
SRIC0
UART0 receive completion
SIO
26
0220H
00000220H
nextPC
Interrupt
INTST0
STIC0
UART0 transmit completion
SIO
27
0230H
00000230H
nextPC
Interrupt
INTSER1
SEIC1
UART1 receive error
SIO
28
0240H
00000240H
nextPC
Interrupt
INTSR1
SRIC1
UART1 receive completion
SIO
29
0250H
00000250H
nextPC
Interrupt
INTST1
STIC1
UART1 transmit completion
SIO
30
0260H
00000260H
nextPC
Interrupt
INTAD
ADIC
A/D conversion completion
ADC
31
0270H
00000270H
nextPC
Remarks 1. Default priority: The default priority level is the level that takes precedence when multiple
maskable interrupt requests having the same priority level occur at the same
time. The highest priority level is level 0.
Restored PC: This is the PC value that is saved to EIPC or FEPC when interrupt or exception
handling is started. However, if an interrupt occurs during execution of the DIVH
(divide) instruction, the restored PC value is the PC value of the current instruction
(DIVH).
2. The invalid instruction execution address can be obtained using (restored PC-4) when an invalid
instruction code exception occurs.
20
Data Sheet U12261EJ2V1DS00
µPD703003
7. CLOCK GENERATION FUNCTIONS
The features of the clock generation functions are shown below.
• Multiplier function using PLL clock synthesizer
• Clock sources
• Oscillation via resonator connection (PLL mode): fXX = φ, 2 × φ, φ/5
• External clock (PLL mode): fXX = φ, 2 × φ, φ/5
• External clock (direct mode): fXX = 2 × φ
• Power saving control
• HALT mode
• IDLE mode
• Software STOP mode
• Clock output inhibit mode
The configuration of the clock generation functions is shown below.
Figure 7-1. Block Diagram of Clock Generation Functions
φ
X1
CPU, On-chip peripheral I/O
(fXX)
X2
Clock generator
CLKOUT
CKSEL
Remark φ : internal system clock
Data Sheet U12261EJ2V1DS00
21
µPD703003
8. TIMER/COUNTER FUNCTIONS (REAL-TIME PULSE UNIT)
The features of the timer/counter functions are shown below.
• Measurement of pulse interval and frequency, programmable pulse output
• 16-bit measurements enabled
• Generates a variety of pulse patterns (interval pulse, one-shot pulse, etc.)
• Timer 1
• 16-bit timer/event counter
• Count clock sources: two types (selection of an internal system clock division, external pulse input)
• Capture/compare (shared) registers: 16
• Count clear pins: TCLR11 to TCLR14
• Interrupt sources: 20 types
• External pulse outputs: 8
• Timer 4
• 16-bit interval timer
• Count clock: selected from an internal system clock division
• Compare register: 1
• Interrupt sources: 1
22
Data Sheet U12261EJ2V1DS00
µPD703003
The configurations of the timer/counter functions are shown below.
Figure 8-1. Block Diagram of Timer 1 (16-bit timer/event counter)
Edge
detect
TCLR1n
φ /2
φ /4
TI1n
INTP1n0
φm
φm
φ m/4
φ m/8
φ m/32
Note 2
Clear and
start
Clear and start
Note 1
INTOV1n
TM1n (16 bits)
Edge detect
Edge detect
INTCC1n0
INTCC1n1
CC1n0
S
Q
TO1n0
INTP1n1
Edge detect
CC1n1
R
Q
INTP1n2
Edge detect
CC1n2
S
Q
CC1n3
RNote3 Q
Note3
TO1n1
INTP1n3
Edge detect
INTCC1n2
INTCC1n3
Notes 1. Internal count clock
2. External count clock
3. Priority to reset
Remark φ : internal system clock
n = 1 to 4
Figure 8-2. Block Diagram of Timer 4 (16-bit interval timer)
φ /2
φ /4 φ m
φ /16
φ /32
Note
φm
φ m/32
TM4 (16-bit)
Clear and start
CM4
INTCM4
Note Internal count clock
Remark φ : Internal system clock
Data Sheet U12261EJ2V1DS00
23
µPD703003
9. SERIAL INTERFACE FUNCTIONS (SIO)
Two types and six channels of serial interfaces are provided.
Up to four channels may be used at the same time.
(1) Asynchronous serial interfaces 0, 1 (UART0, UART1): 2 channels
(2) Clock-synchronized serial interfaces 0 to 3 (CSI0 to CSI3): 4 channels
Caution
UART0 and CSI0 are a shared pin, as are UART1 and CSI1. Either one can be selected via a
register (ASIM00, ASIM10).
9.1 Asynchronous Serial Interfaces 0, 1 (UART0, UART1)
The features of the asynchronous serial interfaces 0, 1 (UART0, UART1) are shown below.
• Transfer rate
150 bps to 76800 bps (@ φ = 33-MHz operation, using baud rate generator)
110 bps to 307200 bps (@ φ = 20-MHz operation, using baud rate generator)
Maximum 1031 Kbytes (@ φ = 33-MHz operation, using φ/2)
• Full duplex communications: Receive buffer (RXBn) included
• Two-pin configuration
TXDn: output pin for transmit data
RXDn: input pin for receive data
• Reception error detection function
• Parity error
• Framing error
• Overrun error
• Three types of interrupt sources
• Reception error interrupt (INTSERn)
• Reception completion interrupt (INTSRn)
• Transmission completion interrupt (INTSTn)
• The character length of transmit and receive data is specified via the ASIMn0, ASIMn1 register
• Character lengths: 7 or 8 bits, or 9 bits (if using expansion bit)
• Parity function: even, odd, zero, or no parity
• Transmission stop bits: 1 or 2 bits
• On-chip baud rate generator
Remark n = 0, 1
φ : internal system clock
24
Data Sheet U12261EJ2V1DS00
µPD703003
The configuration of the asynchronous serial interfaces 0, 1 (UART0, UART1) are shown below.
Figure 9-1. Block Diagram of Asynchronous Serial Interfaces 0, 1 (UART0, UART1)
Internal bus
8
16/8
Receive
buffer
8
ASIMn0
16/8
RXBn
RXBnL 8
TXEn RXEn PSn1 PSn0 CLn SLn SCLSn
ASIMn1
EBSn
ASISn
Receive
shift register
RXDn
PEn FEn OVEn SOTn
Transmit TXSn
shift register TXSnL
TXDn
1
16
INTSRn
Transmission
INTSERn control parity
attachment
INTSTn
1
16
1
2
Selector
Reception
control
parity check
φ
Baud rate generator
Remark n = 0, 1
φ : internal system clock
Data Sheet U12261EJ2V1DS00
25
µPD703003
9.2 Clock-synchronized Serial Interfaces 0 to 3 (CSI0 to CSI3)
The features of the clock-synchronized serial interfaces 0 to 3 (CSI0 to CSI3) are shown below.
• Number of channels: 4 channels (CSIn)
• High-speed transfer
MAX 8.25 Mbps (@ φ = 33-MHz operation)
• Half-duplex communications
• Character length uses 8-bit unit
• Switchable byte ordering (MSB first or LSB first)
• Selectable external serial clock input/internal serial clock output
• 3-wire type
SOn: Serial data output
SIn:
Serial data input
SCKn: Serial clock I/O
• Interrupt source: 1 type
•
Transmission/reception completion interrupt (INTCSIn)
Remark n = 0 to 3
φ : internal system clock
26
Data Sheet U12261EJ2V1DS00
µPD703003
The configuration of the clock-synchronized serial interfaces 0 to 3 (CSI0 to CSI3) is shown below.
Figure 9-2. Block Diagram of Clock-synchronized Serial Interfaces 0 to 3 (CSI0 to CSI3)
Internal bus
CSIMn
CTXEn CRXEn CSOTn MODn CLSn1 CLSn0
SO latch
SIn
Note
Serial clock
control circuit
Serial clock
counter
Note
1
2
Selector
SCKn
Q
Note
Selector
SOn
D
Shift register (SIOn)
Interrupt
control circuit
Baud rate generator
φ /2
φ
INTCSIn
SO0 to SO2, SCK0 to SCK2: CMOS outputs
SO3, SCK3:
N-ch open-drain outputs
Remark n = 0 to 3
φ : internal system clock
Data Sheet U12261EJ2V1DS00
27
µPD703003
9.3 Baud Rate Generators 0 to 2 (BRG0 to BRG2)
The features of the baud rate generators 0 to 2 (BRG0 to BRG2) are shown below.
• Serial clock can be selected via baud rate generator output and φ (internal system clock)
• Identical baud rates during transmission and reception
The configuration of the baud rate generators 0 to 2 (BRG0 to BRG2) is shown below.
Figure 9-3. Block Diagram of Baud Rate Generators 0 to 2 (BRG0 to BRG2)
Baud rate generator 0
CSI0
φ
TMBRG0
Prescaler
UART1
Baud rate generator 1
CSI1
CSI2
Baud rate generator 2
CSI3
28
BPR00
Match
Clear
Data Sheet U12261EJ2V1DS00
1
2
Internal bus
UART0
BPR01
BRG0
BPR02
BRCE0
BPRM0
µPD703003
10. PWM UNIT
The features of the PWM unit are shown below.
• PWMn: 2 channels
• Selectable active level for PWMn output pulse
• Operating clock selectable as φ, φ/2, φ/4, φ/8, or φ/16 (φ : internal system clock)
• PWMn output resolution selectable as 8, 9, 10, or 12 bits
Remark n = 0, 1
The configuration of the PWM unit is shown below.
Figure 10-1. Block Diagram of PWM Unit
7
8
φ
φ /2
φ /4
φ /8
φ /16
9
TMPn (12 bits)
11
Overflow
ALVn
0-7
0-8
0-9
Comparator
0-11
S
Match
Q
PWMn
RNote
CMPn (12 bits)
PWMn (12 bits)
Note Priority to reset
Remark n = 0, 1
φ : internal system clock
Data Sheet U12261EJ2V1DS00
29
µPD703003
11. A/D CONVERTER
The features of the A/D converter are shown below.
• Analog inputs: 8 channels
• On-chip 10-bit A/D converter
• On-chip A/D conversion result registers (ADCR0 to ADCR7)
10 bits × 8 registers
• A/D conversion trigger modes
A/D trigger mode
Timer trigger mode
External trigger mode
• Sequential conversion method
The configuration of the A/D converter is shown below.
Figure 11-1. Block Diagram of A/D Converter
Series resistor string
ANI0
Sample & hold circuit
Input circuit
ANI2
Tap selector
ANI1
ANI3
ANI4
ANI5
ANI6
Voltage comparator
ANI7
9
0
SAR (10)
10
10
INTAD
9
ADCR0
INTCC110
INTCC111
INTCC112
INTCC113
ADTRG
0
ADCR1
Controller
ADCR2
ADCR3
Noise
Edge
elimination detection
ADCR4
ADCR5
7
0
7
0
ADCR6
ADM0 (8)
ADM1 (8)
ADCR7
8
8
10
Internal bus
30
Data Sheet U12261EJ2V1DS00
R/2
AVREF1
R
R/2
AVSS
AVDD
µPD703003
12. D/A CONVERTER
The features of the D/A converter are shown below.
• 8-bit resolution D/A converter: 2 channels
• R-2R conversion method
The configuration of the D/A converter is shown below.
Figure 12-1. Block Diagram of D/A Converter
2R
AVREF2
ANOn
R
2R
Selector
2R
R
2R
AVREF3
DACSn
DACEn
Internal bus
Remark n = 0, 1
Data Sheet U12261EJ2V1DS00
31
µPD703003
13. PORT FUNCTIONS
The features of the port functions are shown below.
•
Number of ports
Input-only ports:
8
I/O ports:
67
• Alternated as I/O pins for other peripheral functions
• I/O setting can be specified bitwise
• Noise elimination
• Edge detection
The configurations of the port functions are shown below.
Figure 13-1. Block Diagram of P00 and P01 (Port 0)
WRPMC
PMC0n
WRPM
TO11n
Selector
P0n
RDIN
Address
Remark n = 0, 1
32
Data Sheet U12261EJ2V1DS00
P0n
Selector
WRPORT
Selector
Internal bus
PM0n
µPD703003
Figure 13-2. Block Diagram of P02 to P07 (Port 0)
WRPMC
PMC0n
WRPM
Internal bus
PM0n
WRPORT
P0n
Selector
Selector
P0n
Address
RDIN
INTP110-INTP112,
INTP113/ADTRG,
TCLR11, TI11
Noise elimination
Edge detection
Remark n = 2 to 7
Figure 13-3. Block Diagram of P10 and P11 (Port 1)
WRPMC
PMC1n
WRPM
Selector
P1n
RDIN
P1n
Selector
TO12n
WRPORT
Selector
Internal bus
PM1n
Address
Remark n = 0, 1
Data Sheet U12261EJ2V1DS00
33
µPD703003
Figure 13-4. Block Diagram of P12 to P14 (Port 1)
WRPMC
PMC1n
WRPM
Internal bus
PM1n
WRPORT
P1n
Selector
Selector
P1n
Address
RDIN
Noise elimination
Edge detection
TCLR12, TI12
INTP120
Remark n = 2 to 4
Figure 13-5. Block Diagram of P15 (Port 1)
PCM1
WRPMC
PMC15
WRPM
SO2
Selector
P15
Address
RDIN
INTP121
34
P15
Selector
WRPORT
Selector
Internal bus
PM15
Noise elimination
Edge detection
Data Sheet U12261EJ2V1DS00
PCM1
µPD703003
Figure 13-6. Block Diagram of P16 (Port 1)
WRPMC
PMC16
WRPM
Internal bus
PM16
WRPORT
P16
Selector
Selector
P16
Address
RDIN
Noise elimination
Edge detection
INTP122
SI2
PCM1
Figure 13-7. Block Diagram of P17 (Port 1)
SCK2 I/O
switch
PCM1
WRPMC
PMC17
WRPM
P17
P17
Selector
SCK2 output
Selector
WRPORT
Selector
Internal bus
PM17
Address
RDIN
INTP123
Noise elimination
Edge detection
SCK2 output
Data Sheet U12261EJ2V1DS00
PCM1
35
µPD703003
Figure 13-8. Block Diagram of P20 and P21 (Port 2)
WRPMC
PMC2n
WRPM
WRPORT
Selector
Internal bus
PM2n
PWM0, PWM1
P2n
Selector
Selector
P2n
RDIN
Address
Remark n = 0, 1
Figure 13-9. Block Diagram of P22 and P25 (Port 2)
SO0, SO1 output
enable
WRPMC
PMC2n
WRPM
TXD0/SO0
TXD1/SO1
Selector
P2n
RDIN
Address
Remark n = 2, 5
36
Data Sheet U12261EJ2V1DS00
P2n
Selector
WRPORT
Selector
Internal bus
PM2n
µPD703003
Figure 13-10. Block Diagram of P23 and P26 (Port 2)
WRPMC
PMC2n
WRPM
Internal bus
PM2n
WRPORT
P2n
Selector
Selector
P2n
Address
RDIN
RXD0/SI0
RXD1/SI1
Remark n = 3, 6
Figure 13-11. Block Diagram of P24 and P27 (Port 2)
SCK0, SCK1
I/O switch
WRPMC
PMC2n
WRPM
SCK0 output
SCK1 output
Selector
P2n
RDIN
P2n
Selector
WRPORT
Selector
Internal bus
PM2n
Address
SCK0 input
SCK1 input
Remark n = 4, 7
Data Sheet U12261EJ2V1DS00
37
µPD703003
Figure 13-12. Block Diagram of P30 and P31 (Port 3)
WRPMC
PMC3n
WRPM
Selector
Internal bus
PM3n
TO13n
WRPORT
P3n
RDIN
Selector
Selector
P3n
Address
Remark n = 0, 1
Figure 13-13. Block Diagram of P32 to P34 (Port 3)
WRPMC
PMC3n
WRPM
Internal bus
PM3n
WRPORT
P3n
RDIN
TCLR13, TI13
INTP130
Selector
Selector
P3n
Address
Noise elimination
Edge detection
Remark n = 2 to 4
38
Data Sheet U12261EJ2V1DS00
µPD703003
Figure 13-14. Block Diagram of P35 (Port 3)
SO3 output
enable
PUO3
PCM3
WRPMC
PMC35
VDD
Internal bus
WRPM
P
SO3
Selector
P35
P
P35
N
Selector
WRPORT
Selector
PM35
Address
RDIN
Noise elimination
Edge detection
INTP131
PCM3
Figure 13-15. Block Diagram of P36 (Port 3)
WRPMC
PUO3
PMC36
VDD
Internal bus
WRPM
P
PM36
WRPORT
P
N
P36
Selector
Selector
P36
Address
RDIN
INTP132
Noise elimination
Edge detection
SI3
PCM3
Data Sheet U12261EJ2V1DS00
39
µPD703003
Figure 13-16. Block Diagram of P37 (Port 3)
WRPMC
SCK3 I/O
switch
PCM3
PUO3
PMC37
VDD
Internal bus
WRPM
P
WRPORT
Selector
PM37
SCK3 output
P37
N
Selector
Selector
P37
P
Address
RDIN
INTP133
Noise elimination
Edge detection
SCK3 input
PCM3
Figure 13-17. Block Diagram of P40 to P47 (Port 4)
MODE
MM0 to MM2
I/O control circuit
WRPM
WRPORT AD0 to AD7 output
Selector
Selector
P4n
Address
RDIN
AD0 to AD7 input
Remark n = 0 to 7
40
Data Sheet U12261EJ2V1DS00
P4n
Selector
Internal bus
PM4n
µPD703003
Figure 13-18. Block Diagram of P50 to P57 (Port 5)
MODE
MM0 to MM2
I/O control circuit
WRPM
WRPORT AD8 to AD15 output
Selector
Internal bus
PM5n
P5n
Selector
Selector
P5n
Address
RDIN
AD8 to AD15 input
Remark n = 0 to 7
Figure 13-19. Block Diagram of P60 to P63 (Port 6)
MODE
MM0 to MM2
I/O control circuit
WRPM
A16 to A19 output
Selector
P6n
P6n
Selector
WRPORT
Selector
Internal bus
PM6n
Address
RDIN
Remark n = 0 to 3
Data Sheet U12261EJ2V1DS00
41
µPD703003
Internal bus
Figure 13-20. Block Diagram of P70 to P77 (Port 7)
P7n
ANI0 to ANI7
Sample & hold
circuit
RDIN
Remark n = 0 to 7
Figure 13-21. Block Diagram of P90 to P95 (Port 9)
MODE
MM0 to MM3
I/O control circuit
WRPM
LBEN, UBEN, R/W,
DSTB, ASTB, HLDAK
Selector
P9n
P9n
Selector
WRPORT
Selector
Internal bus
PM9n
Address
RDIN
Remark n = 0 to 5
42
Data Sheet U12261EJ2V1DS00
µPD703003
Figure 13-22. Block Diagram of P96 (Port 9)
MM3
I/O control circuit
WRPM
WRPORT
P96
P96
Selector
Selector
Internal bus
PM96
Address
RDIN
HLDRQ
Figure 13-23. Block Diagram of P110 and P111 (Port 11)
WRPMC
PMC11n
WRPM
TO14n
Selector
P11n
RDIN
P11n
Selector
WRPORT
Selector
Internal bus
PM11n
Address
Remark n = 0, 1
Data Sheet U12261EJ2V1DS00
43
µPD703003
Figure 13-24. Block Diagram of P112 to P117 (Port 11)
WRPMC
PMC11n
WRPM
Internal bus
PM11n
WRPORT
P11n
Address
RDIN
TCLR14, TI14
INTP140 to INTP143
Noise elimination
Edge detection
Remark n = 2 to 7
44
Data Sheet U12261EJ2V1DS00
Selector
Selector
P11n
µPD703003
14. RESET FUNCTIONS
When low-level input occurs at the RESET pin, a system reset is performed and the various on-chip hardware
devices are reset to their initial settings.
When the input at the RESET pin changes from low level to high level, the reset status is canceled and the CPU
resumes program execution. The contents of the various registers should be initialized within the program as
necessary.
The feature of the reset functions is shown below.
• On-chip noise elimination circuit which uses analog delay (≅ 60 ns) for the RESET pin
Data Sheet U12261EJ2V1DS00
45
µPD703003
15. INSTRUCTION SET
• How to read instruction set tables
Indicates the instruction group. Instructions are listed in these table according to their respective groups.
Indicates the mnemonic abbreviation for the instruction.
Indicates the instruction's operands (see Table 15-1).
Indicates the instruction binary code. The binary codes for 32-bit
instructions are shown in two levels (see Table 15-2).
Indicates instruction operation (see Table 15-3).
Instruction
group
Indicates flag operations
(see Table 15-4).
Flags
Mnemonic
Operand
Opcode
Operation
CY
Table 15-1. Symbols Used to Indicate Operands
Symbol
Description
reg1
General registers (r0 to r31): used as source registers
reg2
General registers (r0 to r31): mainly used as destination registers
ep
Element pointer (r30)
bit#3
3-bit data used to specify bit number
immX
X bits immediate
dispX
X bits displaced
regID
System register number
vector
5-bit data used to specify trap vector (00H to 1FH)
cccc
4-bit data used to indicate condition code
46
Data Sheet U12261EJ2V1DS00
OV
S
Z
SAT
µPD703003
Table 15-2. Symbols Used to Indicate Opcodes
Symbol
Description
R
1-bit data of code specifying reg1 or regID
r
1-bit data of code specifying reg2
d
1 bit of displaced data
i
1 bit of immediate data
cccc
4-bit data used to indicate condition code
bbb
3-bit data used to specify bit number
Table 15-3. Symbols Used to Indicate Operations
Symbol
Description
←
Assign
GR [ ]
General register
SR [ ]
System register
zero-extend (n)
Zero-extend n up until word length
sign-extend (n)
Sign-extend n up until word length
load-memory (a, b)
Read data having size b from address a
store-memory (a, b, c)
Replace data b at address a with data having size c
load-memory-bit (a, b)
Read bit b from address a
store-memory-bit (a, b, c)
Write c to bit b from address a
saturated (n)
Execute saturation processing for n (n = complement to 2)
Calculation of n:
When n ≥ 7FFFFFFFH, result is 7FFFFFFFH.
When n ≤ 80000000H, result is 80000000H.
result
Result is indicated by flag operations
Byte
Byte (8 bits)
Halfword
Half word (16 bits)
Word
Word (32 bits)
+
Add
–
Subtract
||
Bit linkage
×
Multiply
÷
Divide
AND
Logical AND
OR
Logical OR
XOR
Exclusive OR
NOT
Logical NOT
logically shift left by
Logical shift left
logically shift right by
Logical shift right
arithmetically shift right by
Arithmetic shift right
Data Sheet U12261EJ2V1DS00
47
µPD703003
Table 15-4. Flag Operations
Identifier
(Blank)
Description
No change
0
Clear to zero
×
Set or clear according to result
R
Restore previously saved value(s)
Table 15-5. Condition Codes
Condition name (cond)
Condition code (cccc)
Conditional expression
Description
V
0000
OV = 1
Overflow
NV
1000
OV = 0
No overflow
C/L
0001
CY = 1
Carry
Lower (Less than)
NC/NL
1001
CY = 0
No carry
No lower (Greater than or equal)
Z/E
0010
Z=1
Zero
Equal
NZ/NE
1010
Z=0
Not zero
Not equal
NH
0011
(CY OR Z) = 1
Not higher (Less than or equal)
H
1011
(CY OR Z) = 0
Higher (Greater than)
N
0100
S=1
Negative
P
1100
S=0
Positive
T
0101
–
Always (unconditional)
SA
1101
SAT = 1
Saturated
LT
0110
(S XOR OV) = 1
Less than signed
GE
1110
(S XOR OV) = 0
Greater than or equal signed
LE
0111
((S XOR OV) OR Z) = 1
Less than or equal signed
GT
1111
((S XOR OV) OR Z) = 0
Greater than signed
48
Data Sheet U12261EJ2V1DS00
µPD703003
Instruction Set List
Instruction Mnemonic
group
Operand
Opcode
Operation
CY OV S Z SAT
Load/store SLD.B
instructions
disp7[ep], reg2
r r r r r 0 1 1 0 d d d d d d d adr ← ep + zero-extend (disp7)
GR[reg2] ← sign-extend (Load-memory (adr, Byte))
SLD.H
disp8[ep], reg2
r r r r r 1 0 0 0 d d d d d d d adr ← ep + zero-extend (disp8)
Note 1 GR[reg2] ← sign-extend (Load-memory (adr, Halfword))
SLD.W
disp8[ep], reg2
r r r r r 1 0 1 0 d d d d d d 0 adr ← ep + zero-extend (disp8)
Note 2 GR[reg2] ← Load-memory (adr, Word)
LD.B
disp16[reg1], reg2
r r r r r 1 1 1 0 0 0 RRRRR adr ← GR[reg1] + sign-extend (disp16)
d d d d d d d d d d d d d d d d GR[reg2] ← sign-extend (Load-memory (adr, Byte))
LD.H
disp16[reg1], reg2
r r r r r 1 1 1 0 0 1 RRRRR adr ← GR[reg1] + sign-extend (disp16)
d d d d d d d d d d d d d d d 0 GR[reg2] ← sign-extend (Load-memory (adr, Halfword))
Note 3
LD.W
disp16[reg1], reg2
r r r r r 1 1 1 0 0 1 RRRRR adr ← GR[reg1] + sign-extend (disp16)
d d d d d d d d d d d d d d d 1 GR[reg2] ← Load-memory (adr, Word)
Note 3
SST.B
reg2, disp7[ep]
r r r r r 0 1 1 1 d d d d d d d adr ← ep + zero-extend (disp7)
Store-memory (adr, GR[reg2], Byte)
SST.H
reg2, disp8[ep]
r r r r r 1 0 0 1 d d d d d d d adr ← ep + zero-extend (disp8)
Note 1 Store-memory (adr, GR[reg2], Halfword)
SST.W
reg2, disp8[ep]
r r r r r 1 0 1 0 d d d d d d 1 adr ← ep + zero-extend (disp8)
Note 2 Store-memory (adr, GR[reg2], Word)
ST.B
reg2, disp16[reg1]
r r r r r 1 1 1 0 1 0 RRRRR adr ← GR[reg1] + sign-extend (disp16)
d d d d d d d d d d d d d d d d Store-memory (adr, GR[reg2], Byte)
ST.H
reg2, disp16[reg1]
r r r r r 1 1 1 0 1 1 RRRRR adr ← GR[reg1] + sign-extend (disp16)
d d d d d d d d d d d d d d d 0 Store-memory (adr, GR[reg2], Halfword)
Note 3
ST.W
reg2, disp16[reg1]
r r r r r 1 1 1 0 1 1 RRRRR adr ← GR[reg1] + sign-extend (disp16)
d d d d d d d d d d d d d d d 1 Store-memory (adr, GR[reg2], Word)
Note 3
reg1, reg2
r r r r r 0 0 0 0 0 0 RRRRR GR[reg2] ← GR[reg1]
imm5, reg2
r r r r r 010000 i i i i i
Arithmetic MOV
operation MOV
instructions
MOVHI
Flags
GR[reg2] ← sign-extend (imm5)
imm16, reg1, reg2 r r r r r 1 1 0 0 1 0 RRRRR GR[reg2] ← GR[reg1] + (imm16 || 016)
i i i i i i i i i i i i i i i i
MOVEA
imm16, reg1, reg2 r r r r r 1 1 0 0 0 1 RRRRR GR[reg2] ← GR[reg1] + sign-extend (imm16)
i i i i i i i i i i i i i i i i
ADD
reg1, reg2
r r r r r 0 0 1 1 1 0 RRRRR GR[reg2] ← GR[reg2] + GR[reg1]
ADD
imm5, reg2
r r r r r 010010 i i i i i
ADDI
imm16, reg1, reg2 r r r r r 1 1 0 0 0 0 RRRRR GR[reg2] ← GR[reg1] + sign-extend (imm16)
i i i i i i i i i i i i i i i i
SUB
reg1, reg2
SUBR
reg1, reg2
×
× ×
×
×
× ×
×
×
× ×
×
r r r r r 0 0 1 1 0 1 RRRRR GR[reg2] ← GR[reg2] – GR[reg1]
×
× ×
×
r r r r r 0 0 1 1 0 0 RRRRR GR[reg2] ← GR[reg1] – GR[reg2]
×
× ×
×
GR[reg2] ← GR[reg2] + sign-extend (imm5)
Notes 1. ddddddd = high-order 7 bits of disp8
2. dddddd = high-order 6 bits of disp8
3. ddddddddddddddd = high-order 15 bits of disp16
Data Sheet U12261EJ2V1DS00
49
µPD703003
Instruction Mnemonic
group
Arithmetic MULH
operation
instructions MULH
Operand
Opcode
Operation
Flags
CY OV S Z SAT
reg1, reg2
r r r r r 0 0 0 1 1 1 RRRRR GR[reg2] ←
GR[reg2]Note
GR[reg2] ←
GR[reg2]Note
×
GR[reg1]Note
(signed multiplication)
imm5, reg2
r r r r r 010111 i i i i i
× sign-extend (imm5)
(signed multiplication)
MULHI
imm16, reg1, reg2 r r r r r 1 1 0 1 1 1 RRRRR GR[reg2] ← GR[reg1] Note × imm16
i i i i i i i i i i i i i i i i
(signed multiplication)
DIVH
reg1, reg2
r r r r r 0 0 0 0 1 0 RRRRR GR[reg2] ← GR[reg2] ÷ GR[reg1] Note (signed division)
CMP
reg1, reg2
r r r r r 0 0 1 1 1 1 RRRRR result ← GR[reg2] – GR[reg1]
CMP
imm5, reg2
r r r r r 010011 i i i i i
SETF
cccc, reg2
r r r r r 1 1 1 1 1 1 0 c c c c if conditions are satisfied
0000000000000000
then GR[reg2] ← 00000001H
else GR[reg2] ← 00000000H
× ×
×
×
× ×
×
×
× ×
×
×
× ×
×
×
×
× ×
×
×
×
× ×
×
×
SATSUBI imm16, reg1, reg2 r r r r r 1 1 0 0 1 1 RRRRR GR[reg2] ← saturated (GR[reg1] – sign-extend (imm16)) ×
i i i i i i i i i i i i i i i i
× ×
×
×
× ×
×
×
Saturated SATADD reg1, reg2
operation SATADD imm5, reg2
instructions
SATSUB reg1, reg2
SATSUBR reg1, reg2
result ← GR[reg2] – sign-extend (imm5)
r r r r r 0 0 0 1 1 0 RRRRR GR[reg2] ← saturated (GR[reg2] + GR[reg1])
r r r r r 010001 i i i i i
GR[reg2] ← saturated (GR[reg2] + sign-extend (imm5))
r r r r r 0 0 0 1 0 1 RRRRR GR[reg2] ← saturated (GR[reg2] – GR[reg1])
r r r r r 0 0 0 1 0 0 RRRRR GR[reg2] ← saturated (GR[reg1] – GR[reg2])
×
Logical
TST
operation OR
instruction
ORI
reg1, reg2
r r r r r 0 0 1 0 1 1 RRRRR result ← GR[reg2]AND GR[reg1]
0 ×
×
reg1, reg2
r r r r r 0 0 1 0 0 0 RRRRR GR[reg2] ← GR[reg2]OR GR[reg1]
0 ×
×
0 ×
×
AND
reg1, reg2
0 ×
×
ANDI
imm16, reg1, reg2 r r r r r 1 1 0 1 1 0 RRRRR GR[reg2] ← GR[reg1]AND zero-extend (imm16)
i i i i i i i i i i i i i i i i
XOR
reg1, reg2
XORI
imm16, reg1, reg2 r r r r r 1 1 0 1 0 1 RRRRR GR[reg2] ← GR[reg1]XOR zero-extend (imm16)
i i i i i i i i i i i i i i i i
NOT
reg1, reg2
r r r r r 0 0 0 0 1 RRRRR
SHL
reg1, reg2
r r r r r 1 1 1 1 1 1 RRRRR GR[reg2] ← GR[reg2]logically shift left by GR[reg1]
0000000011000000
SHL
imm5, reg2
r r r r r 010110 i i i i i
SHR
imm16, reg1, reg2 r r r r r 1 1 0 1 0 0 RRRRR GR[reg2] ← GR[reg1]OR zero-extend (imm16)
i i i i i i i i i i i i i i i i
r r r r r 0 0 1 0 1 0 RRRRR GR[reg2] ← GR[reg2]AND GR[reg1]
r r r r r 0 0 1 0 0 1 RRRRR GR[reg2] ← GR[reg2]XOR GR[reg1]
0 ×
×
0 ×
×
0 ×
×
×
0 ×
×
GR[reg2] ← GR[reg2]logically shift left by
×
zero-extend (imm5)
0 ×
×
reg1, reg2
r r r r r 1 1 1 1 1 1 RRRRR GR[reg2] ← GR[reg2]logically shift right by GR[reg1] ×
0000000010000000
0 ×
×
SHR
imm5, reg2
r r r r r 010100 i i i i i
GR[reg2] ← GR[reg2]logically shift right by
×
zero-extend (imm5)
0 ×
×
SAR
reg1, reg2
r r r r r 1 1 1 1 1 1 RRRRR GR[reg2] ← GR[reg2]arithmetically shift right by
×
0000000010100000
GR[reg1]
0 ×
×
SAR
imm5, reg2
r r r r r 010101 i i i i i
GR[reg2] ← GR[reg2]arithmetically shift right by
×
zero-extend (imm5)
0 ×
×
GR[reg2] ← NOT (GR[reg1])
Note Only the low-order half word is valid.
50
0 0 ×
Data Sheet U12261EJ2V1DS00
µPD703003
Instruction Mnemonic
group
Operand
Opcode
Operation
CY OV S Z SAT
[reg1]
0 0 0 0 0 0 0 0 0 1 1 RRRRR PC ← GR[reg1]
disp22
0 0 0 0 0 1 1 1 1 0 d d d d d d PC ← PC + sign-extend (disp22)
ddddddddddddddd0
Note 1
JARL
disp22, reg2
r r r r r 1 1 1 1 0 d d d d d d GR[reg2] ← PC + 4
d d d d d d d d d d d d d d d 0 PC ← PC + sign-extend (disp22)
Note 1
Bcond
disp9
d d d d d 1 0 1 1 d d d c c c c if conditions are satisfied
Note 2 then PC ← PC + sign-extend (disp9)
Branch
JMP
instructions JR
Flags
Bit
SET1
manipulation
instructions
bit#3, disp16[reg1] 0 0 b b b 1 1 1 1 1 0 RRRRR adr ← GR[reg1] + sign-extend (disp16)
d d d d d d d d d d d d d d d d Z flag ← Not (Load-memory-bit (adr, bit#3))
Store-memory-bit (adr, bit#3, 1)
×
CLR1
bit#3, disp16[reg1] 1 0 b b b 1 1 1 1 1 0 RRRRR adr ← GR[reg1] + sign-extend (disp16)
d d d d d d d d d d d d d d d d Z flag ← Not (Load-memory-bit (adr, bit#3))
Store-memory-bit (adr, bit#3, 0)
×
NOT1
bit#3, disp16[reg1] 0 1 b b b 1 1 1 1 1 0 RRRRR adr ← GR[reg1] + sign-extend (disp16)
d d d d d d d d d d d d d d d d Z flag ← Not (Load-memory-bit (adr, bit#3))
Store-memory-bit (adr, bit#3, Z flag)
×
TST1
bit#3, disp16[reg1] 1 1 b b b 1 1 1 1 1 0 RRRRR adr ← GR[reg1] + sign-extend (disp16)
d d d d d d d d d d d d d d d d Z flag ← Not (Load-memory-bit (adr, bit#3))
×
Notes 1. ddddddddddddddddddddd = high-order 21 bits of disp22
2. dddddddd = high-order 8 bits of disp9
Data Sheet U12261EJ2V1DS00
51
µPD703003
Instruction Mnemonic
group
Special
LDSR
Operand
Opcode
Operation
Flags
CY OV S Z SAT
reg2, regID
instructions
r r r r r 1 1 1 1 1 1 RRRRR SR[regID] ← GR[reg2]
0000000000100000
Note
regID = EIPC, FEPC
regID = EIPSW, FEPSW
regID = PSW
STSR
regID, reg2
r r r r r 1 1 1 1 1 1 RRRRR GR[reg2] ← SR[regID]
0000000001000000
TRAP
vector
0 0 0 0 0 1 1 1 1 1 1 i i i i i EIPC ← PC + 4 (restored PC)
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 EIPSW ← PSW
ECR.EICC ← Interrupt code
PSW.EP ← 1
PSW.ID ← 1
PC ← 00000040H (when vector is 00H to 0FH)
00000050H (when vector is 10H to 1FH)
RETI
0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 if PSW.EP = 1
0000000101000000
then PC ← EIPC
PSW ← EIPSW
else if PSW.NP = 1
then PC ← FEPC
PSW ← FEPSW
else PC ← EIPC
PSW ← EIPSW
HALT
0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 Stops
0000000100100000
DI
0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 PSW.ID ← 1
0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 (maskable interrupt prohibit)
EI
1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 PSW.ID ← 0
0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 (maskable interrupt enable)
NOP
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 No operation, uses at least one clock
×
× ×
×
×
R R R R R
Note In this instructions, “reg2” is the mnemonic abbreviation for the source register, but the reg1 field is used
for the opcode. Consequently, these instructions differ from other instructions in a way registers are
specified in mnemonics description and opcodes.
rrrrr = regID specification
RRRRR = reg2 specification
52
Data Sheet U12261EJ2V1DS00
µPD703003
16. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C)
Parameter
Rating
Units
–0.5 to +7.0
V
CVDD pin
–0.5 to VDD + 0.3
V
CVSS
CVSS pin
–0.5 to +0.5
V
AVDD
AVDD pin
–0.5 to VDD + 0.3
V
AVSS
AVSS pin
–0.5 to +0.5
V
Input voltage
VI1
Note, VDD = 5.0 V ±10 %
–0.5 to VDD + 0.3
V
Clock input voltage
VK
X1 pin, VDD = 5.0 V ±10 %
–0.5 to VDD + 1.0
V
Low-level output current
IOL
1 pin
4.0
mA
Total for all pins
100
mA
1 pin
–4.0
mA
Power supply voltage
Symbol
Condition
VDD
VDD pin
CVDD
High-level output current
IOH
Output voltage
VO
VDD = 5.0 V ±10 %
Analog input voltage
VIAN
P70/ANI0 to P77/ANI7
Analog reference input voltage
AVREF
AVREF1 to AVREF3
Total for all pins
–100
mA
–0.5 to VDD + 0.3
V
AVDD > VDD
–0.5 to VDD + 0.3
V
VDD ≥ AVDD
–0.5 to AVDD + 0.3
V
AVDD > VDD
–0.5 to VDD + 0.3
V
VDD ≥ AVDD
–0.5 to AVDD + 0.3
V
Operating temperature
TA
–40 to +85
°C
Storage temperature
Tstg
–65 to +150
°C
Note X1, P70/ANI0 to P77/ANI7, and AV REF1 to AV REF3 are excluded.
Cautions 1. Be sure to avoid direct connections among the IC device output (or I/O) pins and between
V DD or V CC and GND. However, open-drain pins and open collector pins can be directly
connected. A direct connection to an external circuit can be made to avoid conflicting
output from high-impedance pins if the external circuit is designed for the correct timing.
2. If the absolute maximum rating for any of the above parameters is exceeded even
momentarily, it may adversely affect the quality of this product. In other words, these
absolute maximum ratings have been set to prevent physical damage to the product. Do
not use the product in such a way as to exceed any of these ratings.
The ratings and conditions shown below for DC characteristics and AC characteristics
are within the range for normal operation and quality assurance.
Capacitance (TA = 25°C, VDD = VSS = 0 V)
Parameter
Symbol
Input capacitance
CI
I/O capacitance
CIO
Output capacitance
CO
Condition
fC = 1 MHz
All pins are 0 V except for testing pin.
Data Sheet U12261EJ2V1DS00
MIN.
TYP.
MAX.
Units
15
pF
15
pF
15
pF
53
µPD703003
Recommended Operating Conditions
Operation Mode
Internal Operating
Clock Frequency (φ)
Operating Ambient
Temperature (TA)
Power Supply
Voltage (VDD)
0 to 33 MHzNote 1
–40 to +85°C
5.0 V ±10%
MHzNote 2
–40 to +85°C
5.0 V ±10%
–40 to +85°C
5.0 V ±10%
Direct mode
5 to 33
PLL mode
Free-running oscillation frequency to 33 MHz
Notes 1. When not using A/D converter
2. When using A/D converter
Remark The range of internal operating clock frequency in PLL mode is the assured range of function
operation. PLL locked frequency is specified by t CYX.
Recommended Oscillator
(a) Ceramic oscillation resonator connection (TA = –40 to +85°C)
X1
X2
C1
Oscillation
Manufacturer
TDK
Part Number
C2
Frequency
Recommended Circuit
Constant
fXX (MHz)
C1 (pF)
C2 (pF)
Oscillation Voltage Oscillation Stabilization
Range
Time (MAX.)
MIN. (V) MAX. (V)
TOST (ms)
CCR5.0MC3
5.0
On-chip
On-chip
4.5
5.5
0.36
FCR5.0MC5
5.0
On-chip
On-chip
4.5
5.5
0.32
CCR6.6MC3
6.6
On-chip
On-chip
4.5
5.5
0.28
Murata Mfg. CSA5.00MG040
5.0
100
100
4.5
5.5
0.46
CST5.00MGW040
5.0
On-chip
On-chip
4.5
5.5
0.46
CSA6.60MTZ040
6.6
100
100
4.5
5.5
0.42
CST6.60MTW040
6.6
On-chip
On-chip
4.5
5.5
0.42
Cautions 1. Set the oscillator as close to the X1 and X2 pins as possible.
2. No other signal lines should be wired in the area enclosed by broken lines.
3. When matching µ PD703003 with a resonator, be sure to perform sufficient evaluation.
54
Data Sheet U12261EJ2V1DS00
µPD703003
(b) External clock input
X1
X2
Open
High-speed CMOS inverter
External clock
Cautions 1. Set high-speed CMOS inverter as close as possible to the X1 pin.
2. When matching µ PD703003 and a high-speed CMOS inverter, be sure to perform
sufficient evaluation.
Data Sheet U12261EJ2V1DS00
55
µPD703003
DC Characteristics (TA = –40 to +85°C, VDD = 5.0 V ±10%, VSS = 0 V)
Parameter
High-level input voltage
Symbol
VIH
(1/2)
Condition
MIN.
MAX.
Units
Except for X1 and pins listed in Note
2.2
VDD + 0.3
V
0.8 VDD
VDD + 0.3
V
–0.5
+0.8
V
Note
Except for X1 and pins listed in Note
TYP.
Low-level input voltage
VIL
–0.5
0.2 VDD
V
High-level clock input voltage
VXH
X1
0.8 VDD
VDD + 0.5
V
Low-level clock input voltage
VXL
X1
–0.5
+0.6
V
Schmitt trigger input
Threshold voltage
VT +
Note, rising edge
3.0
V
VT –
Note, falling edge
2.0
V
Schmitt trigger input hysteresis width
VT+ – VT– Note
High-level output voltage
VOH
Low-level output voltage
VOL
IOL = 2.5 mA
High-level input leak current
ILIH
Low-level input leak current
High-level output leak current
Low-level output leak current
Software pull-up resistance
Note
0.5
V
IOH = –2.5 mA
0.7 VDD
V
IOH = –100 µA
VDD – 0.5
V
0.45
V
VI = VDD
10
µA
ILIL
VI = 0 V
–10
µA
ILOH
VO = VDD
10
µA
ILOL
VO = 0 V
–10
µA
R
P35/INTP131/SO3,
P36/INTP132/SI3,
P37/INTP133/SCK3
90
kΩ
15
40
Note P02/TCLR11, P03/TI11, P04/INTP110 to P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/
INTP121/SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1,
P27/SCK1, P32/TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/
SCK3, P112/TCLR14, P113/TI14, P114/INTP140 to P117/INTP143, RESET, NMI, MODE
Remarks 1. TYP. values are reference values for when TA = 25°C and VDD = 5.0 V.
2. φ = Internal system clock frequency
56
Data Sheet U12261EJ2V1DS00
µPD703003
DC Characteristics (TA = –40 to +85°C, VDD = 5.0 V ±10%, VSS = 0 V)
Parameter
Symbol
Power supply current When
operating
IDD1
Condition
(2/2)
MIN.
TYP.
MAX.
Units
Direct modeNote
2.4 × φ + 6 2.8 × φ + 19
mA
PLL mode
2.5 × φ + 8 2.9 × φ + 22
mA
1.4 × φ + 5 1.5 × φ + 18
mA
modeNote
During
IDD2
HALT mode
Direct
PLL mode
1.5 × φ + 7 1.6 × φ + 20
mA
During
IDLE mode
Direct modeNote
18.6 × φ + 100 22 × φ + 200
µA
PLL mode
0.05 × φ + 4 0.1 × φ + 8
mA
IDD3
During
IDD4
STOP mode
–40°C ≤ TA ≤ +50°C
2
50
µA
50°C < TA ≤ 85°C
2
200
µA
Note When using A/D converter: φ = 5 to 33 MHz
When not using A/D converter: φ = 0 to 33 MHz
Remarks 1. TYP. values are reference values for when TA = 25°C and VDD = 5.0 V. The power supply current
does not include AVREF1 to AVREF3 or the current that flows across the software pull-up resistance.
2. φ = Internal system clock frequency
Data Sheet U12261EJ2V1DS00
57
µPD703003
Data Hold Characteristics (TA = –40 to +85°C)
Parameter
Symbol
Conditions
Data hold voltage
VDDDR
STOP mode
Data hold current
IDDDR
VDD = VDDDR
MIN.
TYP.
1.5
MAX.
Units
5.5
V
–40°C ≤ TA ≤ +50°C
0.2 VDDDR
50
µA
50°C < TA ≤ 85°C
0.2 VDDDR
200
µA
Power supply voltage rise time
tRVD
200
µs
Power supply voltage fall time
tFVD
200
µs
Power supply voltage hold time
(vs. STOP mode setting)
tHVD
0
ms
STOP mode release signal input time tDREL
0
ns
Data hold high-level input voltage
VIHDR
Note
0.9 VDDDR
VDDDR
V
Data hold low-level input voltage
VILDR
Note
0
0.1 VDDDR
V
Note P02/TCLR11, P03/TI11, P04/INTP110 to P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/
INTP121/SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1,
P27/SCK1, P32/TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/
SCK3, P112/TCLR14, P113/TI14, P114/INTP140 to P117/INTP143, RESET, NMI, MODE, X1
Remark TYP. values are reference values for when TA = 25°C and V DD = 5.0 V.
STOP mode setting (fifth clock after PSC register is set)
VDD
VDD
VDD
VDDDR
tHVD
RESET (input)
NMI (input)
(Released at falling edge)
tFVD
tRVD
VIHDR
VIHDR
NMI (input)
(Released at rising edge)
VILDR
58
Data Sheet U12261EJ2V1DS00
tDREL
µPD703003
AC Characteristics (TA = –40 to +85°C, VDD = 5 V ±10%, VSS = 0 V)
AC test input waveform
(a) P02/TCLR11, P03/TI11, P04/INTP110 to P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/INTP121/
SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, P32/
TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/SCK3, P112/TCLR14,
P113/TI14, P114/INTP140 to P117/INTP143, RESET, NMI, MODE, X1
VDD
0.8 VDD
0.8 VDD
Test points
0V
0.2 VDD
0.2 VDD
(b) Pins other than those listed in (a) above
2.4 V
2.2 V
2.2 V
Test points
0.4 V
0.8 V
0.8 V
AC test output test points
2.2 V
2.2 V
Test points
0.8 V
0.8 V
Load condition
DUT
(Device Under Testing)
CL = 50 pF
Caution
In cases where the load capacitance is greater than 50 pF due to the circuit configuration,
insert a buffer or other element to reduce the device’s load capacitance to below 50 pF.
Data Sheet U12261EJ2V1DS00
59
µPD703003
(1) Clock timing
Parameter
Symbol
X1 input cycle
<1>
X1 input high-level width
<2>
tCYX
tWXH
X1 input low-level width
<3>
tWXL
X1 input rise time
<4>
tXR
X1 input fall time
Conditions
<5>
tXF
—
φ
25-MHz Version
Units
MAX.
MIN.
MAX.
Direct mode
20
Note 1
15
Note 1
ns
PLL mode (PLL locked)
200
250
150
250
ns
Direct mode
7
6
ns
PLL mode
80
60
ns
Direct mode
7
6
ns
PLL mode
80
60
ns
Direct mode
7
7
ns
PLL mode
15
10
ns
Direct mode
7
7
ns
PLL mode
CPU operating frequency
33-MHz Version
MIN.
10
ns
Direct mode
Note 2
15
25
Note 2
33
MHz
PLL mode
Note 3
25
Note 3
33
MHz
Note 4
30
Note 4
CLKOUT output cycle
<6>
tCYK
40
CLKOUT input high-level width
<7>
tWKH
0.5T – 5
0.5T – 5
ns
CLKOUT input low-level width
<8>
tWKL
0.5T – 5
0.5T – 5
ns
<9>
CLKOUT input rise time
ns
tKR
5
5
ns
CLKOUT input fall time
<10> tKF
5
5
ns
X1 ↓ → CLKOUT delay time
<11> tDXK
17
ns
Direct mode
Notes 1. When using A/D converter
3
17
3
: 100 ns
When not using A/D converter
: DC
2. When using A/D converter
: 5 MHz
When not using A/D converter
: 0 MHz
3. Free-running oscillation frequency
4. When using A/D converter
: 200 ns
When not using A/D converter
: DC
Remark T = t CYK
Parameter
Symbol
Free-running oscillation frequency
—
φP
Conditions
PLL mode
TYP.
Units
5
MHz
<1>
<2>
<3>
X1 (input)
<4>
<11>
<5>
<6>
<11>
<7>
<8>
CLKOUT (output)
<9>
60
Data Sheet U12261EJ2V1DS00
<10>
µPD703003
(2) Input waveform
(a) P02/TCLR11, P03/TI11, P04/INTP110 to P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/
INTP121/SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/
SCK1, P32/TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/
SCK3, P112/TCLR14, P113/TI14, P114/INTP140 to P117/INTP143, RESET, NMI, MODE
Parameter
Symbol
Conditions
25-MHz Version
MIN.
MAX.
33-MHz Version
MIN.
Units
MAX.
Input rise time
<12> tIR2
20
20
ns
Input fall time
<13> tIF2
20
20
ns
VDD
0.8 VDD
0.8 VDD
Input signal
0.2 VDD
0V
0.2 VDD
<13>
<12>
(b) Pins other than those listed in (a) above
Parameter
Symbol
Conditions
25-MHz Version
MIN.
MAX.
33-MHz Version
MIN.
Units
MAX.
Input rise time
<14> tIR1
10
10
ns
Input fall time
<15> tIF1
10
10
ns
2.4 V
2.2 V
2.2 V
Input signal
0.4 V
0.8 V
0.8 V
<15>
Data Sheet U12261EJ2V1DS00
<14>
61
µPD703003
(3) Output waveform (other than CLKOUT)
Parameter
Symbol
Conditions
25-MHz Version
MIN.
MAX.
33-MHz Version
MIN.
Units
MAX.
Output rise time
<16> tOR
12
12
ns
Output fall time
<17> tOF
12
12
ns
2.2 V
2.2 V
Output signal
0.8 V
0.8 V
<16>
<17>
(4) Reset timing
Parameter
Symbol
Conditions
25-MHz Version
MIN.
RESET high-level width
<18> tWRSH
RESET low-level width
<19> tWRSL
When power supply is ON
and STOP mode has been
released
Other than when power
supply is ON and STOP
mode has been released
RESET (input)
62
Data Sheet U12261EJ2V1DS00
MIN.
Units
MAX.
500
500
ns
500 + TOST
500 + TOST
ns
500
500
ns
Remark TOST : Oscillation stabilization time
<18>
MAX.
33-MHz Version
<19>
µPD703003
[MEMO]
Data Sheet U12261EJ2V1DS00
63
µPD703003
(5) Read timing (1/2)
Parameter
Symbol
Conditions
25-MHz Version
33-MHz Version
Units
MIN.
MAX.
MIN.
MAX.
CLKOUT↑ → address delay time <20> tDKA
3
20
3
20
ns
CLKOUT↑ → R/W, UBEN, LBEN delay time <78> tDKA2
–2
+13
–2
+13
ns
CLKOUT↑ → address float delay time <21> tFKA
3
15
3
15
ns
CLKOUT↓ → ASTB delay time
<22> tDKST
–2
+13
–2
+13
ns
CLKOUT↑ → DSTB delay time
<23> tDKD
–2
+13
–2
+13
ns
Data input setup time (to CLKOUT↑) <24> tSIDK
7
7
ns
Data input hold time (from CLKOUT↑) <25> tHKID
5
5
ns
WAIT setup time (to CLKOUT↓) <26> tSWTK
8
8
ns
WAIT hold time (from CLKOUT↓) <27> tHKWT
5
5
ns
Address hold time (from CLKOUT↑) <28> tHKA
0
0
ns
<29> tSAST
0.5T – 10
0.5T – 10
ns
Address hold time (from ASTB↓) <30> tHSTA
0.5T – 10
0.5T – 10
ns
Address setup time (to ASTB↓)
DSTB↓ → address float delay time <31> tFDA
0
0
ns
Data input setup time (to address) <32> tSAID
(2 + n)T – 20
(2 + n)T – 20
ns
Data input setup time (to DSTB↓) <33> tSDID
(1 + n)T – 20
(1 + n)T – 20
ns
ASTB↓ → DSTB↓ delay time
0.5T – 10
0.5T – 10
ns
Data input hold time (from DSTB↑) <35> tHDID
0
0
ns
DSTB↑ → address output delay time <36> tDDA
(1 + i)T – 3
(1 + i)T – 3
ns
DSTB↑ → ASTB↑ delay time
<37> tDDSTH
0.5T – 10
0.5T – 10
ns
DSTB↑ → ASTB↓ delay time
<38> tDDSTL
(1.5 + i)T – 10
(1.5 + i)T – 10
ns
DSTB low-level width
<39> tWDL
(1 + n)T – 10
(1 + n)T – 10
ns
ASTB high-level width
<40> tWSTH
T – 10
T – 10
ns
WAIT setup time (to address)
<34> tDSTD
<41> tSAWT1
n≥1
<42> tSAWT2
WAIT hold time (from address)
<43> tHAWT1
n≥1
<44> tHAWT2
WAIT setup time (to ASTB↓)
<45> tSSTWT1
<47> tHSTWT1
<48> tHSTWT2
ns
ns
(0.5 + n)T
ns
(1.5 + n)T
(1.5 + n)T
ns
n≥1
n≥1
1.5T – 20
(1.5 + n)T – 20
(0.5 + n)T
<46> tSSTWT2
WAIT hold time (from ASTB↓)
1.5T – 20
(1.5 + n)T – 20
T – 15
T – 15
ns
(1 + n)T – 15
(1 + n)T – 15
ns
nT
nT
ns
(1 + n)T
(1 + n)T
ns
Remarks 1. T = tCYK
2. n indicates the number of wait clocks that are inserted during a bus cycle. The sampling timing may
vary when using the programmable wait insertion function.
3. i indicates the number of idle states (0 or 1) that are inserted after a read cycle.
4. Maintain at least one of the two data input hold times, either tHKID (<25>) or tHDID (<35>).
64
Data Sheet U12261EJ2V1DS00
µPD703003
(5) Read timing (2/2): 1 wait
T1
T2
TW
T3
CLKOUT (output)
<20>
<28>
A16 to A19 (output)
<78>
R/W (output)
UBEN (output)
LBEN (output)
<32>
<21>
AD0 to AD15 (I/O)
<24>
A0 to A15 (output)
D0 to D15 (input)
<22>
<29>
<25>
<35>
<30>
<22>
ASTB (output)
<40>
<37>
<34> <31>
<23>
<23>
<33>
<36>
DSTB (output)
<38>
<39>
<45> <26>
<27>
<26>
<27>
<47>
<46>
<48>
WAIT (input)
<41>
<43>
<42>
<44>
Remark Broken line indicates high impedance.
Data Sheet U12261EJ2V1DS00
65
µPD703003
(6) Write timing (1/2)
Parameter
Symbol
Conditions
25-MHz Version
33-MHz Version
Units
MIN.
MAX.
MIN.
MAX.
CLKOUT↑ → address delay time <20> tDKA
3
20
3
20
ns
CLKOUT↑ → R/W, UBEN, LBEN delay time <78> tDKA2
–2
+13
–2
+13
ns
CLKOUT↓ → ASTB delay time
<22> tDKST
–2
+13
–2
+13
ns
CLKOUT↑ → DSTB delay time
<23> tDKD
–2
+13
–2
+13
ns
WAIT setup time (to CLKOUT↓) <26> tSWTK
8
8
ns
WAIT hold time (from CLKOUT↓) <27> tHKWT
5
5
ns
Address hold time (from CLKOUT↑) <28> tHKA
0
0
ns
<29> tSAST
0.5T – 10
0.5T – 10
ns
Address hold time (from ASTB↓) <30> tHSTA
0.5T – 10
0.5T – 10
ns
ASTB↓ → DSTB↓ delay time
<34> tDSTD
0.5T – 10
0.5T – 10
ns
DSTB↑ → ASTB↑ delay time
<37> tDDSTH
0.5T – 10
0.5T – 10
ns
DSTB low-level width
<39> tWDL
(1 + n)T – 10
(1 + n)T – 10
ns
ASTB high-level width
<40> tWSTH
WAIT setup time (to address)
<41> tSAWT1
Address setup time (to ASTB↓)
T – 10
n≥1
<42> tSAWT2
WAIT hold time (from address)
<43> tHAWT1
n≥1
<44> tHAWT2
WAIT setup time (to ASTB↓)
<45> tSSTWT1
<47> tHSTWT1
n≥1
ns
(1.5 + n)T – 20
(1.5 + n)T – 20
ns
(0.5 + n)T
ns
(1.5 + n)T
(1.5 + n)T
ns
n≥1
<48> tHSTWT2
ns
1.5T – 20
(0.5 + n)T
<46> tSSTWT2
WAIT hold time (from ASTB↓)
T – 10
1.5T – 20
T – 15
T – 15
ns
(1 + n)T – 15
(1 + n)T – 15
ns
nT
nT
ns
(1 + n)T
(1 + n)T
ns
CLKOUT↑ → data output delay time <49> tDKOD
20
DSTB↓ → data output delay time <50> tDDOD
20
10
10
ns
ns
Data output hold time (from CLKOUT↑) <51> tHKOD
0
0
ns
Data output setup time (to DSTB↑) <52> tSODD
(1 + n)T – 15
(1 + n)T – 15
ns
Data output hold time (from DSTB↑) <53> tHDOD
T – 10
T – 10
ns
Remarks 1. T = tCYK
2. n indicates the number of wait clocks that are inserted during a bus cycle. The sampling timing may
vary when using the programmable wait insertion function.
66
Data Sheet U12261EJ2V1DS00
µPD703003
(6) Write timing (2/2): 1 wait
T1
T2
TW
T3
CLKOUT (output)
<20>
<28>
A16 to A19 (output)
<78>
R/W (output)
UBEN (output)
LBEN (output)
<49>
AD0 to AD15 (I/O)
<51>
A0 to A15 (output)
D0 to D15 (output)
<22>
<29>
<30>
<22>
ASTB (output)
<23>
<23>
<40>
<34> <50>
<37>
<53>
<52>
DSTB (output)
<39>
<45> <26>
<27>
<26>
<27>
<47>
<46>
<48>
WAIT (input)
<41>
<43>
<42>
<44>
Remark Broken line indicates high impedance.
Data Sheet U12261EJ2V1DS00
67
µPD703003
(7) Bus hold timing (1/2)
Parameter
Symbol
Conditions
25-MHz Version
MIN.
MAX.
33-MHz Version
MIN.
Units
MAX.
HLDRQ setup time (to CLKOUT↓) <54> tSHQK
8
8
ns
HLDRQ hold time (from CLKOUT↓) <55> tHKHQ
5
5
ns
CLKOUT↑ → HLDAK delay time <56> tDKHA
20
20
ns
HLDRQ high-level width
<57> tWHQH
T + 10
T + 10
ns
HLDAK low-level width
<58> tWHAL
T – 10
T – 10
ns
CLKOUT↑ → bus float delay time <59> tDKF
20
HLDAK↑ → bus output delay time <60> tDHAC
–3
HLDRQ↓ → HLDAK↓ delay time <61> tDHQHA1
20
–3
(2n + 7.5)T + 20
HLDRQ↑ → HLDAK↑ delay time <62> tDHQHA2
0.5T
1.5T + 20
0.5T
ns
ns
(2n + 7.5)T + 20
ns
1.5T + 20
ns
Remarks 1. T = tCYK
2. n indicates the number of wait clocks that are inserted during a bus cycle. The sampling timing may
vary when using the programmable wait insertion function.
68
Data Sheet U12261EJ2V1DS00
µPD703003
(7) Bus hold timing (2/2)
TH
TH
TH
TH
TI
CLKOUT (output)
<54>
<54><55>
<57>
HLDRQ (input)
<56>
<56>
<61>
<62>
HLDAK (output)
<58>
<60>
<59>
A16 to A19 (output)Note
AD0 to AD15 (I/O)
D0 to D15
(input or output)
ASTB (output)
DSTB (output)
R/W (output)
Note UBEN (output), LBEN (output)
Remark Broken line indicates high impedance.
Data Sheet U12261EJ2V1DS00
69
µPD703003
(8) Interrupt timing
Parameter
Symbol
Conditions
25-MHz Version
MIN.
MAX.
33-MHz Version
MIN.
Units
MAX.
NMI high-level width
<63> tWNIH
500
500
ns
NMI low-level width
<64> tWNIL
500
500
ns
INTPn high-level width
<65> tWITH
n = 110 to 113, 120 to 123,
130 to 133, 140 to 143
3T + 10
3T + 10
ns
INTPn low-level width
<66> tWITL
n = 110 to 113, 120 to 123,
130 to 133, 140 to 143
3T + 10
3T + 10
ns
Remark T = t CYK
<63>
<64>
<65>
<66>
NMI (input)
INTPn (input)
Remark n = 110 to 113, 120 to 123, 130 to 133, 140 to 143
70
Data Sheet U12261EJ2V1DS00
µPD703003
[MEMO]
Data Sheet U12261EJ2V1DS00
71
µPD703003
(9) CSI timing (1/2)
(a) Master mode
(i)
Timing of CSI0 to CSI2
Parameter
Symbol
Conditions
25-MHz Version
MIN.
MAX.
33-MHz Version
MIN.
Units
MAX.
SCKn cycle
<67> tCYSK1
Output
160
120
ns
SCKn high-level width
<68> tWSKH1
Output
0.5tCYSK1 – 20
0.5tCYSK1 – 20
ns
SCKn low-level width
<69> tWSKL1
Output
0.5tCYSK1 – 20
0.5tCYSK1 – 20
ns
SIn setup time (to SCKn↑)
<70> tSSISK1
50
50
ns
SIn hold time (from SCKn↑)
<71> tHSKSI1
0
0
ns
SOn output delay time (to SCKn↓) <72> tDSKSO1
18
SOn output hold time (from SCKn↑) <73> tHSKSO1
0.5tCYSK1 – 5
18
0.5tCYSK1 – 5
ns
ns
Remark n = 0 to 2
(ii) Timing of CSI3
Parameter
Symbol
Conditions
25-MHz Version
MIN.
SCK3 cycle
<67> tCYSK3
Output
SCK3 high-level width
<68> tWSKH3
Output
SCK3 low-level width
<69> tWSKL3
Output
SI3 setup time (to SCK3↑)
SI3 hold time (from SCK3↑)
MAX.
MIN.
Units
MAX.
500
500
ns
0.5tCYSK3 – 150
0.5tCYSK3 – 150
ns
0.5tCYSK3 – 70
0.5tCYSK3 – 70
ns
<70> tSSISK3
100
100
ns
<71> tHSKSI3
50
50
ns
SO3 output delay time (to SCK3↓) <72> tDSKSO3
SO3 output hold time (from SCK3↑) <73> tHSKSO3
RL = 1.5 kΩ
CL = 50 pF
33-MHz Version
RL = 1.5 kΩ
CL = 50 pF
150
tWSKH3
150
tWSKH3
ns
ns
Remark R L and C L are the load resistance and load capacitance of the output line for SCK3 and SO3.
(b) Slave mode
(i)
Timing of CSI0 to CSI2
Parameter
Symbol
Conditions
25-MHz Version
MIN.
MAX.
33-MHz Version
MIN.
Units
MAX.
SCKn cycle
<67> tCYSK2
Input
160
120
ns
SCKn high-level width
<68> tWSKH2
Input
50
30
ns
SCKn low-level width
<69> tWSKL2
Input
50
30
ns
SIn setup time (to SCKn↑)
<70> tSSISK2
10
10
ns
SIn hold time (from SCKn↑)
<71> tHSKSI2
10
SOn output delay time (to SCKn↓) <72> tDSKSO2
SOn output hold time (from SCKn↑) <73> tHSKSO2
tWSKH2
Remark n = 0 to 2
72
10
45
Data Sheet U12261EJ2V1DS00
ns
45
tWSKH2
ns
ns
µPD703003
(9) CSI timing (2/2)
(ii) Timing of CSI3
Parameter
Symbol
Conditions
25-MHz Version
MIN.
MAX.
33-MHz Version
MIN.
Units
MAX.
SCK3 cycle
<67> tCYSK4
Input
500
500
ns
SCK3 high-level width
<68> tWSKH4
Input
100
100
ns
SCK3 low-level width
<69> tWSKL4
Input
180
180
ns
SI3 setup time (to SCK3↑)
<70> tSSISK4
100
100
ns
SI3 hold time (from SCK3↑)
<71> tHSKSI4
50
50
ns
SO3 output delay time (to SCK3↓) <72> tDSKSO4
SO3 output hold time (from SCK3↑) <73> tHSKSO4
RL = 1.5 kΩ
CL = 50 pF
150
tWSKH4
150
tWSKH4
ns
ns
Remark R L is the load resistance and CL is the load capacitance of the output line for SCK3 and SO3.
<67>
<69>
<68>
SCKn (I/O)
<70>
SIn (Input)
<71>
Input data
<72>
<73>
SOn (output)
Output data
Remarks 1. Broken line indicates high impedance.
2. n = 0 to 3
Data Sheet U12261EJ2V1DS00
73
µPD703003
(10) RPU timing
Parameter
Symbol
Conditions
25-MHz Version
MIN.
MAX.
33-MHz Version
MIN.
Units
MAX.
TI1n high-level width
<74> tWTIH
3T + 10
3T + 10
ns
TI1n low-level width
<75> tWTIL
3T + 10
3T + 10
ns
TCLR1n high-level width
<76> tWTCH
3T + 10
3T + 10
ns
TCLR1n low-level width
<77> tWTCL
3T + 10
3T + 10
ns
Remark T = t CYK
<74>
<75>
<76>
<77>
TI1n (input)
TCLR1n (input)
Remark n = 1 to 4
74
Data Sheet U12261EJ2V1DS00
µPD703003
A/D Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = 5 V ±10%, VSS = AVSS = 0 V)
Parameter
Symbol
Conditions
25-MHz Version
MIN.
Resolution
Total
—
errorNote 1
Quantization error
Nonlinearity
Analog input
voltageNote 2
Units
MAX.
10
bit
±0.55
%FSR
—
3.5 V ≤ AVREF1 ≤ AVDD
±0.7
±0.7
%FSR
±1/2
±1/2
LSB
—
tSAMP
errorNote 1
TYP.
±0.55
Sampling time
Full scale errorNote 1
10
33-MHz Version
MIN.
4.5 V ≤ AVREF1 ≤ AVDD
tCONV
Zero scale
MAX.
—
Conversion time
errorNote 1
TYP.
4.5 V ≤ AVREF1 ≤ AVDD
48
3.5 V ≤ AVREF1 ≤ AVDD
4.5 V ≤ AVREF1 ≤ AVDD
3.5 V ≤ AVREF1 ≤ AVDD
60
tCYK
48
60
tCYK
8
10
tCYK
8
10
tCYK
—
4.5 V ≤ AVREF1 ≤ AVDD
±3.0
±4.5
±3.0
±4.5
LSB
—
3.5 V ≤ AVREF1 ≤ AVDD
±3.0
±5.5
±3.0
±5.5
LSB
—
4.5 V ≤ AVREF1 ≤ AVDD
±1.5
±2.5
±1.5
±2.5
LSB
—
3.5 V ≤ AVREF1 ≤ AVDD
±1.5
±4.5
±1.5
±4.5
LSB
—
4.5 V ≤ AVREF1 ≤ AVDD
±1.5
±3.5
±1.5
±3.5
LSB
—
3.5 V ≤ AVREF1 ≤ AVDD
±1.5
±4.5
±1.5
±4.5
LSB
AVDD
+0.3
V
VIAN
–0.3
Reference voltage
AVREF1
3.5
AVDD
V
AVREF1 current
AIREF1
1.2
3.0
1.2
3.0
mA
AIDD
2.3
6.0
2.3
6.0
mA
AVDD power supply
current
AVDD
+0.3
–0.3
AVDD
3.5
Notes 1. Does not include quantization error.
2. When VIAN = 0, the conversion result becomes 000H.
When 0 < VIAN < AVREF1, conversion has 10-bit resolution.
When AVREF1 ≤ VIAN ≤ AVDD, the conversion result becomes 3FFH.
Data Sheet U12261EJ2V1DS00
75
µPD703003
D/A Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = 5 V ±10%, VSS = AVSS = 0 V)
Parameter
Symbol
Conditions
25-MHz Version
MIN.
Resolution
—
Total error
—
TYP.
33-MHz Version
MAX.
MIN.
TYP.
Units
MAX.
8
8
bit
Load condition: 2 MΩ, 30 pF
AVREF2 = VDD
AVREF3 = 0
0.8
0.8
%
—
Load condition: 2 MΩ, 30 pF
AVREF2 = 0.75 VDD
AVREF3 = 0.25 VDD
1.0
1.0
%
—
Load condition: 4 MΩ, 30 pF
AVREF2 = VDD
AVREF3 = 0
0.6
0.6
%
—
Load condition: 4 MΩ, 30 pF
AVREF2 = 0.75 VDD
AVREF3 = 0.25 VDD
0.8
0.8
%
Settling time
—
Load condition: 2 MΩ, 30 pF
Output resistance
RO
10
10
10
10
µs
kΩ
AVREF2 input voltage
AVREF2
0.75 VDD
VDD
0.75 VDD
VDD
V
AVREF3 input voltage
AVREF3
0
0.25 VDD
0
0.25 VDD
V
AVREF2 to AVREF3
resistance value
RAIREF
76
DACS0, DACS1 = 55H
2
Data Sheet U12261EJ2V1DS00
5
2
5
kΩ
µPD703003
17. PACKAGE DRAWINGS
100 PIN PLASTIC QFP (FINE PITCH) ( 14)
A
B
75
76
51
50
detail of lead end
S
C D
R
Q
100
1
26
25
F
G
H
I
J
M
K
P
S
N
L
S
M
NOTE
1. Controlling dimension
ITEM
millimeter.
2. Each lead centerline is located within 0.10 mm (0.004 inch) of
its true position (T.P.) at maximum material condition.
MILLIMETERS
INCHES
A
16.0±0.2
B
14.0±0.2
0.630±0.008
0.551 +0.009
–0.008
C
14.0±0.2
0.551 +0.009
–0.008
D
16.0±0.2
0.630±0.008
F
G
1.0
1.0
0.039
0.039
H
0.22 +0.05
–0.04
0.009±0.002
I
0.10
0.004
J
0.5 (T.P.)
0.020 (T.P.)
K
1.0±0.2
0.039 +0.009
–0.008
L
0.5±0.2
0.020 +0.008
–0.009
M
0.17 +0.03
–0.07
0.007 +0.001
–0.003
N
0.10
0.004
P
1.45±0.05
0.057 +0.003
–0.002
Q
0.125±0.075
0.005±0.003
R
S
5°±5°
1.7 MAX.
5°±5°
0.067 MAX.
P100GC-50-7EA-3
Data Sheet U12261EJ2V1DS00
77
µPD703003
18. RECOMMENDED SOLDERING CONDITIONS
The µPD703003 should be soldered and mounted under the following recommended conditions.
For the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology
Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact your NEC sales representative.
Table 18-1. Soldering Conditions
Soldering Method
Soldering Conditions
Symbol
Infrared reflow
Package peak temperature: 235°C, Reflow time: 30 seconds or
below (210°C or higher), Number of reflow processes: 2 max.,
Exposure limit: 7 daysNote (after that, prebaking is necessary at
125°C for 10 hours)
IR35-107-2
VPS
Package peak temperature: 215°C, Reflow time: 40 seconds or
below (200°C or higher), Number of reflow processes: 2 max.,
Exposure limit: 7 daysNote (after that, prebaking is necessary at
125°C for 10 hours)
VP15-107-2
Partial heating
Pin temperature: 300°C or below, Time: 3 seconds or below
(per side of device)
—
Note Exposure limit after dry-pack is opened. Storage conditions: temperature of 25°C and relative humidity
of 65% or less.
Caution
78
Do not use different soldering methods together (except for partial heating).
Data Sheet U12261EJ2V1DS00
µPD703003
[MEMO]
Data Sheet U12261EJ2V1DS00
79
µPD703003
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material.
All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry.
Each unused pin should be connected to VDD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed immediately
after power-on for devices having reset function.
80
Data Sheet U12261EJ2V1DS00
µPD703003
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
Spain Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860
United Square, Singapore 1130
Tel: 65-253-8311
Fax: 65-250-3583
NEC Electronics Italiana s.r.l.
NEC Electronics (Germany) GmbH
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics (France) S.A.
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829
J99.1
Data Sheet U12261EJ2V1DS00
81
µPD703003
RELATED DOCUMENTS
µPD703003A, 703004A, 703025A Data Sheet (Under preparation)
µPD70F3003 Data Sheet (U12036E)
µPD70F3003A, 70F3025A Data Sheet (U13189E)
V850 Family, Instruction Table (U10229J)Note
Note Japanese version
The related documents indicated in this publication may include preliminary version. However, preliminary versions
are not marked as such.
V850 Family and V853 are trademarks of NEC Corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights
or other intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated “quality assurance program“ for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
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Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98.8