ETC UPD70F3107GJ-UEN

User’s Manual
V850E/MA1
TM
32-Bit Single-Chip Microcontroller
Hardware
µPD703103
µPD703105
µPD703106
µPD703107
µPD70F3107
Document No. U14359EJ3V0UM00 (3rd edition)
Date Published February 2001 N CP(K)
1999
©
Printed in Japan
[MEMO]
2
User’s Manual U14359EJ3V0UM
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
V850 Family and V850E/MA1 are trademarks of NEC Corporation.
Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or
other countries.
User’s Manual U14359EJ3V0UM
3
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these
products may be prohibited without governmental license. To export or re-export some or all of these products from a
country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
License not needed:
µPD703103, 70F3107
The customer must judge
the need for license:
µPD703105, 703106, 703107
• The information in this document is current as of December, 2000. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
• NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
• While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
• NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00.4
4
User’s Manual U14359EJ3V0UM
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
NEC Electronics (Germany) GmbH
NEC Electronics Hong Kong Ltd.
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
NEC Electronics Singapore Pte. Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
Madrid Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860
United Square, Singapore
Tel: 65-253-8311
Fax: 65-250-3583
NEC Electronics Italiana s.r.l.
NEC Electronics (Germany) GmbH
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
NEC Electronics Hong Kong Ltd.
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP Brasil
Tel: 55-11-6462-6810
Fax: 55-11-6462-6829
J00.7
User’s Manual U14359EJ3V0UM
5
Major Revisions in This Edition (1/2)
Page
Description
Throughout
• The following products have been developed
µPD703016GJ-xxx-UEN, 703107GJ-xxx-UEN, and 70F3107GJ-UEN
• Addition of product under development
161-pin plastic FBGA package
p.33
Change of pin names in Pin Identification
p.37
Modification of description in 1.6.2 (11) Ports
p.41
Change of pin names in 2.1 (2) Non-port pins
p.57
Addition of description to 2.3 (12) (b) (ii) SDCLK (SDRAM clock output)
p.62
Change of description in 2.4 Pin I/O Circuits and Recommended Connection of Unused Pins
p.80
Addition of Note and modification of Caution 1 in 3.4.5 (3) Internal peripheral I/O area
p.83
Modification of Note in Figure 3-9 Recommended Memory Map
p.93
Change of description in 3.4.10 System wait control register (VSWC)
p.96
Addition of Note to 4.3 Memory Block Function
p.102
Modification of description in 4.5.1 Number of access clocks
p.124
Modification of description in Table 4-1 Bus Cycles in Which Wait Function Is Valid
p.138
Modification of description in 4.9 Bus Priority Order
p.154
Addition of Note to Figure 5-5 Page ROM Access Timing
p.199
Modification of Figure 5-18 CBR Refresh Timing (SDRAM)
p.201
Modification of Figure 5-19 Self-Refresh Timing (SDRAM)
p.253
Modification of Remark 1 in Table 6-1 Relationship Between Transfer Type and Transfer Object
p.294
Modification of Figure 7-14 Pipeline Operation at Interrupt Request Acknowledgement (Outline)
p.295
Addition of description to 7.8 Periods in Which Interrupts Are Not Acknowledged
p.298
Modification of description in 9.3.1 Direct mode
p.299
Modification of Caution in 9.3.2 PLL mode
p.301
Modification of Caution 3 in 9.3.4 Clock control register (CKC)
p.308
Modification of Caution 4 in 9.5.2 (3) Power-save control register (PSC)
p.317
Modification of Figure in 9.6.1 (1) Securing the time using an on-chip time base counter
p.318
Modification of Figure in 9.6.1 (2) Securing the time according to the signal level width (RESET pin
input)
p.326
Addition of Caution to 10.1.5 (1) Timer mode control registers C00 to C30 (TMCC00 to TMCC30)
pp.335, 336
Addition of description to 10.1.6 (4) Compare operation
p.335
Modification and addition in Figure 10-5 Compare Operation Example
p.339
Modification of Figure 10-8 Interval Timer Operation Timing Example
p.341
Modification of Figure 10-10 PWM Output Timing Example
p.344
Modification of Figure 10-12 Cycle Measurement Operation Timing Example
p.352
Modification of Figure 10-14 TMD0 Compare Operation Example
p.359
Modification of Caution in 11.2.3 (1) Asynchronous serial interface mode registers 0 to 2 (ASIM0 to
ASIM2)
p.394
Modification of description in 11.3.4 (1) Transfer mode
6
User’s Manual U14359EJ3V0UM
Major Revisions in This Edition (2/2)
Page
Description
p.404
Addition of description to 12.3 (2) A/D converter mode register 1 (ADM1)
p.405
Modification of Caution in 12.3 (3) A/D converter mode register 2 (ADM2)
p.451
Modification of Figure 14-10 Block Diagram of Type K
p.500
Modification of Remark in Figure 16-1 Connection Example of Adapter (FA-144GJ-UEN) for
V850E/MA1 Flash Memory Programming
p.504
Modification of description in 16.5.6 Port pins
p.508
Addition of description to 16.7.1 Outline of self-programming
p.516
Modification of Table 16-8 Flash Information
p.519
Modification of Caution 1 in 16.7.12 Flash programming mode control register (FLPMC)
The mark
shows major revised points.
User’s Manual U14359EJ3V0UM
7
INTRODUCTION
Readers
This manual is intended for users who wish to understand the functions of the
V850E/MA1 (µPD703103, 703105, 703106, 703107, 70F3107) to design application
systems using the V850E/MA1.
Purpose
The purpose of this manual is for users to gain an understanding of the hardware
functions of the VE850E/MA1.
Organization
The V850E/MA1 User’s Manual is divided into two parts: Hardware (this manual)
and Architecture (V850E1 User’s Manual Architecture). The organization of each
manual is as follows:
Hardware
Architecture
• Pin functions
• Data type
• CPU function
• Register set
• Internal peripheral functions
• Instruction format and instruction set
• Flash memory programming
• Interrupts and exceptions
• Pipeline operation
How to Read This Manual
It is assumed that the readers of this manual have general knowledge in the fields of
electrical engineering, logic circuits, and microcontrollers.
• To find the details of a register where the name is known
→Refer to APPENDIX A REGISTER INDEX.
• To find the details of a function, etc. where the name is known
→Refer to APPENDIX C INDEX.
• To understand the details of an instruction function
→Refer to the V850E1 User’s Manual Architecture.
• To understand the overall functions of the V850E/MA1
→Read this manual according to the CONTENTS.
• How to interpret the register format
→For a bit whose bit number is enclosed in brackets, its bit name is defined as a
reserved word in the device file.
8
User’s Manual U14359EJ3V0UM
Conventions
Data significance:
Higher digits on the left and lower digits on the right
Active low representation:
xxx (overscore over pin or signal name)
Memory map address:
Higher addresses on the top and lower addresses on
the bottom
Note:
Footnote for item marked with Note in the text
Caution:
Information requiring particular attention
Remark:
Supplementary information
Numeric representation:
Binary ... xxxx or xxxxB
Decimal ... xxxx
Hexadecimal ... xxxxH
Prefix indicating power of 2
(address space, memory
K (kilo): 210 = 1,024
capacity):
M (mega): 220 = 1,0242
G (giga): 230 = 1,0243
Data type:
Word ... 32 bits
Halfword ... 16 bits
Byte ... 8 bits
Related documents
The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Document related to V850E/MA1
Document Name
Document No.
V850E1 User’s Manual Architecture
U14559E
V850E/MA1 User’s Manual Hardware
This manual
µPD70F3107 Data Sheet
U14618E
µPD703106, 703107 Data Sheet
U14792E
User’s Manual U14359EJ3V0UM
9
Document related to development tools (User’s Manuals)
Document Name
Document No.
IE-V850E-MC, IE-V850E-MC-A (In-circuit emulator)
U14487E
IE-703107-MC-EM1 (Peripheral I/O board)
U14481E
CA850 (Ver. 2.30 or later)
(C compiler package)
Operation
U14568E
C Language
U14566E
Project Manager
U14569E
Assembly Language
TM
U14567E
ID850 (Ver. 2.20 or later) (Integrated debugger)
Operation Windows
RX850 (Ver. 3.13 or later) (Real-time OS)
Basics
U13430E
Installation
U13410E
Technical
U13431E
Basics
U13773E
Installation
U13774E
Technical
U13772E
RX850 Pro (Ver. 3.13) (Real-time OS)
Based
U14580E
RD850 (Ver. 3.01) (Task debugger)
U13737E
RD850 Pro (Ver. 3.01) (Task debugger)
U13916E
AZ850 (System performance analyzer)
U14410E
PG-FP3 (Flash memory programmer)
U13502E
10
User’s Manual U14359EJ3V0UM
CONTENTS
CHAPTER 1 INTRODUCTION............................................................................................................... 26
1.1
Outline ....................................................................................................................................... 26
1.2
Features..................................................................................................................................... 27
1.3
Applications .............................................................................................................................. 29
1.4
Ordering Information ............................................................................................................... 29
1.5
Pin Configuration (Top View) .................................................................................................. 30
1.6
Function Blocks........................................................................................................................ 34
1.6.1
Internal block diagram ................................................................................................................. 34
1.6.2
On-chip units ............................................................................................................................... 35
CHAPTER 2 PIN FUNCTIONS .............................................................................................................. 38
2.1
List of Pin Functions................................................................................................................ 38
2.2
Pin Status .................................................................................................................................. 45
2.3
Description of Pin Functions .................................................................................................. 46
2.4
Pin I/O Circuits and Recommended Connection of Unused Pins ....................................... 61
2.5
Pin I/O Circuits.......................................................................................................................... 63
CHAPTER 3 CPU FUNCTION ............................................................................................................... 64
3.1
Features..................................................................................................................................... 64
3.2
CPU Register Set ...................................................................................................................... 65
3.3
3.4
3.2.1
Program register set.................................................................................................................... 66
3.2.2
System register set...................................................................................................................... 67
Operating Modes ...................................................................................................................... 69
3.3.1
Operating modes......................................................................................................................... 69
3.3.2
Operating mode specification ...................................................................................................... 70
Address Space.......................................................................................................................... 71
3.4.1
CPU address space .................................................................................................................... 71
3.4.2
Image .......................................................................................................................................... 72
3.4.3
Wrap-around of CPU address space........................................................................................... 73
3.4.4
Memory map ............................................................................................................................... 74
3.4.5
Area............................................................................................................................................. 76
3.4.6
External memory expansion........................................................................................................ 81
3.4.7
Recommended use of address space ......................................................................................... 82
3.4.8
Peripheral I/O registers ............................................................................................................... 84
3.4.9
Specific registers ......................................................................................................................... 93
3.4.10
System wait control register (VSWC) .......................................................................................... 93
3.4.11
Cautions ...................................................................................................................................... 93
CHAPTER 4 BUS CONTROL FUNCTION ............................................................................................ 94
4.1
Features..................................................................................................................................... 94
User’s Manual U14359EJ3V0UM
11
4.2
Bus Control Pins....................................................................................................................... 94
4.2.1
4.3
Memory Block Function ........................................................................................................... 96
4.3.1
4.4
4.6
Chip select control function.......................................................................................................... 97
Bus Cycle Type Control Function......................................................................................... 100
4.4.1
4.5
Pin status during internal ROM, internal RAM, and peripheral I/O access .................................. 95
Bus cycle type configuration registers 0, 1 (BCT0, BCT1)......................................................... 101
Bus Access ............................................................................................................................. 102
4.5.1
Number of access clocks........................................................................................................... 102
4.5.2
Bus sizing function..................................................................................................................... 103
4.5.3
Endian control function .............................................................................................................. 104
4.5.4
Big endian method usage restrictions in NEC development tools ............................................. 105
4.5.5
Bus width ................................................................................................................................... 107
Wait Function .......................................................................................................................... 118
4.6.1
Programmable wait function ...................................................................................................... 118
4.6.2
External wait function ................................................................................................................ 123
4.6.3
Relationship between programmable wait and external wait ..................................................... 123
4.6.4
Bus cycles in which wait function is valid................................................................................... 124
4.7
Idle State Insertion Function ................................................................................................. 125
4.8
Bus Hold Function.................................................................................................................. 126
4.9
4.8.1
Function outline ......................................................................................................................... 126
4.8.2
Bus hold procedure ................................................................................................................... 127
4.8.3
Operation in power-save mode.................................................................................................. 127
4.8.4
Bus hold timing (SRAM) ............................................................................................................ 128
4.8.5
Bus hold timing (EDO DRAM) ................................................................................................... 130
4.8.6
Bus hold timing (SDRAM).......................................................................................................... 134
Bus Priority Order................................................................................................................... 138
4.10 Boundary Operation Conditions ........................................................................................... 139
4.10.1
Program space .......................................................................................................................... 139
4.10.2
Data space ................................................................................................................................ 139
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION.................................................................. 140
5.1
5.2
SRAM, External ROM, External I/O Interface ....................................................................... 140
5.1.1
Features .................................................................................................................................... 140
5.1.2
SRAM connection...................................................................................................................... 141
5.1.3
SRAM, external ROM, external I/O access................................................................................ 143
Page ROM Controller (ROMC) ............................................................................................... 149
5.2.1
5.3
12
Features .................................................................................................................................... 149
5.2.2
Page ROM connection .............................................................................................................. 150
5.2.3
On-page/off-page judgment....................................................................................................... 151
5.2.4
Page ROM configuration register (PRC).................................................................................... 153
5.2.5
Page ROM access..................................................................................................................... 154
DRAM Controller (EDO DRAM).............................................................................................. 158
5.3.1
Features .................................................................................................................................... 158
5.3.2
DRAM connection...................................................................................................................... 159
5.3.3
Address multiplex function......................................................................................................... 160
5.3.4
DRAM configuration registers 1, 3, 4, 6 (SCR1, SCR3, SCR4, SCR6) ..................................... 161
User’s Manual U14359EJ3V0UM
5.4
5.3.5
DRAM access............................................................................................................................ 164
5.3.6
Refresh control function ............................................................................................................ 169
5.3.7
Self-refresh control function ...................................................................................................... 174
DRAM Controller (SDRAM).................................................................................................... 176
5.4.1
Features .................................................................................................................................... 176
5.4.2
SDRAM connection ................................................................................................................... 176
5.4.3
Address multiplex function ........................................................................................................ 177
5.4.4
SDRAM configuration registers 1, 3, 4, 6 (SCR1, SCR3, SCR4, SCR6)................................... 179
5.4.5
SDRAM access ......................................................................................................................... 181
5.4.6
Refresh control function ............................................................................................................ 195
5.4.7
Self-refresh control function ...................................................................................................... 200
5.4.8
SDRAM initialization sequence ................................................................................................. 202
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER) .................................................................... 205
6.1
Features................................................................................................................................... 205
6.2
Configuration .......................................................................................................................... 206
6.3
Control Registers ................................................................................................................... 207
6.3.1
6.4
6.5
6.6
6.7
DMA source address registers 0 to 3 (DSA0 to DSA3) ............................................................. 207
6.3.2
DMA destination address registers 0 to 3 (DDA0 to DDA3) ...................................................... 209
6.3.3
DMA byte count registers 0 to 3 (DBC0 to DBC3)..................................................................... 211
6.3.4
DMA addressing control registers 0 to 3 (DADC0 to DADC3) ................................................... 212
6.3.5
DMA channel control registers 0 to 3 (DCHC0 to DCHC3) ....................................................... 214
6.3.6
DMA disable status register (DDIS)........................................................................................... 215
6.3.7
DMA restart register (DRST) ..................................................................................................... 215
6.3.8
DMA terminal count output control register (DTOC).................................................................. 216
6.3.9
DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3) ............................................................. 217
DMA Bus States...................................................................................................................... 220
6.4.1
Types of bus states ................................................................................................................... 220
6.4.2
DMAC bus cycle state transition................................................................................................ 222
Transfer Modes....................................................................................................................... 223
6.5.1
Single transfer mode ................................................................................................................. 223
6.5.2
Single-step transfer mode ......................................................................................................... 224
6.5.3
Block transfer mode .................................................................................................................. 225
Transfer Types........................................................................................................................ 226
6.6.1
2-cycle transfer.......................................................................................................................... 226
6.6.2
Flyby transfer............................................................................................................................. 242
Transfer Object ....................................................................................................................... 253
6.7.1
Transfer type and transfer object............................................................................................... 253
6.7.2
External bus cycles during DMA transfer .................................................................................. 254
6.8
DMA Channel Priorities ......................................................................................................... 254
6.9
Next Address Setting Function............................................................................................. 255
6.10 DMA Transfer Start Factors................................................................................................... 256
6.11 Terminal Count Output upon DMA Transfer End................................................................ 257
6.12 Forcible Interruption .............................................................................................................. 257
6.13 Forcible Termination.............................................................................................................. 258
User’s Manual U14359EJ3V0UM
13
6.14 Times Related to DMA Transfer ............................................................................................ 259
6.15 Maximum Response Time for DMA Transfer Request........................................................ 259
6.16 One-Time Transfer During Single Transfer via DMARQ0 to DMARQ3 Signals ................ 260
6.17 Cautions .................................................................................................................................. 261
6.17.1
Interrupt factors ......................................................................................................................... 261
6.18 DMA Transfer End .................................................................................................................. 261
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION ............................................... 262
7.1
Features ................................................................................................................................... 262
7.2
Non-Maskable Interrupts........................................................................................................ 265
7.3
7.4
7.2.1
Operation................................................................................................................................... 266
7.2.2
Restore ...................................................................................................................................... 268
7.2.3
Non-maskable interrupt status flag (NP).................................................................................... 269
7.2.4
Noise elimination ....................................................................................................................... 269
7.2.5
Edge detection function ............................................................................................................. 269
Maskable Interrupts................................................................................................................ 270
7.3.1
Operation................................................................................................................................... 270
7.3.2
Restore ...................................................................................................................................... 272
7.3.3
Priorities of maskable interrupts ................................................................................................ 273
7.3.4
Interrupt control register (xxICn) ................................................................................................ 277
7.3.5
Interrupt mask registers 0 to 3 (IMR0 to IMR3).......................................................................... 280
7.3.6
In-service priority register (ISPR)............................................................................................... 281
7.3.7
Maskable interrupt status flag (ID)............................................................................................. 281
7.3.8
Noise elimination ....................................................................................................................... 282
7.3.9
Interrupt trigger mode selection ................................................................................................. 282
Software Exception ................................................................................................................ 285
7.4.1
7.5
Operation................................................................................................................................... 285
7.4.2
Restore ...................................................................................................................................... 286
7.4.3
Exception status flag (EP) ......................................................................................................... 287
Exception Trap........................................................................................................................ 288
7.5.1
Illegal opcode definition ............................................................................................................. 288
7.5.2
Debug trap................................................................................................................................. 290
7.6
Multiple Interrupt Servicing Control ..................................................................................... 292
7.7
Interrupt Latency Time ........................................................................................................... 294
7.8
Periods in Which Interrupts Are Not Acknowledged .......................................................... 295
CHAPTER 8 PRESCALER UNIT (PRS) ............................................................................................ 296
CHAPTER 9 CLOCK GENERATION FUNCTION ............................................................................. 297
14
9.1
Features ................................................................................................................................... 297
9.2
Configuration .......................................................................................................................... 297
9.3
Input Clock Selection ............................................................................................................. 298
9.3.1
Direct mode ............................................................................................................................... 298
9.3.2
PLL mode .................................................................................................................................. 299
User’s Manual U14359EJ3V0UM
9.3.3
Peripheral command register (PHCMD).................................................................................... 299
9.3.4
Clock control register (CKC)...................................................................................................... 300
9.3.5
Peripheral status register (PHS)................................................................................................ 302
9.4
PLL Lockup ............................................................................................................................. 303
9.5
Power-Save Control ............................................................................................................... 304
9.5.1
9.6
Overview ................................................................................................................................... 304
9.5.2
Control registers ........................................................................................................................ 306
9.5.3
HALT mode ............................................................................................................................... 309
9.5.4
IDLE mode ................................................................................................................................ 311
9.5.5
Software STOP mode ............................................................................................................... 314
Securing Oscillation Stabilization Time............................................................................... 317
9.6.1
Oscillation stabilization time security specification .................................................................... 317
9.6.2
Time base counter (TBC) .......................................................................................................... 319
CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT) ................................... 320
10.1 Timer C .................................................................................................................................... 320
10.1.1
Features (timer C) ..................................................................................................................... 320
10.1.2
Function overview (timer C) ...................................................................................................... 320
10.1.3
Basic configuration of timer C.................................................................................................... 321
10.1.4
Timer C ..................................................................................................................................... 322
10.1.5
Timer C control registers ........................................................................................................... 326
10.1.6
Timer C operation...................................................................................................................... 331
10.1.7
Application examples (timer C).................................................................................................. 338
10.1.8
Cautions (timer C) ..................................................................................................................... 345
10.2 Timer D .................................................................................................................................... 346
10.2.1
Features (timer D) ..................................................................................................................... 346
10.2.2
Function overview (timer D) ...................................................................................................... 346
10.2.3
Basic configuration of timer D.................................................................................................... 346
10.2.4
Timer D ..................................................................................................................................... 347
10.2.5
Timer D control registers ........................................................................................................... 350
10.2.6
Timer D operation...................................................................................................................... 352
10.2.7
Application examples (timer D).................................................................................................. 354
10.2.8
Cautions (timer D) ..................................................................................................................... 354
CHAPTER 11 SERIAL INTERFACE FUNCTION.............................................................................. 355
11.1 Features................................................................................................................................... 355
11.1.1
Switching between UART and CSI modes ................................................................................ 355
11.2 Asynchronous Serial Interfaces 0 to 2 (UART0 to UART2)................................................ 356
11.2.1
Features .................................................................................................................................... 356
11.2.2
Configuration ............................................................................................................................. 357
11.2.3
Control registers ........................................................................................................................ 359
11.2.4
Interrupt requests ...................................................................................................................... 366
11.2.5
Operation .................................................................................................................................. 367
11.2.6
Dedicated baud rate generators 0 to 2 (BRG0 to BRG2) .......................................................... 377
11.2.7
Cautions .................................................................................................................................... 384
11.3 Clocked Serial Interfaces 0 to 2 (CSI0 to CSI2) ................................................................... 385
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15
11.3.1
Features .................................................................................................................................... 385
11.3.2
Configuration ............................................................................................................................. 385
11.3.3
Control registers ........................................................................................................................ 387
11.3.4
Operation................................................................................................................................... 394
11.3.5
Output pins ................................................................................................................................ 397
11.3.6
System configuration example................................................................................................... 398
CHAPTER 12 A/D CONVERTER......................................................................................................... 399
12.1 Features ................................................................................................................................... 399
12.2 Configuration .......................................................................................................................... 399
12.3 Control Registers.................................................................................................................... 402
12.4 A/D Converter Operation........................................................................................................ 408
12.4.1
Basic operation of A/D converter ............................................................................................... 408
12.4.2
Operation mode and trigger mode............................................................................................. 409
12.5 Operation in A/D Trigger Mode ............................................................................................. 414
12.5.1
Select mode operation............................................................................................................... 414
12.5.2
Scan mode operations............................................................................................................... 416
12.6 Operation in Timer Trigger Mode.......................................................................................... 417
12.6.1
Select mode operation............................................................................................................... 418
12.6.2
Scan mode operation ................................................................................................................ 422
12.7 Operation in External Trigger Mode ..................................................................................... 426
12.7.1
Select mode operations (external trigger select) ....................................................................... 426
12.7.2
Scan mode operation (external trigger scan)............................................................................. 428
12.8 Notes on Operation ................................................................................................................ 430
12.8.1
Stopping conversion operation .................................................................................................. 430
12.8.2
External/timer trigger interval..................................................................................................... 430
12.8.3
Operation in standby mode........................................................................................................ 430
12.8.4
Compare match interrupt in timer trigger mode ......................................................................... 431
CHAPTER 13 PWM UNIT...................................................................................................................... 432
13.1 Features ................................................................................................................................... 432
13.2 Block Diagram......................................................................................................................... 432
13.3 Control Register...................................................................................................................... 433
13.4 Operation................................................................................................................................. 435
13.4.1
Basic operations ........................................................................................................................ 435
13.4.2
Repetition frequency.................................................................................................................. 438
13.5 Cautions .................................................................................................................................. 438
CHAPTER 14 PORT FUNCTIONS...................................................................................................... 439
14.1 Features ................................................................................................................................... 439
14.2 Port Configuration .................................................................................................................. 440
14.3 Port Pin Functions.................................................................................................................. 456
16
14.3.1
Port 0 ......................................................................................................................................... 456
14.3.2
Port 1 ......................................................................................................................................... 459
User’s Manual U14359EJ3V0UM
14.3.3
Port 2......................................................................................................................................... 461
14.3.4
Port 3......................................................................................................................................... 465
14.3.5
Port 4......................................................................................................................................... 468
14.3.6
Port 5......................................................................................................................................... 471
14.3.7
Port 7......................................................................................................................................... 473
14.3.8
Port AL ...................................................................................................................................... 474
14.3.9
Port AH...................................................................................................................................... 476
14.3.10 Port DL ...................................................................................................................................... 478
14.3.11 Port CS...................................................................................................................................... 480
14.3.12 Port CT...................................................................................................................................... 484
14.3.13 Port CM ..................................................................................................................................... 486
14.3.14 Port CD ..................................................................................................................................... 489
14.3.15 Port BD...................................................................................................................................... 492
CHAPTER 15 RESET FUNCTIONS ................................................................................................... 494
15.1 Features................................................................................................................................... 494
15.2 Pin Functions.......................................................................................................................... 494
15.3 Initialization............................................................................................................................. 496
CHAPTER 16
FLASH MEMORY (µPD70F3107) ............................................................................. 499
16.1 Features................................................................................................................................... 499
16.2 Writing with Flash Programmer ............................................................................................ 499
16.3 Programming Environment ................................................................................................... 501
16.4 Communication Mode............................................................................................................ 501
16.5 Pin Connection ....................................................................................................................... 502
16.5.1
MODE2/VPP pin ......................................................................................................................... 502
16.5.2
Serial interface pin..................................................................................................................... 502
16.5.3
RESET pin ................................................................................................................................ 504
16.5.4
NMI pin...................................................................................................................................... 504
16.5.5
MODE0 to MODE2 pins ............................................................................................................ 504
16.5.6
Port pins .................................................................................................................................... 504
16.5.7
Other signal pins ....................................................................................................................... 504
16.5.8
Power supply............................................................................................................................. 504
16.6 Programming Method ............................................................................................................ 505
16.6.1
Flash memory control................................................................................................................ 505
16.6.2
Flash memory programming mode............................................................................................ 506
16.6.3
Selection of communication mode............................................................................................. 506
16.6.4
Communication commands....................................................................................................... 507
16.7 Flash Memory Programming by Self-Programming ........................................................... 508
16.7.1
Outline of self-programming ...................................................................................................... 508
16.7.2
Self-programming function ........................................................................................................ 509
16.7.3
Outline of self-programming interface ....................................................................................... 509
16.7.4
Hardware environment .............................................................................................................. 510
16.7.5
Software environment ............................................................................................................... 512
16.7.6
Self-programming function number ........................................................................................... 513
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17
16.7.7
Calling parameters .................................................................................................................... 514
16.7.8
Contents of RAM parameters .................................................................................................... 515
16.7.9
Errors during self-programming ................................................................................................. 516
16.7.10 Flash information ....................................................................................................................... 516
16.7.11 Area number.............................................................................................................................. 517
16.7.12 Flash programming mode control register (FLPMC).................................................................. 518
16.7.13 Calling device internal processing ............................................................................................. 520
16.7.14 Erasing flash memory flow......................................................................................................... 523
16.7.15 Successive writing flow.............................................................................................................. 524
16.7.16 Internal verify flow...................................................................................................................... 525
16.7.17 Acquiring flash information flow ................................................................................................. 526
16.7.18 Self-programming library ........................................................................................................... 527
16.8 How to Distinguish Flash Memory and Mask ROM Versions............................................. 529
APPENDIX A REGISTER INDEX........................................................................................................ 530
APPENDIX B INSTRUCTION SET LIST............................................................................................ 538
B.1
Convention .............................................................................................................................. 538
B.2
Instruction Set (In Alphabetical Order)................................................................................. 541
APPENDIX C INDEX ............................................................................................................................ 548
18
User’s Manual U14359EJ3V0UM
LIST OF FIGURES (1/5)
Figure No.
Title
Page
3-1
Program Counter (PC) ................................................................................................................................... 66
3-2
Interrupt Source Register (ECR) .................................................................................................................... 67
3-3
Program Status Word (PSW)......................................................................................................................... 68
3-4
CPU Address Space ...................................................................................................................................... 71
3-5
Images on Address Space............................................................................................................................. 72
3-6
Memory Map (µPD703103, 703105).............................................................................................................. 74
3-7
Memory Map (µPD703106, 703107, 70F3107).............................................................................................. 75
3-8
Internal ROM Area in Single-Chip Mode 1..................................................................................................... 78
3-9
Recommended Memory Map......................................................................................................................... 83
4-1
Example When CSC0 Register Is Set to 0703H ............................................................................................ 99
4-2
Big Endian Addresses Within Word ............................................................................................................. 105
4-3
Little Endian Addresses Within Word........................................................................................................... 105
4-4
Timing Example of Access to SRAM, External ROM, and External I/O (Read → Write) ............................. 122
4-5
Example of Wait Insertion ............................................................................................................................ 123
5-1
Examples of Connection to SRAM............................................................................................................... 141
5-2
SRAM, External ROM, External I/O Access Timing ..................................................................................... 143
5-3
Examples of Connection to Page ROM ....................................................................................................... 150
5-4
On-Page/Off-Page Judgment During Page ROM Connection ..................................................................... 151
5-5
Page ROM Access Timing........................................................................................................................... 154
5-6
Examples of Connection to DRAM............................................................................................................... 159
5-7
Row Address/Column Address Output ........................................................................................................ 160
5-8
EDO DRAM Access Timing ......................................................................................................................... 164
5-9
CBR Refresh Timing .................................................................................................................................... 173
5-10
Self-Refresh Timing (DRAM) ....................................................................................................................... 175
5-11
Example of Connection to SDRAM .............................................................................................................. 176
5-12
Row Address/Column Address Output ........................................................................................................ 177
5-13
State Transition of SDRAM Access ............................................................................................................. 181
5-14
SDRAM Single Read Cycle ......................................................................................................................... 183
5-15
SDRAM Single Write Cycle.......................................................................................................................... 187
5-16
SDRAM Access Timing................................................................................................................................ 191
5-17
Auto-Refresh Cycle...................................................................................................................................... 198
5-18
CBR Refresh Timing (SDRAM).................................................................................................................... 199
5-19
Self-Refresh Timing (SDRAM) ..................................................................................................................... 201
5-20
SDRAM Mode Register Setting Cycle.......................................................................................................... 203
5-21
SDRAM Register Write Operation Timing.................................................................................................... 204
User’s Manual U14359EJ3V0UM
19
LIST OF FIGURES (2/5)
Figure No.
Title
Page
6-1
DMAC Bus Cycle State Transition ............................................................................................................... 222
6-2
Single Transfer Example 1 ........................................................................................................................... 223
6-3
Single Transfer Example 2 ........................................................................................................................... 223
6-4
Single-Step Transfer Example 1 .................................................................................................................. 224
6-5
Single-Step Transfer Example 2 .................................................................................................................. 224
6-6
Block Transfer Example ............................................................................................................................... 225
6-7
Timing of Access to SRAM, External ROM, and External I/O During 2-Cycle DMA Transfer ...................... 227
6-8
Timing of 2-Cycle DMA Transfer (External I/O → SRAM) ............................................................................ 229
6-9
Timing of 2-Cycle DMA Transfer (SRAM → EDO DRAM)............................................................................ 230
6-10
Timing of 2-Cycle DMA Transfer (EDO DRAM → SRAM)............................................................................ 233
6-11
Timing of 2-Cycle DMA Transfer (SRAM → SDRAM) .................................................................................. 236
6-12
Timing of 2-Cycle DMA Transfer (SDRAM → SRAM) .................................................................................. 239
6-13
Circuit Example When Flyby Transfer Is Performed Between External I/O and SRAM ............................... 242
6-14
Timing of Flyby Transfer (DRAM → External I/O) ........................................................................................ 243
6-15
Timing of Access to SRAM, External ROM, and External I/O During DMA Flyby Transfer .......................... 246
6-16
Page ROM Access Timing During DMA Flyby Transfer............................................................................... 248
6-17
DRAM Access Timing During DMA Flyby Transfer ...................................................................................... 249
6-18
Buffer Register Configuration ....................................................................................................................... 255
6-19
Terminal Count Signal (TCn) Timing Example ............................................................................................. 257
6-20
Example of Forcible Interrupt of DMA Transfer ............................................................................................ 257
6-21
Example of Forcible Termination of DMA Transfer ...................................................................................... 258
6-22
Time to Perform Single Transfer One Time.................................................................................................. 260
7-1
Servicing Configuration of Non-Maskable Interrupt...................................................................................... 266
7-2
Acknowledging Non-Maskable Interrupt Request ........................................................................................ 267
7-3
RETI Instruction Processing......................................................................................................................... 268
7-4
Maskable Interrupt Servicing........................................................................................................................ 271
7-5
RETI Instruction Processing......................................................................................................................... 272
7-6
Example of Processing in Which Another Interrupt Request Is Issued While an Interrupt Is
Being Serviced ............................................................................................................................................. 274
7-7
Example of Servicing Interrupt Requests Simultaneously Generated .......................................................... 276
7-8
Software Exception Processing.................................................................................................................... 285
7-9
RETI Instruction Processing......................................................................................................................... 286
7-10
Exception Trap Processing .......................................................................................................................... 289
7-11
Restore Processing from Exception Trap..................................................................................................... 289
7-12
Debug Trap Processing ............................................................................................................................... 290
7-13
Restore Processing from Debug Trap.......................................................................................................... 291
7-14
Pipeline Operation at Interrupt Request Acknowledgement (Outline) .......................................................... 294
20
User’s Manual U14359EJ3V0UM
LIST OF FIGURES (3/5)
Figure No.
Title
Page
9-1
Power-Save Mode State Transition Diagram............................................................................................... 305
10-1
Basic Operation of Timer C.......................................................................................................................... 331
10-2
Operation After Overflow (When OSTn = 1) ................................................................................................ 332
10-3
Capture Operation Example ........................................................................................................................ 333
10-4
TMC1 Capture Operation Example (When Both Edges Are Specified) ....................................................... 334
10-5
Compare Operation Example ...................................................................................................................... 335
10-6
TMC1 Compare Operation Example (Set/Reset Output Mode) ................................................................... 337
10-7
Contents of Register Settings When Timer C Is Used as Interval Timer...................................................... 338
10-8
Interval Timer Operation Timing Example.................................................................................................... 339
10-9
Contents of Register Settings When Timer C Is Used for PWM Output....................................................... 340
10-10 PWM Output Timing Example...................................................................................................................... 341
10-11 Contents of Register Settings When Timer C Is Used for Cycle Measurement ........................................... 343
10-12 Cycle Measurement Operation Timing Example.......................................................................................... 344
10-13 Example of Timing During TMDn Operation ................................................................................................ 349
10-14 TMD0 Compare Operation Example............................................................................................................ 352
11-1
Asynchronous Serial Interface Block Diagram ............................................................................................. 358
11-2
Asynchronous Serial Interface Transmit/Receive Data Format ................................................................... 367
11-3
Asynchronous Serial Interface Transmission Completion Interrupt Timing.................................................. 369
11-4
Continuous Transmission Starting Procedure.............................................................................................. 370
11-5
Continuous Transmission Ending Procedure............................................................................................... 371
11-6
Asynchronous Serial Interface Reception Completion Interrupt Timing ....................................................... 373
11-7
When Reception Error Interrupt Is Separated from INTSRn Interrupt (ISRMn Bit = 0) ................................ 374
11-8
When Reception Error Interrupt Is Included in INTSRn Interrupt (ISRMn Bit = 1)........................................ 374
11-9
Noise Filter Circuit........................................................................................................................................ 376
11-10 Timing of RXDn Signal Judged as Noise ..................................................................................................... 376
11-11 Baud Rate Generator Configuration............................................................................................................. 377
11-12 Allowable Baud Rate Range During Reception ........................................................................................... 382
11-13 Transfer Rate During Continuous Transmission .......................................................................................... 384
11-14 Clocked Serial Interface Block Diagram....................................................................................................... 386
11-15 Transfer Timing............................................................................................................................................ 395
11-16 Clock Timing ................................................................................................................................................ 396
11-17 System Configuration Example of CSI......................................................................................................... 398
12-1
Block Diagram of A/D Converter .................................................................................................................. 401
12-2
Relationship Between Analog Input Voltage and A/D Conversion Results .................................................. 407
12-3
Select Mode Operation Timing: 1-Buffer Mode (ANI1)................................................................................. 411
User’s Manual U14359EJ3V0UM
21
LIST OF FIGURES (4/5)
Figure No.
Title
Page
12-4
Select Mode Operation Timing: 4-Buffer Mode (ANI6)................................................................................. 412
12-5
Scan Mode Operation Timing: 4-Channel Scan (ANI0 to ANI3)................................................................... 413
12-6
Example of 1-Buffer Mode Operation (A/D Trigger Select: 1 Buffer)............................................................ 414
12-7
Example of 4-Buffer Mode Operation (A/D Trigger Select: 4 Buffers) .......................................................... 415
12-8
Example of Scan Mode Operation (A/D Trigger Scan)................................................................................. 416
12-9
Example of 1-Trigger Mode Operation (Timer Trigger Select: 1 Buffer 1 Trigger)........................................ 418
12-10 Example of 4-Trigger Mode Operation (Timer Trigger Select: 1 Buffer 4 Triggers)...................................... 419
12-11 Example of 1-Trigger Mode Operation (Timer Trigger Select: 4 Buffers 1 Trigger)...................................... 420
12-12 Example of 4-Trigger Mode Operation (Timer Trigger Select: 4 Buffers 4 Triggers) .................................... 421
12-13 Example of 1-Trigger Mode Operation (Timer Trigger Scan: 1 Trigger)....................................................... 423
12-14 Example of 4-Trigger Mode Operation (Timer Trigger Scan: 4 Triggers) ..................................................... 425
12-15 Example of 1-Buffer Mode Operation (External Trigger Select: 1 Buffer)..................................................... 426
12-16 Example of 4-Buffer Mode Operation (External Trigger Select: 4 Buffers)................................................... 427
12-17 Example of Scan Mode Operation (External Trigger Scan) ......................................................................... 429
13-1
PWM Basic Operation Timing ...................................................................................................................... 436
13-2
Timing for Write Operation to PWMBn Register........................................................................................... 436
13-3
Timing When PWMBn Register Is Set to 00H .............................................................................................. 437
13-4
Timing When PWMBn Register Is Set to FFH.............................................................................................. 437
14-1
Block Diagram of Type A.............................................................................................................................. 444
14-2
Block Diagram of Type B.............................................................................................................................. 445
14-3
Block Diagram of Type C ............................................................................................................................. 445
14-4
Block Diagram of Type D ............................................................................................................................. 446
14-5
Block Diagram of Type E.............................................................................................................................. 447
14-6
Block Diagram of Type F.............................................................................................................................. 447
14-7
Block Diagram of Type H ............................................................................................................................. 448
14-8
Block Diagram of Type I ............................................................................................................................... 449
14-9
Block Diagram of Type J .............................................................................................................................. 450
14-10 Block Diagram of Type K.............................................................................................................................. 451
14-11 Block Diagram of Type L .............................................................................................................................. 452
14-12 Block Diagram of Type M ............................................................................................................................. 453
14-13 Block Diagram of Type N ............................................................................................................................. 454
14-14 Block Diagram of Type O ............................................................................................................................. 455
16-1
Connection Example of Adapter (FA-144GJ-UEN) for V850E/MA1 Flash Memory Programming ............... 500
16-2
Outline of Self-Programming ........................................................................................................................ 508
16-3
Outline of Self-Programming Interface ......................................................................................................... 510
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LIST OF FIGURES (5/5)
Figure No.
Title
Page
16-4
Example of Self-Programming Circuit Configuration.................................................................................... 510
16-5
Timing to Apply Voltage to VPP Pin .............................................................................................................. 511
16-6
Area Configuration ....................................................................................................................................... 517
16-7
Erasing Flash Memory Flow ........................................................................................................................ 523
16-8
Successive Writing Flow .............................................................................................................................. 524
16-9
Internal Verify Flow ...................................................................................................................................... 525
16-10 Acquiring Flash Information Flow................................................................................................................. 526
16-11 Functional Outline of Self-Programming Library .......................................................................................... 527
16-12 Outline of Self-Programming Library Configuration...................................................................................... 528
User’s Manual U14359EJ3V0UM
23
LIST OF TABLES (1/2)
Table No.
Title
Page
3-1
Program Registers ......................................................................................................................................... 66
3-2
System Register Numbers ............................................................................................................................. 67
3-3
Interrupt/Exception Table ............................................................................................................................... 77
4-1
Bus Cycles in Which Wait Function Is Valid ................................................................................................. 124
4-2
Bus Priority Order......................................................................................................................................... 138
5-1
Example of DRAM and Address Multiplex Width ......................................................................................... 160
5-2
Interval Factor Setting Examples ................................................................................................................. 171
5-3
Example of Interval Factor Settings ............................................................................................................. 197
6-1
Relationship Between Transfer Type and Transfer Object........................................................................... 253
6-2
External Bus Cycles During DMA Transfer .................................................................................................. 254
6-3
Number of Minimum Execution Clocks in DMA Cycle.................................................................................. 259
7-1
Interrupt/Exception Source List .................................................................................................................... 263
9-1
Clock Generator Operation Using Power-Save Control ............................................................................... 305
9-2
Operation Status in HALT Mode .................................................................................................................. 309
9-3
Operation After HALT Mode Is Released by Interrupt Request.................................................................... 310
9-4
Operation Status in IDLE Mode.................................................................................................................... 312
9-5
Operation After IDLE Mode Is Released by Interrupt Request..................................................................... 313
9-6
Operation Status in Software STOP Mode................................................................................................... 315
9-7
Operation After Software STOP Mode Is Released by Interrupt Request.................................................... 316
9-8
Counting Time Examples (φ = 10 × fXX)........................................................................................................ 319
10-1
Timer C Configuration .................................................................................................................................. 321
10-2
TO0n Output Control.................................................................................................................................... 337
10-3
Timer D Configuration .................................................................................................................................. 346
11-1
Generated Interrupts and Default Priorities .................................................................................................. 366
11-2
Transmission Status and Whether or Not Writing Is Enabled....................................................................... 369
11-3
Reception Error Causes ............................................................................................................................... 373
11-4
Baud Rate Generator Setting Data .............................................................................................................. 381
11-5
Maximum and Minimum Allowable Baud Rate Error .................................................................................... 383
15-1
Operation Status of Each Pin During Reset ................................................................................................. 494
15-2
Initial Value of CPU, Internal RAM, and On-Chip Peripheral I/O After Reset ............................................... 496
24
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LIST OF TABLES (2/2)
Table No.
Title
Page
16-1
List of Communication Modes...................................................................................................................... 506
16-2
Function List ................................................................................................................................................ 509
16-3
Software Environmental Conditions ............................................................................................................. 512
16-4
Self-Programming Function Number............................................................................................................ 513
16-5
Calling Parameters ...................................................................................................................................... 514
16-6
Description of RAM Parameter .................................................................................................................... 515
16-7
Errors During Self-Programming.................................................................................................................. 516
16-8
Flash Information ......................................................................................................................................... 516
User’s Manual U14359EJ3V0UM
25
CHAPTER 1 INTRODUCTION
The V850E/MA1 is a product of NEC’s single-chip microcontroller “V850 FamilyTM”. This chapter gives a simple
outline of the V850E/MA1.
1.1
Outline
The V850E/MA1 is a 32-bit single-chip microcontroller that integrates the V850E1 CPU, which is a 32-bit RISCtype CPU core for ASIC, newly developed as the CPU core central to system LSI for the current age of system-onchip. This device incorporates ROM, RAM, and various peripheral functions such as memory controllers, a DMA
controller, real-time pulse unit, serial interfaces, and an A/D converter for realizing high-capacity data processing and
sophisticated real-time control.
(1) V850E1 CPU
The V850E1 CPU is a CPU core that enhances the external bus interface performance of the V850 CPU,
which is the CPU core integrated in the V850 Family, and has added instructions supporting high-level
languages,
such as C-language switch statement processing, table lookup branching, stack frame
creation/deletion, and data conversion. This enhances the performance of both data processing and control.
It is possible to use the software resources of the V850 CPU integrated system since the instruction codes of
the V850E1 are upwardly compatible at the object code level with those of the V850 CPU.
(2) External memory interface function
The V850E/MA1 features various on-chip external memory interfaces including separately configured
address (26 bits) and data (16 bits) buses, and SDRAM and ROM interfaces, as well as on-chip memory
controllers that can be directly linked to EDO DRAM, page ROM, etc., thereby raising system performance
and reducing the number of parts needed for application systems.
Also, through the DMA controller, CPU internal calculations and data transfers can be performed
simultaneously with transfers to and from the external memory, so it is possible to process large volumes of
image data or voice data, etc., and through high-speed execution of instructions using internal ROM and
RAM, motor control, communications control and other real-time control tasks can be realized simultaneously.
(3) On-chip flash memory (µPD70F3107)
The on-chip flash memory version (µPD70F3107) has on-chip flash memory, which is capable of high-speed
access, and since it is possible to rewrite a program with the V850E/MA1 mounted as is in the application
system, system development time can be reduced and system maintainability after shipping can be markedly
improved.
(4) A full range of middleware and development environment products
The V850E/MA1 can execute middleware such as JPEG, JBIG, and MH/MR/MMR at high speed. Also,
middleware that enables speech recognition, voice synthesis, and other such processing is available, and by
including these middleware programs, a multimedia system can be easily realized.
A development environment system that includes an optimized C compiler, debugger, in-circuit emulator,
simulator, system performance analyzer, and other elements is also available.
26
User’s Manual U14359EJ3V0UM
CHAPTER 1 INTRODUCTION
1.2
Features
{ Number of instructions:
83
{ Minimum instruction execution time:
20 ns (at internal 50 MHz operation)
{ General-purpose registers:
32 bits × 32
{ Instruction set:
V850E1 CPU
Signed multiplication (16 bits × 16 bits → 32 bits or 32 bits × 32 bits →
64 bits): 1 to 2 clocks
Saturated operation instructions (with overflow/underflow detection
function)
32-bit shift instructions: 1 clock
Bit manipulation instructions
Load/store instructions with long/short format
Signed load instructions
{ Memory space:
256 MB linear address space (common program/data use)
Chip select output function: 8 spaces
Memory block division function: 2, 4, 8 MB/block
Programmable wait function
Idle state insertion function
{ External bus interface:
16-bit data bus (address/data separated)
16-/8-bit bus sizing function
Bus hold function
External wait function
Address setup wait function
Endian control function
{ Internal memory
{ Interrupts/exceptions:
Part Number
Internal ROM
Internal RAM
µPD703103
None
4 KB
µPD703105
128 KB (Mask ROM)
4 KB
µPD703106
128 KB (Mask ROM)
10 KB
µPD703107
256 KB (Mask ROM)
10 KB
µPD70F3107
256 KB (Flash memory)
10 KB
External interrupts: 25 (including NMI)
Internal interrupts: 33 sources
Exceptions:
1 source
Eight levels of priorities can be set.
{ Memory access controller
DRAM controller (compatible with EDO DRAM and SDRAM)
Page ROM controller
User’s Manual U14359EJ3V0UM
27
CHAPTER 1 INTRODUCTION
{ DMA controller:
4 channels
Transfer unit: 8 bits/16 bits
Maximum transfer count: 65,536 (216)
Transfer type: Flyby (1-cycle)/2-cycle
Transfer mode: Single/Single step/Block
Transfer target: Memory ↔ memory, memory ↔ I/O
Transfer request: External request/On-chip peripheral I/O/ Software
DMA transfer terminate (terminal count) output signal
Next address setting function
{ I/O lines:
Input ports: 9
I/O ports:
{ Real-time pulse unit:
106
16-bit timer/event counter: 4 channels
16-bit timers: 4
16-bit capture/compare registers: 8
16-bit interval timer: 4 channels
{ Serial interfaces (SIO):
Asynchronous serial interface (UART)
Clocked serial interface (CSI)
CSI/UART: 2 channels
UART: 1 channel
CSI: 1 channel
{ A/D converter:
10-bit resolution A/D converter: 8 channels
{ PWM (Pulse Width Modulation):
8-/9-/10-/12-bit resolution PWM: 2 channels
{ Clock generator:
A ×10 function through a PLL clock synthesizer.
Divide-by-two function through an external clock input.
{ Power-save function:
HALT/IDLE/software STOP mode
{ Package:
144-pin plastic LQFP (fine pitch) (20 × 20)
161-pin plastic FBGA (13 × 13)
{ CMOS technology:
28
All static circuits
User’s Manual U14359EJ3V0UM
CHAPTER 1 INTRODUCTION
1.3
Applications
Ink-jet printers, facsimiles, digital still cameras, DVD players, video printers, PPC, information equipment, etc.
1.4
Ordering Information
Part Number
Package
Note
µPD703103GJ-UEN
144-pin plastic LQFP (fine pitch) (20 × 20)
µPD703105GJ-×××-UEN
Note
144-pin plastic LQFP (fine pitch) (20 × 20)
Internal ROM
Internal RAM
None
4 KB
Mask ROM
4 KB
(128 KB)
µPD703106GJ-×××-UEN
144-pin plastic LQFP (fine pitch) (20 × 20)
Mask ROM
10 KB
(128 KB)
µPD703107GJ-×××-UEN
144-pin plastic LQFP (fine pitch) (20 × 20)
Mask ROM
10 KB
(256 KB)
µPD70F3107GJ-UEN
144-pin plastic LQFP (fine pitch) (20 × 20)
Flash memory
10 KB
(256 KB)
Note
µPD703106F1-×××-EN4
161-pin plastic FBGA (13 × 13)
Mask ROM
10 KB
(128 KB)
Note
µPD703107F1-×××-EN4
161-pin plastic FBGA (13 × 13)
Mask ROM
10 KB
(256 KB)
Note
µPD70F3107F1-EN4
161-pin plastic FBGA (13 × 13)
Flash memory
10 KB
(256 KB)
Note Under development
Remark
××× indicates ROM code suffix.
User’s Manual U14359EJ3V0UM
29
CHAPTER 1 INTRODUCTION
1.5
Pin Configuration (Top View)
• 144-pin plastic LQFP (fine pitch) (20 × 20)
µPD703103GJ-UEN
µPD703105GJ-×××-UEN
µPD703106GJ-×××-UEN
µPD703107GJ-×××-UEN
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
PDL15/D15
PAL0/A0
PAL1/A1
PAL2/A2
PAL3/A3
PAL4/A4
PAL5/A5
PAL6/A6
PAL7/A7
VSS
VDD
PAL8/A8
PAL9/A9
PAL10/A10
PAL11/A11
PAL12/A12
PAL13/A13
PAL14/A14
PAL15/A15
VSS
VDD
PAH0/A16
PAH1/A17
PAH2/A18
PAH3/A19
PAH4/A20
PAH5/A21
PAH6/A22
PAH7/A23
PAH8/A24
PAH9/A25
VSS
VDD
PCD0/SDCKE
PCD1/SDCLK
PCD2/LBE/SDCAS
µPD70F3107GJ-UEN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
VDD
VSS
TC3/INTP113/P27
TC2/INTP112/P26
TC1/INTP111/P25
TC0/INTP110/P24
TO02/P23
INTP021/P22
TI020/INTP020/P21
NMI/P20
VDD
VSS
ADTRG/INTP123/P37
INTP122/P36
INTP121/P35
RXD2/INTP120/P34
TXD2/INTP133/P33
SCK2/INTP132/P32
SI2/INTP131/P31
SO2/INTP130/P30
MODE1
MODE0
RESET
CKSEL
CVDD
X2
X1
CVSS
SCK1/P45
RXD1/SI1/P44
TXD1/SO1/P43
SCK0/P42
RXD0/SI0/P41
TXD0/SO0/P40
AVDD/AVREF
AVSS
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
D14/PDL14
D13/PDL13
D12/PDL12
D11/PDL11
D10/PDL10
D9/PDL9
D8/PDL8
VDD
VSS
D7/PDL7
D6/PDL6
D5/PDL5
D4/PDL4
D3/PDL3
D2/PDL2
D1/PDL1
D0/PDL0
MODE2 (VPP/MODE2)
DMARQ3/INTP103/P07
DMARQ2/INTP102/P06
DMARQ1/INTP101/P05
DMARQ0/INTP100/P04
TO00/P03
INTP001/P02
TI000/INTP000/P01
PWM0/P00
VDD
VSS
DMAAK3/PBD3
DMAAK2/PBD2
DMAAK1/PBD1
DMAAK0/PBD0
TO01/P13
INTP011/P12
TI010/INTP010/P11
PWM1/P10
Remark
30
Items in parentheses are pin names in the µPD70F3107.
User’s Manual U14359EJ3V0UM
PCD3/UBE/SDRAS
PCS0/CS0
PCS1/CS1/RAS1
PCS2/CS2/IOWR
PCS3/CS3/RAS3
PCS4/CS4/RAS4
PCS5/CS5/IORD
PCS6/CS6/RAS6
PCS7/CS7
VSS
VDD
PCT0/LCAS/LWR/LDQM
PCT1/UCAS/UWR/UDQM
PCT4/RD
PCT5/WE
PCT6/OE
PCT7/BCYST
PCM0/WAIT
PCM1/CLKOUT/BUSCLK
PCM2/HLDAK
PCM3/HLDRQ
PCM4/REFRQ
PCM5/SELFREF
P50/INTP030/TI030
P51/INTP031
P52/TO03
VSS
VDD
P70/ANI0
P71/ANI1
P72/ANI2
P73/ANI3
P74/ANI4
P75/ANI5
P76/ANI6
P77/ANI7
CHAPTER 1 INTRODUCTION
• 161-pin plastic FBGA (13 × 13)
µPD703106F1-×××-EN4
µPD703107F1-×××-EN4
µPD70F3107F1-EN4
Top View
Bottom View
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A BCDE FGH J K LMNP
PNML K J HGF EDCB A
Index mark
Index mark
(1/2)
Pin
Number
Pin Name
A1
–
Pin
Number
Pin Name
Pin
Number
B7
VSS
C13
Pin Name
D9/PDL9
A2
D15/PDL15
B8
A13/PAL13
C14
A3
A2/PAL2
B9
A8/PAL8
D1
VSS
A4
A5/PAL5
B10
VSS
D2
D10/PDL10
B11
A4/PAL4
D3
D14/PDL14
A5
–
–
A6
A9/PAL9
B12
A0/PAL0
D4
A3/PAL3
A7
A12/PAL12
B13
D12/PDL12
D5
A6/PAL6
A8
A15/PAL15
B14
–
D6
A10/PAL10
A9
A17/PAH1
C1
–
D7
A14/PAL14
A10
–
C2
CS2/IOWR/PCS2
D8
A16/PAH0
A11
A24/PAH8
C3
CS3/RAS3/PCS3
D9
A20/PAH4
A12
VDD
C4
VSS
D10
A23/PAH7
A13
LBE/SDCAS/PCD2
C5
A22/PAH6
D11
SDCKE/PCD0
A14
UBE/SDRAS/PCD3
C6
A19/PAH3
D12
CS0/PCS0
C7
VDD
D13
CS5/IORD/PCS5
B1
–
B2
CS1/RAS1/PCS1
C8
A11/PAL11
D14
B3
SDCLK/PCD1
C9
VDD
E1
D5/PDL5
B4
A25/PAH9
C10
A7/PAL7
E2
D7/PDL7
B5
A21/PAH5
C11
A1/PAL1
E3
D8/PDL8
B6
A18/PAH2
C12
D13/PDL13
E4
D11/PDL11
User’s Manual U14359EJ3V0UM
–
31
CHAPTER 1 INTRODUCTION
(2/2)
Pin
Number
Pin Name
E5
–
Pin
Number
Pin Name
Pin
Number
Pin Name
J12
TI030/INTP030/P50
M10
SCK1/P45
E11
CS6/RAS6/PCS6
J13
SELFREF/PCM5
M11
TXD0/SO0/P40
E12
CS4/RAS4/PCS4
J14
INTP031/P51
M12
ANI6/P76
E13
CS7/PCS7
K1
PWM0/P00
M13
ANI5/P75
E14
VSS
K2
VSS
M14
–
F1
D2/PDL2
K3
DMAAK1/PBD1
N1
–
F2
D3/PDL3
K4
DMAAK3/PBD3
N2
PWM1/P10
F3
D4/PDL4
K11
ANI1/P71
N3
TC3/INTP113/P27
F4
VDD
K12
ANI0/P70
N4
TC0/INTP110/P24
F11
RD/PCT4
K13
VSS
N5
NMI/P20
F12
VDD
K14
VDD
N6
ADTRG/INTP123/P37
F13
LCAS/LWR/LDQM/PCT0
L1
N7
TXD2/INTP133/P33
F14
UCAS/UWR/UDQM/PCT1
L2
DMAAK2/PBD2
N8
SO2/INTP130/P30
G1
MODE2 (MODE2/VPP)
L3
TI010/INTP010/P11
N9
X2
G2
DMARQ3/INTP103/P07
L4
DMAAK0/PBD0
N10
CVSS
G3
D0/PDL0
L5
TO02/P23
N11
SCK0/P42
G4
D6/PDL6
L6
VDD
N12
AVDD/AVREF
G11
WAIT/PCM0
L7
INTP122/P36
N13
AVSS
G12
WE/PCT5
L8
SI2/INTP131/P31
N14
G13
BCYST/PCT7
L9
RESET
P1
VDD
G14
OE/PCT6
L10
TXD1/SO1/P43
P2
VSS
H1
DMARQ2/INTP102/P06
L11
ANI7/P77
P3
TC1/INTP111/P25
H2
DMARQ1/INTP101/P05
L12
ANI4/P74
P4
INTP021/P22
H3
DMARQ0/INTP100/P04
L13
ANI3/P73
P5
H4
D1/PDL1
L14
ANI2/P72
P6
INTP121/P35
H11
REFRQ/PCM4
M1
P7
SCK2/INTP132/P32
H12
HLDRQ/PCM3
M2
INTP011/P12
P8
MODE1
H13
HLDAK/PCM2
M3
TO01/P13
P9
CVDD
H14
CLKOUT/BUSCLK/PCM1
M4
TC2/INTP112/P26
P10
X1
J1
TO00/P03
M5
TI020/INTP020/P21
P11
–
J2
TI000/INTP000/P01
M6
VSS
P12
RXD1/SI1/P44
J3
VDD
M7
RXD2/INTP120/P34
P13
RXD0/SI0/P41
J4
INTP001/P02
M8
MODE0
P14
–
J11
TO03/P52
M9
CKSEL
–
–
–
–
Remarks 1. Leave the A1, A5, A10, B1, B14, C1, C14, D14, E5, L1, M1, M14, N1, N14, P5, P11, and P14 pins
open.
2. Items in parentheses are pin names in the µPD70F3107.
32
User’s Manual U14359EJ3V0UM
CHAPTER 1 INTRODUCTION
Pin Identification
A0 to A25:
Address bus
P70 to P77:
Port 7
ADTRG:
AD trigger input
PAH0 to PAH9:
Port AH
ANI0 to ANI7:
Analog input
PAL0 to PAL15:
Port AL
AVDD:
Analog power supply
PBD0 to PBD3:
Port BD
AVREF:
Analog reference voltage
PCD0 to PCD3:
Port CD
AVSS:
Analog ground
PCM0 to PCM5:
Port CM
BCYST:
Bus cycle start timing
PCS0 to PCS7:
Port CS
BUSCLK:
Bus clock output
PCT0, PCT1, :
Port CT
CKSEL:
Clock generator operating mode select
PCT4 to PCT7
CLKOUT:
Clock output
PDL0 to PDL15:
Port DL
CS0 to CS7:
Chip select
PWM0, PWM1:
Pulse width modulation
CVDD:
Clock generator power supply
RAS1, RAS3, :
Row address strobe
CVSS:
Clock generator ground
RAS4, RAS6
D0 to D15:
Data bus
RD:
Read
DMAAK0 to DMAAK3:
DMA acknowledge
REFRQ:
Refresh request
DMARQ0 to DMARQ3:
DMA request
RESET:
Reset
HLDAK:
Hold acknowledge
RXD0 to RXD2:
Receive data
HLDRQ:
Hold request
SCK0 to SCK2:
Serial clock
INTP000, INTP001,
Interrupt request from peripherals
SDCAS:
SDRAM column address strobe
INTP010, INTP011,
SDCKE:
SDRAM clock enable
INTP020, INTP021,
SDCLK:
SDRAM clock output
INTP030, INTP031,
SDRAS:
SDRAM row address strobe
INTP100 to INTP103,
SELFREF:
Self-refresh request
INTP110 to INTP113,
SI0 to SI2:
Serial input
INTP120 to INTP123,
SO0 to SO2:
Serial output
INTP130 to INTP133
TC0 to TC3:
Terminal count signal
TI000, TI010, :
Timer input
IORD:
I/O read strobe
IOWR:
I/O write strobe
TI020, TI030:
LBE:
Lower byte enable
TO00 to TO03:
Timer output
LCAS:
Lower column address strobe
TXD0 to TXD2:
Transmit data
LDQM:
Lower DQ mask enable
UBE:
Upper byte enable
LWR:
Lower write strobe
UCAS:
Upper column address strobe
MODE0 to MODE2:
Mode
UDQM:
Upper DQ mask enable
NMI:
Non-maskable interrupt request
UWR:
Upper write strobe
OE:
Output enable
VDD:
Power supply
P00 to P07:
Port 0
VPP:
Programming power supply
P10 to P13:
Port 1
VSS:
Ground
P20 to P27:
Port 2
WAIT:
Wait
P30 to P37:
Port 3
WE:
Write enable
P40 to P45:
Port 4
X1, X2:
Crystal
P50 to P52:
Port 5
User’s Manual U14359EJ3V0UM
33
CHAPTER 1 INTRODUCTION
1.6
Function Blocks
1.6.1 Internal block diagram
NMI
INTP100 to INTP103,
INTP110 to INTP113,
INTP120 to INTP123,
INTP130 to INTP133
INTP000 to INTP001,
INTP010 to INTP011,
INTP020 to INTP021,
INTP030 to INTP031
CPU
BCU
MEMC
Instruction
queue
DRAMC
INTC
ROM
PC
Note 1
32-bit barrel
shifter
RPU
Multiplier
(32 × 32 → 64)
TO00 to TO03
TI000, TI010,
TI020, TI030
SIO
SO0/TXD0
SI0/RXD0
SCK0
UART0/CSI0
SO1/TXD1
SI1/RXD1
SCK1
UART1/CSI1
System
registers
RAM
ALU
General-purpose
registers
(32 bits × 32)
Note 2
TXD2
DMAC
UART2
SO2
SI2
SCK2
CSI2
PWM0
PWM0
Ports
PWM1
PWM1
PDL0 to PDL15
PAL0 to PAL15
PAH0 to PAH9
PCS0 to PCS7
PCT0, PCT1, PCT4 to PCT7
PCM0 to PCM5
PCD0 to PCD3
PBD0 to PBD3
P70 to P77
P50 to P52
P40 to P45
P30 to P37
P21 to P27
P20
P10 to P13
P00 to P07
RXD2
ANI0 to ANI7
AVREF/AVDD
AVSS
ADTRG
Notes 1.
ADC
µPD703103:
ROMless
µPD703105, 703106: 128 KB (mask ROM)
2.
µPD703107:
256 KB (mask ROM)
µPD70F3107:
256 KB (flash memory)
µPD703103, 703105:
4 KB
µPD703106, 703107, 70F3107: 10 KB
3.
34
ROMC
Valid for µPD70F3107 only
User’s Manual U14359EJ3V0UM
CG
System
controller
HLDRQ
HLDAK
CS0, CS7
CS1/RAS1, CS3/RAS3
CS4/RAS4, CS6/RAS6
CS2/IORD
CS5/IOWR
SELFREF
REFRQ
BCYST
LBE/SDCAS
UBE/SDRAS
SDCLK
SDCKE
WE
RD
OE
UWR/UCAS/UDQM
LWR/LCAS/LDQM
WAIT
A0 to A25
D0 to D15
BUSCLK
DMARQ0 to DMARQ3
DMAAK0 to DMAAK3
TC0 to TC3
CKSEL
CLKOUT
X1
X2
CVDD
CVSS
MODE0, MODE1
MODE2/VPPNote 3
RESET
VDD
VSS
CHAPTER 1 INTRODUCTION
1.6.2 On-chip units
(1) CPU
The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic
logic operations, data transfers, and almost all other instruction processing.
Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits → 32 bits or 32 bits × 32 bits → 64
bits) and a barrel shifter (32 bits), help accelerate processing of complex instructions.
(2) Bus control unit (BCU)
The BCU starts the required external bus cycle based on the physical address obtained by the CPU. When
an instruction is fetched from external memory area and the CPU does not send a bus cycle start request, the
BCU generates a prefetch address and prefetches the instruction code. The prefetched instruction code is
stored in an instruction queue in the CPU.
The BCU controls a DRAM controller (DRAMC), page ROM controller (ROMC), and DMA controller (DMAC)
and performs external memory access and DMA transfer.
(a) DRAM controller (DRAMC)
(i) SDRAM
The DRAM controller generates the SDRAS, SDCAS, UDQM, and LDQM signals and performs
access control for SDRAM.
CAS latency 2 and 3 are supported, and the burst length is fixed to 1.
A refresh function that supports the CBR refresh cycle and a dynamic self-refresh function based on
an external input are also available.
(ii) EDO DRAM
The DRAM controller generates the RAS, UCAS, and LCAS signals (2CAS control) and performs
access control for EDO DRAM.
EDO DRAM is supported, and there are two types of access: normal access (off page) and page
access (on page).
A refresh function that supports the CBR refresh cycle and a dynamic self-refresh function based on
an external input are also available.
(b) Page ROM controller (ROMC)
This controller supports accessing ROM that includes the page access function.
It performs address comparisons with the immediately preceding bus cycle and executes wait control for
normal access (off-page)/page access (on-page). It can handle page widths of 8 to 128 bytes.
(c) DMA controller (DMAC)
This controller controls data transfer between memory and I/O instead of the CPU.
There are two address modes: flyby (1-cycle) transfer, and 2-cycle transfer. There are three bus modes,
single transfer, single step transfer, and block transfer.
User’s Manual U14359EJ3V0UM
35
CHAPTER 1 INTRODUCTION
(3) ROM
The µPD703105 and 703106 have 128 KB of on-chip mask ROM, the µPD703107 has 256 KB of on-chip
mask ROM and the µPD70F3107 has 256 KB of on-chip flash memory. The µPD703103 does not include
on-chip ROM.
During instruction fetch, ROM/flash memory can be accessed from the CPU in 1-clock cycles.
If single-chip mode 0 or flash memory programming mode is set, memory mapping occurs from address
00000000H.
If single-chip mode 1 is set, memory mapping occurs from address 00100000H.
If ROMless mode is set, access is not possible.
(4) RAM
RAM is mapped from address FFFFC000H.
During data access, data can be accessed from the CPU in 1-clock cycles.
(5) Interrupt controller (INTC)
This controller handles hardware interrupt requests (NMI, INTP0n0, INTP0n1, INTP1nn) from on-chip
peripheral I/O and external hardware (n = 0 to 3). Eight levels of interrupt priorities can be specified for these
interrupt requests, and multiple-interrupt servicing control can be performed for interrupt sources.
(6) Clock generator (CG)
This clock generator supplies frequencies which are 10 times the input clock (fXX) (using an on-chip PLL) or
1/2 the input clock (when an on-chip PLL is not used) as the internal system clock (φ). As the input clock, an
external oscillator is connected to pins X1 and X2 (only when an on-chip PLL synthesizer is used) or an
external clock is input from the X1 pin.
(7) Real-time pulse unit (RPU)
This unit incorporates a 4-channel 16-bit timer/event counter and 4-channel 16-bit interval timer, and can
measure pulse widths or frequency and output a programmable pulse.
(8) Serial interfaces (SIO)
The serial interfaces consist of 4 channels divided between an asynchronous serial interface (UART) and
clocked serial interface (CSI). Two of these channels can be switched between UART and CSI, one channel
is fixed to CSI, and the remaining channel is fixed to UART.
UART transfers data by using the TXDn and RXDn pins (n = 0 to 2).
CSI transfers data by using the SOn, SIn, and SCKn pins (n = 0 to 2).
(9) A/D converter (ADC)
This high-speed, high-resolution 10-bit A/D converter includes 8 analog input pins. Conversion is performed
using the successive approximation method.
(10) PWM
Two channels for PWM signal output of 8-/9-/10-/12-bit resolution have been provided. By connecting an
external low-pass filter, PWM output can be used as digital/analog conversion output. PWM is ideal for
actuator control signals such as those in motors.
36
User’s Manual U14359EJ3V0UM
CHAPTER 1 INTRODUCTION
(11) Ports
As shown below, the following ports have general port functions and control pin functions.
Port
Port Function
Control Function
Port 0
8-bit I/O
Real-time pulse unit I/O, external interrupt input, PWM output, DMA controller
input
Port 1
4-bit I/O
Real-time pulse unit I/O, external interrupt input, PWM output
Port 2
1-bit input,
7-bit I/O
NMI input, real-time pulse unit I/O, external interrupt input, DMA controller output
Port 3
8-bit I/O
Serial interface I/O, external interrupt input, A/D converter external trigger input
Port 4
6-bit I/O
Serial interface I/O
Port 5
3-bit I/O
Real-time pulse unit I/O, external interrupt input
Port 7
8-bit input
A/D converter input
Port AL
16-bit I/O
External address bus
Port AH
10-bit I/O
External address bus
Port DL
16-bit I/O
External data bus
Port CS
8-bit I/O
External bus interface control signal output
Port CT
6-bit I/O
External bus interface control signal output
Port CM
6-bit I/O
Wait insertion signal input, internal system clock output, external bus interface
control signal I/O, self-refresh request signal input
Port CD
4-bit I/O
External bus interface control signal output
Port BD
4-bit I/O
DMA controller output
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CHAPTER 2 PIN FUNCTIONS
The names and functions of the pins in the V850E/MA1 are listed below. These pins can be divided into port pins
and non-port pins according to their functions.
2.1
List of Pin Functions
(1) Port pins
(1/3)
Pin Name
P00
I/O
I/O
P01
Function
Port 0
8-bit I/O port
Input/output can be specified in 1-bit units.
Alternate Function
PWM0
TI000/INTP000
P02
INTP001
P03
TO00
P04
DMARQ0/INTP100
P05
DMARQ1/INTP101
P06
DMARQ2/INTP102
P07
DMARQ3/INTP103
P10
I/O
P11
Port 1
4-bit I/O port
Input/output can be specified in 1-bit units.
PWM1
INTP010/TI010
P12
INTP011
P13
TO01
P20
Input
P21
I/O
P22
P23
P24
Port 2
P20 is an input-only port.
If a valid edge is input, it operates as an NMI input. Also, the
status of the NMI input is shown by bit 0 of the P2 register.
P21 to P27 are a 7-bit I/O port.
Input/output can be specified in 1-bit units.
NMI
INTP020/TI020
INTP021
TO02
TC0/INTP110
P25
TC1/INTP111
P26
TC2/INTP112
P27
TC3/INTP113
P30
P31
I/O
Port 3
8-bit I/O port
Input/output can be specified in 1-bit units.
SO2/INTP130
SI2/INTP131
P32
SCK2/INTP132
P33
TXD2/INTP133
P34
RXD2/INTP120
P35
INTP121
P36
INTP122
P37
ADTRG/INTP123
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PIN FUNCTIONS
(2/3)
Pin Name
P40
I/O
I/O
P41
Function
Port 4
6-bit I/O port
Input/output can be specified in 1-bit units.
Alternate Function
TXD0/SO0
RXD0/SI0
P42
SCK0
P43
TXD1/SO1
P44
RXD1/SI1
P45
SCK1
P50
I/O
P51
Port 5
3-bit I/O port
Input/output can be specified in 1-bit units.
INTP031
TO03
P52
P70 to P77
INTP030/TI030
Input
Port 7
8-bit input-only port
ANI0 to ANI7
PBD0 to PBD3
I/O
Port BD
4-bit I/O port
Input/output can be specified in 1-bit units.
DMAAK0 to DMAAK3
PCM0
I/O
Port CM
6-bit I/O port
Input/output can be specified in 1-bit units.
WAIT
PCM1
CLKOUT/BUSCLK
PCM2
HLDAK
PCM3
HLDRQ
PCM4
REFRQ
PCM5
SELFREF
PCT0
I/O
PCT1
Port CT
6-bit I/O port
Input/output can be specified in 1-bit units.
LCAS/LWR/LDQM
UCAS/UWR/UDQM
PCT4
RD
PCT5
WE
PCT6
OE
PCT7
BCYST
PCS0
I/O
PCS1
Port CS
8-bit I/O port
Input/output can be specified in 1-bit units.
CS0
CS1/RAS1
PCS2
CS2/IOWR
PCS3
CS3/RAS3
PCS4
CS4/RAS4
PCS5
CS5/IORD
PCS6
CS6/RAS6
PCS7
CS7
PCD0
PCD1
I/O
Port CD
4-bit I/O port
Input/output can be specified in 1-bit units.
SDCKE
SDCLK
PCD2
LBE/SDCAS
PCD3
UBE/SDRAS
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CHAPTER 2
PIN FUNCTIONS
(3/3)
Pin Name
I/O
Function
Alternate Function
PAH0 to PAH9
I/O
Port AH
8-/10-bit I/O port
Input/output can be specified in 1-bit units.
A16 to A25
PAL0 to PAL15
I/O
Port AL
8-/16-bit I/O port
Input/output can be specified in 1-bit units.
A0 to A15
PDL0 to PDL15
I/O
Port DL
8-/16-bit I/O port
Input/output can be specified in 1-bit units.
D0 to D15
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(2) Non-port pins
(1/4)
Pin Name
TO00
I/O
Output
Function
Pulse signal output of timer C0 to C3
Alternate Function
P03
TO01
P13
TO02
P23
TO03
P52
TI000
Input
External count input of timer C0 to C3
P01/INTP000
TI010
P11/INTP010
TI020
P21/INTP020
TI030
P50/INTP030
INTP000
Input
INTP001
INTP010
External maskable interrupt request input, or timer C1 external
capture trigger input
INTP011
INTP020
External maskable interrupt request input, or timer C2 external
capture trigger input
INTP021
External maskable interrupt request input, or timer C3 external
capture trigger input
INTP030
INTP031
INTP100
External maskable interrupt request input, or timer C0 external
capture trigger input
Input
External maskable interrupt request input
P01/TI000
P02
P11/TI010
P12
P21/TI020
P22
P50/TI030
P51
P04/DMARQ0
INTP101
P05/DMARQ1
INTP102
P06/DMARQ2
INTP103
P07/DMARQ3
INTP110
P24/TC0
INTP111
P25/TC1
INTP112
P26/TC2
INTP113
P27/TC3
INTP120
P34/RXD2
INTP121
P35
INTP122
P36
INTP123
P37/ADTRG
INTP130
P30/SO2
INTP131
P31/SI2
INTP132
P32/SCK2
INTP133
P33/TXD2
SO0
Output
CSI0 to SCI2 serial transmission data output (3-wire)
P40/TXD0
SO1
P43/TXD1
SO2
P30/INTP130
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PIN FUNCTIONS
(2/4)
Pin Name
SI0
I/O
Input
Function
CSI0 to CSI2 serial reception data input (3-wire)
Alternate Function
P41/RXD0
SI1
P44/RXD1
SI2
P31/INTP131
SCK0
I/O
CSI0 to CSI2 serial clock I/O (3-wire)
P42
SCK1
P45
SCK2
P32/INTP132
TXD0
Output
UART0 to UART2 serial transmission data output
P40/SO0
TXD1
P43/SO1
TXD2
P33/INTP133
RXD0
Input
UART0 to UART2 serial reception data input
P41/SI0
RXD1
P44/SI1
RXD2
P34/INTP120
PWM0
Output
PWM pulse signal output
PWM1
P00
P10
ANI0 to ANI7
Input
Analog inputs to A/D converter
P70 to P77
ADTRG
Input
A/D converter external trigger input
P37/INTP123
DMARQ0
Input
DMA request signal input
P04/INTP100
DMARQ1
P05/INTP101
DMARQ2
P06/INTP102
DMARQ3
P07/INTP103
DMAAK0
Output
DMA acknowledge signal output
PBD0
DMAAK1
PBD1
DMAAK2
PBD2
DMAAK3
PBD3
TC0
Output
DMA transfer end (terminal count) signal output
P24/INTP110
TC1
P25/INTP111
TC2
P26/INTP112
TC3
P27/INTP113
NMI
Input
Non-maskable interrupt request signal input
MODE0
Input
V850E/MA1 operating mode specification
P20
−
−
MODE1
MODE2
VPP
VPP
Input
Flash memory programming power-supply application pin
(µPD70F3107 only)
MODE2
WAIT
Input
Control signal input that inserts a wait in the bus cycle
PCM0
Bus hold acknowledge output
PCM2
Bus hold request input
PCM3
Refresh request signal output for DRAM
PCM4
Self-refresh request input for DRAM
PCM5
HLDAK
Output
HLDRQ
Input
REFRQ
Output
SELFREF
42
Input
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PIN FUNCTIONS
(3/4)
Pin Name
I/O
Function
Alternate Function
LCAS
Output
Column address strobe signal output for DRAM lower data
PCT0/LWR/LDQM
UCAS
Output
Column address strobe signal output for DRAM higher data
PCT1/UWR/UDQM
LWR
Output
External data lower byte write enable signal output
PCT0/LCAS/LDQM
UWR
Output
External data higher byte write enable signal output
PCT1/UCAS/UDQM
LDQM
Output
Output disable/write mask signal output for SDRAM lower data
PCT0/LCAS/LWR
UDQM
Output
Output disable/write mask signal output for SDRAM higher data
PCT1/UCAS/UWR
RD
Output
External data bus read strobe signal output
PCT4
WE
Output
Write enable signal output for DRAM
PCT5
OE
Output
Output enable signal output for DRAM
PCT6
BCYST
Output
Strobe signal output that shows the start of the bus cycle
PCT7
CS0
Output
Chip select signal output
PCS0
CS1
PCS1/RAS1
CS2
PCS2/IOWR
CS3
PCS3/RAS3
CS4
PCS4/RAS4
CS5
PCS5/IORD
CS6
PCS6/RAS6
CS7
PCS7
RAS1
Output
Row address strobe signal output for DRAM
PCS1/CS1
RAS3
PCS3/CS3
RAS4
PCS4/CS4
RAS6
PCS6/CS6
IOWR
Output
DMA write strobe signal output
PCS2/CS2
IORD
Output
DMA read strobe signal output
PCS5/CS5
SDCKE
Output
SDRAM clock enable signal output
PCD0
SDCLK
Output
SDRAM clock signal output
PCD1
SDCAS
Output
Column address strobe signal output for SDRAM
PCD2/LBE
SDRAS
Output
Row address strobe signal output for SDRAM
PCD3/UBE
LBE
Output
External data bus lower byte enable signal output
PCD2/SDCAS
UBE
Output
External data bus higher byte enable signal output
PCD3/SDRAS
16-bit data bus for external memory
PDL0 to PDL15
26-bit address bus for external memory
PAL0 to PAL15
D0 to D15
I/O
A0 to A15
Output
A16 to A25
PAH0 to PAH9
RESET
Input
System reset input
−
X1
Input
−
X2
−
Connects the crystal resonator for system clock oscillation. In the
case of an external source supplying the clock, it is input to X1.
−
CLKOUT
Output
System clock output
PCM1/BUSCLK
BUSCLK
Output
Bus clock output
PCM1/CLKOUT
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PIN FUNCTIONS
(4/4)
Pin Name
I/O
Function
Alternate Function
−
CKSEL
Input
Input specifying the clock generator's operating mode
AVREF
Input
Reference voltage applied to A/D converter
AVDD
AVDD
−
Positive power supply for A/D converter
AVREF
AVSS
−
Ground potential for A/D converter
−
CVDD
−
Positive power supply for dedicated clock generator
−
CVSS
−
Ground potential for dedicated clock generator
−
VDD
−
Positive power supply
−
VSS
−
Ground potential
−
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2.2
PIN FUNCTIONS
Pin Status
The status of each pin after reset, in power-save mode (software STOP, IDLE, HALT modes), and during DMA
transfer, refresh, and bus hold (TH) is shown below.
Operating Status
Reset
Reset
IDLE Mode/Software
HALT Mode/During
STOP Mode
DMA Transfer,
(Single-Chip Mode 0) (Single-Chip Mode 1,
Pin
ROMless Mode 0,1)
Bus Hold
(TH)
Refresh
A0 to A15 (PAL0 to PAL15)
Hi-Z
Hi-Z
Hi-Z
Operating
Hi-Z
A16 to A25 (PAH0 to PAH9)
Hi-Z
Hi-Z
Hi-Z
Operating
Hi-Z
D0 to D15 (PDL0 to PDL15)
Hi-Z
Hi-Z
Hi-Z
Operating
Hi-Z
CS0 to CS7 (PCS0 to PCS7)
Hi-Z
Hi-Z
SELF
Operating
Hi-Z
RAS1, RAS3, RAS4, RAS6
(PCS1, PCS3, PCS4, PCS6)
−
−
CBR
Operating
Hi-Z
IOWR (PCS2)
−
−
H
Operating
Hi-Z
IORD (PCS5)
−
−
H
Operating
Hi-Z
H
Operating
Hi-Z
LWR, UWR (PCT0, PCT1)
Hi-Z
Hi-Z
LCAS,UCAS (PCT0, PCT1)
−
−
CBR
Operating
Hi-Z
LDQM, UDQM (PCT0, PCT1)
−
−
H
Operating
Hi-Z
RD (PCT4)
Hi-Z
Hi-Z
H
Operating
Hi-Z
WE (PCT5)
Hi-Z
Hi-Z
H
Operating
Hi-Z
OE (PCT6)
Hi-Z
Hi-Z
H
Operating
Hi-Z
BCYST (PCT7)
Hi-Z
Hi-Z
H
Operating
Hi-Z
WAIT (PCM0)
Hi-Z
Hi-Z
CLKOUT (PCM1)
Hi-Z
Operating
−
−
BUSCLK (PCM1)
−
Operating
−
L
Operating
Operating
L
Operating
Operating
H
Operating
L
Operating
Operating
Operating
Operating
Operating
−
HLDAK (PCM2)
Hi-Z
Hi-Z
HLDRQ (PCM3)
Hi-Z
Hi-Z
REFRQ (PCM4)
Hi-Z
Hi-Z
SELFREF (PCM5)
Hi-Z
Hi-Z
SDCKE (PCD0)
Hi-Z
Hi-Z
L
Operating
Operating
SDCLK (PCD1)
Hi-Z
Hi-Z
L
Operating
Operating
SELF
Operating
Hi-Z
H
Operating
Hi-Z
SELF
Operating
Hi-Z
−
SDCAS (PCD2)
LBE (PCD2)
CBR
−
−
Hi-Z
Hi-Z
−
SDRAS (PCD3)
−
−
UBE (PCD3)
Hi-Z
Hi-Z
H
Operating
Hi-Z
DMAAK0 to DMAAK3
(PBD0 to PBD3)
Hi-Z
Hi-Z
H
Operating
H
Remark Hi-Z:
High-impedance
Hold:
Status during immediately preceding external bus cycle hold
H:
High-level output
L:
Low-level output
:
No sampling of input
CBR:
A DRAM refresh state
SELF:
Self-refresh state when pins are connected to SDRAM
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2.3
PIN FUNCTIONS
Description of Pin Functions
(1) P00 to P07 (Port 0) ··· 3-state I/O
P00 to P07 function as an 8-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, in the control mode, these pins operate as I/O for the real-time pulse unit
(RPU), external interrupt request inputs, a PWM output, and DMA request inputs.
The operation mode can be set to port or control mode in 1-bit units, specified by the port 0 mode control
register (PMC0).
(a) Port mode
P00 to P07 can be set to input or output in 1-bit units using the port 0 mode register (PM0).
(b) Control mode
P00 to P07 can be set to port/control mode in 1-bit units using the PMC0 register.
(i) PWM0 (Pulse width modulation) ··· output
This pin outputs the PWM pulse signal.
(ii) TI000 (Timer input) ··· input
This is the external count clock input pin for timer C0.
(iii) TO00 (Timer output) ··· output
This pin outputs the pulse signals for timer C0.
(iv) INTP000, INTP001 (Interrupt request from peripherals) ··· input
These are external interrupt request input pins and the external capture trigger input pins for timer
C0.
(v) INTP100 to INTP103 (Interrupt request from peripherals) ··· input
These are external interrupt request input pins.
(vi) DMARQ0 to DMARQ3 (DMA request) ··· input
These are DMA service request signals. They correspond to DMA channels 0 to 3, respectively, and
operate independently of each other. The priority order is fixed to DMARQ0 > DMARQ1 > DMARQ2
> DMARQ3.
These signals are sampled at the falling edge of the CLKOUT signal. Maintain an active level until a
DMA request is acknowledged.
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(2) P10 to P13 (Port 1) ··· 3-state I/O
P10 to P13 function as a 4-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, in the control mode, these pins operate as I/O for the real-time pulse unit
(RPU), external interrupt request inputs, and a PWM output.
The operation mode can be set to port or control mode in 1-bit units, specified by the port 1 mode control
register (PMC1).
(a) Port mode
P10 to P13 can be set to input or output in 1-bit units using the port 1 mode register (PM1).
(b) Control mode
P10 to P13 can be set to port/control mode in 1-bit units using the PMC1 register.
(i) PWM1 (Pulse width modulation) ··· output
This pin outputs the PWM pulse signal.
(ii) TI010 (Timer input) ··· input
This is the external count clock input pin for timer C1.
(iii) TO01 (Timer output) ··· output
This pin outputs the pulse signal for timer C1.
(iv) INTP010, INTP011 (Interrupt request from peripherals) ··· input
These are external interrupt request input pins and the external capture trigger input pins for timer
C1.
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(3) P20 to P27 (Port 2) ··· 3-state I/O
P20 is an input-only pin. P21 to P27 function as a 7-bit I/O port that can be set to input or output in 1-bit
units.
Besides functioning as an I/O port, in the control mode, these pins operate as I/O for the real-time pulse unit
(RPU), external interrupt request inputs, and DMA transfer termination outputs (terminal count).
The operation mode can be set to port or control mode in 1-bit units, specified by the port 2 mode control
register (PMC2).
(a) Port mode
P21 to P27 can be set to input or output in 1-bit units using the port 2 mode register (PM2). P20 is an
input-only port, and if a valid edge is input, it operates as an NMI input.
(b) Control mode
P21 to P27 can be set to port/control mode in 1-bit units using the PMC2 register.
(i) NMI (Non-maskable interrupt request) ··· input
This is the non-maskable interrupt request input pin.
(ii) TI020 (Timer input) ··· input
This is the external count clock input pin for timer C2.
(iii) TO02 (Timer output) ··· output
This pin outputs the pulse signal for timer C2.
(iv) INTP020, INTP021 (Interrupt request from peripherals) ··· input
These are external interrupt request input pins and the external capture trigger input pins for timer
C2.
(v) INTP110 to INTP113 (Interrupt request from peripherals) ··· input
These are external interrupt request input pins.
(vi) TC0 to TC3 (Terminal count) ··· output
These are signals from the DMA controller indicating that DMA transfer is complete. These signals
become active for 1 clock at the rising edge of the CLKOUT signal.
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(4) P30 to P37 (Port 3) ··· 3-state I/O
P30 to P37 function as an 8-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, in the control mode, these pins operate as I/O for the serial interfaces
(CSI2, UART2), external interrupt request inputs, and the A/D converter external trigger input.
The operation mode can be set to port or control mode in 1-bit units, specified by the port 3 mode control
register (PMC3).
(a) Port mode
P30 to P37 can be set to input or output in 1-bit units using the port 3 mode register (PM3).
(b) Control mode
P30 to P37 can be set to port/control mode in 1-bit units using the PMC3 register.
(i) TXD2 (Transmit data) ··· output
This pin outputs the serial transmit data of UART2.
(ii) RXD2 (Receive data) ··· input
This pin inputs the serial receive data of UART2.
(iii) SO2 (Serial output) ··· output
This pin outputs the serial transmit data of CSI2.
(iv) SI2 (Serial input) ··· input
This pin inputs the serial receive data of CSI2.
(v) SCK2 (Serial clock) ··· 3-state I/O
This is the CSI2 serial clock I/O pin.
(vi) INTP120 to INTP123, INTP130 to INTP133 (Interrupt request from peripherals) ··· input
These are external interrupt request input pins.
(vii) ADTRG (AD trigger input) ··· input
This is the external trigger input pin for the AD converter.
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(5) P40 to P45 (Port 4) ··· 3-state I/O
P40 to P45 function as a 6-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, in the control mode, these pins operate as I/O for the serial interfaces
(UART0/CSI0, UART1/CSI1).
The operation mode can be set to port or control mode in 1-bit units, specified by the port 4 mode control
register (PMC4).
(a) Port mode
P40 to P45 can be set to input or output in 1-bit units using the port 4 mode register (PM4).
(b) Control mode
P40 to P45 can be set to port/control mode in 1-bit units using the PMC4 register.
(i) TXD0, TXD1 (Transmit data) ··· output
These pins output UART0, UART1 serial transmit data.
(ii) RXD0, RXD1 (Receive data) ··· input
These pins input UART0, UART1 serial receive data.
(iii) SO0, SO1 (Serial output) ··· output
These pins output CSI0, CSI1 serial transmit data.
(iv) SI0, SI1 (Serial input) ··· input
These pins input CSI0, CSI1 serial receive data.
(v) SCK0, SCK1 (Serial clock) ··· 3-state I/O
These are the CSI0, CSI1 serial clock I/O pins.
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(6) P50 to P52 (Port 5) ··· 3-state I/O
P50 to P52 function as a 3-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, in the control mode, these pins operate as I/O for the real-time pulse unit
(RPU) and external interrupt request inputs.
The operation mode can be set to port or control mode in 1-bit units, specified by the port 5 mode control
register (PMC5).
(a) Port mode
P50 to P52 can be set to input or output in 1-bit units using the port 5 mode register (PM5).
(b) Control mode
P50 to P52 can be set to port/control mode in 1-bit units using the PMC5 register.
(i) TI030 (Timer input) ··· input
This is the external count clock input pin for timer C3.
(ii) TO03 (Timer output) ··· output
This pin outputs the pulse signal for timer C3.
(iii) INTP030, INTP031 (Interrupt request from peripherals) ··· input
These are external interrupt request input pins and the external capture trigger input pins for timer
C3.
(7) P70 to P77 (Port 7) ··· 3-state I/O
P70 to P77 function as an 8-bit input-only port in which all pins are fixed as input pins.
Besides functioning as a port, in the control mode, these pins operate as analog inputs for the A/D converter.
However, the input ports and analog input pins cannot be switched.
(a) Port mode
P70 to P77 are input-only pins.
(b) Control mode
P70 to P77 have alternate functions as pins ANI0 to ANI7, but these alternate functions are not
switchable.
(i) ANI0 to ANI7 (Analog input) ··· input
These are analog input pins for the A/D converter.
Connect a capacitor between these pins and AVSS to prevent noise-related operation faults. Also, do
not apply voltage that is outside the range for AVSS and AVREF to pins that are being used as inputs
for the A/D converter. If it is possible for noise above the AVREF range or below the AVSS to enter,
clamp these pins using a diode that has a small VF value.
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PIN FUNCTIONS
(8) PBD0 to PBD3 (Port BD) ··· 3-state I/O
PBD0 to PBD3 function as a 4-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as an I/O port, in the control mode, these pins operate as DMA acknowledge outputs.
The operation mode can be set to port or control in 1-bit units, specified by the port BD mode control register
(PMCBD).
(a) Port mode
PBD0 to PBD3 can be set to input or output in 1-bit units using the port BD mode register (PMBD).
(b) Control mode
PBD0 to PBD3 can be set to port/control mode in 1-bit units using the PMCBD register.
(i) DMAAK0 to DMAAK3 (DMA acknowledge) ··· output
These signals show that a DMA service request was granted. They correspond to DMA channel 0 to
3, respectively, and operate independently of each other.
These signals become active only when external memory is being accessed. When DMA transfers
are being executed between internal RAM and internal peripheral I/O, they do not become active.
These signals are activated at the falling edge of the CLKOUT signal in the T0, T1R, T1FH state of
the DMA cycle, and maintained at an active level during DMA transfers.
(9) PCM0 to PCM5 (Port CM) ··· 3-state I/O
PCM0 to PCM5 function as a 6-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as a port, in the control mode, these pins operate as the wait insertion signal input,
system clock output, bus hold control signal, refresh request signal output for DRAM, and self-refresh request
signal input.
The operation mode can be set to port or control in 1-bit units, specified by the port CM mode control register
(PMCCM).
(a) Port mode
PCM0 to PCM5 can be set to input or output in 1-bit units using the port CM mode register (PMCM).
(b) Control mode
PCM0 to PCM5 can be set to port/control mode in 1-bit units using the PMCCM register.
(i) WAIT (Wait) ··· input
This is the control signal input pin at which a data wait is inserted in the bus cycle. The WAIT signal
can be input asynchronously to the CLKOUT signal. When the CLKOUT signal falls, sampling is
executed. When the set/hold time is not terminated within the sampling timing, wait insertion may
not be executed.
(ii) CLKOUT (Clock output) ··· output
This is the internal system clock output pin. In single-chip mode 0, because port mode is entered
during the reset period, output does not occur from the CLKOUT pin. CLKOUT output can be
executed by setting the port CM mode control register (PMCCM) and the port CM function control
register (PFCCM).
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(iii) BUSCLK (Bus clock output) ··· output
This is the bus clock output pin. The bus clock operates at the operating frequency of 1/2 the
internal system clock by setting the bus cycle period control register (BCP). To execute BUSCLK
output, set the port CM mode control register (PMCCM) and the port CM function control register
(PFCCM).
(iv) HLDAK (Hold acknowledge) ··· output
In this mode, this pin is the acknowledge signal output pin that indicates the high impedance status
for the address bus, data bus, and control bus when the V850E/MA1 receives a bus hold request.
While this signal is active, the impedance of the address bus, data bus and control bus becomes
high and the bus mastership is transferred to the external bus master.
(v) HLDRQ (Hold request) ··· input
In this mode, this pin is the input pin through which an external device requests the V850E/MA1 to
release the address bus, data bus, and control bus. The HLDRQ signal can be input asynchronously
to the CLKOUT signal. When this pin is active, the address bus, data bus, and control bus are set to
the high impedance status. This occurs either when the V850E/MA1 completes execution of the
current bus cycle or immediately if no bus cycle is being executed, then the HLDAK signal is set as
active and the bus is released.
In order to make the bus hold state secure, keep the HLDRQ signal active until the HLDAK signal is
output.
(vi) REFRQ (Refresh request) ··· output
This is the refresh request signal for DRAM.
In cases when the address is decoded by an external circuit to increase the connected DRAM, or in
cases when external SIMM’s are connected, this signal is used for RAS control during the refresh
cycle.
This signal becomes active during the refresh cycle. Also, during bus hold, it becomes active when a
refresh request is generated and informs the external bus master that a refresh request was
generated.
(vii) SELFREF (Self-refresh request) ··· input
This is a self-refresh request signal input for DRAM.
The internal ROM and internal RAM can be accessed even in the self-refresh cycle. However,
access to a peripheral I/O register or external device is held pending until the self-refresh cycle is
cancelled.
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PIN FUNCTIONS
(10) PCT0, PCT1, PCT4 to PCT7 (Port CT) ··· 3-state I/O
PCT0, PCT1, PCT4 to PCT7 function as a 6-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as a port, in the control mode, these pins operate as control signal outputs for when
memory is expanded externally.
The operation mode can be set to port or control mode in 1-bit units, specified by the port CT mode control
register (PMCCT).
(a) Port mode
PCT0, PCT1, PCT4 to PCT7 can be set to input or output in 1-bit units using the port CT mode register
(PMCT).
(b) Control mode
PCT0, PCT1, PCT4 to PCT7 can be set to port/control mode in 1-bit units using the PMCCT register.
(i) LCAS (Lower column address strobe) ··· 3-state output
This is the column address strobe signal for DRAM and the strobe signal for the CBR refresh cycle.
For the data bus, the lower byte is valid.
(ii) UCAS (Upper column address strobe) ··· 3-state output
This is the column address strobe signal for DRAM and the strobe signal for the CBR refresh cycle.
For the data bus, the higher byte is valid.
(iii) LWR (Lower byte write strobe) ··· 3-state output
This strobe signal shows whether the bus cycle currently being executed is a write cycle for the
SRAM, external ROM, or external peripheral I/O area.
For the data bus, the lower byte becomes valid. If the bus cycle is a lower memory write, it becomes
active at the falling edge of the CLKOUT signal in the T1 state and becomes inactive at the falling
edge of the CLKOUT signal in the T2 state.
(iv) UWR (Upper byte write strobe) ··· 3-state output
This strobe signal shows whether the bus cycle currently being executed is a write cycle for the
SRAM, external ROM, or external peripheral I/O area.
For the data bus, the higher byte becomes valid. If the bus cycle is a higher memory write, it
becomes active at the falling edge of the CLKOUT signal in the T1 state and becomes inactive at the
falling edge of the CLKOUT signal in the T2 state.
(v) LDQM (Lower DQ mask enable) ··· 3-state output
This is a control signal for the data bus to SDRAM. For the data bus, the lower byte is valid. This
signal carries out SDRAM output disable control during a read operation, and SDRAM byte mask
control during a write operation.
(vi) UDQM (Upper DQ mask enable) ··· 3-state output
This is a control signal for the data bus to SDRAM. For the data bus, the higher byte is valid. This
signal carries out SDRAM output disable control during a read operation, and SDRAM byte mask
control during a write operation.
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(vii) RD (Read strobe) ··· 3-state output
This strobe signal shows that the bus cycle currently being executed is a read cycle for the SRAM,
external ROM, external peripheral I/O, or page ROM area. In the idle state (TI), it becomes inactive.
(viii) WE (Write enable) ··· 3-state output
This signal shows that the bus cycle currently being executed is a write cycle for the DRAM area. In
the idle state (TI), it becomes inactive.
(ix) OE (Output enable) ··· 3-state output
This signal shows that the bus cycle currently being executed is a read cycle for the DRAM area. In
the idle state (TI), it becomes inactive.
(x) BCYST (Bus cycle start timing) ··· 3-state output
This outputs a status signal showing the start of the bus cycle. It becomes active for 1-clock cycle
from the start of each cycle. In the idle state (TI), it becomes inactive.
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PIN FUNCTIONS
(11) PCS0 to PCS7 (Port CS) ··· 3-state I/O
PCS0 to PCS7 function as an 8-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as a port, in the control mode, these pins operate as control signal outputs for when
memory and peripheral I/O are expanded externally.
The operation mode can be set to port or control mode in 1-bit units, specified by the port CS mode control
register (PMCCS).
(a) Port mode
PCS0 to PCS7 can be set to input or output in 1-bit units using the port CS mode register (PMCS).
(b) Control mode
PCS0 to PCS7 can be set to port/control mode in 1-bit units using the PMCCS register.
(i) CS0 to CS7 (Chip select) ··· 3-state output
These are the chip select signals for the SRAM, external ROM, external peripheral I/O, and page
ROM area.
The CSn signal is assigned to memory block n (n = 0 to 7).
It becomes active while the bus cycle that accesses the corresponding memory block is activated.
In the idle state (TI), it becomes inactive.
(ii) RAS1, RAS3, RAS4, RAS6 (Row address strobe) ··· 3-state output
These are the row address strobe signals for the DRAM area and the strobe signal for the refresh
cycle.
The RASn signal is assigned to memory block n (n = 1, 3, 4, 6).
During on-page disable, after the DRAM access bus cycle ends, it becomes inactive.
During on-page enable, even after the DRAM access bus cycle ends, it remains in the active state.
During the reset period and during a bus hold period, it is in the high-impedance state, so connect it
to VDD via a resistor.
(iii) IOWR (I/O write) ··· 3-state output
This is the write strobe signal for external I/O during DMA flyby transfer. It indicates whether the bus
cycle currently being executed is a write cycle for external I/O during flyby transfer, or a write cycle
for the SRAM area.
Note that if the IOEN bit of the BCP register is set (1), this signal can be output even in the normal
SRAM, external ROM, or external I/O cycle.
(iv) IORD (I/O read) ··· 3-state output
This is the read strobe signal for external I/O during DMA flyby transfer. It indicates whether the bus
cycle currently being executed is a read cycle for external I/O during flyby transfer, or a read cycle
for the SRAM area.
Note that if the IOEN bit of the BCP register is set (1), this signal can be output even in the normal
SRAM, external ROM, or external I/O cycle.
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(12) PCD0 to PCD3 (Port CD) ··· 3-state I/O
PCD0 to PCD3 function as a 4-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as a port, in control mode, these pins operate as control signal outputs for when the
memory and peripheral I/O are expanded externally.
The operation mode can be set to port or control mode in 1-bit units, specified by the port CD mode control
register (PMCCD).
(a) Port mode
PCD0 to PCD3 can be set to input or output in 1-bit units using the port CD mode register (PMCD).
(b) Control mode
PCD0 to PCD3 can be set to port or control mode in 1-bit units using the PMCCD register.
(i) SDCKE (SDRAM clock enable) ··· 3-state output
This is the SDRAM clock enable output signal. It becomes inactive in self-refresh and standby
mode.
(ii) SDCLK (SDRAM clock output) ··· 3-state output
This is an SDRAM dedicated clock output signal. The same frequency as the internal system clock
is output.
(iii) SDCAS (SDRAM column address strobe) ··· 3-state output
This is a command output signal for SDRAM.
(iv) SDRAS (SDRAM row address strobe) ··· 3-state output
This is a command output signal for SDRAM.
(v) LBE (Lower byte enable) ··· 3-state output
This is the signal that enables the lower byte of the external data bus.
(vi) UBE (Upper byte enable) ··· 3-state output
This is the signal that enables the higher byte of the external data bus.
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PIN FUNCTIONS
(13) PAH0 to PAH9 (Port AH) ··· 3-state I/O
PAH0 to PAH9 function as an 8- or 10-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as a port, in control mode (external expansion mode), these pins operate as an address
bus (A16 to A25) for when the memory is expanded externally.
The operation mode can be set to port or control mode in 1-bit units, specified by the port AH mode control
register (PMCAH).
(a) Port mode
PAH0 to PAH9 can be set to input or output in 1-bit units using the port AH mode register (PMAH).
(b) Control mode
PAH0 to PAH9 can be set to function alternately as A16 to A25 using the PMCAH register.
(i) A16 to A25 (Address) ··· 3-state output
These are the address output pins of the higher 10 bits of the address bus’s 26-bit address when
the external memory is accessed.
The output changes in synchronization with the fall of the CLKOUT signal in the T1 state. In the idle
state (TI), the address of the bus cycle immediately before is retained.
(14) PAL0 to PAL15 (Port AL) ··· 3-state I/O
PAL0 to PAL15 function as an 8- or 16-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as a port, in control mode (external expansion mode), these pins operate as an address
bus (A0 to A15) for when the memory is expanded externally.
The operation mode can be set to port or control mode in 1-bit units, specified by the port AL mode control
register (PMCAL).
(a) Port mode
PAL0 to PAL15 can be set to input or output in 1-bit units using the port AL mode register (PMAL).
(b) Control mode
PAL0 to PAL15 can be set to function alternately as A0 to A15 using the PMCAL register.
(i) A0 to A15 (Address) ··· 3-state output
These are the address output pins of the lower 16 bits of the address bus’s 26-bit address when the
external memory is accessed.
The output changes in synchronization with the fall of the CLKOUT signal in the T1 state. In the idle
state (TI), the address of the bus cycle immediately before is retained.
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(15) PDL0 to PDL15 (Port DL) ··· 3-state I/O
PDL0 to PDL15 function as an 8- or 16-bit I/O port that can be set to input or output in 1-bit units.
Besides functioning as a port, in control mode (external expansion mode), these pins operate as a data bus
(D0 to D15) for when the memory is expanded externally.
The operation mode can be set to port or control mode in 1-bit units, specified by the port DL mode control
register (PMCDL).
(a) Port mode
PDL0 to PDL15 can be set to input or output in 1-bit units using the port DL mode register (PMDL).
(b) Control mode
PDL0 to PDL15 can be set to function alternately as D0 to D15 using the PMCDL register.
(i) D0 to D15 (Data) ··· 3-state I/O
These pins constitute a data bus for when the external memory is accessed. These are 16-bit data
I/O bus pins.
The output changes in synchronization with the rise of the CLKOUT signal in the T1 state. In the
idle state (TI), these pins become high impedance.
(16) CKSEL (Clock generator operating mode select) ··· input
This is an input pin used to specify the clock generator’s operating mode.
(17) MODE0 to MODE2 (Mode) ··· input
These are input pins used to specify the operating mode.
(18) RESET (Reset) ··· input
RESET is a signal that is input asynchronously and that has a constant low level width regardless of the
operating clock’s status. When this signal is input, a system reset is executed as the first priority ahead of all
other operations.
In addition to being used for ordinary initialization/start operations, this pin can also be used to release a
standby mode (HALT, IDLE, or software STOP).
(19) X1, X2 (Crystal)
These pins are used to connect the resonator that generates the system clock.
(20) CVDD (Power supply for clock generator)
This pin supplies positive power to the clock generator.
(21) CVSS (Ground for clock generator)
This is the ground pin for the clock generator.
(22) VDD (Power supply)
These are the positive power supply pins for each internal unit. All the VDD pins should be connected to a
positive power source.
(23) VSS (Ground)
These are ground pins. All the VSS pins should be grounded.
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(24) AVDD (Analog power supply)
This is the analog positive power supply pin for the A/D converter.
(25) AVSS (Analog ground)
This is the ground pin for the A/D converter.
(26) AVREF (Analog reference voltage) ··· input
This is the reference voltage supply pin for the A/D converter.
(27) VPP (Programming power supply)
This is the positive power supply pin used for flash memory programming mode.
This pin is used for the µPD70F3107.
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2.4
PIN FUNCTIONS
Pin I/O Circuits and Recommended Connection of Unused Pins
It is recommended that 1 to 10 kΩ resistors be used when connecting to VDD or VSS via resistors.
(1/2)
Pin Name
I/O Circuit Type
P00/PWM0
5
P01/INTP000/TI000
5-AC
Recommended Connection
Independently connect to VDD or VSS
via a resistor
Output: Leave open
Input:
P02/INTP001
P03/TO00
5
P04/DMARQ0/INTP100 to P07/DMARQ3/INTP103
P10/PWM1
P11/INTP010/TI010, P12/INTP011
5-AC
5
5-AC
P13/TO01
5
P20/NMI
2
P21/INTP020/TI020, P22/INTP021
P23/TO02
P24/TC0/INTP110 to P27/TC3/INTP113
5-AC
5
Connect to VSS directly.
Independently connect to VDD or VSS
via a resistor
Output: Leave open
Input:
5-AC
P30/SO2/INTP130
P31/SI2/INTP131
P32/SCK2/INTP132
P33/TXD2/INTP133
P34/RXD2/INTP120
P35/INTP121
P36/INTP122
P37/ADTRG/INTP123
P40/TXD0/SO0
5
P41/RXD0/SI0
5-AC
P42/SCK0
P43/TXD1/SO1
5
P44/RXD1/SI1
5-AC
P45/SCK1
P50/INTP030/TI030, P51/INTP031
P52/TO03
5
P70/ANI0 to P77/ANI7
9
Connect to VSS directly.
PBD0/DMAAK0 to PBD3/DMAAK3
5
Input:
Independently connect to VDD or VSS
via a resistor
Output: Leave open
PCM0/WAIT
5
Input:
PCM1/CLKOUT/BUSCLK
5
Input:
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Independently connect to VDD via a
resistor
Independently connect to VDD or VSS
via a resistor
Output: Leave open
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PIN FUNCTIONS
(2/2)
Pin Name
I/O Circuit Type
Recommended Connection
PCM2/HLDAK
5
Independently connect to VDD or VSS
via a resistor
Output: Leave open
PCM3/HLDRQ
5
Input:
PCM4/REFRQ
5
Input:
Independently connect to VDD or VSS
via a resistor
Output: Leave open
PCM5/SELFREF
5
Input:
PCT0/LCAS/LWR/LDQM
5
Independently connect to VDD or VSS
via a resistor
Output: Leave open
PCT1/UCAS/UWR/UDQM
Input:
Independently connect to VDD via a
resistor
Independently connect to VSS via a
resistor
Input:
PCT4/RD
PCT5/WE
PCT6/OE
PCT7/BCYST
PCS0/CS0
PCS1/CS1/RAS1
PCS2/CS2/IOWR
PCS3/CS3/RAS3
PCS4/CS4/RAS4
PCS5/CS5/IORD
PCS6/CS6/RAS6
PCS7/CS7
PCD0/SDCKE
PCD1/SDCLK
PCD2/LBE/SDCAS
PCD3/UBE/SDRAS
PAH0/A16 to PAH9/A25
PAL0/A0 to PAL15/A15
PDL0/D0 to PDL15/D15
MODE0, MODE1
−
2
Note 1
MODE2
Note 2
MODE2/VPP
−
RESET
−
CKSEL
1
AVSS
−
Connect to VSS.
AVDD/AVREF
−
Connect to VDD.
Notes 1.
2.
62
µPD703103, 703105, 703106, 703107 only.
µPD70F3107 only
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2.5
PIN FUNCTIONS
Pin I/O Circuits
Type 1
Type 5-AC
VDD
VDD
Data
P-ch
IN/OUT
P-ch
IN
Output
disable
N-ch
N-ch
Input
enable
Type 2
Type 9
P-ch
IN
IN
+
Comparator
N-ch
VREF (threshold voltage)
Schmitt-triggered input with hysteresis characteristics
Input enable
Type 5
VDD
Data
P-ch
IN/OUT
Output
disable
N-ch
Input
enable
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CHAPTER 3 CPU FUNCTION
The CPU of the V850E/MA1 is based on RISC architecture and executes almost all the instructions in one clock
cycle using 5-stage pipeline control.
3.1
Features
• Minimum instruction cycle: 20 ns (@ 50 MHz internal operation)
• Memory space
Program space: 64 MB linear
Data space:
4 GB linear
• Thirty-two 32-bit general-purpose registers
• Internal 32-bit architecture
• Five-stage pipeline control
• Multiply/divide instructions
• Saturated operation instructions
• One-clock 32-bit shift instruction
• Long/short instruction format
• Four types of bit manipulation instructions
• SET1
• CLR1
• NOT1
• TST1
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3.2
CPU FUNCTION
CPU Register Set
The registers of the V850E/MA1 can be classified into two categories: a general-purpose program register set and
a dedicated system register set. All the registers have a 32-bit width.
For details, refer to V850E1 User’s Manual Architecture.
(1) Program register set
31
r0
(2) System register set
0
31
0
(Zero register)
EIPC
(Status saving register during interrupt)
(Assembler-reserved register)
EIPSW
(Status saving register during interrupt)
r3
(Stack pointer (SP))
FEPC
(Status saving register during NMI)
r4
(Global pointer (GP))
FEPSW (Status saving register during NMI)
r5
(Text pointer (TP))
r1
r2
r6
ECR
(Interrrupt source register)
PSW
(Program status word)
CTPC
(Status saving register during CALLT execution)
r7
r8
r9
r10
r11
CTPSW (Status saving register during CALLT execution)
r12
r13
DBPC
r14
(Status saving register during exception/debug trap)
DBPSW (Status saving register during exception/debug trap)
r15
r16
CTBP
r17
(CALLT base pointer)
r18
r19
r20
r21
r22
r23
r24
r25
r26
r27
r28
r29
r30
(Element pointer (EP))
r31
(Link pointer (LP))
31
PC
0
(Program counter)
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3.2.1
CPU FUNCTION
Program register set
The program register set includes general-purpose registers and a program counter.
(1) General-purpose registers
Thirty-two general-purpose registers, r0 to r31, are available. Any of these registers can be used as a data
variable or address variable.
However, r0 and r30 are implicitly used by instructions, and care must be exercised when using these
registers. r0 is a register that always holds 0, and is used for operations using 0 and offset 0 addressing. r30
is used, by means of the SLD and SST instructions, as a base pointer for when memory is accessed. Also,
r1, r3 to r5, and r31 are implicitly used by the assembler and C compiler. Therefore, before using these
registers, their contents must be saved so that they are not lost. The contents must be restored to the
registers after the registers have been used. r2 may be used by the real-time OS. If the real-time OS does
not use r2, it can be used as a variable register.
Table 3-1. Program Registers
Name
Usage
Operation
r0
Zero register
Always holds 0
r1
Assembler-reserved register
Working register for generating 32-bit immediate data
r2
Address/data variable register (when r2 is not used by the real-time OS)
r3
Stack pointer
Used to generate stack frame when function is called
r4
Global pointer
Used to access global variable in data area
r5
Text pointer
Register to indicate the start of the text area (where program
code is located)
r6 to r29
Address/data variable registers
r30
Element pointer
Base pointer when memory is accessed
r31
Link pointer
Used by compiler when calling function
PC
Program counter
Holds instruction address during program execution
(2) Program counter
This register holds the instruction address during program execution. The lower 26 bits of this register are
valid, and bits 31 to 26 are fixed to 0. If a carry occurs from bit 25 to 26, it is ignored.
Bit 0 is fixed to 0, and branching to an odd address cannot be performed.
Figure 3-1. Program Counter (PC)
31
PC
66
26 25
Fixed to 0
1 0
Instruction address during execution
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0
After reset
00000000H
CHAPTER 3
3.2.2
CPU FUNCTION
System register set
System registers control the status of the CPU and hold interrupt information.
To read/write these system registers, specify a system register number indicated below using the system register
load/store instruction (LDSR or STSR instruction).
Table 3-2. System Register Numbers
No.
System Register Name
Operand Specification
LDSR Instruction
STSR Instruction
0
Status saving register during interrupt (EIPC)
{
{
1
Status saving register during interrupt (EIPSW)
{
{
2
Status saving register during NMI (FEPC)
{
{
3
Status saving register during NMI (FEPSW)
{
{
4
Interrupt source register (ECR)
×
{
Note 1
Program status word (PSW)
{
{
Reserved for future function expansion (operations that access these
register numbers cannot be guaranteed).
×
×
16
Status saving register during CALLT execution (CTPC)
{
{
17
Status saving register during CALLT execution (CTPSW)
{
{
5
6 to 15
18
Status saving register during exception/debug trap (DBPC)
{
19
Status saving register during exception/debug trap (DBPSW)
{Note 2
{
CALLT base pointer (CTBP)
{
{
Reserved for future function expansion (operations that access these
register numbers cannot be guaranteed).
×
×
20
21 to 31
Notes 1.
Note 2
{
Because this register has only one set, to approve multiple interrupts, it is necessary to save this
register by program.
2.
Caution
Access is only possible when the DBTRAP instruction is executed.
Even if bit 0 of EIPC, FEPC, or CTPC is set to 1 with the LDSR instruction, bit 0 will be ignored
when the program is returned by the RETI instruction after interrupt servicing (because bit 0 of
the PC is fixed to 0). When setting the value of EIPC, FEPC, or CTPC, use an even value (bit 0 =
0).
Remark
{: Access allowed
×: Access prohibited
Figure 3-2. Interrupt Source Register (ECR)
31
16 15
ECR
Bit position
FECC
0
EICC
Bit name
After reset
00000000H
Function
31 to 16
FECC
Exception code of non-maskable interrupt (NMI)
15 to 0
EICC
Exception code of exception/maskable interrupt
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CPU FUNCTION
Figure 3-3. Program Status Word (PSW)
31
8 7 6 5 4 3 2 1 0
PSW
NP EP ID SAT CY OV S Z
RFU
After reset
00000020H
Bit position
Flag
31 to 8
RFU
7
NP
Indicates that non-maskable interrupt (NMI) servicing is in progress. This flag is
set when an NMI is acknowledged, and disables multiple interrupts.
0: NMI servicing not under execution.
1: NMI servicing under execution.
6
EP
Indicates that exception processing is in progress. This flag is set when an
exception is generated. Moreover, interrupt requests can be acknowledged
when this bit is set.
0: Exception processing not under execution.
1: Exception processing under execution.
5
ID
Indicates whether a maskable interrupt request can be acknowledged or not.
0: Interrupt enabled.
1: Interrupt disabled.
4
SAT
3
CY
2
OV
1
S
0
Note
Note
Function
Reserved field (fixed to 0).
Indicates that the operation result of a saturated operation processing instruction
is saturated due to overflow. Due to the cumulative flag, if the operation result is
saturated by the saturation operation instruction, this bit is set (1), but is not
cleared (0) even if the operation results of subsequent instructions are not
saturated. To clear (0) this bit, load data in PSW. Note that in a general
arithmetic operation, this bit is neither set (1) nor cleared (0).
0: Not saturated.
1: Saturated.
This flag is set if a carry or borrow occurs as the result of an operation (if a carry
or borrow does not occur, it is reset).
0: Carry or borrow does not occur.
1: Carry or borrow occurs.
This flag is set if an overflow occurs during operation (if an overflow does not
occur, it is reset).
0: Overflow does not occur.
1: Overflow occurs.
Note
This flag is set if the result of an operation is negative (it is reset if the result is
positive).
0: The operation result was positive or 0.
1: The operation result was negative.
Z
This flag is set if the result of an operation is zero (if the result is not zero, it is
reset).
0: The operation result was not 0.
1: The operation result was 0.
Note The result of a saturation-processed operation is determined by the contents of the OV and S flags in the
saturation operation. Simply setting the OV flag (1) will set the SAT flag (1) in a saturation operation.
Status of operation result
Flag status
SAT
S
Maximum positive value exceeded
1
1
0
7FFFFFFFH
Maximum negative value exceeded
1
1
1
80000000H
Positive (not exceeding the maximum)
Retains
the value
before
operation
0
0
Operation result itself
Negative (not exceeding the maximum)
68
OV
Saturation-processed
operation result
1
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3.3
CPU FUNCTION
Operating Modes
3.3.1
Operating modes
The V850E/MA1 has the following operating modes.
Mode specification is carried out using the MODE0 to
MODE2 pins.
(1) Normal operation mode
(a) Single-chip modes 0, 1
Access to the internal ROM is enabled.
In single-chip mode 0, after system reset is cleared, each pin related to the bus interface enters the port
mode, program execution branches to the reset entry address of the internal ROM, and instruction
processing starts. By setting the PMCAL, PMCAH, PMCDL, PMCCS, PMCCT, PMCCM, and PMCCD
registers to control mode by instruction, an external device can be connected to the external memory
area.
In single-chip mode 1, after system reset is cleared, each pin related to the bus interface enters the
control mode, program execution branches to the external device’s (memory) reset entry address, and
instruction processing starts.
The internal ROM area is mapped from address 100000H.
(b) ROMless modes 0, 1
After system reset is cleared, each pin related to the bus interface enters the control mode, program
execution branches to the external device’s (memory) reset entry address, and instruction processing
starts. Fetching of instructions and data access for internal ROM becomes impossible.
In ROMless mode 0, the data bus is a 16-bit data bus and in ROMless mode 1, the data bus is an 8-bit
data bus.
(2) Flash memory programming mode (µPD70F3107 only)
If this mode is specified, it becomes possible for the flash programmer to run a program to the on-chip flash
memory.
The initial value of the register differs depending on the mode.
Operating Mode
Normal
operation
mode
PMCAL
PMCAH
PMCDL
PMCCS
PMCCT
PMCCM
PMCCD
BSC
ROMless mode 0
FFFFH
03FFH
FFFFH
FFH
F3H
3FH
0FH
5555H
ROMless mode 1
FFFFH
03FFH
FFFFH
FFH
F3H
3FH
0FH
0000H
Single-chip mode 0
0000H
0000H
0000H
00H
00H
00H
00H
5555H
Single-chip mode 1
FFFFH
03FFH
FFFFH
FFH
F3H
3FH
0FH
5555H
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3.3.2
CPU FUNCTION
Operating mode specification
The operating mode is specified according to the status of the MODE0 to MODE2 pins. In an application system
fix the specification of these pins and do not change them during operation. Operation is not guaranteed if these pins
are changed during operation.
(a) µPD703103
MODE2
MODE1
MODE0
L
L
L
L
L
H
Other than above
Operating Mode
Normal operation mode
Remarks
ROMless mode 0
16-bit data bus
ROMless mode 1
8-bit data bus
Setting prohibited
(b) µPD703105, 703106, 703107
MODE2
MODE1
MODE0
L
L
L
L
L
L
L
Operating Mode
Remarks
ROMless mode 0
16-bit data bus
H
ROMless mode 1
8-bit data bus
H
L
Single-chip mode 0
Internal ROM area is allocated
from address 000000H.
H
H
Single-chip mode 1
Internal ROM area is allocated
from address 100000H.
Other than above
Normal operation mode
Setting prohibited
(c) µPD70F3107
MODE2/
VPP
MODE1
MODE0
0V
L
L
0V
L
0V
Remarks
ROMless mode 0
16-bit data bus
H
ROMless mode 1
8-bit data bus
H
L
Single-chip mode 0
Internal ROM area is allocated
from address 000000H.
0V
H
H
Single-chip mode 1
Internal ROM area is allocated
from address 100000H.
7.8 V
H
H/L
Other than above
70
Operating Mode
Remarks L:
Low-level input
H:
High-level input
Normal operation mode
Flash memory programming mode
Setting prohibited
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CHAPTER 3
3.4
3.4.1
CPU FUNCTION
Address Space
CPU address space
The CPU of the V850E/MA1 is of 32-bit architecture and supports up to 4 GB of linear address space (data space)
during operand addressing (data access). Also, in instruction address addressing, a maximum of 64 MB of linear
address space (program space) is supported.
Figure 3-4 shows the CPU address space.
Figure 3-4. CPU Address Space
CPU address space
FFFFFFFFH
Data area
(4 GB linear)
04000000H
03FFFFFFH
Program area
(64 MB linear)
00000000H
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CHAPTER 3
3.4.2
CPU FUNCTION
Image
A 256 MB physical address space is seen as 16 images in the 4 GB CPU address space. In actuality, the same
256 MB physical address space is accessed regardless of the values of bits 31 to 28 of the CPU address. Figure 3-5
shows the image of the virtual addressing space.
Physical address x0000000H can be seen as CPU address 00000000H, and in addition, can be seen as address
10000000H, address 20000000H, … , address E0000000H, or address F0000000H.
Figure 3-5. Images on Address Space
CPU address space
FFFFFFFFH
Image
F0000000H
EFFFFFFFH
Image
Physical address space
E0000000H
DFFFFFFFH
Peripheral I/O
FFFFFFFH
Internal RAM
Image
External memory
20000000H
1FFFFFFFH
Internal ROM
Image
10000000H
0FFFFFFFH
Image
00000000H
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0000000H
CHAPTER 3
3.4.3
CPU FUNCTION
Wrap-around of CPU address space
(1) Program space
Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0, and only the lower 26 bits are
valid. Even if a carry or borrow occurs from bit 25 to 26 as a result of a branch address calculation, the
higher 6 bits ignore the carry or borrow.
Therefore, the lower-limit address of the program space, address 00000000H, and the upper-limit address
03FFFFFFH become contiguous addresses. Wrap-around refers to a situation like this whereby the lowerlimit address and upper-limit address become contiguous.
Caution
The 4 KB area of 03FFF000H to 03FFFFFFH can be seen as an image of 0FFFF000H to
0FFFFFFFH. No instruction can be fetched from this area because this area is defined as
peripheral I/O area. Therefore, do not execute any branch address calculation in which the
result will reside in any part of this area.
03FFFFFEH
Program space
03FFFFFFH
(+) direction
( ) direction
00000000H
00000001H
Program space
(2) Data space
The result of an operand address calculation that exceeds 32 bits is ignored.
Therefore, the lower-limit address of the program space, address 00000000H, and the upper-limit address
FFFFFFFFH are contiguous addresses, and the data space is wrapped around at the boundary of these
addresses.
FFFFFFFEH
Data space
FFFFFFFFH
(+) direction
( ) direction
00000000H
00000001H
Data space
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3.4.4
CPU FUNCTION
Memory map
The V850E/MA1 reserves areas as shown in Figures 3-6 and 3-7. The mode is specified by the MODE0 to
MODE2 pins.
Figure 3-6. Memory Map (µPD703103, 703105)
Single-chip mode 0
Single-chip mode 1
ROMless mode 0, 1
Internal peripheral
Internal peripheral
Internal peripheral
I/O area
I/O area
I/O area
Internal RAM area
Internal RAM area
Internal RAM area
xFFFFFFFH
4 KB
xFFFF000H
xFFFEFFFH
xFFFD000H
xFFFCFFFH
4 KB
xFFFC000H
xFFFBFFFH
256 MB
Access prohibitedNote
External memory
area
External memory
area
x0200000H
x01FFFFFH
Internal ROM area
1 MB
External memory
area
1 MB
x0100000H
x00FFFFFH
Internal ROM area
x0000000H
Note By setting the PMCAL, PMCAH, PMCDL, PMCCS, PMCCT, PMCCM, and PMCCD registers to control
mode, this area can be used as external memory area.
Remark
74
For the µPD703103, only ROMless modes 0 and 1 are supported as the operating mode.
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CPU FUNCTION
Figure 3-7. Memory Map (µPD703106, 703107, 70F3107)
Single-chip mode 0
Single-chip mode 1
ROMless mode 0, 1
Internal peripheral
Internal peripheral
Internal peripheral
I/O area
I/O area
I/O area
Internal RAM area
Internal RAM area
Internal RAM area
xFFFFFFFH
4 KB
xFFFF000H
xFFFEFFFH
xFFFE800H
xFFFE7FFH
10 KB
xFFFC000H
xFFFBFFFH
256 MB
Access prohibitedNote
External memory
area
External memory
area
x0200000H
x01FFFFFH
Internal ROM area
1 MB
External memory
area
1 MB
x0100000H
x00FFFFFH
Internal ROM area
x0000000H
Note By setting the PMCAL, PMCAH, PMCDL, PMCCS, PMCCT, PMCCM, and PMCCD registers to control
mode, this area can be used as external memory area.
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CHAPTER 3
3.4.5
CPU FUNCTION
Area
(1) Internal ROM area
(a) Memory map (µPD703105, 703106, 703107, 70F3107)
1 MB of internal ROM area, addresses 00000H to FFFFFH, is reserved.
<1> µPD703105, 703106
128 KB are provided at the following addresses as physical internal ROM (mask ROM).
• In single-chip mode 0: Addresses 000000H to 01FFFFH
• In single-chip mode 1: Addresses 100000H to 11FFFFH
<2> µPD703107
256 KB are provided at the following addresses as physical internal ROM (mask ROM).
• In single-chip mode 0: Addresses 000000H to 03FFFFH
• In single-chip mode 1: Addresses 100000H to 13FFFFH
<3> µPD70F3107
256 KB are provided at the following addresses as physical internal ROM (flash memory).
• In single-chip mode 0: Addresses 000000H to 03FFFFH
• In single-chip mode 1: Addresses 100000H to 13FFFFH
(b) Interrupt/exception table
The V850E/MA1 increases the interrupt response speed by assigning handler addresses corresponding
to interrupts/exceptions.
The collection of these handler addresses is called an interrupt/exception table, which is located in the
internal ROM area.
When an interrupt/exception request is acknowledged, execution jumps to the
handler address, and the program written in that memory is executed. Table 3-3 shows the sources of
interrupts/exceptions, and the corresponding addresses.
Remark
When in ROMless modes 0 and 1, in single-chip mode 1, or in the case of the µPD703103, in
order to restore correct operation after reset, provide a handler address to the reset routine at
address 0 of the external memory.
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Table 3-3. Interrupt/Exception Table (1/2)
Start Address of Interrupt/Exception Table
Interrupt/Exception Source
00000000H
RESET
00000010H
NMI
00000040H
TRAP0n (n = 0 to F)
00000050H
TRAP1n (n = 0 to F)
00000060H
ILGOP/DBG0
00000080H
INTOV00
00000090H
INTOV01
000000A0H
INTOV02
000000B0H
INTOV03
000000C0H
INTP000/INTM000
000000D0H
INTP001/INTM001
000000E0H
INTP010/INTM010
000000F0H
INTP011/INTM011
00000100H
INTP020/INTM020
00000110H
INTP021/INTM021
00000120H
INTP030/INTM030
00000130H
INTP031/INTM031
00000140H
INTP100
00000150H
INTP101
00000160H
INTP102
00000170H
INTP103
00000180H
INTP110
00000190H
INTP111
000001A0H
INTP112
000001B0H
INTP113
000001C0H
INTP120
000001D0H
INTP121
000001E0H
INTP122
000001F0H
INTP123
00000200H
INTP130
00000210H
INTP131
00000220H
INTP132
00000230H
INTP133
00000240H
INTCMD0
00000250H
INTCMD1
00000260H
INTCMD2
00000270H
INTCMD3
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Table 3-3. Interrupt/Exception Table (2/2)
Start Address of Interrupt/Exception Table
Interrupt/Exception Source
00000280H
INTDMA0
00000290H
INTDMA1
000002A0H
INTDMA2
000002B0H
INTDMA3
000002C0H
INTCSI0
000002D0H
INTSER0
000002E0H
INTSR0
000002F0H
INTST0
00000300H
INTCSI1
00000310H
INTSER1
00000320H
INTSR1
00000330H
INTST1
00000340H
INTCSI2
00000350H
INTSER2
00000360H
INTSR2
00000370H
INTST2
00000380H
INTAD
(c) Internal ROM area relocation function
If set in single-chip mode 1, the internal ROM area is located beginning from address 100000H, so
booting from external memory becomes possible.
Therefore, in order to resume correct operation after reset, provide a handler address to the reset routine
at address 0 of the external memory.
Figure 3-8. Internal ROM Area in Single-Chip Mode 1
200000H
1FFFFFH
Internal ROM area
100000H
0FFFFFH
Block 0
External memory area
000000H
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(2) Internal RAM area
The 12 KB of addresses FFFC000H to FFFEFFFH are reserved for the internal RAM area.
The 12 KB area of 3FFC000H to 3FFEFFFH can be seen as an image of FFFC000H to FFFEFFFH. When
the internal RAM area is used as the program space, access addresses 3FFC000H to 3FFEFFFH.
In the µPD703103 and 703105, the 4 KB of addresses FFFC000H to FFFCFFFH are provided as physical
internal RAM.
In the µPD703106, 703107, and 70F3107, the 10 KB of addresses FFFC000H to FFFE7FFH are provided as
physical internal RAM.
µPD703103, 703105
FFFEFFFH
µPD703106, 703107, 70F3107
FFFEFFFH
FFFE800H
FFFE7FFH
Internal RAM area (10 KB)
FFFD000H
FFFCFFFH
Internal RAM area (4 KB)
FFFC000H
FFFC000H
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(3) Internal peripheral I/O area
4 KB of memory, addresses FFFF000H to FFFFFFFH, are provided as an internal peripheral I/O area.
Note
An image of addresses FFFF000H to FFFFFFFH can be seen at addresses 3FFF000H to 3FFFFFFH
.
Note Addresses 3FFF000H to 3FFFFFFH are access-prohibited. To access the internal peripheral I/O of
this area, specify addresses FFFF000H to FFFFFFFH.
FFFFFFFH
Internal peripheral I/O area
(4 KB)
FFFF000H
Peripheral I/O registers associated with the operating mode specification and the state monitoring for the
internal peripheral I/O are all memory-mapped to the internal peripheral I/O area. Program fetches cannot be
executed from this area.
Cautions 1. In the V850E/MA1, no registers exist which are capable of word access, but if a register
is word accessed, halfword access is performed twice in the order of lower address,
then higher address of the word area, disregarding the lower 2 bits of the address.
2. For registers in which byte access is possible, if halfword access is executed, the
higher 8 bits become undefined during the read operation, and the lower 8 bits of data
are written to the register during the write operation.
3. Addresses that are not defined as registers are reserved for future expansion. If these
addresses are accessed, the operation is undefined and not guaranteed.
4. Addresses 3FFF000H to 3FFFFFFH cannot be specified as the source/destination
address of DMA transfer. Be sure to use addresses FFFF000H to FFFFFFFH for the
source/destination address of DMA transfer.
(4) External memory area
256 MB are available for external memory area. The lower 64 MB can be used as program/data area and the
higher 192 MB as data area.
When in single-chip mode 0:
x0100000H to xFFFBFFFH
When in single-chip mode 1:
x0000000H to x00FFFFFH, x0200000H to xFFFBFFFH
When in ROMless modes 0 and 1:
x0000000H to xFFFBFFFH
Access to the external memory area uses the chip select signal assigned to each memory block (which is
carried out in the CS unit set by chip area select control registers 0 and 1 (CSC0, CSC1)).
Note that the internal ROM, internal RAM, and internal peripheral I/O areas cannot be accessed as external
memory areas.
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3.4.6
CPU FUNCTION
External memory expansion
By setting the port n mode control register (PMCn) to control mode, an external memory device can be connected
to the external memory space using each pin of ports AL, AH, DL, CS, CT, CM, and CD. Each register is set by
selecting control mode for each pin of these ports using PMCn (n = AL, AH, DL, CS, CT, CM, CD).
Note that the status after reset differs as shown below in accordance with the operating mode specification set by
pins MODE0 to MODE2 (refer to 3.3 Operating Modes for details of the operating modes).
(a) In the case of ROMless mode 0
Because each pin of ports AL, AH, DL, CS, CT, CM, and CD enters control mode following a reset,
external memory can be used without making changes to the port n mode control register (PMCn) (the
external data bus width is 16 bits).
(b) In the case of ROMless mode 1
Because each pin of ports AL, AH, DL, CS, CT, CM, and CD enters control mode following a reset,
external memory can be used without making changes to the port n mode control register (PMCn) (the
external data bus width is 8 bits).
(c) In the case of single-chip mode 0
After reset, since the internal ROM area is accessed, each pin of ports AL, AH, DL, CS, CT, CM, and CD
enters the port mode and external devices cannot be used.
To use external memory, set the port n mode control register (PMCn).
(d) In the case of single-chip mode 1
The internal ROM area is allocated from address 100000H. As a result, because each pin of ports AL,
AH, DL, CS, CT, CM, and CD enters control mode following a reset, external memory can be used
without making changes to the port n mode control register (PMCn) (the external data bus width is 16
bits).
Remark
n = AL, AH, DL, CS, CT, CM, CD
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CHAPTER 3
3.4.7
CPU FUNCTION
Recommended use of address space
The architecture of the V850E/MA1 requires that a register that serves as a pointer be secured for address
generation in operand data accessing of data space. Operand data access from instruction can be directly executed
at the address in this pointer register ±32 KB. However, because the general-purpose registers that can be used as a
pointer register are limited, by minimizing the deterioration of address calculation performance when changing the
pointer value, the number of usable general-purpose registers for handling variables is maximized, and the program
size can be saved.
(1) Program space
Of the 32 bits of the PC (program counter), the higher 6 bits are fixed to 0, and only the lower 26 bits are
valid. Therefore, a contiguous 64 MB space, starting from address 00000000H, unconditionally corresponds
to the memory map of the program space.
When the internal RAM area is used as program space, access addresses 3FFC000H to 3FFEFFFH.
(2) Data space
With the V850E/MA1, a 256 MB physical address space is seen as 16 images in the 4 GB CPU address
space. The highest bit (bit 25) of this 26-bit address is assigned as an address sign-extended to 32 bits.
Example Application of wrap-around (µPD703105)
0001FFFFH
00007FFFH
Internal ROM area
32 KB
Internal peripheral
I/O area
4 KB
Internal RAM area
4 KB
External memory
area
16 KB
(R=) 00000000H
FFFFF000H
FFFFEFFFH
FFFFD000H
FFFFCFFFH
FFFFC000H
FFFFBFFFH
FFFF8000H
When R = r0 (zero register) is specified with the LD/ST disp16 [R] instruction, an addressing range of
00000000H ±32 KB can be referenced with the sign-extended disp 16. By mapping the external memory in
the 16 KB area in the figure, all resources including internal hardware can be accessed with one pointer.
The zero register (r0) is a register set to 0 by the hardware, and eliminates the need for additional registers
for the pointer.
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Figure 3-9. Recommended Memory Map
Program space
Data space
FFFFFFFFH
FFFFFC14H
FFFFFC13H
On-chip
peripheral I/O
FFFFF000H
FFFFEFFFH
xFFFFFFFH
xFFFFC14H
xFFFFC13H
Internal RAM
FFFFC000H
FFFFBFFFH
On-chip
peripheral I/O
xFFFF000H
xFFFEFFFH
xFFFD000H
xFFFCFFFH
Internal RAM
04000000H
03FFFFFFH
03FFF000H
03FFEFFFH
xFFFC000H
xFFFFBFFFH
On-chip
peripheral I/ONote
03FFD000H
03FFCFFFH
Internal RAM
03FFC000H
03FFBFFFH
Program space
64 MB
External
memory
External
memory
External
memory
x0100000H
x00FFFFFH
x0020000H
x001FFFFH
Internal ROM
x0000000H
00100000H
000FFFFFH
00020000H
0001FFFFH
Internal ROM
Internal ROM
00000000H
Note This area is access-prohibited. To access the on-chip peripheral I/O of this area, specify addresses
FFFF000H to FFFFFFFH.
Remarks 1. The arrows indicate the recommended area.
2. This is a recommended memory map when the µPD703105 is set to single-chip mode 0, and
used in external expansion mode.
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CHAPTER 3
3.4.8
CPU FUNCTION
Peripheral I/O registers
(1/9)
Address
Function Register Name
Symbol
R/W
Bit Units for Manipulation
1 Bit
FFFFF000H
8 Bits
After Reset
16 Bits
{
Port AL
PAL
R/W
FFFFF000H
Port ALL
PALL
R/W
{
{
Undefined
FFFFF001H
Port ALH
PALH
R/W
{
{
Undefined
Port AH
PAH
R/W
FFFFF002H
Port AHL
PAHL
R/W
{
{
Undefined
FFFFF003H
Port AHH
PAHH
R/W
{
{
Undefined
Port DL
PDL
R/W
FFFFF004H
Port DLL
PDLL
R/W
{
{
Undefined
FFFFF005H
Port DLH
PDLH
R/W
{
{
Undefined
FFFFF008H
Port CS
PCS
R/W
{
{
Undefined
FFFFF00AH
Port CT
PCT
R/W
{
{
Undefined
FFFFF00CH
Port CM
PCM
R/W
{
{
Undefined
FFFFF00EH
Port CD
PCD
R/W
{
{
Undefined
FFFFF012H
Port BD
PBD
R/W
{
{
Undefined
FFFFF020H
Port AL mode register
PMAL
R/W
FFFFF020H
Port AL mode register L
PMALL
R/W
{
{
FFH
FFFFF021H
Port AL mode register H
PMALH
R/W
{
{
FFH
Port AH mode register
PMAH
R/W
FFFFF022H
Port AH mode register L
PMAHL
R/W
{
{
FFH
FFFFF023H
Port AH mode register H
PMAHH
R/W
{
{
FFH
Port DL mode register
PMDL
R/W
FFFFF024H
Port DL mode register L
PMDLL
R/W
{
{
FFH
FFFFF025H
Port DL mode register H
PMDLH
R/W
{
{
FFH
FFFFF028H
Port CS mode register
PMCS
R/W
{
{
FFH
FFFFF02AH
Port CT mode register
PMCT
R/W
{
{
FFH
FFFFF02CH
Port CM mode register
PMCM
R/W
{
{
FFH
FFFFF02EH
Port CD mode register
PMCD
R/W
{
{
FFH
FFFFF032H
Port BD mode register
PMBD
R/W
{
{
FFH
FFFFF040H
Port AL mode control register
PMCAL
R/W
FFFFF040H
Port AL mode control register L
PMCALL
R/W
{
{
00H/FFH
FFFFF041H
Port AL mode control register H
PMCALH
R/W
{
{
00H/FFH
Port AH mode control register
PMCAH
R/W
FFFFF042H
Port AH mode control register L
PMCAHL
R/W
{
{
00H/FFH
FFFFF043H
Port AH mode control register H
PMCAHH
R/W
{
{
00H/03H
FFFFF002H
FFFFF004H
FFFFF022H
FFFFF024H
FFFFF042H
84
User’s Manual U14359EJ3V0UM
{
{
{
{
{
{
{
Undefined
Undefined
Undefined
FFFFH
FFFFH
FFFFH
0000H/FFFFH
0000H/03FFH
CHAPTER 3
CPU FUNCTION
(2/9)
Address
Function Register Name
Symbol
R/W
Bit Units for Manipulation
1 Bit
FFFFF044H
8 Bits
After Reset
16 Bits
{
Port DL mode control register
PMCDL
R/W
FFFFF044H
Port DL mode control register L
PMCDLL
R/W
{
{
00H/FFH
FFFFF045H
Port DL mode control register H
PMCDLH
R/W
{
{
00H/FFH
FFFFF048H
Port CS mode control register
PMCCS
R/W
{
{
00H/FFH
FFFFF049H
Port CS function control register
PFCCS
R/W
{
{
00H
FFFFF04AH
Port CT mode control register
PMCCT
R/W
{
{
00H/F3H
FFFFF04CH
Port CM mode control register
PMCCM
R/W
{
{
00H/3FH
FFFFF04DH
Port CM function control register
PFCCM
R/W
{
{
00H
FFFFF04EH
Port CD mode control register
PMCCD
R/W
{
{
00H/0FH
FFFFF04FH
Port CD function control register
PFCCD
R/W
{
{
00H
FFFFF052H
Port BD mode control register
PMCBD
R/W
{
{
00H
FFFFF060H
Chip area select control register 0
CSC0
R/W
{
2C11H
FFFFF062H
Chip area select control register 1
CSC1
R/W
{
2C11H
FFFFF066H
Bus size configuration register
BSC
R/W
{
0000H/5555H
FFFFF068H
Endian configuration register
BEC
R/W
{
0000H
FFFFF06EH
System wait control register
VSWC
R/W
FFFFF080H
DMA source address register 0L
DSA0L
R/W
{
Undefined
FFFFF082H
DMA source address register 0H
DSA0H
R/W
{
Undefined
FFFFF084H
DMA destination address register 0L
DDA0L
R/W
{
Undefined
FFFFF086H
DMA destination address register 0H
DDA0H
R/W
{
Undefined
FFFFF088H
DMA source address register 1L
DSA1L
R/W
{
Undefined
FFFFF08AH
DMA source address register 1H
DSA1H
R/W
{
Undefined
FFFFF08CH
DMA destination address register 1L
DDA1L
R/W
{
Undefined
FFFFF08EH
DMA destination address register 1H
DDA1H
R/W
{
Undefined
FFFFF090H
DMA source address register 2L
DSA2L
R/W
{
Undefined
FFFFF092H
DMA source address register 2H
DSA2H
R/W
{
Undefined
FFFFF094H
DMA destination address register 2L
DDA2L
R/W
{
Undefined
FFFFF096H
DMA destination address register 2H
DDA2H
R/W
{
Undefined
FFFFF098H
DMA source address register 3L
DSA3L
R/W
{
Undefined
FFFFF09AH
DMA source address register 3H
DSA3H
R/W
{
Undefined
FFFFF09CH
DMA destination address register 3L
DDA3L
R/W
{
Undefined
FFFFF09EH
DMA destination address register 3H
DDA3H
R/W
{
Undefined
FFFFF0C0H
DMA transfer count register 0
DBC0
R/W
{
Undefined
FFFFF0C2H
DMA transfer count register 1
DBC1
R/W
{
Undefined
FFFFF0C4H
DMA transfer count register 2
DBC2
R/W
{
Undefined
FFFFF0C6H
DMA transfer count register 3
DBC3
R/W
{
Undefined
FFFFF0D0H
DMA addressing control register 0
DADC0
R/W
{
0000H
User’s Manual U14359EJ3V0UM
{
0000H/FFFFH
77H
85
CHAPTER 3
CPU FUNCTION
(3/9)
Address
Function Register Name
Symbol
R/W
Bit Units for Manipulation
1 Bit
8 Bits
After Reset
16 Bits
FFFFF0D2H
DMA addressing control register 1
DADC1
R/W
{
0000H
FFFFF0D4H
DMA addressing control register 2
DADC2
R/W
{
0000H
FFFFF0D6H
DMA addressing control register 3
DADC3
R/W
{
0000H
FFFFF0E0H
DMA channel control register 0
DCHC0
R/W
{
{
00H
FFFFF0E2H
DMA channel control register 1
DCHC1
R/W
{
{
00H
FFFFF0E4H
DMA channel control register 2
DCHC2
R/W
{
{
00H
FFFFF0E6H
DMA channel control register 3
DCHC3
R/W
{
{
00H
FFFFF0F0H
DMA disable status register
DDIS
R
{
00H
FFFFF0F2H
DMA restart register
DRST
R/W
{
00H
FFFFF100H
Interrupt mask register 0
IMR0
R/W
FFFFF100H
Interrupt mask register 0L
IMR0L
R/W
{
{
FFH
FFFFF101H
Interrupt mask register 0H
IMR0H
R/W
{
{
FFH
Interrupt mask register 1
IMR1
R/W
FFFFF102H
Interrupt mask register 1L
IMR1L
R/W
{
{
FFH
FFFFF103H
Interrupt mask register 1H
IMR1H
R/W
{
{
FFH
Interrupt mask register 2
IMR2
R/W
FFFFF104H
Interrupt mask register 2L
IMR2L
R/W
{
{
FFH
FFFFF105H
Interrupt mask register 2H
IMR2H
R/W
{
{
FFH
Interrupt mask register 3
IMR3
R/W
FFFFF106H
Interrupt mask register 3L
IMR3L
R/W
{
{
FFH
FFFFF107H
Interrupt mask register 3H
IMR3H
R/W
{
{
FFH
FFFFF110H
Interrupt control register
OVIC00
R/W
{
{
47H
FFFFF112H
Interrupt control register
OVIC01
R/W
{
{
47H
FFFFF114H
Interrupt control register
OVIC02
R/W
{
{
47H
FFFFF116H
Interrupt control register
OVIC03
R/W
{
{
47H
FFFFF118H
Interrupt control register
P00IC0
R/W
{
{
47H
FFFFF11AH
Interrupt control register
P00IC1
R/W
{
{
47H
FFFFF11CH
Interrupt control register
P01IC0
R/W
{
{
47H
FFFFF11EH
Interrupt control register
P01IC1
R/W
{
{
47H
FFFFF120H
Interrupt control register
P02IC0
R/W
{
{
47H
FFFFF122H
Interrupt control register
P02IC1
R/W
{
{
47H
FFFFF124H
Interrupt control register
P03IC0
R/W
{
{
47H
FFFFF126H
Interrupt control register
P03IC1
R/W
{
{
47H
FFFFF128H
Interrupt control register
P10IC0
R/W
{
{
47H
FFFFF12AH
Interrupt control register
P10IC1
R/W
{
{
47H
FFFFF12CH
Interrupt control register
P10IC2
R/W
{
{
47H
FFFFF12EH
Interrupt control register
P10IC3
R/W
{
{
47H
FFFFF102H
FFFFF104H
FFFFF106H
86
User’s Manual U14359EJ3V0UM
{
{
{
{
FFFFH
FFFFH
FFFFH
FFFFH
CHAPTER 3
CPU FUNCTION
(4/9)
Address
Function Register Name
Symbol
R/W
Bit Units for Manipulation
1 Bit
8 Bits
After Reset
16 Bits
FFFFF130H
Interrupt control register
P11IC0
R/W
{
{
47H
FFFFF132H
Interrupt control register
P11IC1
R/W
{
{
47H
FFFFF134H
Interrupt control register
P11IC2
R/W
{
{
47H
FFFFF136H
Interrupt control register
P11IC3
R/W
{
{
47H
FFFFF138H
Interrupt control register
P12IC0
R/W
{
{
47H
FFFFF13AH
Interrupt control register
P12IC1
R/W
{
{
47H
FFFFF13CH
Interrupt control register
P12IC2
R/W
{
{
47H
FFFFF13EH
Interrupt control register
P12IC3
R/W
{
{
47H
FFFFF140H
Interrupt control register
P13IC0
R/W
{
{
47H
FFFFF142H
Interrupt control register
P13IC1
R/W
{
{
47H
FFFFF144H
Interrupt control register
P13IC2
R/W
{
{
47H
FFFFF146H
Interrupt control register
P13IC3
R/W
{
{
47H
FFFFF148H
Interrupt control register
CMICD0
R/W
{
{
47H
FFFFF14AH
Interrupt control register
CMICD1
R/W
{
{
47H
FFFFF14CH
Interrupt control register
CMICD2
R/W
{
{
47H
FFFFF14EH
Interrupt control register
CMICD3
R/W
{
{
47H
FFFFF150H
Interrupt control register
DMAIC0
R/W
{
{
47H
FFFFF152H
Interrupt control register
DMAIC1
R/W
{
{
47H
FFFFF154H
Interrupt control register
DMAIC2
R/W
{
{
47H
FFFFF156H
Interrupt control register
DMAIC3
R/W
{
{
47H
FFFFF158H
Interrupt control register
CSIIC0
R/W
{
{
47H
FFFFF15AH
Interrupt control register
SEIC0
R/W
{
{
47H
FFFFF15CH
Interrupt control register
SRIC0
R/W
{
{
47H
FFFFF15EH
Interrupt control register
STIC0
R/W
{
{
47H
FFFFF160H
Interrupt control register
CSIIC1
R/W
{
{
47H
FFFFF162H
Interrupt control register
SEIC1
R/W
{
{
47H
FFFFF164H
Interrupt control register
SRIC1
R/W
{
{
47H
FFFFF166H
Interrupt control register
STIC1
R/W
{
{
47H
FFFFF168H
Interrupt control register
CSIIC2
R/W
{
{
47H
FFFFF16AH
Interrupt control register
SEIC2
R/W
{
{
47H
FFFFF16CH
Interrupt control register
SRIC2
R/W
{
{
47H
FFFFF16EH
Interrupt control register
STIC2
R/W
{
{
47H
FFFFF170H
Interrupt control register
ADIC
R/W
{
{
47H
FFFFF1FAH
In-service priority register
ISPR
R
{
{
00H
FFFFF1FCH
Command register
PRCMD
W
{
Undefined
FFFFF1FEH
Power-save control register
PSC
R/W
{
{
00H
FFFFF200H
A/D converter mode register 0
ADM0
R/W
{
{
00H
User’s Manual U14359EJ3V0UM
87
CHAPTER 3
CPU FUNCTION
(5/9)
Address
Function Register Name
Symbol
R/W
Bit Units for Manipulation
1 Bit
8 Bits
After Reset
16 Bits
{
07H
{
00H
FFFFF201H
A/D converter mode register 1
ADM1
R/W
FFFFF202H
A/D converter mode register 2
ADM2
R/W
FFFFF210H
A/D conversion result register 0 (10 bits)
ADCR0
R
{
0000H
FFFFF212H
A/D conversion result register 1 (10 bits)
ADCR1
R
{
0000H
FFFFF214H
A/D conversion result register 2 (10 bits)
ADCR2
R
{
0000H
FFFFF216H
A/D conversion result register 3 (10 bits)
ADCR3
R
{
0000H
FFFFF218H
A/D conversion result register 4 (10 bits)
ADCR4
R
{
0000H
FFFFF21AH
A/D conversion result register 5 (10 bits)
ADCR5
R
{
0000H
FFFFF21CH
A/D conversion result register 6 (10 bits)
ADCR6
R
{
0000H
FFFFF21EH
A/D conversion result register 7 (10 bits)
ADCR7
R
{
0000H
FFFFF220H
A/D conversion result register 0H (8 bits)
ADCR0H
R
{
00H
FFFFF221H
A/D conversion result register 1H (8 bits)
ADCR1H
R
{
00H
FFFFF222H
A/D conversion result register 2H (8 bits)
ADCR2H
R
{
00H
FFFFF223H
A/D conversion result register 3H (8 bits)
ADCR3H
R
{
00H
FFFFF224H
A/D conversion result register 4H (8 bits)
ADCR4H
R
{
00H
FFFFF225H
A/D conversion result register 5H (8 bits)
ADCR5H
R
{
00H
FFFFF226H
A/D conversion result register 6H (8 bits)
ADCR6H
R
{
00H
FFFFF227H
A/D conversion result register 7H (8 bits)
ADCR7H
R
{
00H
FFFFF400H
Port 0
P0
R/W
{
{
Undefined
FFFFF402H
Port 1
P1
R/W
{
{
Undefined
FFFFF404H
Port 2
P2
R/W
{
{
Undefined
FFFFF406H
Port 3
P3
R/W
{
{
Undefined
FFFFF408H
Port 4
P4
R/W
{
{
Undefined
FFFFF40AH
Port 5
P5
R/W
{
{
Undefined
FFFFF40EH
Port 7
P7
R/W
{
{
Undefined
FFFFF420H
Port 0 mode register
PM0
R/W
{
{
FFH
FFFFF422H
Port 1 mode register
PM1
R/W
{
{
FFH
FFFFF424H
Port 2 mode register
PM2
R/W
{
{
FFH
FFFFF426H
Port 3 mode register
PM3
R/W
{
{
FFH
FFFFF428H
Port 4 mode register
PM4
R/W
{
{
FFH
FFFFF42AH
Port 5 mode register
PM5
R/W
{
{
FFH
FFFFF440H
Port 0 mode control register
PMC0
R/W
{
{
00H
FFFFF442H
Port 1 mode control register
PMC1
R/W
{
{
00H
FFFFF444H
Port 2 mode control register
PMC2
R/W
{
{
01H
FFFFF446H
Port 3 mode control register
PMC3
R/W
{
{
00H
FFFFF448H
Port 4 mode control register
PMC4
R/W
{
{
00H
FFFFF44AH
Port 5 mode control register
PMC5
R/W
{
{
00H
88
User’s Manual U14359EJ3V0UM
{
CHAPTER 3
CPU FUNCTION
(6/9)
Address
Function Register Name
Symbol
R/W
Bit Units for Manipulation
1 Bit
8 Bits
After Reset
16 Bits
FFFFF460H
Port 0 function control register
PFC0
R/W
{
{
00H
FFFFF464H
Port 2 function control register
PFC2
R/W
{
{
00H
FFFFF466H
Port 3 function control register
PFC3
R/W
{
{
00H
FFFFF468H
Port 4 function control register
PFC4
R/W
{
{
00H
FFFFF480H
Bus cycle type configuration register 0
BCT0
R/W
{
8888H
FFFFF482H
Bus cycle type configuration register 1
BCT1
R/W
{
8888H
FFFFF484H
Data wait control register 0
DWC0
R/W
{
7777H
FFFFF486H
Data wait control register 1
DWC1
R/W
{
7777H
FFFFF488H
Bus cycle control register
BCC
R/W
{
FFFFH
FFFFF48AH
Address setup wait control register
ASC
R/W
{
FFFFH
FFFFF48CH
Bus cycle period control register
BCP
R/W
FFFFF49AH
Page-ROM configuration register
PRC
R/W
FFFFF49EH
Refresh wait control register
RWC
R/W
FFFFF4A4H
DRAM configuration register 1
SCR1
R/W
{
3FC1H
R/W
{
0000H
R/W
{
0000H
R/W
{
0000H
R/W
{
3FC1H
R/W
{
0000H
R/W
{
0000H
R/W
{
0000H
R/W
{
3FC1H
R/W
{
0000H
R/W
{
0000H
R/W
{
0000H
R/W
{
3FC1H
R/W
{
0000H
R/W
{
0000H
R/W
{
0000H
SDRAM configuration register 1
FFFFF4A6H
Refresh control register 1
RFS1
SDRAM refresh control register 1
FFFFF4ACH
DRAM configuration register 3
SCR3
SDRAM configuration register 3
FFFFF4AEH
Refresh control register 3
RFS3
SDRAM refresh control register 3
FFFFF4B0H
DRAM configuration register 4
SCR4
SDRAM configuration register 4
FFFFF4B2H
Refresh control register 4
RFS4
SDRAM refresh control register 4
FFFFF4B8H
DRAM configuration register 6
SCR6
SDRAM configuration register 6
FFFFF4BAH
Refresh control register 6
RFS6
SDRAM refresh control register 6
{
00H
{
{
7000H
00H
FFFFF540H
Timer D0
TMD0
R
{
0000H
FFFFF542H
Compare register D0
CMD0
R/W
{
0000H
FFFFF544H
Timer mode control register D0
TMCD0
R/W
FFFFF550H
Timer D1
TMD1
R
{
0000H
FFFFF552H
Compare register D1
CMD1
R/W
{
0000H
FFFFF554H
Timer mode control register D1
TMCD1
R/W
FFFFF560H
Timer D2
TMD2
R
{
0000H
FFFFF562H
Compare register D2
CMD2
R/W
{
0000H
User’s Manual U14359EJ3V0UM
{
{
{
00H
{
00H
89
CHAPTER 3
CPU FUNCTION
(7/9)
Address
Function Register Name
Symbol
R/W
R/W
Bit Units for Manipulation
1 Bit
8 Bits
{
{
After Reset
16 Bits
FFFFF564H
Timer mode control register D2
TMCD2
FFFFF570H
Timer D3
TMD3
R
{
0000H
FFFFF572H
Compare register D3
CMD3
R/W
{
0000H
FFFFF574H
Timer mode control register D3
TMCD3
R/W
FFFFF600H
Timer C0
TMC0
R
{
0000H
FFFFF602H
Capture/compare register C00
CCC00
R/W
{
0000H
FFFFF604H
Capture/compare register C01
CCC01
R/W
{
0000H
FFFFF606H
Timer mode control register C00
TMCC00
R/W
FFFFF608H
Timer mode control register C01
TMCC01
FFFFF609H
Valid edge select register C0
FFFFF610H
{
{
00H
{
00H
{
00H
R/W
{
20H
SESC0
R/W
{
00H
Timer C1
TMC1
R
{
0000H
FFFFF612H
Capture/compare register C10
CCC10
R/W
{
0000H
FFFFF614H
Capture/compare register C11
CCC11
R/W
{
0000H
FFFFF616H
Timer mode control register C10
TMCC10
R/W
FFFFF618H
Timer mode control register C11
TMCC11
FFFFF619H
Valid edge select register C1
FFFFF620H
{
{
00H
R/W
{
20H
SESC1
R/W
{
00H
Timer C2
TMC2
R
{
0000H
FFFFF622H
Capture/compare register C20
CCC20
R/W
{
0000H
FFFFF624H
Capture/compare register C21
CCC21
R/W
{
0000H
FFFFF626H
Timer mode control register C20
TMCC20
R/W
FFFFF628H
Timer mode control register C21
TMCC21
FFFFF629H
Valid edge select register C2
FFFFF630H
{
{
00H
R/W
{
20H
SESC2
R/W
{
00H
Timer C3
TMC3
R
{
0000H
FFFFF632H
Capture/compare register C30
CCC30
R/W
{
0000H
FFFFF634H
Capture/compare register C31
CCC31
R/W
{
0000H
FFFFF636H
Timer mode control register C30
TMCC30
R/W
FFFFF638H
Timer mode control register C31
TMCC31
FFFFF639H
Valid edge select register C3
FFFFF800H
{
00H
R/W
{
20H
SESC3
R/W
{
00H
Peripheral command register
PHCMD
W
{
Undefined
FFFFF802H
Peripheral status register
PHS
R/W
{
{
00H
FFFFF810H
DMA trigger factor register 0
DTFR0
R/W
{
{
00H
FFFFF812H
DMA trigger factor register 1
DTFR1
R/W
{
{
00H
FFFFF814H
DMA trigger factor register 2
DTFR2
R/W
{
{
00H
FFFFF816H
DMA trigger factor register 3
DTFR3
R/W
{
{
00H
FFFFF820H
Power-save mode register
PSMR
R/W
{
{
00H
FFFFF822H
Clock control register
CKC
R/W
{
00H
FFFFF824H
Lock register
LOCKR
{
0xH
90
User’s Manual U14359EJ3V0UM
R
{
{
CHAPTER 3
CPU FUNCTION
(8/9)
Address
Function Register Name
Symbol
R/W
Bit Units for Manipulation
After Reset
1 Bit
8 Bits
16 Bits
{
{
00H
FFFFF880H
External interrupt mode register 0
INTM0
R/W
FFFFF882H
External interrupt mode register 1
INTM1
R/W
{
00H
FFFFF884H
External interrupt mode register 2
INTM2
R/W
{
00H
FFFFF886H
External interrupt mode register 3
INTM3
R/W
{
00H
FFFFF888H
External interrupt mode register 4
INTM4
R/W
{
00H
FFFFF8A0H
DMA terminal count output control register
DTOC
R/W
{
01H
FFFFF8D4H
Flash programming mode control register
FLPMC
R/W
{
{
08H/0CH/00H
FFFFF900H
Clocked serial interface mode register 0
CSIM0
R/W
{
{
00H
FFFFF901H
Clocked serial interface clock select register 0
CSIC0
R/W
{
00H
FFFFF902H
Serial I/O shift register 0
SIO0
R
{
00H
FFFFF903H
Receive-only serial I/O shift register 0
SIOE0
R
{
00H
FFFFF904H
Clocked serial interface transmit buffer register 0
SOTB0
R/W
{
00H
FFFFF910H
Clocked serial interface mode register 1
CSIM1
R/W
{
00H
FFFFF911H
Clocked serial interface clock select register 1
CSIC1
R/W
{
00H
FFFFF912H
Serial I/O shift register 1
SIO1
R
{
00H
FFFFF913H
Receive-only serial I/O shift register 1
SIOE1
R
{
00H
FFFFF914H
Clocked serial interface transmit buffer register 1
SOTB1
R/W
{
00H
FFFFF920H
Clocked serial interface mode register 2
CSIM2
R/W
{
00H
FFFFF921H
Clocked serial interface clock select register 2
CSIC2
R/W
{
00H
FFFFF922H
Serial I/O shift register 2
SIO2
R
{
00H
FFFFF923H
Receive-only serial I/O shift register 2
SIOE2
R
{
00H
FFFFF924H
Clocked serial interface transmit buffer register 2
SOTB2
R/W
{
00H
FFFFFA00H
Asynchronous serial interface mode register 0
ASIM0
R/W
{
01H
FFFFFA02H
Receive buffer register 0
RXB0
R
{
FFH
FFFFFA03H
Asynchronous serial interface status register 0
ASIS0
R
{
00H
FFFFFA04H
Transmit buffer register 0
TXB0
R/W
{
FFH
FFFFFA05H
Asynchronous serial interface transmit status
register 0
ASIF0
R
{
00H
FFFFFA06H
Clock select register 0
CKSR0
R/W
{
00H
FFFFFA07H
Baud rate generator control register 0
BRGC0
R/W
{
FFH
FFFFFA10H
Aynchronous serial interface mode register 1
ASIM1
R/W
{
01H
FFFFFA12H
Receive buffer register 1
RXB1
R
{
FFH
FFFFFA13H
Asynchronous serial interface status register 1
ASIS1
R
{
00H
FFFFFA14H
Transmit buffer register 1
TXB1
R/W
{
FFH
FFFFFA15H
Aynchronous serial interface transmit status
register 1
ASIF1
R
{
00H
FFFFFA16H
Clock select register 1
CKSR1
R/W
{
00H
FFFFFA17H
Baud rate generator control register 1
BRGC1
R/W
{
FFH
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{
{
{
{
{
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CPU FUNCTION
(9/9)
Address
Function Register Name
Symbol
R/W
Bit Units for Manipulation
After Reset
1 Bit
8 Bits
16 Bits
{
{
01H
FFFFFA20H
Aynchronous serial interface mode register 2
ASIM2
R/W
FFFFFA22H
Receive buffer register 2
RXB2
R
{
FFH
FFFFFA23H
Asynchronous serial interface status register 2
ASIS2
R
{
00H
FFFFFA24H
Transmit buffer register 2
TXB2
R/W
{
FFH
FFFFFA25H
Asynchronous serial interface transmit status
register 2
ASIF2
R
{
00H
FFFFFA26H
Clock select register 2
CKSR2
R/W
{
00H
FFFFFA27H
Baud rate generator control register 2
BRGC2
R/W
{
FFH
FFFFFC00H
PWM control register 0
PWMC0
R/W
{
40H
FFFFFC02H
PWM buffer register 0
PWMB0
R/W
FFFFFC10H
PWM control register 1
PWMC1
R/W
FFFFFC12H
PWM buffer register 1
PWMB1
R/W
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{
{
{
{
{
0000H
40H
{
0000H
CHAPTER 3
3.4.9
CPU FUNCTION
Specific registers
Specific registers are registers that are protected from being written with illegal data due to erroneous program
execution, etc. The V850E/MA1 has three specific registers, the power-save control register (PSC) (refer to 9.5.2 (3)
Power-save control register (PSC)), clock control register (CKC) (refer to 9.3.4 Clock control register (CKC)), and
flash programming mode control register (FLPMC). Disable DMA transfer when writing to a specific register.
There are also two protection registers supporting write operations for specific registers to avoid an unexpected
stoppage of the application system due to erroneous program execution. These two registers are the command
register (PRCMD) and peripheral command register (PHCMD) (refer to 9.5.2 (2) Command register (PRCMD) and
9.3.3 Peripheral command register (PHCMD)).
3.4.10 System wait control register (VSWC)
The system wait control register (VSWC) is a register that controls the bus access wait for the on-chip peripheral
I/O registers.
Access to on-chip peripheral I/O registers is made in 3 clocks (without wait), however, in the V850E/MA1 waits may
be required depending on the operation frequency. Set the values described in the table below to the VSWC in
accordance with the operation frequency used.
This register can be read/written in 8-bit units (address: FFFFF06EH, initial value: 77H).
Operation Frequency (φ)
Set Value of VSWC
Number of Waits for On-chip
Peripheral I/O Register Access
4 MHz ≤ φ < 25 MHz
11H
2
25 MHz ≤ φ < 50 MHz
12H
3
φ = 50 MHz
13H
4
3.4.11 Cautions
When using the V850E/MA1, the following registers must be set in the beginning.
• System wait control register (VSWC)
(See 3.4.10 System wait control register (VSWC))
• Clock control register (CKC)
(See 9.3.4 Clock control register (CKC))
After setting VSWC and CKC, set other registers if necessary.
To use the external bus, initialize each register in the following sequence after setting the above registers.
<1> Set each pin to the control mode by setting each port-related register.
<2> Select a chip select space by using chip area select control register n (CSCn) (n = 0 or 1).
<3> Specify the type of memory of each chip select space by using bus cycle type configuration register n
(BCTn).
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CHAPTER 4 BUS CONTROL FUNCTION
The V850E/MA1 is provided with an external bus interface function by which external I/O and memories, such as
ROM and RAM, can be connected.
4.1
Features
• 16-bit/8-bit data bus sizing function
• 8-space chip select function
• Wait function
• Programmable wait function, through which up to 7 wait states can be inserted for each memory block
• External wait function via WAIT pin
• Idle state insertion function
• Bus mastership arbitration function
• Bus hold function
• External device connection enabled via bus control/port alternate function pins
4.2
Bus Control Pins
The following pins are used for connection to external devices.
Bus Control Pin (Function When in Control Mode)
Function When in Port Mode
Register for Port/Control
Mode Switching
Data bus (D0 to D15)
PDL0 to PDL15 (Port DL)
PMCDL
Address bus (A0 to A15)
PAL0 to PAL15 (Port AL)
PMCAL
Address bus (A16 to A25)
PAH0 to PAH9 (Port AH)
PMCAH
Chip select (CS0 to SC7, RAS1, RAS3, RAS4, RAS6,
IOWR, IORD)
PCS0 to PCS7 (Port CS)
PMCCS
SDRAM sync control (SDCKE, SDCLK)
PCD0, PCD1 (Port CD)
PMCCD
Byte access control/SDRAM control (LBE/SDCAS,
UBE/SDRAS)
PCD2, PCD3 (Port CD)
Read/write control (LCAS/LWR/LDQM, UCAS/UWR/UDQM,
RD, WE, OE)
PCT0, PCT1, PCT4 to PCT6
(Port CT)
Bus cycle start (BCYST)
PCT7 (Port CT)
External wait control (WAIT)
PCM0 (Port CM)
Internal system clock (CLKOUT)
PCM1 (Port CM)
Bus hold control (HLDRQ, HLDAK)
PCM2, PCM3 (Port CM)
DRAM refresh control (REFRQ)
PCM4 (Port CM)
Self-refresh control (SELFREF)
PCM5 (Port CM)
Remark
PMCCT
PMCCM
In the case of single-chip mode 1 and ROMless modes 0 and 1, when the system is reset, each bus
control pin becomes unconditionally valid. (However, D8 to D15 are valid only in single-chip mode 1
and ROMless mode 0.)
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4.2.1 Pin status during internal ROM, internal RAM, and peripheral I/O access
While accessing internal ROM and RAM, the address bus becomes undefined, and the data bus and external bus
control signals are not output and enter the high-impedance state.
While accessing peripheral I/O, the address bus outputs the address data of the on-chip peripheral I/O currently
being accessed, and the data bus control signals are not output and enter the high-impedance state. The external
bus control signals become inactive.
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4.3
BUS CONTROL FUNCTION
Memory Block Function
The 256 MB memory space is divided into memory blocks of 2 MB and 64 MB units. The programmable wait
function and bus cycle operation mode can be independently controlled for each block.
The area that can be used as program area is the 64 MB space of addresses 0000000H to 3FFFFFFH.
FFFFFFFH
FE00000H
FDFFFFFH
FC00000H
FBFFFFFH
CS7, CS6, CS5
Area 3
FA00000H
F9FFFFFH
F800000H
F7FFFFFH
FFFFFFFH
On-chip peripheral I/O area (4 KB)
FFFF000H
FFFEFFFH
Internal RAM area (12 KBNote 1)
FFFC000H
Block 7
(2 MB)
Block 6
(2 MB)
Block 5
(2 MB)
Block 4
(2 MB)
CS6
C000000H
BFFFFFFH
CS4
External memory area
64 MB
Area 2
8000000H
7FFFFFFH
CS3
64 MB
Area 1
4000000H
3FFFFFFH
3FFFFFFH
On-chip peripheral I/O area (4 KB)Note 2
3FFF000H
3FFEFFFH
Internal RAM area (12 KBNote 1)
3FFC000H
CS1
0800000H
07FFFFFH
Area 0
CS2, CS1, CS0
0600000H
05FFFFFH
0400000H
03FFFFFH
0200000H
01FFFFFH
0000000H
Notes 1.
Block 3
(2 MB)
Block 2
(2 MB)
External memory area
Block 1
(2 MB)
Block 0
(2 MB)
0100000H
Internal ROM area (1 MB)Note 3
0000000H
µPD703103, 703105: 4 KB
µPD703106, 703107, 70F3107: 10 KB
2.
This area is access-prohibited. To access the on-chip peripheral I/O of this area, specify addresses
FFFF000H to FFFFFFFH.
3.
When in single-chip mode 1 and ROMless modes 0 and 1, this becomes an external memory area.
When in single-chip mode 1, addresses 0100000H to 01FFFFFH become an internal ROM area.
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4.3.1 Chip select control function
Of the 256 MB memory area, the lower 8 MB (0000000H to 07FFFFFH) and the higher 8 MB (F800000H to
FFFFFFFH) can be divided into 2 MB memory blocks by chip area select control registers 0 and 1 (CSC0, CSC1) to
control the chip select signal.
The memory area can be effectively used by dividing it into memory blocks using the chip select control function.
The priority order is described below.
(1) Chip area select control registers 0, 1 (CSC0, CSC1)
These registers can be read/written in 16-bit units and become valid by setting each bit to 1.
If different chip select signal outputs are set to the same block, the priority order is controlled as follows.
CSC0: Peripheral I/O area: CS0 > CS2 > CS1
CSC1: Peripheral I/O area: CS7 > CS5 > CS6
If both the CS0n and CS2n bits of the CSC0 register are set to 0, CS1 is output to the corresponding block (n
= 0 to 3).
Similarly, if both the CS5n and CS7n bits of the CSC1 register are set to 0, CS6 is output to the
corresponding block (n = 0 to 3).
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CHAPTER 4
15
CSC0
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CS33 CS32 CS31 CS30 CS23 CS22 CS21 CS20 CS13 CS12 CS11 CS10 CS03 CS02 CS01 CS00
15
CSC1
14
BUS CONTROL FUNCTION
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit name
15 to 0
CSnm
(n = 0 to 7)
(m = 0 to 3)
After reset
2C11H
Address
FFFFF062H
After reset
2C11H
0
CS43 CS42 CS41 CS40 CS53 CS52 CS51 CS50 CS63 CS62 CS61 CS60 CS73 CS72 CS71 CS70
Bit position
Address
FFFFF060H
Function
Chip Select
Chip select is enabled by setting the CSnm bit to 1.
CSnm
CS operation
CS00
CS0 output during block 0 access
CS01
CS0 output during block 1 access.
CS02
CS0 output during block 2 access.
CS03
CS0 output during block 3 access.
CS10 to CS13
Setting has no meaning.
CS20
CS2 output during block 0 access.
CS21
CS2 output during block 1 access.
CS22
CS2 output during block 2 access.
CS23
CS2 output during block 3 access.
CS30 to CS33
Setting has no meaning.
CS40 to CS43
Setting has no meaning.
CS50
CS5 output during block 7 access.
CS51
CS5 output during block 6 access.
CS52
CS5 output during block 5 access.
CS53
CS5 output during block 4 access.
CS60 to CS63
Setting has no meaning.
CS70
CS7 output during block 7 access.
CS71
CS7 output during block 6 access.
CS72
CS7 output during block 5 access.
CS73
CS7 output during block 4 access.
The following diagram shows the CS signal that is enabled for area 0 when the CSC0 register is set to
0703H.
When the CSC0 register is set to 0703H, CS0 and CS2 are output to block 0 and block 1, but since CS0 has
priority over CS2, CS0 is output if the addresses of block 0 and block 1 are accessed.
If the address of block 3 is accessed, both the CS03 and CS23 bits of the CSC0 register are 0, and CS1 is
output.
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BUS CONTROL FUNCTION
Figure 4-1. Example When CSC0 Register Is Set to 0703H
3FFFFFFH
58 MB
CS1 is output.
0800000H
07FFFFFH
Block 3
(2 MB)
0600000H
05FFFFFH
Block 2
(2 MB)
2 MB
CS2 is output.
0400000H
03FFFFFH
Block 1
(2 MB)
4 MB
0200000H
01FFFFFH
CS0 is output.
Block 0
(2 MB)
0000000H
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CHAPTER 4
4.4
BUS CONTROL FUNCTION
Bus Cycle Type Control Function
In the V850E/MA1, the following external devices can be connected directly to each memory block.
• SRAM, external ROM, external I/O
• Page ROM
• EDO DRAM
• SDRAM
Connected external devices are specified by bus cycle type configuration registers 0 and 1 (BCT0 and BCT1).
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4.4.1 Bus cycle type configuration registers 0, 1 (BCT0, BCT1)
(1) Bus cycle type configuration registers 0, 1 (BCT0, BCT1)
These registers can be read/written in 16-bit units.
Caution
Write to the BCT0 and BCT1 registers after reset, and then do not change the set value.
Also, do not access an external memory area other than the one for this initialization
routine until the initial setting of the BCT0 and BCT1 registers is complete. However, it is
possible to access external memory areas whose initialization settings are complete.
BCT0
15
14
ME3
0
CSn signal
BCT1
13
12
11
10
BT31 BT30 ME2 0
9
0
CS3
15
14
13
ME7
0
0
CSn signal
12
15, 11, 7, 3
(BCT0),
15, 11, 7, 3
(BCT1)
MEn
(n = 0 to 7)
8, 0 (BCT0),
12, 4 (BCT1)
11
CS7
Bit name
7
6
BT20 ME1 0
5
2
1
0
BT11 BT10 ME0 0
0
BT00
CS2
10
BT70 ME6 0
Bit position
8
9
8
7
6
5
BT61 BT60 ME5 0
0
CS6
BTn1, BTn0
(n = 1, 3, 4, 6)
Address
FFFFF480H
After reset
8888H
Address
FFFFF482H
After reset
8888H
CS0
4
3
2
BT50 ME4 0
1
0
BT41 BT40
CS5
CS4
Function
Memory Controller Enable
Sets memory controller operation enable for each chip select.
Memory controller operation enable
0
Operation disabled
1
Operation enabled
Bus Cycle Type
Specifies the device to be connected to the CSn signal.
BTn0
13, 12, 5, 4
(BCT0),
9, 8, 1, 0
(BCT1)
3
CS1
MEn
BTn0
(n = 0, 2, 5, 7)
4
External device connected to CSn signal
0
SRAM, external I/O
1
Page ROM
Bus Cycle Type
Specifies the device to be connected to the CSn signal.
BTn1
BTn0
External device connected to CSn signal
0
0
SRAM, external I/O
0
1
Page ROM
1
0
EDO DRAM
1
1
SDRAM
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CHAPTER 4
4.5
BUS CONTROL FUNCTION
Bus Access
4.5.1 Number of access clocks
The number of basic clocks necessary for accessing each resource is as follows.
Bus Cycle Configuration
Instruction Fetch
Random Access
Operand Data Access
Sequential Access
Normal Access
Sequential Access
1
5
−
−
1
−
Resource (Bus Width)
Internal ROM (32 bits)
Internal RAM (32 bits)
Notes 1.
2.
Remark
102
Note 1
2
Note 2
1 or 2
In the case of branch instructions
See 3.4.5 (2) Internal RAM area when using internal RAM as program space.
Unit: Clock/access
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BUS CONTROL FUNCTION
4.5.2 Bus sizing function
The bus sizing function controls the data bus width for each CS space. The data bus width is specified by using
the bus size configuration register (BSC).
(1) Bus size configuration register (BSC)
This register can be read/written in 16-bit units.
Cautions 1. Write to the BSC register after reset, and then do not change the set value. Also, do not
access an external memory area other than the one for this initialization routine until the
initial setting of the BSC register is complete. However, it is possible to access external
memory areas whose initialization settings are complete.
2. When the data bus width is specified as 8 bits, only the signals shown below become
active.
LWR:
When accessing SRAM, external ROM, or external I/O (write cycle)
LCAS: When accessing EDO DRAM
BSC
CSn signal
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
BS70
0
BS60
0
BS50
0
BS40
0
BS30
0
BS20
0
BS10
0
BS00
CS7
CS6
CS5
CS4
CS3
CS2
CS1
Address
FFFFF066H
After resetNote
0000H/5555H
CS0
Note When in single-chip mode 0, 1: 5555H
When in ROMless mode 0:
5555H
When in ROMless mode 1:
0000H
Bit position
14, 12, 10, 8,
6, 4, 2, 0
Bit name
BSn0
(n = 0 to 7)
Function
Data Bus Width
Sets the data bus width of the CSn space.
BSn0
Data bus width of CSn space
0
8 bits
1
16 bits
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4.5.3 Endian control function
The endian control function can be used to set processing of word data in memory using either the big endian
method or the little endian method for each CS space selected with the chip select signals (CS0 to CS7). Switching of
the endian method is specified using the endian configuration register (BEC).
Caution In the following areas, the data processing method is fixed to little endian, so the setting of the
BEC register is invalid.
• On-chip peripheral I/O area
• Internal ROM area
• Internal RAM area
• Fetch area for external memory
(1) Endian configuration register (BEC)
This register can be read/written in 16-bit units.
Be sure to set bits 15, 13, 11, 9, 7, 5, 3, and 1 to 0. If they are set to 1, the operation is not guaranteed.
BEC
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
BE70
0
BE60
0
BE50
0
BE40
0
BE30
0
BE20
0
BE10
0
BE00
CSn signal
CS7
Bit position
14, 12, 10, 8,
6, 4, 2, 0
CS6
CS5
CS4
CS3
CS2
Bit name
BEn0
(n = 0 to 7)
CS1
Function
Big Endian
Specifies the endian method.
BEn0
104
CS0
Endian control
0
Little endian method
1
Big endian method
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Address
FFFFF068H
After reset
0000H
CHAPTER 4
BUS CONTROL FUNCTION
Figure 4-2. Big Endian Addresses Within Word
31
24 23
16 15
8 7
0
0008H
0009H
000AH
000BH
0004H
0005H
0006H
0007H
0000H
0001H
0002H
0003H
Figure 4-3. Little Endian Addresses Within Word
31
24 23
16 15
8 7
0
000BH
000AH
0009H
0008H
0007H
0006H
0005H
0004H
0003H
0002H
0001H
0000H
4.5.4 Big endian method usage restrictions in NEC development tools
(1) When using a debugger (ID850)
The big endian method is supported only in the memory window display.
(2) When using a compiler (CA850)
(a) Restrictions in C language
(i)
There are restrictions for variables allocated to/located in the big endian space, as shown below.
• union cannot be used.
• bitfield cannot be used.
• Access with cast (changing access size) cannot be used.
• Variables with initial values cannot be used.
(ii) It is necessary to specify the following optimization inhibit options because optimization may cause a
change in the access size.
• For global optimization part (opt850)… -Wo, -XTb
• For optimization depending on model part (impr850)… -Wi, +arg_reg_opt=OFF, +stld_trans_opt=OFF
The specification of the optimization inhibit options shown above is not necessary, however, if the
access is not an access with cast or with masking/shifting
Note
.
Note This is on the condition that a pattern that may cause the following optimization is not used.
However, because it is very difficult for users to check the patterns completely in cases such
as when several patterns are mixed (especially for optimization depending on model part), it
is recommended that the optimization inhibit options shown above be specified.
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BUS CONTROL FUNCTION
[Related global optimization part]
• 1-bit set using bit or
int i;
i ^=1;
• 1-bit clear using bit and
i &= ~1;
• 1-bit not using bit xor
i ^= 1;
• 1-bit test using bit and
if(i & 1);
[Related optimization depending on model part]
Accessing the same variable in a different size
• Cast
• Mask
• Shift
Example
int i, *ip;
char c;
.
.
.
c=*((char*)ip);
.
.
.
c = 0xff & i;
.
.
.
i = (i<<24) >>24;
(b) Restrictions in assembly language
For variables located in the big endian space, a quasi directive that secures an area of other than byte
size (.hword, .word, .float, .shword) cannot be used.
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BUS CONTROL FUNCTION
4.5.5 Bus width
The V850E/MA1 accesses peripheral I/O and external memory in 8-bit, 16-bit, or 32-bit units. The following shows
the operation for each type of access. All data is accessed in order starting from the lower order side.
(1) Byte access (8 bits)
(a) When the data bus width is 16 bits (little endian)
<1> Access to even address (2n)
<2> Access to odd address (2n + 1)
Address
Address
15
15
7
8
7
7
8
7
0
0
0
0
Byte data
External
data bus
Byte data
External
data bus
2n + 1
2n
(b) When the data bus width is 8 bits (little endian)
<1> Access to even address (2n)
<2> Access to odd address (2n + 1)
Address
7
7
0
Byte data
Address
7
7
0
0
0
External
data bus
Byte data
External
data bus
2n
2n + 1
(c) When the data bus width is 16 bits (big endian)
<1> Access to even address (2n)
<2> Access to odd address (2n + 1)
Address
Address
15
15
2n
7
8
7
7
8
7
0
0
0
0
Byte data
External
data bus
Byte data
External
data bus
2n + 1
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(d) When the data bus width is 8 bits (big endian)
<1> Access to even address (2n)
<2> Access to odd address (2n + 1)
Address
7
7
0
Byte data
Address
7
7
0
0
0
External
data bus
Byte data
External
data bus
2n
2n + 1
(2) Halfword access (16 bits)
(a) When the bus width is 16 bits (little endian)
<1> Access to even address (2n)
<2> Access to odd address (2n + 1)
1st access
Address
15
15
8
7
8
7
0
Halfword
data
2nd access
Address
Address
15
15
15
15
8
7
8
7
8
7
8
7
0
0
0
0
0
External
data bus
Halfword
data
External
data bus
Halfword
data
External
data bus
2n + 1
2n + 1
2n + 2
2n
(b) When the data bus width is 8 bits (little endian)
<1> Access to even address (2n)
1st access
15
2nd access
1st access
15
Address
8
7
7
0
Halfword
data
15
Address
8
7
7
0
0
External
data bus
Halfword
data
2nd access
15
Address
8
7
7
0
0
External
data bus
Halfword
data
Address
8
7
7
0
0
0
External
data bus
Halfword
data
External
data bus
2n + 1
2n
108
<2> Access to odd address (2n + 1)
2n + 2
2n + 1
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CHAPTER 4
BUS CONTROL FUNCTION
(c) When the data bus width is 16 bits (big endian)
<1> Access to even address (2n)
<2> Access to odd address (2n + 1)
1st access
Address
15
15
8
7
8
7
0
Halfword
data
2nd access
Address
Address
15
15
15
15
8
7
8
7
8
7
8
7
0
0
0
0
0
External
data bus
Halfword
data
External
data bus
Halfword
data
External
data bus
2n
2n + 2
2n + 1
2n + 1
(d) When the data bus width is 8 bits (big endian)
<1> Access to even address (2n)
1st access
15
<2> Access to odd address (2n + 1)
2nd access
1st access
15
Address
8
7
7
0
Halfword
data
15
Address
8
7
7
0
0
External
data bus
Halfword
data
15
Address
8
7
7
0
0
External
data bus
Halfword
data
Address
8
7
7
0
0
0
External
data bus
Halfword
data
External
data bus
2n + 1
2n
2nd access
2n + 2
2n + 1
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BUS CONTROL FUNCTION
(3) Word access (32 bits)
(a) When the bus width is 16 bits (little endian) (1/2)
<1> Access to address 4n
1st access
2nd access
31
31
24
23
24
23
Address
16
15
15
Address
16
15
15
4n + 1
8
7
8
7
4n + 3
8
7
8
7
4n
0
4n + 2
0
Word data
0
External
data bus
0
Word data
External
data bus
<2> Access to address 4n + 1
1st access
2nd access
3rd access
31
31
31
24
23
24
23
24
23
Address
16
15
15
8
7
0
Address
16
15
15
8
7
8
7
8
7
0
0
0
4n + 1
Address
16
15
15
8
7
8
7
0
0
4n + 3
4n + 2
Word data
110
External
data bus
Word data
External
data bus
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4n + 4
Word data
External
data bus
CHAPTER 4
BUS CONTROL FUNCTION
(a) When the bus width is 16 bits (little endian) (2/2)
<3> Access to address 4n + 2
1st access
2nd access
31
31
24
23
24
23
Address
16
15
15
Address
16
15
15
4n + 3
8
7
8
7
4n + 5
8
7
8
7
4n + 2
0
0
Word data
4n + 4
0
External
data bus
0
External
data bus
Word data
<4> Access to address 4n + 3
1st access
2nd access
3rd access
31
31
31
24
23
24
23
24
23
Address
16
15
15
8
7
0
Address
16
15
15
8
7
8
7
8
7
0
0
0
4n + 3
Address
16
15
15
8
7
8
7
0
0
4n + 5
4n + 4
Word data
External
data bus
Word data
External
data bus
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Word data
External
data bus
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BUS CONTROL FUNCTION
(b) When the data bus width is 8 bits (little endian) (1/2)
<1> Access to address 4n
1st access
2nd access
3rd access
4th access
31
31
31
31
24
23
24
23
24
23
24
23
16
15
16
15
16
15
16
15
Address
8
7
7
0
0
Address
8
7
7
0
0
4n
Word data
External
data bus
Address
8
7
7
0
0
4n + 1
Word data
External
data bus
Address
8
7
7
0
0
4n + 2
Word data
External
data bus
4n + 3
Word data
External
data bus
<2> Access to address 4n + 1
1st access
2nd access
3rd access
4th access
31
31
31
31
24
23
24
23
24
23
24
23
16
15
16
15
16
15
16
15
Address
8
7
7
0
0
Address
8
7
7
0
0
4n + 1
Word data
112
External
data bus
Address
8
7
7
0
0
4n + 2
Word data
External
data bus
Address
8
7
7
0
0
4n + 3
Word data
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External
data bus
4n + 4
Word data
External
data bus
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BUS CONTROL FUNCTION
(b) When the data bus width is 8 bits (little endian) (2/2)
<3> Access to address 4n + 2
1st access
2nd access
3rd access
4th access
31
31
31
31
24
23
24
23
24
23
24
23
16
15
16
15
16
15
16
15
Address
8
7
7
0
0
Address
8
7
7
0
0
4n + 2
Word data
External
data bus
Address
8
7
7
0
0
4n + 3
Word data
External
data bus
Address
8
7
7
0
0
4n + 4
Word data
External
data bus
4n + 5
Word data
External
data bus
<4> Access to address 4n + 3
1st access
2nd access
3rd access
4th access
31
31
31
31
24
23
24
23
24
23
24
23
16
15
16
15
16
15
16
15
Address
8
7
7
0
0
Address
8
7
7
0
0
4n + 3
Word data
External
data bus
Address
8
7
7
0
0
4n + 4
Word data
External
data bus
Address
8
7
7
0
0
4n + 5
Word data
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External
data bus
4n + 6
Word data
External
data bus
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BUS CONTROL FUNCTION
(c) When the data bus width is 16 bits (big endian) (1/2)
<1> Access to address 4n
1st access
2nd access
31
31
24
23
24
23
Address
16
15
15
Address
16
15
15
4n
4n + 2
8
7
8
7
8
7
8
7
4n + 1
0
0
Word data
4n + 3
0
External
data bus
0
External
data bus
Word data
<2> Access to address 4n + 1
1st access
2nd access
3rd access
31
31
31
24
23
24
23
24
23
Address
Address
16
15
15
16
15
15
8
7
8
7
8
7
8
7
0
0
0
0
Address
16
15
15
8
7
8
7
0
0
4n + 4
4n + 2
4n + 1
Word data
114
External
data bus
4n + 3
Word data
External
data bus
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Word data
External
data bus
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BUS CONTROL FUNCTION
(c) When the data bus width is 16 bits (big endian) (2/2)
<3> Access to address 4n + 2
1st access
2nd access
31
31
24
23
24
23
Address
16
15
15
Address
16
15
15
4n + 2
8
7
8
7
4n + 4
8
7
8
7
4n + 3
0
0
Word data
4n + 5
0
External
data bus
0
External
data bus
Word data
<4> Access to address 4n + 3
1st access
2nd access
3rd access
31
31
31
24
23
24
23
24
23
Address
Address
16
15
15
16
15
15
8
7
8
7
8
7
8
7
0
0
0
0
Address
16
15
15
8
7
8
7
0
0
4n + 6
4n + 4
4n + 3
Word data
External
data bus
4n + 5
Word data
External
data bus
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Word data
External
data bus
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BUS CONTROL FUNCTION
(d) When the data bus width is 8 bits (big endian) (1/2)
<1> Access to address 4n
1st access
2nd access
3rd access
4th access
31
31
31
31
24
23
24
23
24
23
24
23
16
15
16
15
16
15
16
15
Address
8
7
7
0
0
Address
8
7
7
0
0
4n
Word data
External
data bus
Address
8
7
7
0
0
4n + 1
Word data
External
data bus
Address
8
7
7
0
0
4n + 3
4n + 2
Word data
External
data bus
Word data
External
data bus
<2> Access to address 4n + 1
1st access
2nd access
3rd access
4th access
31
31
31
31
24
23
24
23
24
23
24
23
16
15
16
15
16
15
16
15
Address
8
7
7
0
0
Address
8
7
7
0
0
4n + 1
Word data
116
External
data bus
Address
8
7
7
0
0
4n + 2
Word data
External
data bus
Address
8
7
7
0
0
4n + 4
4n + 3
Word data
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External
data bus
Word data
External
data bus
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BUS CONTROL FUNCTION
(d) When the data bus width is 8 bits (big endian) (2/2)
<3> Access to address 4n + 2
1st access
2nd access
3rd access
4th access
31
31
31
31
24
23
24
23
24
23
24
23
16
15
16
15
16
15
16
15
Address
8
7
7
0
0
Address
8
7
7
0
0
4n + 2
Word data
External
data bus
Address
8
7
7
0
0
4n + 3
Word data
External
data bus
Address
8
7
7
0
0
4n + 5
4n + 4
Word data
External
data bus
Word data
External
data bus
<4> Access to address 4n + 3
1st access
2nd access
3rd access
4th access
31
31
31
31
24
23
24
23
24
23
24
23
16
15
16
15
16
15
16
15
Address
8
7
7
0
0
Address
8
7
7
0
0
4n + 3
Word data
External
data bus
Address
8
7
7
0
0
4n + 4
Word data
External
data bus
Address
8
7
7
0
0
4n + 6
4n + 5
Word data
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data bus
Word data
External
data bus
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4.6
BUS CONTROL FUNCTION
Wait Function
4.6.1 Programmable wait function
(1) Data wait control registers 0, 1 (DWC0, DWC1)
To facilitate interfacing with low-speed memory and I/Os, it is possible to insert up to 7 data wait states in the
starting bus cycle for each CS space.
The number of wait states can be specified by program using data wait control registers 0 and 1 (DWC0,
DWC1). Just after system reset, all blocks have 7 data wait states inserted.
These registers can be read/written in 16-bit units.
Cautions 1. The internal ROM area and internal RAM area are not subject to programmable waits
and ordinarily no wait access is carried out. The on-chip peripheral I/O area is also not
subject to programmable wait states, with wait control performed by each peripheral
function only.
2. In the following cases, the settings of registers DWC0 and DWC1 are invalid (wait
control is performed by each memory controller).
• Page ROM on-page access
• EDO DRAM access
• SDRAM access
3. Write to the DWC0 and DWC1 registers after reset, and then do not change the set
values.
Also, do not access an external memory area other than the one for this
initialization routine until the initial setting of the DWC0 and DWC1 registers is
complete. However, it is possible to access external memory areas whose initialization
settings are complete.
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15
DWC0
14
12
11
10
9
8
7
6
5
4
3
2
1
0
0 DW32 DW31 DW30 0 DW22 DW21 DW20 0 DW12 DW11 DW10 0 DW02 DW01 DW00
CSn signal
CS3
15
DWC1
13
BUS CONTROL FUNCTION
14
13
CS2
12
11
10
9
CS1
8
7
6
5
CS7
Bit position
Bit name
14 to 12,
10 to 8,
6 to 4,
2 to 0
DWn2 to
DWn0
(n = 0 to 7)
CS6
After reset
7777H
Address
FFFFF486H
After reset
7777H
CS0
4
3
2
1
0
0 DW72 DW71 DW70 0 DW62 DW61 DW60 0 DW52 DW51 DW50 0 DW42 DW41 DW40
CSn signal
Address
FFFFF484H
CS5
CS4
Function
Data Wait
Specifies the number of wait states inserted in the CSn space.
DWn2
DWn1
DWn0
Number of wait states inserted in CSn space
0
0
0
Not inserted
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
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BUS CONTROL FUNCTION
(2) Address setup wait control register (ASC)
The V850E/MA1 allows insertion of address setup wait states before the SRAM/page ROM cycle (the setting
of the ASC register in the EDO DRAM/SDRAM cycle is invalid).
The number of address setup wait states can be set with the ASC register for each CS space.
This register can be read/written in 16-bit units.
Caution
15
ASC
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
AC71 AC70 AC61 AC60 AC51 AC50 AC41 AC40 AC31 AC30 AC21 AC20 AC11 AC10 AC01 AC00
CSn signal
120
During an address setup wait, the WAIT pin-based external wait function is disabled.
CS7
CS6
CS5
CS4
CS3
CS2
CS1
Address
FFFFF48AH
After reset
FFFFH
CS0
Bit position
Bit name
Function
15 to 0
ACn1, ACn0
(n = 0 to 7)
Address Cycle
Specifies the number of address setup wait states inserted before the SRAM/page ROM
cycle for each CS space.
ACn1
ACn0
Number of wait states
0
0
Not inserted
0
1
1
1
0
2
1
1
3
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BUS CONTROL FUNCTION
(3) Bus cycle period control register (BCP)
In the V850E/MA1, the bus cycle period can be doubled during SRAM, external ROM, external I/O, page
ROM, and EDO DRAM access. The bus cycle period is controlled using the BCP register. When the BCP bit
of the BCP register is set to 1, the external bus operates at one half the frequency of the internal system
clock.
Use the BUSCLK pin to output the half clock of the internal system clock. Specify the bus cycle period as
“Double” with the BCP bit of the BCP register, then set the port CM mode control register (PMCCM) and port
CM function control register (PFCCM).
This register can be read/written in 8-bit units.
Cautions 1. During a flyby DMA transfer for SRAM, external ROM, or external I/O, the IORD and
IOWR signals are always output, irrespective of the IOEN bit setting.
In page ROM and EDO DRAM cycles, on the other hand, the IOEN bit setting has no
meaning.
2. Write to the BCP register after reset, and then do not change the set values.
3. If the CLKOUT output mode is selected for the PCM1 pin by using the PMCCM register
when the bus cycle period is doubled (BCP = 1), the bus cycle is half the frequency of
the internal system clock, but the same frequency as the internal system clock is output
from the PCM1 pin.
BCP
7
6
5
4
3
2
1
0
BCP
0
0
0
IOEN
0
0
0
Bit position
7
Bit name
BCP
IOEN
After reset
00H
Function
Bus Cycle Period
Specifies the length of the bus cycle period.
BCP
3
Address
FFFFF48CH
Bus cycle period
0
Normal
1
Double
IORD, IOWR Enable
Specifies whether to enable/disable the operation of IORD and IOWR in SRAM, external
ROM, and external I/O cycles.
IOEN
Enable/disable IORD and IOWR operation
0
Disables the operation of IORD and IOWR in SRAM, external ROM,
and external I/O cycles.
1
Enables the operation of IORD and IOWR in SRAM, external ROM,
and external I/O cycles.
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Figure 4-4. Timing Example of Access to SRAM, External ROM, and External I/O (Read → Write)
T1
T2
T1
T2
Internal system
clock
BUSCLK (output)
A0 to A25 (output)
Address
Address
BCYST (output)
CSn/RASm (output)
RD (output)
OE (output)
WE (output)
UWR/UCAS (output)
LWR/LCAS (output)
Note
IORD (output)
IOWR (output)
LBE (output)
UBE (output)
Data
D0 to D15 (I/O)
WAIT (input)
Note When the IOEN bit of the BCP register is set to 1.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6
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BUS CONTROL FUNCTION
4.6.2 External wait function
When an extremely slow device, I/O, or asynchronous system is connected, an arbitrary number of wait states can
be inserted in the bus cycle by the external wait pin (WAIT) for synchronization with the external device.
Just as with programmable waits, accessing internal ROM, internal RAM, and on-chip peripheral I/O areas cannot
be controlled by external waits.
The external WAIT signal can be input asynchronously to CLKOUT and is sampled at the falling edge of the clock
in the T1 and TW states of a bus cycle. If the setup/hold time in the sampling timing is not satisfied, the wait state
may or may not be inserted in the next state.
4.6.3 Relationship between programmable wait and external wait
A wait cycle is inserted as the result of an OR operation between the wait cycle specified by the set value of the
programmable wait and the wait cycle controlled by the WAIT pin. In other words, the number of wait cycles is
determined by the side with the greatest number of cycles.
Programmable wait
Wait control
Wait by WAIT pin
For example, if the timings of the programmable wait and the WAIT pin signal are as illustrated below, three wait
states will be inserted in the bus cycle.
Figure 4-5. Example of Wait Insertion
T1
TW
TW
TW
T2
CLKOUT
WAIT pin
Wait by WAIT pin
Programmable wait
Wait control
Remark
The circle { indicates the sampling timing
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BUS CONTROL FUNCTION
4.6.4 Bus cycles in which wait function is valid
In the V850E/MA1, the number of waits can be specified according to the memory type specified for each memory
block. The following shows the bus cycles in which the wait function is valid and the registers used for wait setting.
Table 4-1. Bus Cycles in Which Wait Function Is Valid
Bus Cycle
Type of Wait
Programmable Wait Setting
Register
SRAM, external ROM, external I/O cycles Address setup wait
Read access
0 to 3
– (invalid)
DWC0, DWC1
DWn2 to DWn0
0 to 7
√ (valid)
Address setup wait
ASC
ACn1, ACn0
0 to 3
– (invalid)
Off-page
Data access wait
DWC0, DWC1
DWn2 to DWn0
0 to 7
√ (valid)
On-page
Data access wait
PRC
PRW2 to PRW0
0 to 7
√ (valid)
Off-page
RAS precharge
SCRm
RPC1m, RPC0m
1 to 3
– (invalid)
Row address hold
SCRm
RHC1m, RHC0m
0 to 3
– (invalid)
Data access wait
SCRm
DAC1m, DAC0m
0 to 3
– (invalid)
CAS precharge
SCRm
CPC1m, CPC0m
0 to 3
– (invalid)
Data access wait
SCRm
DAC1m, DAC0m
0 to 3
– (invalid)
RAS precharge
SCRm
RPC1m, RPC0m
1 to 3
– (invalid)
Row address hold
SCRm
RHC1m, RHC0m
0 to 3
– (invalid)
On-page
Write access
ACn1, ACn0
Wait from
Wait
WAIT pin
Count
Data access wait
Page ROM cycle
EDO DRAM
cycle
ASC
Bit
Off-page
On-page
CBR refresh cycle
CBR self-refresh cycle
Data access wait
SCRm
DAC1m, DAC0m
0 to 3
– (invalid)
CAS precharge
SCRm
CPC1m, CPC0m
1 to 3
– (invalid)
Data access wait
SCRm
DAC1m, DAC0m
0 to 3
– (invalid)
RAS precharge
RWC
RRW1, RRW0
0 to 3
– (invalid)
RAS active width
RWC
RCW2 to RCW0
1 to 7
– (invalid)
RAS precharge
RWC
RRW1, RRW0
0 to 3
– (invalid)
RAS active width
RWC
RCW2 to RCW0
1 to 7
– (invalid)
Self-refresh release width
RWC
SRW2 to SRW0
0 to 7
– (invalid)
SDRAM cycle
Row address precharge
SCRm
BCW1m, BCW0m 1 to 3
– (invalid)
DMA flyby
External I/O → SRAM
transfer cycle DRAM →
Off-page
external I/O
Data access wait
DWC0, DWC1
DWn2 to DWn0
0 to 7
√ (valid)
RAS precharge
SCRm
RPC1m, RPC0m
1 to 3
– (invalid)
Row address hold
SCRm
RHC1m, RHC0m
0 to 3
– (invalid)
Data access wait
SCRm
DAC1m, DAC0m
0 to 3
√ (valid)
On-page
CAS precharge
SCRm
CPC1m, CPC0m
0 to 3
– (invalid)
Data access wait
SCRm
DAC1m, DAC0m
0 to 3
√ (valid)
Off-page
RAS precharge
SCRm
RPC1m, RPC0m
1 to 3
– (invalid)
Row address hold
SCRm
RHC1m, RHC0m
0 to 3
√ (valid)
Data access wait
SCRm
DAC1m, DAC0m
0 to 3
– (invalid)
CAS precharge
SCRm
CPC1m, CPC0m
1 to 3
√ (valid)
Data access wait
SCRm
DAC1m, DAC0m
0 to 3
– (invalid)
External I/O
→ DRAM
On-page
Remark
124
n = 0 to 7, m = 1, 3, 4, 6
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4.7
BUS CONTROL FUNCTION
Idle State Insertion Function
To facilitate interfacing with low-speed memory devices, an idle state (TI) can be inserted into the current bus cycle
after the T2 state to meet the data output float delay time (tDF) on memory read access for each CS space. The bus
cycle following the T2 state starts after the idle state is inserted.
An idle state is inserted at the timing shown below.
• After read/write cycles for SRAM, external I/O, or external ROM
• After a read cycle for page ROM
• After a read cycle for EDO DRAM (no idle state is inserted when accessing the same CS space)
• After a read cycle for SDRAM
The idle state insertion setting can be specified by program using the bus cycle control register (BCC).
Immediately after the system reset, idle state insertion is automatically programmed for all memory blocks.
For the timing when an idle state is inserted, see the memory access timings in Chapter 5.
(1) Bus cycle control register (BCC)
This register can be read/written in 16-bit units.
Cautions 1. The internal ROM area, internal RAM area, and on-chip peripheral I/O area are not
subject to idle state insertion.
2. Write to the BCC register after reset, and then do not change the set value. Also, do not
access an external memory area other than the one for this initialization routine until the
initial setting of the BCC register is complete. However, it is possible to access external
memory areas whose initialization settings are complete.
15
BCC
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BC71 BC70 BC61 BC60 BC51 BC50 BC41 BC40 BC31 BC30 BC21 BC20 BC11 BC10 BC01 BC00
CSn signal
CS7
CS6
Bit position
Bit name
15 to 0
BCn1, BCn0
(n = 0 to 7)
CS5
CS4
CS3
CS2
CS1
Address
FFFFF488H
After reset
FFFFH
CS0
Function
Data Cycle
Specifies the insertion of an idle state in the CSn space.
BCn1
BCn0
Idle state in CSn space
0
0
Not inserted
0
1
1
1
0
2
1
1
3
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4.8
BUS CONTROL FUNCTION
Bus Hold Function
4.8.1 Function outline
If the PCM2 and PCM3 pins are specified in the control mode, the HLDAK and HLDRQ functions become valid.
If it is determined that the HLDRQ pin has become active (low level) as a bus mastership request from another bus
master, the external address/data bus and each strobe pin are shifted to high impedance and then released (bus hold
state). If the HLDRQ pin becomes inactive (high level) and the bus mastership request is canceled, driving of these
pins begins again.
During the bus hold period, the internal operations of the V850E/MA1 continue until the external memory is
accessed.
The bus hold state can be known by the HLDAK pin becoming active (low level). The period from when the
HLDRQ pin becomes active (low level) to when the HLDAK pin becomes active (low level) is at least 2 clocks.
In a multiprocessor configuration, etc., a system with multiple bus masters can be configured.
State
Data Bus
Width
CPU bus lock
16 bits
8 bits
Access Type
Timing at Which Bus Hold Request
Cannot Be Acknowledged
Word access for even
address
Between first and second accesses
Word access for odd
address
Between first and second accesses
Halfword access for odd
address
Between first and second accesses
Word access
Between first and second accesses
Between second and third accesses
Between second and third accesses
Between third and forth accesses
Halfword access
Read modify write access of
bit manipulation instruction
–
–
Between first and second accesses
Between read access and write access
Cautions 1. When an external bus master accesses EDO DRAM during a bus hold state, make sure that
the external bus master secures the RAS precharge time.
2. When an external bus master accesses SDRAM during a bus hold state, make sure that the
external bus master executes the all bank precharge command.
The CPU always executes the all bank precharge command to release a bus hold state. In a
bus hold state, do not allow an external bus master to change the SDRAM command
register value.
3. The HLDRQ function is invalid during a reset period. The HLDAK pin becomes active either
immediately after or after the insertion of a 1-clock address cycle from when the RESET pin
is set to inactive following the simultaneous activation of the RESET and HLDRQ pins.
When a bus master other than the V850E/MA1 is externally connected, use the RESET
signal for bus arbitration at power-on.
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BUS CONTROL FUNCTION
4.8.2 Bus hold procedure
The procedure of the bus hold function is illustrated below.
<1> HLDRQ = 0 acknowledged
<2> All bus cycle start requests held pending
Normal state
<3> End of current bus cycle
<4> Transition to bus idle state
<5> HLDAK = 0
Bus hold state
<6> HLDRQ = 1 acknowledged
<7> HLDAK = 1
<8> Pending bus cycle start requests released
Normal state
<9> Start of bus cycle
HLDRQ (input)
HLDAK (output)
<1> <2>
<3><4> <5>
<6> <7><8><9>
4.8.3 Operation in power-save mode
In the software STOP or IDLE mode, the internal system clock is stopped. Consequently, the bus hold state is not
set since the HLDRQ pin cannot be acknowledged even if it becomes active.
In the HALT mode, the HLDAK pin immediately becomes active when the HLDRQ pin becomes active, and the bus
hold state is set. When the HLDRQ pin becomes inactive after that, the HLDAK pin also becomes inactive. As a
result, the bus hold state is cleared and the HALT mode is set again.
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4.8.4 Bus hold timing (SRAM)
(1) SRAM (when read, no idle states inserted)
T1
T2
TI
Note 1
TH
TH
TI
Note 1
CLKOUT (input)
HLDRQ (input)
HLDAK (output)
A0 to A25 (output)
Address
BCYST (output)
CSn/RASm (output)
RD (output)
OE (output)
WE (output)
UWR/UCAS (output)
LWR/LCAS (output)
IORD (output)
Note 2
IOWR (output)
LBE (output)
UBE (output)
D0 to D15 (I/O)
Data
WAIT (input)
Notes 1.
2.
This idle state (TI) is independent of the BCC register setting.
When the IOEN bit of the BCP register is set to 1.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6
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BUS CONTROL FUNCTION
(2) SRAM (when written, three idle states inserted)
T1
T2
TI
Note 1
Note 1
TI
Note 1
TI
Note 2
TI
TH
TH
Note 2
TI
CLKOUT (input)
HLDRQ (input)
HLDAK (output)
A0 to A25 (output)
Address
Undefined
BCYST (output)
CSn/RASm (output)
RD (output)
OE (output)
WE (output)
UWR/UCAS (output)
LWR/LCAS (output)
IORD (output)
Note 3
IOWR (output)
LBE (output)
UBE (output)
D0 to D15 (I/O)
Data
WAIT (input)
Notes 1.
This idle state (TI) is inserted by means of a BCC register setting.
2.
This idle state (TI) is independent of the BCC register setting.
3.
When the IOEN bit of the BCP register is set to 1.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6
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BUS CONTROL FUNCTION
4.8.5 Bus hold timing (EDO DRAM)
(1) EDO DRAM (when read, no idle states inserted)
Note 1
TRPW
T1
T2
TE
TH
TH
TI
Note 3
CLKOUT (input)
HLDRQ (input)
HLDAK (output)
A0 to A25 (output)
Row
address
Column
address
Undefined
BCYST (output)
CSn/RASm (output)
Note 2
RD (output)
OE (output)
WE (output)
UWR/UCAS (output)
LWR/LCAS (output)
IORD (output)
IOWR (output)
D0 to D15 (I/O)
Data
WAIT (input)
Notes 1.
TRPW is always inserted for 1 or more cycles.
2.
This timing applies when in the RAS hold mode.
3.
This idle state (TI) is independent of the BCC register setting.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6
4. Timing from DRAM access to bus hold state.
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BUS CONTROL FUNCTION
(2) EDO DRAM (when read, three idle states inserted)
Note 1
TRPW
T1
T2
Note 3
TE
TI
TH
TH
Note 4
TI
CLKOUT (input)
HLDRQ (input)
HLDAK (output)
A0 to A25 (output)
Row
address
Column
address
Undefined
BCYST (output)
CSn/RASm (output)
Note 2
RD (output)
OE (output)
WE (output)
UWR/UCAS (output)
LWR/LCAS (output)
IORD (output)
IOWR (output)
D0 to D15 (I/O)
Data
WAIT (input)
Notes 1.
TRPW is always inserted for 1 or more cycles.
2.
This timing applies when in the RAS hold mode.
3.
This idle state (TI) is inserted by means of a BCC register setting. The number of idle states (TI)
to be inserted depends on the timing of bus hold request acknowledgement.
4.
This idle state (TI) is independent of the BCC register setting.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6
4. Timing from DRAM access to bus hold state.
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BUS CONTROL FUNCTION
(3) EDO DRAM (when written)
TRPW
Note 1
T1
T2
TE
TH
TH
Note 3
TI
CLKOUT (input)
HLDRQ (input)
HLDAK (output)
A0 to A25 (output)
Row
address
Column
address
Undefined
BCYST (output)
CSn/RASm (output)
Note 2
RD (output)
OE (output)
WE (output)
UWR/UCAS (output)
LWR/LCAS (output)
IORD (output)
IOWR (output)
D0 to D15 (I/O)
Data
WAIT (input)
Notes 1.
TRPW is always inserted for 1 or more cycles.
2.
This timing applies when in the RAS hold mode.
3.
This idle state (TI) is independent of the BCC register setting.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6
4. Timing from DRAM access to bus hold state.
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BUS CONTROL FUNCTION
(4) EDO DRAM (when written, when bus hold request acknowledged during on-page access)
Off-page
cycle
TRPW
Note 1
T1
T2
TCPW
Note 1
TB
Note 2
TI
TH
TH
Note 2
TI
TRPW
Note 1
CLKOUT (input)
HLDRQ (input)
HLDAK (output)
A0 to A25 (output)
Row
address
Column
address
Column
address
Undefined
BCYST (output)
CSn/RASm (output)
RD (output)
OE (output)
WE (output)
UWR/UCAS (output)
LWR/LCAS (output)
IORD (output)
IOWR (output)
D0 to D15 (I/O)
Data
Data
WAIT (input)
Notes 1.
2.
TRPW and TCPW are always inserted for 1 or more cycles.
This idle state (TI) is independent of the BCC register setting.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6
4. Timing from DRAM access to bus hold state.
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4.8.6 Bus hold timing (SDRAM)
(1) SDRAM (when read, latency = 2, no idle states inserted)
TW
Note 1
TACT TBCW TREAD TLATE TLATE TI
TH
TH
Note 1
TI
BCW
SDCLK (output)
HLDRQ (input)
HLDAK (output)
Address
Note 3 (output)
Undefined
Bank
Address address
Undefined
A10 (output)
Row
Address address
Undefined
A0 to A9 (output)
Row
Address address
Bank address (output)
Column address
BCYST (output)
CSn (output)
SDRAS (output)
SDCAS (output)
RD (output)
OE (output)
WE (output)
LDQM (output)
UDQM (output)
Data
D0 to D15 (I/O)
SDCKE (output)
Notes 1.
H
This idle state (TI) is independent of the BCC register setting.
2.
The all bank precharge command is always executed.
3.
Addresses other than the bank address, A10, and A0 to A9.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 1, 3, 4, 6
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Undefined
TW
Note 2
TPRE
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BUS CONTROL FUNCTION
(2) SDRAM (when read, latency = 2, three idle states inserted)
TW
Note 1
TACT TBCW TREAD TLATE TLATE TI
TI
Note 1
TI
Note 1
TI
Note 2
TH
TH
TI
Note 2
TW
TPRE
Note 3
BCW
SDCLK (output)
HLDRQ (input)
HLDAK (output)
Address
Note 4 (output)
Bank address (output)
Bank
Address address
A10 (output)
Address address
Undefined
Undefined
Row
A0 to A9 (output)
Address
Row
address
Undefined
Column address
Undefined
BCYST (output)
CSn (output)
SDRAS (output)
SDCAS (output)
RD (output)
OE (output)
WE (output)
LDQM (output)
UDQM (output)
Data
D0 to D15 (I/O)
SDCKE (output)
Notes 1.
H
This idle state (TI) is inserted by means of a BCC register setting.
2.
This idle state (TI) is independent of the BCC register setting.
3.
The all bank precharge command is always executed.
4.
Addresses other than the bank address, A10, and A0 to A9.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 1, 3, 4, 6
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BUS CONTROL FUNCTION
(3) SDRAM (when written)
TW
Note 1
TACT TBCW TWR TWPRE TWE TI
TH
TH
TI
Note 1
BCW
SDCLK (output)
HLDRQ (input)
HLDAK (output)
Address
Note 3 (output)
Bank address (output)
Bank
Address address
A10 (output)
Address address
Undefined
Row
A0 to A9 (output)
Address
Row
address
Undefined
Column address
BCYST (output)
CSn (output)
SDRAS (output)
SDCAS (output)
RD (output)
OE (output)
WE (output)
LDQM (output)
UDQM (output)
Data
D0 to D15 (I/O)
SDCKE (output)
Notes 1.
H
This idle state (TI) is independent of the BCC register setting.
2.
The all bank precharge command is always executed.
3.
Addresses other than the bank address, A10, and A0 to A9.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 1, 3, 4, 6
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TW
Note 2
TPRE
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BUS CONTROL FUNCTION
(4) SDRAM (when written, when bus hold request acknowledged during on-page access)
TW
TACT TBCW TWR
Note 1
TWR TWPRE TWE TI
TH
TH
Note 1
TI
TW
Note 2
TPRE
BCW
SDCLK (output)
HLDRQ (input)
HLDAK (output)
Address
Note 3 (output)
Bank address (output)
Bank
Address address
A10 (output)
Address address
Address
Undefined
Row
A0 to A9 (output)
Address
Undefined
Undefined
Row
address Column address
Column address
Undefined
BCYST (output)
CSn (output)
SDRAS (output)
SDCAS (output)
RD (output)
OE (output)
WE (output)
LDQM (output)
UDQM (output)
Data
D0 to D15 (I/O)
SDCKE (output)
Notes 1.
Data
H
This idle state (TI) is independent of the BCC register setting.
2.
The all bank precharge command is always executed.
3.
Addresses other than the bank address, A10, and A0 to A9.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 1, 3, 4, 6
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4.9
BUS CONTROL FUNCTION
Bus Priority Order
There are five external bus cycles: bus hold, instruction fetch, operand data access, DMA cycle, and refresh cycle.
In order of priority, bus hold is the highest, followed by the refresh cycle, DMA cycle, operand data access, and
instruction fetch, in that order.
An instruction fetch may be inserted between a read access and write access during a read modify write access.
Also, an instruction fetch may be inserted between bus accesses when the CPU bus clock is used.
Table 4-2. Bus Priority Order
Priority
Order
High
Low
138
External Bus Cycle
Bus Master
Bus hold
External device
Refresh cycle
DRAM controller
DMA cycle
DMA controller
Operand data access
CPU
Instruction fetch
CPU
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4.10 Boundary Operation Conditions
4.10.1 Program space
(1) Branching to the on-chip peripheral I/O area or successive fetches from the internal RAM area to the on-chip
peripheral I/O area are prohibited. If the above is performed (branching or successive fetch), undefined data
is fetched, and fetching from the external memory is not performed.
(2) If a branch instruction exists at the upper limit of the internal RAM area, a prefetch operation (invalid fetch)
that straddles over the on-chip peripheral I/O area does not occur.
(3) If a burst fetch is performed for contiguous memory blocks, it is terminated at the upper limit of a block, and
the startup cycle is started at the lower limit of the next block.
(4) Burst fetch is valid only in the external memory area. In memory block 7, it is terminated when the internal
address count value has reached the upper limit of the external memory area.
4.10.2 Data space
The V850E/MA1 is provided with an address misalign function.
Through this function, regardless of the data format (word or halfword), data can be allocated to all addresses.
However, in the case of word data and halfword data, if the data is not subject to boundary alignment, the bus cycle
will be generated at least 2 times and bus efficiency will drop.
(1) In the case of halfword-length data access
When the address’s LSB is 1, a byte-length bus cycle will be generated 2 times.
(2) In the case of word-length data access
(a) When the address’s LSB is 1, bus cycles will be generated in the order of byte-length bus cycle,
halfword-length bus cycle, and byte-length bus cycle.
(b) When the address’s lower 2 bits are 10, a halfword-length bus cycle will be generated 2 times.
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CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION
5.1
SRAM, External ROM, External I/O Interface
5.1.1 Features
• SRAM is accessed in a minimum of 2 states.
• Up to 7 states of programmable data waits can be inserted by setting the DWC0 and DWC1 registers.
• Data wait can be controlled via WAIT pin input.
• Up to 3 idle states can be inserted after a read/write cycle by setting the BCC register.
• Up to 3 address setup wait states can be inserted by setting the ASC register.
• DMA flyby transfer can be activated (SRAM → external I/O, external I/O → SRAM)
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5.1.2 SRAM connection
Examples of connection to SRAM are shown below.
Figure 5-1. Examples of Connection to SRAM (1/2)
(a) When data bus width is 8 bits
A1 to A17
A0 to A16
D0 to D7
D1 to D8
CSn
CS
RD
OE
LWR
WE
1 Mb SRAM
(128 Kwords × 8 bits)
A0 to A16
D1 to D8
D8 to D15
CS
OE
UWR
WE
1 Mb SRAM
(128 Kwords × 8 bits)
V850E/MA1
(b) When data bus width is 16 bits
A1 to A17
A0 to A16
D0 to D15
D1 to D16
CSn
CS
RD
OE
LWR
WE
UWR
LBE
LBE
UBE
UBE
2 Mb SRAM
(256 Kwords × 16 bits)
V850E/MA1
Remark
n = 0 to 7
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Figure 5-1. Examples of Connection to SRAM (2/2)
(c) Mixture of SRAM (256 Kwords × 16 bits) and SDRAM (1 Mword × 16 bits)
A1 to A17, A21, A22
A0 to A16
D0 to D15
D1 to D16
CSn
CS
RD
LDQM/LWR
OE
WE
UDQM/UWR
LBE
UBE
2 Mb SRAM
(256 Kwords × 16 bits)
A1 to A12
A0 to A11
A21Note, A22
A12, A13
DQ0 to DQ15
CS
CSm
LDQM
UDQM
SDRAS/UBE
RAS
SDCAS/LBE
CAS
WE
WE
SDCLK
CLK
SDCKE
CKE
64 Mb SDRAM
(1 Mword × 4 bits × 4 banks)
V850E/MA1
Note The address signals used depend on the SDRAM model.
Remark
142
n = 0 to 7, m = 1, 3, 4, 6 (n ≠ m)
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5.1.3 SRAM, external ROM, external I/O access
Figure 5-2. SRAM, External ROM, External I/O Access Timing (1/6)
(a) When read
T1
T2
T1
TW
T2
CLKOUT (output)
A0 to A25 (output)
Address
Address
BCYST (output)
CSn/RASm (output)
RD (output)
OE (output)
WE (output)
UWR/UCAS (output)
LWR/LCAS (output)
Note
IORD (output)
IOWR (output)
LBE (output)
UBE (output)
D0 to D15 (I/O)
Data
Data
WAIT (input)
Note When the IOEN bit of the BCP register is set to 1.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6
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Figure 5-2. SRAM, External ROM, External I/O Access Timing (2/6)
(b) When read (address setup wait, idle state insertion)
TASW
T2
T1
CLKOUT (output)
Address
A0 to A25 (output)
BCYST (output)
CSn/RASm (output)
RD (output)
OE (output)
WE (output)
UWR/UCAS (output)
LWR/LCAS (output)
IORD (output)
Note
IOWR (output)
LBE (output)
UBE (output)
Data
D0 to D15 (I/O)
WAIT (input)
Note When the IOEN bit of the BCP register is set to 1.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6
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MEMORY ACCESS CONTROL FUNCTION
Figure 5-2. SRAM, External ROM, External I/O Access Timing (3/6)
(c) When written
T1
T2
T1
TW
T2
CLKOUT (output)
A0 to A25 (output)
Address
Address
BCYST (output)
CSn/RASm (output)
RD (output)
OE (output)
WE (output)
UWR/UCAS (output)
LWR/LCAS (output)
IORD (output)
IOWR (output)Note
LBE (output)
UBE (output)
D0 to D15 (I/O)
Data
Data
WAIT (input)
Note When the IOEN bit of the BCP register is set to 1.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6
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Figure 5-2. SRAM, External ROM, External I/O Access Timing (4/6)
(d) When written (address setup wait, idle state insertion)
TASW
T1
T2
CLKOUT (output)
Address
A0 to A25 (output)
BCYST (output)
CSn/RASm (output)
RD (output)
OE (output)
WE (output)
UWR/UCAS (output)
LWR/LCAS (output)
IORD (output)
Note
IOWR (output)
LBE (output)
UBE (output)
Data
D0 to D15 (I/O)
WAIT (input)
Note When the IOEN bit of the BCP register is set to 1.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6
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Figure 5-2. SRAM, External ROM, External I/O Access Timing (5/6)
(e) For read → write operation
T1
T2
T1
T2
CLKOUT (output)
A0 to A25 (output)
Address
Address
BCYST (output)
CSn/RASm (output)
RD (output)
OE (output)
WE (output)
UWR/UCAS (output)
LWR/LCAS (output)
IORD (output)
IOWR (output)
Note
Note
LBE (output)
UBE (output)
D0 to D15 (I/O)
Data
Data
WAIT (input)
Note When the IOEN bit of the BCP register is set to 1.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6
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Figure 5-2. SRAM, External ROM, External I/O Access Timing (6/6)
(f) For write → read operation
T1
T2
T1
T2
CLKOUT (output)
A0 to A25 (output)
Address
Address
BCYST (output)
CSn/RASm (output)
RD (output)
OE (output)
WE (output)
UWR/UCAS (output)
LWR/LCAS (output)
IORD (output)
IOWR (output)
Note
Note
LBE (output)
UBE (output)
Data
D0 to D15 (I/O)
WAIT (input)
Note When the IOEN bit of the BCP register is set to 1.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6
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5.2
MEMORY ACCESS CONTROL FUNCTION
Page ROM Controller (ROMC)
The page ROM controller (ROMC) is provided for accessing ROM (page ROM) with a page access function.
Addresses are compared with the immediately preceding bus cycle and wait control for normal access (off-page)
and page access (on-page) is executed. This controller can handle page widths from 8 to 128 bytes.
5.2.1 Features
• Direct connection to 8-bit/16-bit page ROM supported
• For 16-bit bus width: 4/8/16/32/64-word page access supported
For 8-bit bus width: 8/16/32/64/128-word page access supported
• Page ROM is accessed in a minimum of 2 states.
• On-page judgment function
• Addresses to be compared can be changed by setting the PRC register.
• Up to 7 states of programmable data waits can be inserted during an on-page cycle by setting the PRC
register.
• Up to 7 states of programmable data waits can be inserted during an off-page cycle by setting the DWC0 and
DWC1 registers.
• Waits can be controlled via WAIT pin input.
• DMA flyby cycle can be activated (page ROM → external I/O)
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5.2.2 Page ROM connection
Examples of connection to page ROM are shown below.
Figure 5-3. Examples of Connection to Page ROM
(a) When data bus width is 16 bits
A1 to A20
A0 to A19
D0 to D15
O1 to O16
CSn
CE
RD
OE
V850E/MA1
16 Mb page ROM
(1 Mword × 16 bits)
(b) When data bus width is 8 bits
A1 to A21
A0 to A20
D0 to D7
O1 to O8
CSn
CE
RD
OE
16 Mb page ROM
(2 Mwords × 8 bits)
A0 to A20
D8 to D15
O0 to O8
CE
OE
16 Mb page ROM
(2 Mwords × 8 bits)
V850E/MA1
Remark
150
n = 0 to 7
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5.2.3 On-page/off-page judgment
Whether a page ROM cycle is on-page or off-page is judged by latching the address of the previous cycle and
comparing it with the address of the current cycle.
Through the page ROM configuration register (PRC), according to the configuration of the connected page ROM
and the number of continuously readable bits, one of the addresses (A3 to A6) is set as the masking address (no
comparison is made).
Figure 5-4. On-Page/Off-Page Judgment During Page ROM Connection (1/2)
(a) In case of 16 Mb (1 M × 16 bits) page ROM (4-word page access)
Internal address latch
(immediately preceding
address)
a25
a24
a23
a22
a21
a20
a7
a6
a5
a4
a3
MA6 MA5 MA4 MA3
0
0
0
0
PRC register setting
Comparison
V850E/MA1
address output
A25
A24
A23
A22
A21
A20
A7
A6
A5
A4
A3
A2
A1
Page ROM address
A19
A6
A5
A4
A3
A2
A1
A0
Off-page address
A0
On-page address
Continuous reading possible: 16-bit data bus width × 4 words
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Figure 5-4. On-Page/Off-Page Judgment During Page ROM Connection (2/2)
(b) In case of 16 Mb (1 M × 16 bits) page ROM (8-word page access)
Internal address latch
(immediately preceding
address)
a25
a24
a23
a22
a21
a20
a7
a6
a5
a4
a3
MA6 MA5 MA4 MA3
0
0
0
1
PRC register setting
Comparison
A24
A23
A22
A21
A20
A7
A6
A5
A4
A3
A2
A1
Page ROM address
A19
A6
A5
A4
A3
A2
A1
A0









A25





















V850E/MA1
address output
Off-page address
On-page address
A0
Continuous reading possible:
16-bit data bus width × 8 words
(c) In case of 32 Mb (2 M × 16 bits) page ROM (16-word page access)
Internal address latch
(immediately preceding
address)
a25
a24
a23
a22
a21
a20
a7
a6
a5
a4
a3
MA6 MA5 MA4 MA3
0
0
1
1
PRC register setting
Comparison
A24
A23
A22
A21
A20
A7
A6
A5
A4
A3
A2
A1
Page ROM address
A19
A6
A5
A4
A3
A2
A1
A0
Off-page address
A0












A25


















V850E/MA1
address output
On-page address
Continuous reading possible:
16-bit data bus width × 16 words
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5.2.4 Page ROM configuration register (PRC)
This register specifies whether page ROM cycle on-page access is enabled or disabled. If on-page access is
enabled, the masking address (no comparison is made) out of the addresses (A3 to A6) corresponding to the
configuration of the connected page ROM and the number of bits that can be read continuously, as well as the
number of waits corresponding to the internal system clock, are set.
This register can be read/written in 16-bit units.
Caution
Write to the PRC register after reset, and then do not change the set value. Also, do not
access an external memory area other than the one for this initialization routine until the
initial setting of the PRC register is complete. However, it is possible to access external
memory areas whose initialization settings are complete.
15
PRC
14
13
12
11
0 PRW2 PRW1 PRW0 0
Bit position
14 to 12
3 to 0
10
9
8
7
6
5
4
0
0
0
0
0
0
0
Bit name
PRW2 to
PRW0
MA6 to
MA3
3
2
1
0
MA6 MA5 MA4 MA3
Address
FFFFF49AH
After reset
7000H
Function
Page-ROM On-page Wait Control
Sets the number of waits corresponding to the internal system clock.
The number of waits set by these bits is inserted only for on-page access. For off-page
access, the waits set by registers DWC0 and DWC1 are inserted.
PRW2
PRW1
PRW0
Number of inserted wait cycles
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
Mask Address
Each respective address (A6 to A3) corresponding to MA6 to MA3 is masked (by 1). The
masked address is not subject to comparison during on/off-page judgment, and is set
according to the number of continuously readable bits.
MA6
MA5
MA4
MA3
0
0
0
0
4 words × 16 bits (8 words × 8 bits)
0
0
0
1
8 words × 16 bits (16 words × 8 bits)
0
0
1
1
16 words × 16 bits (32 words × 8 bits)
0
1
1
1
32 words × 16 bits (64 words × 8 bits)
1
1
1
1
64 words × 16 bits (128 words × 8 bits)
Other than above
Number of continuously readable bits
Setting prohibited
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5.2.5 Page ROM access
Figure 5-5. Page ROM Access Timing (1/4)
(a) When read (halfword/word access with 8-bit bus width or
word access with 16-bit bus width)
T1
TW
T2
TO1
TO2
CLKOUT (output)
A0 to A25 (output)
Off-page address
On-page address
BCYST (output)
CSn/RASm (output)
Note
RD (output)
OE (output)
WE (output)
UWR/UCAS (output)
LWR/LCAS (output)
IORD (output)
IOWR (output)
D0 to D7 (I/O)
D0 to D15 (I/O)
Data
WAIT (input)
Note When accessing a word boundary with 8-bit bus width.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6
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Figure 5-5. Page ROM Access Timing (2/4)
(b) When read (byte access with 8-bit bus width or byte/halfword access with 16-bit bus width)
T1
TW
T2
TO1
TO2
CLKOUT (output)
A0 to A25 (output)
Off-page address
On-page address
BCYST (output)
CSn/RASm (output)
RD (output)
OE (output)
WE (output)
UWR/UCAS (output)
LWR/LCAS (output)
IORD (output)
IOWR (output)
D0 to D7 (I/O)
D0 to D15 (I/O)
Data
Data
WAIT (input)
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6
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Figure 5-5. Page ROM Access Timing (3/4)
(c) When read (address setup wait, idle state insertion)
(halfword/word access with 8-bit bus width or word
access with 16-bit bus width)
TASW
T1
T2
TASW
TO1
TO2
CLKOUT (output)
A0 to A25 (output)
Off-page address
On-page address
BCYST (output)
CSn/RASm (output)
RD (output)
OE (output)
WE (output)
UWR/UCAS (output)
LWR/LCAS (output)
IORD (output)
IOWR (output)
D0 to D7 (I/O)
D0 to D15 (I/O)
Data
WAIT (input)
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6
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Figure 5-5. Page ROM Access Timing (4/4)
(d) When read (address setup wait, idle state insertion)
(byte access with 8-bit bus width or byte/halfword
access with 16-bit bus width)
TASW
T1
T2
TASW
TO1
TO2
TI
CLKOUT (output)
A0 to A25 (output)
Off-page address
On-page address
BCYST (output)
CSn/RASm (output)
RD (output)
OE (output)
WE (output)
UWR/UCAS (output)
LWR/LCAS (output)
IORD (output)
IOWR (output)
D0 to D7 (I/O)
D0 to D15 (I/O)
Data
Data
WAIT (input)
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6
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5.3
MEMORY ACCESS CONTROL FUNCTION
DRAM Controller (EDO DRAM)
5.3.1 Features
• Generates the RAS, LCAS, and UCAS signals
• Can be connected directly to EDO DRAM.
• Supports the RAS hold mode.
• 4 types of DRAM can be assigned to 4 memory block spaces.
• Supports 2CAS type DRAM.
• Row and column address multiplex widths can be changed.
• Waits (0 to 3 waits) can be inserted at the following timings:
• Row address precharge wait
• Row address hold wait
• Data access wait
• Column address precharge wait
• Supports CBR refresh and CBR self-refresh.
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5.3.2 DRAM connection
Examples of connection to DRAM are shown below.
Figure 5-6. Examples of Connection to DRAM
(a) When DRAM is 64 Mb (4 M × 16 bits)
A1 to A12
A0 to A11
D0 to D15
I/O1 to I/O16
RASn
RAS
LCAS
LCAS
UCAS
UCAS
WE
WE
OE
OE
V850E/MA1
64 Mb DRAM
(4 Mwords × 16 bits)
(b) When DRAM is 16 Mb (2 M × 8 bits)
A1 to A12
A0 to A11
D0 to D7
I/O1 to I/O8
RASn
RAS
LCAS
LCAS
WE
WE
OE
OE
16 Mb DRAM
(2 Mwords × 8 bits)
A0 to A11
D8 to D15
I/O1 to I/O8
RAS
UCAS
UCAS
WE
OE
16 Mb DRAM
(2 Mwords × 8 bits)
V850E/MA1
Remark
n = 1, 3, 4, 6
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5.3.3 Address multiplex function
Depending on the value of the DAW0n and DAW1n bits in DRAM configuration register n (SCRn), the row address
and column address outputs in the DRAM cycle are multiplexed as shown in Figure 5-7 (n = 1, 3, 4, 6). In Figure 5-7,
a0 to a25 show the addresses output from the CPU and A0 to A25 show the address pins of the V850E/MA1.
For example, when DAW1n and DAW0n = 11, it indicates that a12 to a22 are output as row addresses and a1 to
a11 are output as column addresses from the address pins (A1 to A11).
Figure 5-7. Row Address/Column Address Output
Address pin A25 to A18 A17 A16 A15 A14 A13 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Row address
(DAW1n, DAW0n = 11) a25 to a18 a17 a16 a15 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11
Row address
(DAW1n, DAW0n = 10) a25 to a18 a17 a16 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10
Row address
(DAW1n, DAW0n = 01) a25 to a18 a17 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9
Row address
(DAW1n, DAW0n = 00) a25 to a18 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9
Column address a25 to a18 a17 a16 a15 a14 a13 a12 a11 a10 a9
Remark
a8
a7
a6
a5
a4
a3
a2
a1
a8
a0
n = 1, 3, 4, 6
Table 5-1 shows the relationship between the DRAM that can be connected and the address multiplex width. The
DRAM space differs according to the DRAM that is connected, as shown in Table 5-1.
Table 5-1. Example of DRAM and Address Multiplex Width
Address Multiplex Width
Note
DRAM Space
DRAM Capacity (Bits) and Configuration
(Bytes)
256 K
1M
4M
16 M
64 M
8 bits (DAW1n, DAW0n = 00)
64 K × 4
−
−
−
−
128 K
9 bits (DAW1n, DAW0n = 01)
−
256 K × 4
256 K × 16
−
−
512 K
−
−
512 K × 8
−
−
1M
−
−
−
−
4 M × 16
8M
−
−
1M×4
1 M × 16
−
2M
−
−
−
2M×8
−
4M
−
−
−
−
4 M × 16
8M
−
−
−
4M×4
−
8M
10 bits (DAW1n, DAW0n = 10)
11 bits (DAW1n, DAW0n = 11)
Note When the data bus width is 16 bits
Remark
160
n = 1, 3, 4, 6
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5.3.4 DRAM configuration registers 1, 3, 4, 6 (SCR1, SCR3, SCR4, SCR6)
These registers are used to set the type of DRAM to be connected. SCRn corresponds to CSn (n = 1, 3, 4, 6). For
example, to connect DRAM to CS1, set SCR1. These registers can be read/written in 16-bit units.
Cautions 1. If the object of access is a DRAM area, the wait set by registers DWC0 and DWC1 becomes
invalid. In this case, waits are controlled by registers SCR1, SCR3, SCR4, and SCR6.
2. If bit 14 is set to 1, the operation is not guaranteed.
3. Write to the SCR1, SCR3, SCR4, and SCR6 registers after reset, and then do not change the
set values.
Also, do not access an external memory area other than the one for this
initialization routine until the initial settings of the SCR1, SCR3, SCR4, and SCR6 registers
are complete. However, it is possible to access external memory areas whose initialization
settings are complete.
(1/3)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SCR1
PAE11
0 RPC11 RPC01 RHC11 RHC01 DAC11 DAC01 CPC11 CPC01 0
RHD1 ASO11 ASO01 DAW11 DAW01
Address
FFFFF4A4H
After reset
3FC1H
SCR3
PAE13
0 RPC13 RPC03 RHC13 RHC03 DAC13 DAC03 CPC13 CPC03 0
RHD3 ASO13 ASO03 DAW13DAW03
FFFFF4ACH
3FC1H
SCR4
PAE14
0 RPC14 RPC04 RHC14 RHC04 DAC14 DAC04 CPC14 CPC04 0
RHD4 ASO14 ASO04 DAW14DAW04
FFFFF4B0H
3FC1H
SCR6
PAE16
0 RPC16 RPC06 RHC16 RHC06 DAC16 DAC06 CPC16 CPC06 0
RHD6 ASO16 ASO06 DAW16DAW06
FFFFF4B8H
3FC1H
Bit position
15
Bit name
PAE1n
(n = 1, 3,
4, 6)
Function
DRAM On-page Access Mode Control
Sets the on-page access cycle.
PAE1n
13, 12
RPC1n,
RPC0n
(n = 1, 3,
4, 6)
Access mode
0
On-page access disabled
1
On-page access enabled
Row Address Pre-charge Control
Specifies the number of wait states inserted as row address precharge time.
RPC1n
RPC0n
Number of wait states inserted
0
0
1 (at least 1 wait is always inserted.)
0
1
1
1
0
2
1
1
3
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(2/3)
Bit position
11, 10
9, 8
7, 6
4
162
Bit name
RHC1n,
RHC0n
(n = 1, 3,
4, 6)
DAC1n,
DAC0n
(n = 1, 3,
4, 6)
CPC1n,
CPC0n
(n = 1, 3,
4, 6)
RHDn
(n = 1, 3,
4, 6)
Function
Row Address Hold Wait Control
Specifies the number of wait states inserted as row address hold time.
RHC1n
RHC0n
Number of wait states inserted
0
0
0
0
1
1
1
0
2
1
1
3
Data Access Programmable Wait Control
Specifies the number of wait states inserted as data access time during DRAM access.
DAC1n
DAC0n
Number of wait states inserted
0
0
0
0
1
1
1
0
2
1
1
3
Column Address Pre-charge Control
Specifies the number of wait states inserted as column address precharge time.
CPC1n
CPC0n
Number of wait states inserted
0
0
0 (at least 1 wait is always inserted during on-page write access)
0
1
1
1
0
2
1
1
3
RAS Hold Disable
Sets the RAS hold mode.
If access to DRAM during on-page operation is not continuous and another space is
accessed midway, the RASn signal is maintained in the active state (low level) during the
time the other space is being accessed in the RAS hold mode. In this way, if access
continues in the same DRAM row address following access of the other space, on-page
operation can be continued.
0: RAS hold mode enabled
1: RAS hold mode disabled
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(3/3)
Bit position
3, 2
1, 0
Bit name
ASO1n,
ASO0n
(n = 1, 3,
4, 6
DAW1n,
DAW0n
(n = 1, 3,
4, 6)
Function
Address Shift Width On-page Control
This sets the address shift width during on-page judgment.
When the external data bus width is 8 bits: Set ASO1n, ASO0n = 00B
When the external data bus width is 16 bits: Set ASO1n, ASO0n = 01B
ASO1n
ASO0n
Address shift width
0
0
0 (data bus width: 8 bits)
0
1
1 (data bus width: 16 bits)
1
0
Setting prohibited
1
1
Setting prohibited
DRAM Address Multiplex Width Control
This sets the address multiplex width (refer to 5.3.3 Address multiplex function).
DAW1n
DAW0n
Address multiplex width
0
0
8 bits
0
1
9 bits
1
0
10 bits
1
1
11 bits
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5.3.5 DRAM access
Figure 5-8. EDO DRAM Access Timing (1/5)
(a) Read timing (when no waits are inserted)
TRPWNote 1
T1
T2
TB
TE
TB
CLKOUT (output)
A0 to A25 (output)
Row address Column address Column address Column address
BCYST (output)
Note 2
CSn/RASm (output)
RD (output)
OE (output)
WE (output)
UWR/UCAS (output)
LWR/LCAS (output)
IORD (output)
IOWR (output)
Data
D0 to D15 (I/O)
Data
Data
WAIT (input)
Notes 1.
2.
TRPW is always inserted for 1 or more cycles.
When a bus cycle accessing another CS space or a write cycle accessing the same CS space
follows this read cycle.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6
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Figure 5-8. EDO DRAM Access Timing (2/5)
(b) Read timing (when TRHW and TW are inserted)
TRPWNote 1
T1
TRHW
T2
TW
TB
TW
TE
CLKOUT (output)
A0 to A25 (output)
Row address
Column address
Column address
BCYST (output)
Note 2
CSn/RASm (output)
RD (output)
OE (output)
WE (output)
UWR/UCAS (output)
LWR/LCAS (output)
IORD (output)
IOWR (output)
Data
D0 to D15 (I/O)
Data
WAIT (input)
Notes 1.
2.
TRPW is always inserted for 1 or more cycles.
When a bus cycle accessing another CS space or a write cycle accessing the same CS space
follows this read cycle.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6
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Figure 5-8. EDO DRAM Access Timing (3/5)
(c) Read timing (when two idle states are inserted)
TRPWNote
T1
TRHW
T2
TCPWNote
TW
TB
TW
CLKOUT (output)
A0 to A25 (output)
Row address
Column address
Column address
BCYST (output)
CSn/RASm (output)
RD (output)
OE (output)
WE (output)
UWR/UCAS (output)
LWR/LCAS (output)
IORD (output)
IOWR (output)
D0 to D15 (I/O)
Data
WAIT (input)
Note TRPW and TCPW are always inserted for 1 or more cycles.
Remarks 1. The broken lines indicate the high-impedance state.
2. n = 0 to 7, m = 1, 3, 4, 6
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Data
TE
TI
TI
T1
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MEMORY ACCESS CONTROL FUNCTION
Figure 5-8. EDO DRAM Access Timing (4/5)
(d) Write timing (when no waits are inserted)
TRPWNote 1
T1
T2
TCPWNote 1
TB
TCPWNote 1
TB
TE
CLKOUT (output)
Row address Column address
A0 to A25 (output)
Column address
Column address
BCYST (output)
Note 2
CSn/RASm (output)
RD (output)
OE (output)
WE (output)
UWR/UCAS (output)
LWR/LCAS (output)
IORD (output)
IOWR (output)
D0 to D15 (I/O)
(During Read to Write)
D0 to D15 (I/O)
(During Read to Write)
Data
Data
Data
Data
Data
Data
Data
Data
WAIT (input)
Notes 1.
2.
TRPW and TCPW are always inserted for 1 or more cycles.
When a bus cycle accessing another CS space or a read cycle accessing the same CS space
follows this write cycle.
Remarks 1. The broken lines indicate the high-impedance state.
2. n = 0 to 7, m = 1, 3, 4, 6
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Figure 5-8. EDO DRAM Access Timing (5/5)
(e) Write timing (when TRHW and TW are inserted)
TRPWNote 1
T1
TRHW
T2
TW
TCPWNote 1
TB
TW
TE
CLKOUT (output)
A0 to A25 (output)
Column address
Row address
Column address
BCYST (output)
Note 2
CSn/RASm (output)
RD (output)
OE (output)
WE (output)
UWR/UCAS (output)
LWR/LCAS (output)
IORD (output)
IOWR (output)
D0 to D15 (I/O)
Data
Data
WAIT (input)
Notes 1.
2.
TRPW and TCPW are always inserted for 1 or more cycles.
When a bus cycle accessing another CS space or a read cycle accessing the same CS space
follows this write cycle.
Remarks 1. The broken lines indicate the high-impedance state.
2. n = 0 to 7, m = 1, 3, 4, 6
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5.3.6 Refresh control function
The V850E/MA1 can generate the CBR (CAS-before-RAS) refresh cycle. The refresh cycle is set with refresh
control registers 1, 3, 4, and 6 (RFS1, RFS3, RFS4, RFS6). RFSn corresponds to CSn (n = 1, 3, 4, 6). For example,
to connect DRAM to CS1, set RFS1.
When another bus master occupies the external bus, the DRAM controller cannot occupy the external bus. In this
case, the DRAM controller issues a refresh request to the bus master by changing the REFRQ signal to active (low
level).
During a refresh operation, the address bus retains the state it was in just before the refresh cycle.
(1) Refresh control registers 1, 3, 4, 6 (RFS1, RFS3, RFS4, RFS6)
These registers are used to enable or disable a refresh and set the refresh interval. The refresh interval is
determined by the following calculation formula.
Refresh interval (µs) = Refresh count clock (TRCY) × Interval factor
The refresh count clock and interval factor are determined by the RENn bit and RIN5n to RIN0n bits,
respectively, of the RFSn register.
Note that n corresponds to the register number (1, 3, 4, 6) of DRAM configuration registers 1, 3, 4, 6 (SCR1,
SCR3, SCR4, SCR6).
These registers can be read/written in 16-bit units.
Caution
Write to the RFS1, RFS3, RFS4, and RFS6 registers after reset, and then do not change the
set values.
Also, do not access an external memory area other than the one for this
initialization routine until the initial settings of the RFS1, RFS3, RFS4, and RFS6 registers
are complete. However, it is possible to access external memory areas whose initialization
settings are complete.
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15
14
13
12
11
10
RFS1
REN1
0
0
0
0
0 RCC11 RCC01 0
0 RIN51 RIN41 RIN31 RIN21 RIN11 RIN01
Address
FFFFF4A6H
After reset
0000H
RFS3
REN3
0
0
0
0
0 RCC13 RCC03 0
0 RIN53 RIN43 RIN33 RIN23 RIN13 RIN03
FFFFF4AEH
0000H
RFS4
REN4
0
0
0
0
0 RCC14 RCC04 0
0 RIN54 RIN44 RIN34 RIN24 RIN14 RIN04
FFFFF4B2H
0000H
RFS6
REN6
0
0
0
0
0 RCC16 RCC06 0
0 RIN56 RIN46 RIN36 RIN26 RIN16 RIN06
FFFFF4BAH
0000H
Bit position
8
7
6
5
4
3
Bit name
2
1
RENn
(n = 1, 3,
4, 6)
Refresh Enable
Specifies whether CBR refresh is enabled or disabled.
0: Refresh disabled
1: Refresh enabled
9, 8
RCC1n,
RCC0n
(n = 1, 3,
4, 6)
Refresh Count Clock
Specifies the refresh count clock (TRCY)
Remark
RIN5n to
RIN0n
(n = 1, 3,
4, 6)
0
Function
15
5 to 0
170
9
RCC1n RCC0n
Refresh count clock (TRCY)
0
0
32/φ
0
1
128/φ
1
0
256/φ
1
1
Setting prohibited
Refresh Interval
Sets the interval factor of the interval timer for the generation of the refresh timing.
RIN5n
RIN4n
RIN3n
RIN2n
RIN1n
RIN0n
0
0
0
0
0
0
1
0
0
0
0
0
1
2
0
0
0
0
1
0
3
0
0
0
0
1
1
4
:
:
:
:
:
:
:
1
1
1
1
1
1
64
φ: Internal system clock frequency
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CHAPTER 5
MEMORY ACCESS CONTROL FUNCTION
Table 5-2. Interval Factor Setting Examples
Specified Refresh Interval
Value (µs)
7.8
Notes 1, 2
Interval Factor Value
Refresh Count Clock (TRCY)
φ = 20 MHz
31.2
62.5
125
250
Notes 1.
2.
φ = 50 MHz
32/φ
4 (6.4)
8 (7.8)
12 (7.7)
128/φ
1 (6.4)
2 (7.8)
5 (7.7)
1 (7.8)
1 (5.1)
256/φ
15.6
φ = 33 MHz
−
32/φ
9 (14.4)
16 (15.5)
24 (15.4)
128/φ
2 (12.8)
4 (15.5)
6 (15.4)
256/φ
1 (12.8)
2 (15.5)
3 (15.4)
32/φ
19 (30.4)
32 (31.0)
48 (30.7)
128/φ
4 (25.6)
8 (31.0)
12 (30.7)
256/φ
2 (25.6)
4 (31.0)
6 (30.7)
32/φ
39 (62.4)
64 (62.1)
128/φ
9 (57.6)
16 (62.1)
24 (61.4)
256/φ
4 (51.2)
8 (62.1)
12 (61.4)
128/φ
19 (121.6)
32 (124.1)
48 (122.9)
256/φ
9 (115.2)
16 (124.1)
24 (122.9)
128/φ
39 (249.6)
64 (248.2)
−
256/φ
19 (243.2)
32 (248.2)
48 (245.8)
−
The interval factor is set by bits RIN0n to RIN5n of the RFSn register (n = 1, 3, 4, 6).
The values in parentheses are the calculated values for the refresh interval (µs).
Refresh interval (µs) = Refresh count clock (TRCY) × Interval factor
Remark
φ: Internal system clock frequency
(2) Refresh wait control register (RWC)
This register specifies the number of wait states inserted during the refresh cycle.
This register can be read/written in 8-bit units.
Caution
Write to the RWC register after reset, and then do not change the set value. Also, do not
access an external memory area other than the one for this initialization routine until the
initial setting of the RWC register is complete. However, it is possible to access external
memory areas whose initialization settings are complete.
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RWC
7
6
5
4
3
2
1
0
RRW1
RRW0
RCW2
RCW1
RCW0
SRW2
SRW1
SRW0
Bit position
7, 6
5 to 3
2 to 0
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MEMORY ACCESS CONTROL FUNCTION
Bit name
RRW1,
RRW0
RCW2 to
RCW0
SRW2 to
SRW0
Address
FFFFF49EH
After reset
00H
Function
Refresh RAS Wait Control
Specifies the number of wait states inserted as hold time for the RASm signal's high level
width during CBR refresh (m = 1, 3, 4, 6).
RRW1
RRW0
Number of inserted wait states
0
0
0
0
1
1
1
0
2
1
1
3
Refresh Cycle Wait Control
Specifies the number of wait states inserted as hold time for the RASm signal's low level
width during CBR refresh (m = 1, 3, 4, 6).
RCW2
RCW1
RCW0
0
0
0
1 (at least 1 wait is always inserted)
Number of inserted wait states
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
Self-refresh Release Wait Control
Specifies the number of wait states inserted as CBR self-refresh release time.
SRW2
SRW1
SRW0
Number of inserted wait states
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
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MEMORY ACCESS CONTROL FUNCTION
(3) Refresh timing
Figure 5-9. CBR Refresh Timing
TRRW
T1
T2
TRCWNote 1
TRCW
T3
T4
TINote 2
TINote 2
CLKOUT (output)
REFRQ (output)
A0 to A25 (output)
BCYST (output)
CSn/RASm (output)
RD (output)
OE (output)
WE (output)
UWR/UCAS (output)
LWR/LCAS (output)
IORD (output)
IOWR (output)
D0 to D15 (I/O)
WAIT (input)
Notes 1.
The TRCW cycle is always inserted for one or more clocks, irrespective of the setting of bits RCW2 to
RCW0 of the RWC register.
2.
Remark
This idle state (TI) is independent of the BCC register setting.
n = 0 to 7, m = 1, 3, 4, 6
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5.3.7 Self-refresh control function
When transferring to the IDLE or software STOP mode, or if the SELFREF signal becomes active, the DRAM
controller generates the CBR self-refresh cycle.
Note that the RASn pulse width of DRAM must meet the specifications for DRAM to enable the self-refresh
operation (n = 1, 3, 4, 6).
Cautions 1. When the transition to the self-refresh cycle is caused by SELFREF signal input, releasing
the self-refresh cycle is only possible by inputting an inactive level to the SELFREF pin.
2. The internal ROM and internal RAM can be accessed even in the self-refresh cycle.
However, access to a peripheral I/O register or external device is held pending until the selfrefresh cycle is cleared.
To release the self-refresh cycle, use one of the three methods below.
(1) Release by NMI input
(a) In the case of self-refresh cycle in IDLE mode
To release the self-refresh cycle, make the RASn, LCAS, and UCAS signals inactive (high level)
immediately.
(b) In the case of self-refresh cycle in software STOP mode
To release the self-refresh cycle, make the RASn, LCAS, and UCAS signals inactive (high level) after
stabilizing oscillation.
(2) Release by INTP0n0 and INTP0n1 inputs (n = 0 to 3)
(a) In the case of self-refresh cycle in IDLE mode
To release the self-refresh cycle, make the RASn, LCAS, and UCAS signals inactive (high level)
immediately.
(b) In the case of self-refresh cycle in software STOP mode
To release the self-refresh cycle, make the RASn, LCAS, and UCAS signals inactive (high level) after
stabilizing oscillation.
(3) Release by RESET input
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Figure 5-10. Self-Refresh Timing (DRAM)
TRCW
Note 2
TRRW
TSRW
TSRW
Note 1
CLKOUT (output)
REFRQ (output)
A0 to A25 (output)
BCYST (output)
CSn/RASm (output)
RD (output)
OE (output)
WE (output)
UWR/UCAS (output)
LWR/LCAS (output)
IORD (output)
IOWR (output)
D0 to D15 (I/O)
WAIT (input)
Notes 1.
Shown above is the case when the self-refresh cycle is started in the IDLE or software STOP mode.
If the self-refresh cycle is started by inputting the active level of the SELFREF signal, CLKOUT is
output without going low.
2.
The TRCW cycle is always inserted for one or more clocks, irrespective of the setting of bits RCW2
to RCW0 of the RWC register.
Remarks 1. This timing is obtained when the bits of the RWC register have the following settings.
RRW1, RRW0 = 01B:
1 wait (TRRW)
RCW2 to RCW0 = 001B: 1 wait (TRCW)
SRW2 to SRW0 = 001B: 1 wait (TSRW) (double the number of wait states than the set value will be
inserted)
2. n = 0 to 7, m = 1, 3, 4, 6
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5.4
MEMORY ACCESS CONTROL FUNCTION
DRAM Controller (SDRAM)
5.4.1 Features
• Burst length: 1
• Wrap type: Sequential
• CAS latency: 2 and 3 supported
• 4 types of SDRAM can be assigned to 4 memory blocks.
• Row and column address multiplex widths can be changed.
• Waits (0 to 3 waits) can be inserted between the bank active command and the read/write command.
• Supports CBR refresh and CBR self-refresh.
5.4.2 SDRAM connection
An example of connection to SDRAM is shown below.
Figure 5-11. Example of Connection to SDRAM
A1 to A12
A0 to A11
A21, A22Note
A12, A13
DQ0 to DQ15
D0 to D15
SDCLK
CLK
SDCKE
CKE
CS
CSn
SDRAS
RAS
SDCAS
CAS
LDQM
LDQM
UDQM
UDQM
WE
WE
V850E/MA1
64 Mb SDRAM
(1 Mword × 16 bits × 4 banks)
Note The address signals to be used differ depending on the SDRAM product.
Remark
176
n = 1, 3, 4, 6
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5.4.3 Address multiplex function
Depending on the value of the SAW0n and SAW1n bits in SDRAM configuration register n (SCRn), the row
address output in the SDRAM cycle is multiplexed as shown in Figure 5-12 (a) (n = 1, 3, 4, 6). Depending on the
value of the SSO0n and SSO1n bits, the column address output in the SDRAM cycle is multiplexed as shown in
Figure 5-12 (b) (n = 1, 3, 4, 6). In Figures 5-12 (a) and (b), a0 to a25 indicate the addresses output from the CPU,
and A0 to A25 indicate the address pins of the V850E/MA1.
Figure 5-12. Row Address/Column Address Output (1/2)
(a) Row address output
Address pin A25 to A18 A17 A16 A15 A14 A13 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Row address
(SAW1n, SAW0n = 10) a25 to a18 a17 a16 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10
Row address
(SAW1n, SAW0n = 01) a25 to a18 a17 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9
Row address
(SAW1n, SAW0n = 00) a25 to a18 a25 a24 a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9
Remark
a8
n = 1, 3, 4, 6
(b) Column address output (using all bank precharge command)
Address pin A25 to A18 A17 A16 A15 A14 A13 A12 A11 A10 A9
Column address
(SSO1n, SSO0n = 00) a25 to a18 a17 a16 a15 a14 a13 a12 a11
Column address
(SSO1n, SSO0n = 01) a25 to a18 a17 a16 a15 a14 a13 a12
Remark
1
A8
A7
A6
A5
A4
A3
A2
A1
A0
a9
a8
a7
a6
a5
a4
a3
a2
a1
a0
a10 a9
a8
a7
a6
a5
a4
a3
a2
a1
a0
A4
A3
A2
A1
A0
0
0
0
0
0
0
0
0
1
n = 1, 3, 4, 6
(c) Column address output (using register write command)
Address pin A25 to A18 A17 A16 A15 A14 A13 A12 A11 A10 A9
A8
A7
0
Column address
(SSO1n, SSO0n = 00)
0
0
0
0
0
0
0
0
0
0
0
Column address
(SSO1n, SSO0n = 01)
0
0
0
0
0
0
0
0
0
0
0
Remark
A6
A5
LTM2 LTM1 LTM0
LTM2 LTM1 LTM0
0
n = 1, 3, 4, 6
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Figure 5-12. Row Address/Column Address Output (2/2)
(d) Column address output (using read/write command)
Address pin A25 to A18 A17 A16 A15 A14 A13 A12 A11 A10 A9
Column address
(SSO1n, SSO0n = 00) a25 to a18 a17 a16 a15 a14 a13 a12 a11
Column address
(SSO1n, SSO0n = 01) a25 to a18 a17 a16 a15 a14 a13 a12
Remark
178
0
A8
A7
A6
A5
A4
A3
A2
A1
A0
a9
a8
a7
a6
a5
a4
a3
a2
a1
a0
a10 a9
a8
a7
a6
a5
a4
a3
a2
a1
a0
0
n = 1, 3, 4, 6
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5.4.4 SDRAM configuration registers 1, 3, 4, 6 (SCR1, SCR3, SCR4, SCR6)
These registers specify the number of waits and the address multiplex width. SCRn corresponds to CSn (n = 1, 3,
4, 6). For example, to connect SDRAM to CS1, set SCR1.
These registers can be read/written in 16-bit units.
Cautions 1. The SDRAM read/write cycle is not generated prior to executing the power-on cycle. Access
SDRAM after waiting 20 clocks following a program write to the SCR register. To write to
the SCR register again following access to SDRAM, clear the MEn bit of the BCT0 and BCT1
registers to 0, and then set it to 1 again before performing access (n = 0 to 7).
2. Do not execute continuous instructions to write to the SCR register. Be sure to insert
another instruction between commands to write to the SCR register.
(1/2)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SCR1
0
LTM21 LTM11 LTM01
0
0
0
0
BCW11 BCW01 SSO11 SSO01 RAW11 RAW01 SAW11 SAW01
Address
FFFFF4A4H
After reset
0000H
SCR3
0
LTM23 LTM13 LTM03
0
0
0
0
BCW13 BCW03 SSO13 SSO03 RAW13 RAW03 SAW13 SAW03
FFFFF4ACH
0000H
SCR4
0
LTM24 LTM14 LTM04
0
0
0
0
BCW14 BCW04 SSO14 SSO04 RAW14 RAW04 SAW14 SAW04
FFFFF4B0H
0000H
SCR6
0
LTM26 LTM16 LTM06
0
0
0
0
BCW16 BCW06 SSO16 SSO06 RAW16 RAW06 SAW16 SAW06
FFFFF4B8H
0000H
Bit position
Bit name
14 to 12
LTM2n to
LTM0n
(n = 1, 3,
4, 6)
7, 6
BCW1n,
BCW0n
(n = 1, 3,
4, 6)
Function
Latency
Sets the CAS latency value for reading.
LTM2n LTM1n LTM0n
0
×
2
0
1
0
2
0
1
1
3
1
×
×
Setting prohibited
Bank Active Command Wait Control
Specifies the number of wait states inserted from the bank active command to a read/write
command, or from the precharge command to the bank active command.
BCW1n BCW0n
Remark
Latency
0
Number of wait states inserted
0
0
1 (at least 1 wait is always inserted)
0
1
1
1
0
2
1
1
3
×: don't care
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(2/2)
Bit position
5, 4
Bit name
SSO1n,
SSO0n
(n = 1 3,
4, 6)
Function
SDRAM Shift Width On-Page Control
Specifies the address shift width during on-page judgment.
When the external data bus width is 8 bits: Set SSO1n, SSO0n = 00B
When the external data bus width is 16 bits: Set SSO1n, SSO0n = 01B
SSO1n SSO0n
3, 2
1, 0
180
RAW1n,
RAW0n
(n = 1, 3,
4, 6)
SAW1n,
SAW0n
(n = 1, 3,
4, 6)
Address shift width
0
0
8 bits
0
1
16 bits
1
0
Setting prohibited
1
1
Setting prohibited
Row Address Width Control
Specifies the row address width.
RAW1n RAW0n
Row address width
0
0
11
0
1
12
1
0
Setting prohibited
1
1
Setting prohibited
Row Address Multiplex Width Control
Specifies the address multiplex width during SDRAM access.
SAW1n SAW0n
Address multiplex width
0
0
8
0
1
9
1
0
10
1
1
Setting prohibited
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MEMORY ACCESS CONTROL FUNCTION
5.4.5 SDRAM access
During power-on or a refresh operation, the all bank precharge command is always issued for SDRAM. When
accessing SDRAM after that, therefore, the active command and read/write command are issued in that order (see
<1> in Figure 5-13).
If a page change occurs following this, the precharge command, active command, and read/write command are
issued in that order (see <2> in Figure 5-13).
If a bank change occurs, the active command and read/write command for the bank to be accessed next are
issued in that order. Following this read/write command, the precharge command for the bank that was accessed
before the bank currently being accessed will be issued (see <3> in Figure 5-13).
Figure 5-13. State Transition of SDRAM Access
All bank
pre-charge command
(Power on/refresh)
Bank A
active
command
<1>
Read/Write
command
(On-page access)
(Page change)
Read/Write
command
(Bank change)
Bank A
precharge
command
Bank B
active
command
Bank A
active
command
Bank B
Read/Write
command
<2>
<3>
Bank A precharge
command
Bank A
Read/Write
command
(Bank change)
Bank A
active
command
Bank A
Read/Write
command
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(1) SDRAM single read cycle
The SDRAM single read cycle is a cycle for reading from SDRAM by executing a load instruction (LD) for the
SDRAM area, by fetching an instruction, or by 2-cycle DMA transfer.
In the SDRAM single read cycle, the active command (ACT) and read command (RD) are issued for SDRAM
in that order.
During on-page access, however, only the read command is issued and the precharge
command and active command are not issued.
When a page change occurs in the same bank, the
precharge command (PR) is issued before the active command.
The timing to sample data is synchronized with rising of the UDQM and LDQM signals.
A one-state TW cycle is always inserted immediately before every read command, which is activated by the
CPU.
The number of idle states set by the bus cycle control register (BCC) are inserted before the read cycle (no
idle states are inserted, however, if BCn1 and BCn0 are 00) (n = 1, 3, 4, 6). The timing charts of the SDRAM
single read cycle are shown below.
Caution
When executing a write access to SRAM or external I/O after read accessing SDRAM, data
conflict may occur depending on the SDRAM data output float delay time. In such a case,
avoid data conflict by inserting an idle state in the SDRAM space via a setting in the BCC
register.
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Figure 5-14. SDRAM Single Read Cycle (1/3)
(a) During off-page access (when latency = 2)
Off-page
TW
TACT
TREAD
TLATE
TLATE
SDCLK (output)
ACT
Command
RD
BCYST (output)
SDCKE (output)
H
CSn (output)
SDRAS (output)
SDCAS (output)
WE (output)
LDQM (output)
UDQM (output)
Note (output)
Address
Address
Bank address (output)
Address
Bank
address
Address
A10 (output)
Address
Row
address
Address
A0 to A9 (output)
Address
Row
address
Column address
D0 to D15 (I/O)
Data
Note Addresses other than the bank address, A10, and A0 to A9.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 1, 3, 4, 6
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Figure 5-14. SDRAM Single Read Cycle (2/3)
(b) During off-page access (when latency = 2, page change)
Off-page
TW
TPREC
TACT
TREAD TLATE
TLATE
SDCLK (output)
PRE
Command
ACT
RD
BCYST (output)
SDCKE (output)
H
CSn (output)
SDRAS (output)
SDCAS (output)
WE (output)
LDQM (output)
UDQM (output)
Note (output)
Address
Bank address (output)
Address
A10 (output)
Address
A0 to A9 (output)
Address
Bank
address
Row
address
Address
Bank
address
Address
Row
address
Address
Row
address
Column address
D0 to D15 (I/O)
Data
Note Addresses other than the bank address, A10, and A0 to A9.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 1, 3, 4, 6
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Figure 5-14. SDRAM Single Read Cycle (3/3)
(c) During on-page access (when latency = 2)
On-page
TW
TREAD
TLATE
TLATE
SDCLK (output)
RD
Command
BCYST (output)
SDCKE (output)
H
CSn (output)
SDRAS (output)
H
SDCAS (output)
WE (output)
LDQM (output)
UDQM (output)
Note (output)
Address
Address
Bank address (output)
Address
A10 (output)
Address
A0 to A9 (output)
Column address
D0 to D15 (I/O)
Data
Note Addresses other than the bank address, A10, and A0 to A9.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 1, 3, 4, 6
4. The timing chart shown here is the timing when the previous cycle accessed another CS space
or when the bus was in an idle state. If access to the same CS space continues, a TW state is
not inserted (the BCYST signal becomes active in the TREAD state).
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(2) SDRAM single write cycle
The SDRAM single write cycle is a cycle for writing to SDRAM by executing a write instruction (ST) for the
SDRAM area or by 2-cycle DMA transfer.
In the SDRAM single write cycle, the active command (ACT) and write command (WR) are issued for
SDRAM in that order. During on-page access, however, only the write command is issued and the precharge
command and active command are not issued.
When a page change occurs in the same bank, the
precharge command (PR) is issued before the active command.
A one-state TW cycle is always inserted immediately before every write command, which is activated by the
CPU.
The timing charts of the SDRAM single write cycle are shown below.
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Figure 5-15. SDRAM Single Write Cycle (1/3)
(a) During off-page access
Off-page
TW
TACT
TWR
TWPRE
TWE
SDCLK (output)
Command
ACT
WR
BCYST (output)
SDCKE (output)
H
CSn (output)
SDRAS (output)
SDCAS (output)
WE (output)
LDQM (output)
UDQM (output)
Note (output)
Address
Address
Bank address (output)
Address
Bank
address
Address
A10 (output)
Address
Row
address
Address
A0 to A9 (output)
Address
Row
address
Column address
D0 to D15 (I/O)
Data
Note Addresses other than the bank address, A10, and A0 to A9.
Remarks 1. The broken lines indicate the high-impedance state.
2. n = 1, 3, 4, 6
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Figure 5-15. SDRAM Single Write Cycle (2/3)
(b) During off-page access (page change)
Off-page
TW
TPREC
TACT
TWR1
TWR2
TWR3
SDCLK (output)
PRE
Command
ACT
WR
BCYST (output)
SDCKE (output)
H
CSn (output)
SDRAS (output)
SDCAS (output)
WE (output)
LDQM (output)
UDQM (output)
Address
Note (output)
Bank address (output)
A10 (output)
A0 to A9 (output)
Address
Bank
address
Address
Address
Row
address
Address
Bank
address
Address
Row
address
Aaddress
Row
address
Column address
D0 to D15 (I/O)
Data
Note Addresses other than the bank address, A10, and A0 to A9.
Remarks 1. The broken lines indicate the high-impedance state.
2. n = 1, 3, 4, 6
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Figure 5-15. SDRAM Single Write Cycle (3/3)
(c) During on-page access
On-page
TW
TWR
TWPRE
TWE
SDCLK (output)
Command
WR
BCYST (output)
SDCKE (output)
H
CSn (output)
SDRAS (output)
H
SDCAS (output)
WE (output)
LDQM (output)
UDQM (output)
Note (output)
Address
Address
Bank address (output)
Address
A10 (output)
Address
A0 to A9 (output)
Column address
D0 to D15 (I/O)
Data
Note Addresses other than the bank address, A10, and A0 to A9.
Remarks 1. The broken lines indicate the high-impedance state.
2. n = 1, 3, 4, 6
3. The timing chart shown here is the timing when the previous cycle accessed another CS space
or when the bus is an idle state. If access to the same CS space continues, a TW state is not
inserted (the BCYST signal becomes active in the TWR1 state).
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(3) SDRAM access timing control
The SDRAM access timing can be controlled by SDRAM configuration register n (SCRn) (n = 1, 3, 4, 6). For
details, see 5.4.4 SDRAM configuration registers 1, 3, 4, 6 (SCR1, SCR3, SCR4, SCR6).
Caution
Wait control by the WAIT pin is not available during SDRAM access.
(a) Number of waits from bank active command to read/write command
The number of wait states from bank active command issue to read/write command issue can be set by
setting the BCW1n and BCW0n bits of the SCRn register.
BCW1n, BCW0n = 01B:
1 wait
BCW1n, BCW0n = 10B:
2 waits
BCW1n, BCW0n = 11B:
3 waits
(b) Number of waits from precharge command to bank active command
The number of wait states from precharge command issue to bank active command issue can be set by
setting the BCW1n and BCW0n bits of the SCRn register.
BCW1n, BCW0n = 01B:
1 wait
BCW1n, BCW0n = 10B:
2 waits
BCW1n, BCW0n = 11B:
3 waits
(c) CAS latency setting when read
The CAS latency during a read operation can be set by setting the LTM2n to LTM0n bits of the SCRn
register.
LTM2n to LTM0n = 010B:
Latency = 2
LTM2n to LTM0n = 011B:
Latency = 3
(d) Number of waits from refresh command to next command
The number of wait states from refresh command issue to next command issue can be set by setting the
BCW1n and BCW0n bits of the SCRn register. The number of wait states becomes four times the value
set by BCW1n and BCW0n.
190
BCW1n, BCW0n = 01B:
4 waits
BCW1n, BCW0n = 10B:
8 waits
BCW1n, BCW0n = 11B:
12 waits
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Figure 5-16. SDRAM Access Timing (1/4)
(a) Read timing (16-bit bus width word access, page change, BCW = 2, latency = 2)
TW
TACT TBCW TREAD TREAD TLATE TLATE
TW TPREC TBCW TACT TBCW TREAD TREAD TLATE TLATE
BCW
BCW
BCW
SDCLK (output)
Note (output)
Address
Address
Address
Bank address (output)
Bank
Address address
Address
Bank Address Bank
Address address
address
Address
A11 (output)
Row
Address address
Address
Address
Row
Address address
Address
Row Column address
Address address
A0 to A10 (output)
Column address
Address
Row
address Column address
Column address
BCYST (output)
CSn (output)
SDRAS (output)
SDCAS (output)
RD (output)
OE (output)
WE (output)
LDQM (output)
UDQM (output)
D0 to D15 (I/O)
Data
Data
Data
Bank A read
command
(On-page)
Bank A read
command
Bank A active
command
Bank A precharge
command
(Page change)
Bank A read
command
(On-page)
Bank A read
command
H
Bank A active
command
SDCKE (output)
Data
Note Addresses other than the bank address, A11, and A0 to A10.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 1, 3, 4, 6
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Figure 5-16. SDRAM Access Timing (2/4)
(b) Read timing (8-bit bus width word access, page change, BCW = 2, latency = 2)
TA TACT TBCW TREAD TREAD TREAD TREAD TLATE TLATE TW TPREC TBCW TACT TBCW TREAD TREAD TREAD TREAD TLATE TLATE
BCW
BCW
BCW
SDCLK (output)
Note (output)
Address
Address Address
Address
Address
Address
Address Address
Bank address (output)
Address
Bank
address
Address
Bank Address Bank
Address address
address
Address
A10 (output)
Address
Row
address
Address
Address
Row
Address address
Address
Row Column address Column Column
Address address
address address
A0 to A9 (output)
Column address
Address
Row
address Column address
Column Column
address address
Column address
BCYST (output)
CSn (output)
SDRAS (output)
SDCAS (output)
RD (output)
OE (output)
WE (output)
LDQM (output)
UDQM (output)
D0 to D7 (I/O)
Data Data Data Data
Note Addresses other than the bank address, A10, and A0 to A9.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 1, 3, 4, 6
User’s Manual U14359EJ3V0UM
Bank A read
command
Bank A read
command
Bank A read
command
Bank A read
command
(Page change)
(On-page)
192
Bank A
active
command
Bank A
precharge
command
Bank A read
command
Bank A read
command
Bank A read
command
Bank A read
command
H
Bank A active
command
SDCKE (output)
Data Data Data Data
(On-page)
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MEMORY ACCESS CONTROL FUNCTION
Figure 5-16. SDRAM Access Timing (3/4)
(c) Write timing (16-bit bus width word access, bank change, BCW = 1, latency = 2)
Bank A write
TW
Bank B write
TACT TWR TWR TWPRE TWE
BCW
TW
Bank B write
TACT TWR TWR TWPRE TWE
BCW
TW
TW TWR TWR TWPRE TWE
BCW
SDCLK (output)
Note (output)
Address
Address
Address
Bank address (output)
Bank
Address address
Address
Bank
Address address
Address
Bank
address Address
Address
A11 (output)
Row
Address address
Address
Row
Address address
Address
Address
Address
Row
Column
Address address
address
Column address
Row
Column
Address address
address
A0 to A10 (output)
Address
Address
Column address
Address
Column address
Column address
BCYST (output)
CSn (output)
SDRAS (output)
SDCAS (output)
RD (output)
OE (output)
WE (output)
LDQM (output)
UDQM (output)
Data
D0 to D15 (I/O)
Data
Data
Data
Data
Bank B write
command
Bank B write
command
Bank A precharge
command
Bank B write
command
Bank B write
command
Bank B active
command
Bank A write
command
Bank A write
command
H
Bank A active
command
SDCKE (Output)
Data
When write-accessing the page
that includes bank B, which was
accessed by the previous write
access.
Note Addresses other than the bank address, A11, and A0 to A10.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 1, 3, 4, 6
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Figure 5-16. SDRAM Access Timing (4/4)
(d) Write timing (8-bit bus width word access, bank change, BCW = 1, latency = 2)
Bank A write
TW
Bank B write
TACT TWR TWR TWR TWR TWPRE TWE
BCW
TW
Bank A read
TACT TWR TWR TWR TWR TWPRE TWE
BCW
TW
TACT TREAD TREAD TREAD TREAD TLATE TLATE
BCW
SDCLK (output)
Note (output)
Address
Address Address
Address
Address
Address Address
Address
Bank address (output)
Bank
Address address
Address
Bank
Address address
Address
A10 (output)
Row
Address address
Address
Row
Address address
Address
Column Column Column
Row
Address address
address address address
A0 to A9 (output)
Column address
Column Column Column
Row
Address address
address address address
Bank
address
Address Address Address Address
Address
Bank
Address Address address
Address
Row
Address Address address
Address
Column address
Bank
address
Address
Address
Column Column Column
Row
Address address
address address address
Column address
BCYST (output)
CSn (output)
SDRAS (output)
SDCAS (output)
RD (output)
OE (output)
WE (output)
LDQM (output)
UDQM (output)
Data
D0 to D7 (I/O)
Data
Data
Data Data
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 1, 3, 4, 6
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Data
Data Data
Data
Bank B precharge
command
Bank A read
command
Bank A read
command
Bank A read
command
Bank A read
command
Bank A active
command
Bank B write
command
Bank A precharge
command
Bank B write
command
Bank B write
command
Bank B write
command
Bank B active
command
Bank A write
command
Bank A write
command
Bank A write
command
Bank A write
command
Note Addresses other than the bank address, A10, and A0 to A9.
194
Data
H
Bank A active
command
SDCKE (output)
Data Data
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MEMORY ACCESS CONTROL FUNCTION
5.4.6 Refresh control function
The V850E/MA1 can generate a refresh cycle. The refresh cycle is set with SDRAM refresh control registers 1, 3,
4, and 6 (RFS1, RFS3, RFS4, RFS6). RFSn corresponds to CSn (n = 1, 3, 4, 6). For example, to connect SDRAM to
CS1, set RFS1.
When another bus master occupies the external bus, the DRAM controller cannot occupy the external bus. In this
case, the DRAM controller issues a refresh request to the bus master by changing the REFRQ signal to active (low
level).
During a refresh operation, the address bus retains the state it was in just before the refresh cycle.
(1) SDRAM refresh control registers 1, 3, 4, 6 (RFS1, RFS3, RFS4, RFS6)
These registers are used to enable or disable a refresh and set the refresh interval. The refresh interval is
determined by the following calculation formula.
Refresh interval (µs) = Refresh count clock (TRCY) × Interval factor
The refresh count clock and interval factor are determined by the RENn bit and RIN5n to RIN0n bits,
respectively, of the RFSn register.
Note that n corresponds to the register number (1, 3, 4, 6) of SDRAM configuration registers 1, 3, 4, 6 (SCR1,
SCR3, SCR4, SCR6).
These registers can be read/written in 16-bit units.
Caution
Write to the RFS1, RFS3, RFS4, and RFS6 registers after reset, and then do not change the
set values.
Also, do not access an external memory area other than the one for this
initialization routine until the initial settings of the RFS1, RFS3, RFS4, and RFS6 registers
are complete. However, it is possible to access external memory areas whose initialization
settings are complete.
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15
14
13
12
11
10
RFS1
REN1
0
0
0
0
0
RFS3
REN3
0
0
0
0
RFS4
REN4
0
0
0
RFS6
REN6
0
0
0
Bit position
9
8
7
6
5
4
3
RCC11 RCC01
0
0
RIN51 RIN41 RIN31 RIN21 RIN11 RIN01
Address
FFFFF4A6H
After reset
0000H
0
RCC13 RCC03
0
0
RIN53 RIN43 RIN33 RIN23 RIN13 RIN03
FFFFF4AEH
0000H
0
0
RCC14 RCC04
0
0
RIN54 RIN44 RIN34 RIN24 RIN14 RIN04
FFFFF4B2H
0000H
0
0
RCC16 RCC06
0
0
RIN56 RIN46 RIN36 RIN26 RIN16 RIN06
FFFFF4BAH
0000H
Bit name
2
1
RENn
(n = 1, 3,
4, 6)
Refresh Enable
Specifies whether CBR refresh is enabled or disabled.
0: Refresh disabled
1: Refresh enabled
9, 8
RCC1n,
RCC0n
(n = 1, 3,
4, 6)
Refresh Count Clock
Specifies the refresh count clock (TRCY).
Remark
RIN5n to
RIN0n
(n = 1, 3,
4, 6)
0
Function
15
5 to 0
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MEMORY ACCESS CONTROL FUNCTION
RCC1n RCC0n
Refresh count clock (TRCY)
0
0
32/φ
0
1
128/φ
1
0
256/φ
1
1
Setting prohibited
Refresh Interval
Sets the interval factor of the interval timer for the generation of the refresh timing.
RIN5n
RIN4n
RIN3n
RIN2n
RIN1n
RIN0n
0
0
0
0
0
0
1
0
0
0
0
0
1
2
0
0
0
0
1
0
3
0
0
0
0
1
1
4
:
:
:
:
:
:
:
1
1
1
1
1
1
64
φ: Internal system clock frequency
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CHAPTER 5
MEMORY ACCESS CONTROL FUNCTION
Table 5-3. Example of Interval Factor Settings
Specified Refresh Interval
Value (µs)
15.6
Notes 1.
2.
Notes 1, 2
Interval Factor Value
Refresh Count Clock (TRCY)
φ = 20 MHz
φ = 33 MHz
φ = 50 MHz
32/φ
9 (14.4)
16 (15.5)
24 (15.4)
128/φ
2 (12.8)
4 (15.5)
6 (15.4)
256/φ
1 (12.8)
2 (15.5)
3 (15.4)
The interval factor is set by bits RIN0n to RIN5n of the RFSn register (n = 1, 3, 4, 6).
The values in parentheses are the calculated values for the refresh interval (µs).
Refresh interval (µs) = Refresh count clock (TRCY) × Interval factor
Remark
φ: Internal system clock frequency
The V850E/MA1 can automatically generate an auto-refresh cycle and a self-refresh cycle.
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(2) Auto-refresh cycle
In the auto-refresh cycle, the auto-refresh command (REF) is issued four clocks after the precharge
command for all banks (PALL) is issued.
Figure 5-17. Auto-Refresh Cycle
Auto-refresh cycle
TABPW TREFW TREFW TREFW
TREF
SDCLK (output)
REF
PALL
Command
BCYST (output)
H
SDCKE (output)
H
CSn (output)
SDRAS (output)
SDCAS (output)
WE (output)
LDQM (output)
H
UDQM (output)
H
Address (output)
Address
A10 (output)
D0 to D15 (I/O)
Remarks 1. The broken lines indicate the high-impedance state.
2. n = 1, 3, 4, 6
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(3) Refresh timing
Figure 5-18. CBR Refresh Timing (SDRAM)
BCW × 4clk
ALLPRE TW
TW
TW TREF TBCW
TBCW TBCW
TBCW TBCW
TBCW TBCW TBCW
TI
TI
SDCLK (output)
A10 (output)
A0 to A9, A11 to A23
(output)
BCYST (output)
CSn (output)
SDRAS (output)
SDCAS (output)
RD (output)
OE (output)
WE (output)
LDQM (output)
H
UDQM (output)
H
D0 to D15 (I/O)
Refresh command
H
All-bank precharge
command
SDCKE (output)
Remarks 1. The number of wait states set by the BCW1n and BCW0n bits of the SCRn register × 4 clocks will
be inserted in the BCW × 4 clk period.
2. n = 1, 3, 4, 6
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5.4.7 Self-refresh control function
In the case of transition to the IDLE or software STOP mode, or if the SELFREF signal becomes active, the DRAM
controller generates the CBR self-refresh cycle (the system enters a state in which not only SDRAM, but also all
DRAM is self-refreshed).
Note that the SDRAS pulse width of SDRAM must meet the specifications for SDRAM to enter the self-refresh
operation.
Cautions 1. When the transition to the self-refresh cycle is caused by SELFREF signal input, releasing
the self-refresh cycle is only possible by inputting an inactive level to the SELFREF pin.
2. The internal ROM and internal RAM can be accessed even in the self-refresh cycle.
However, access to an on-chip peripheral I/O register or external device is held pending
until the self-refresh cycle is cleared.
To release the self-refresh cycle, use one of the three methods below.
(1) Release by NMI input
(a) In the case of self-refresh cycle in IDLE mode
To release the self-refresh cycle, make the SDRAS, SDCAS, LDQM, and UDQM signals inactive
immediately.
(b) In the case of self-refresh cycle in software STOP mode
To release the self-refresh cycle, make the SDRAS, SDCAS, LDQM, and UDQM signals inactive after
stabilizing oscillation.
(2) Release by INTP0n0 and INTP0n1 inputs (n = 0 to 3)
(a) In the case of self-refresh cycle in IDLE mode
To release the self-refresh cycle, make the SDRAS, SDCAS, LDQM, and UDQM signals inactive
immediately.
(b) In the case of self-refresh cycle in software STOP mode
To release the self-refresh cycle, make the SDRAS, SDCAS, LDQM, and UDQM signals inactive after
stabilizing oscillation.
(3) Release by RESET input
200
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Figure 5-19. Self-Refresh Timing (SDRAM)
BCW × 4clk
TW
TW
NOP TREF
SDCLK (output)
TW
TW
TW
TW
TW TDCW TDCW TDCW TDCW
TI
TI
Note
A10 (output)
A0 to A9, A11 to A23
(output)
BCYST (output)
CSn (output)
SDRAS (output)
SDCAS (output)
RD (output)
OE (output)
WE (output)
LDQM (output)
H
UDQM (output)
H
D0 to D15 (I/O)
Refresh command
NOP command
All-bank precharge
command
SDCKE (output)
Note Shown above is the case when the self-refresh cycle is started in the IDLE or software STOP mode. If the
self-refresh cycle is started by inputting the active level of the SELFREF signal, SDCLK is output without
going low.
Remarks 1. The number of wait states set by the BCW1n and BCW0n bits of the SCRn register × 4 clocks will
be inserted in the BCW × 4 clk period.
2. n = 1, 3, 4, 6
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5.4.8 SDRAM initialization sequence
Be sure to initialize SDRAM when applying power.
(1) Set the registers of SDRAM (other than SDRAM configuration register n (SCRn))
• Bus cycle type configuration registers 0 and 1 (BCT0 and BCT1)
• Bus cycle control register (BCC)
• SDRAM refresh control registers 1, 3, 4, 6 (RFS1, RFS3, RFS4, RFS6)
(2) Set SDRAM configuration registers 1, 3, 4, 6 (SCR1, SCR3, SCR4, SCR6). When writing data to these
registers, the following commands are issued for SDRAM in the order shown below.
• All bank precharge command
• Refresh command (8 times)
• Command that is used to set a mode register
Figures 5-20 and 5-21 show examples of the SDRAM mode register setting timing.
Caution
When using the SDCLK and SDCKE signals, it is necessary to set the SDCLK output mode
and the SDCKE output mode for these signals by setting the PMCCD register. In this case,
however, these settings must not be executed at the same time.
Be sure to set the SDCKE output mode after setting the SDCLK output mode (refer to
14.3.14 (2) (b) Port CD mode control register (PMCCD)).
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Figure 5-20. SDRAM Mode Register Setting Cycle
Mode register setting cycle
TABPW TREFW TREFW TREFW
TREF
SDCLK (output)
Command
REF
PALL
BCYST (output)
H
SDCKE (output)
H
MRS
CSn (output)
SDRAS (output)
SDCAS (output)
WE (output)
LDQM (output)
H
UDQM (output)
H
Address (output)
MD
A10 (output)
MD
D0 to D15 (I/O)
Refresh command (REF)
(generated 8 times)
Remarks 1. The broken lines indicate the high-impedance state.
2. n = 1, 3, 4, 6
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Figure 5-21. SDRAM Register Write Operation Timing
ALPRE TW
TW
TW TREF TW
TW
TW TREF TW
TW
TW REGW TW
TW
TW
TW
TW
SDCLK (output)
Note (output)
Bank address
(output)
A10 (output)
A0 to A9 (output)
BCYST (output)
CSn (output)
SDRAS (output)
SDCAS (output)
RD (output)
OE (output)
WE (output)
LDQM (output)
UDQM (output)
D0 to D15 (I/O)
Note Addresses other than the bank address, A10, and A0 to A9.
Remark
204
n = 1, 3, 4, 6
User’s Manual U14359EJ3V0UM
Register write
command
Refresh end
(8th time)
Refresh
(7 times)
Refresh
command
(2nd time)
Refresh end
(1st time)
Refresh
command
(1st time)
All-bank
precharge
command
H
SCRn register
write
SDCKE (output)
SDRAM access
enabled
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
The V850E/MA1 includes a direct memory access (DMA) controller (DMAC) that executes and controls DMA
transfer.
The DMAC controls data transfer between memory and I/O, or among memories, based on DMA requests issued
by the on-chip peripheral I/O (serial interface, real-time pulse unit, and A/D converter), DMARQ0 to DMARQ3 pins, or
software triggers (memory refers to internal RAM or external memory).
6.1
Features
• 4 independent DMA channels
• Transfer unit: 8/16 bits
• Maximum transfer count: 65,536 (216)
• Two types of transfer
• Flyby (1-cycle) transfer
• 2-cycle transfer
• Three transfer modes
• Single transfer mode
• Single-step transfer mode
• Block transfer mode
• Transfer requests
• Request by interrupts from on-chip peripheral I/O (serial interface, real-time pulse unit, A/D converter)
• Requests via DMARQ0 to DMARQ3 pin input
• Requests by software trigger
• Transfer objects
• Memory ↔ I/O
• Memory ↔ memory
• DMA transfer end output signals (TC0 to TC3)
• Next address setting function
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6.2
DMA FUNCTIONS (DMA CONTROLLER)
Configuration
On-chip
peripheral I/O
Internal RAM
Internal bus
On-chip peripheral I/O bus
CPU
Data
Control
Address
Control
DMA source address
register (DSAnH/DSAnL)
DMA destination address
register (DDAnH/DDAnL)
Count
control
TCn
DMA transfer count
register (DBCn)
DMA terminal count output
control register (DTOC)
DMA channel control
register (DCHCn)
DMARQn
DMAAKn
Channel
control
DMA addressing control
register (DADCn)
DMA disable status
register (DDIS)
DMA restart register (DRST)
DMA trigger factor
register (DTFRn)
DMAC
Bus interface
External bus
External I/O
Remark
206
External
RAM
External
ROM
n = 0 to 3
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CHAPTER 6
6.3
DMA FUNCTIONS (DMA CONTROLLER)
Control Registers
6.3.1 DMA source address registers 0 to 3 (DSA0 to DSA3)
These registers are used to set the DMA source address (28 bits) for DMA channel n (n = 0 to 3). They are divided
into two 16-bit registers, DSAnH and DSAnL.
Since these registers are configured as 2-stage FIFO buffer registers, a new source address for DMA transfer can
be specified during DMA transfer. (Refer to 6.9 Next Address Setting Function.)
When flyby transfer is specified with the TTYP bit of DMA addressing control register n (DADCn), the external
memory addresses are set by the DSAn register. At this time, the setting of DMA destination address register n
(DDAn) is ignored (n = 0 to 3).
(1) DMA source address registers 0H to 3H (DSA0H to DSA3H)
These registers can be read/written in 16-bit units.
Caution
When setting an address of a peripheral I/O register for the source address, be sure to
specify an address between FFFF000H and FFFFFFFH. An address of the peripheral I/O
register image (3FFF000H to 3FFFFFFH) must not be specified.
15
14
13
12
DSA0H
IR
0
0
0
SA27 SA26 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16
Address
FFFFF082H
After reset
Undefined
DSA1H
IR
0
0
0
SA27 SA26 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16
FFFFF08AH
Undefined
DSA2H
IR
0
0
0
SA27 SA26 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16
FFFFF092H
Undefined
DSA3H
IR
0
0
0
SA27 SA26 SA25 SA24 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA16
FFFFF09AH
Undefined
Bit position
15
11 to 0
Bit name
11
10
9
8
7
6
5
4
3
2
1
0
Function
IR
Internal RAM Select
Specifies the DMA source address.
0: External memory, on-chip peripheral I/O
1: Internal RAM
SA27 to
SA16
Source Address
Sets the DMA source address (A27 to A16). During DMA transfer, it stores the next
DMA transfer source address. During flyby transfer, it stores an external memory
address.
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(2) DMA source address registers 0L to 3L (DSA0L to DSA3L)
These registers can be read/written in 16-bit units.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DSA0L
SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0
Address
FFFFF080H
After reset
Undefined
DSA1L
SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0
FFFFF088H
Undefined
DSA2L
SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0
FFFFF090H
Undefined
DSA3L
SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0
FFFFF098H
Undefined
208
Bit position
Bit name
Function
15 to 0
SA15 to SA0
Source Address
Sets the DMA source address (A15 to A0). During DMA transfer, it stores the next DMA
transfer source address. During flyby transfer, it stores an external memory address.
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DMA FUNCTIONS (DMA CONTROLLER)
6.3.2 DMA destination address registers 0 to 3 (DDA0 to DDA3)
These registers are used to set the DMA destination address (28 bits) for DMA channel n (n = 0 to 3). They are
divided into two 16-bit registers, DDAnH and DDAnL.
Since these registers are configured as 2-stage FIFO buffer registers, a new destination address for DMA transfer
can be specified during DMA transfer. (Refer to 6.9 Next Address Setting Function.)
When flyby transfer is specified with bit TTYP of DMA addressing control register n (DADCn), the setting of DMA
destination address register n (DDAn) is ignored (n = 0 to 3).
(1) DMA destination address registers 0H to 3H (DDA0H to DDA3H)
These registers can be read/written in 16-bit units.
Caution
When setting an address of a peripheral I/O register for the destination address, be sure to
specify an address between FFFF000H and FFFFFFFH. An address of the peripheral I/O
register image (3FFF000H to 3FFFFFFH) must not be specified.
15
14
13
12
DDA0H
IR
0
0
0
DA27 DA26 DA25 DA24 DA23 DA22 DA21 DA20 DA19 DA18 DA17 DA16
Address
FFFFF086H
After reset
Undefined
DDA1H
IR
0
0
0
DA27 DA26 DA25 DA24 DA23 DA22 DA21 DA20 DA19 DA18 DA17 DA16
FFFFF08EH
Undefined
DDA2H
IR
0
0
0
DA27 DA26 DA25 DA24 DA23 DA22 DA21 DA20 DA19 DA18 DA17 DA16
FFFFF096H
Undefined
DDA3H
IR
0
0
0
DA27 DA26 DA25 DA24 DA23 DA22 DA21 DA20 DA19 DA18 DA17 DA16
FFFFF09EH
Undefined
Bit position
15
11 to 0
Bit name
11
10
9
8
7
6
5
4
3
2
1
0
Function
IR
Internal RAM Select
Specifies the DMA destination address.
0: External memory, on-chip peripheral I/O
1: Internal RAM
DA27 to
DA16
Destination Address
Sets the DMA destination address (A27 to A16). During DMA transfer, it stores the next
DMA transfer destination address. This setting is ignored during flyby transfer.
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(2) DMA destination address registers 0L to 3L (DDA0L to DDA3L)
These registers can be read/written in 16-bit units.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DDA0L
DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
Address
FFFFF084H
After reset
Undefined
DDA1L
DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
FFFFF08CH
Undefined
DDA2L
DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
FFFFF094H
Undefined
DDA3L
DA15 DA14 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
FFFFF09CH
Undefined
210
Bit position
Bit name
15 to 0
DA15 to DA0
Function
Destination Address
Sets the DMA destination address (A15 to A0). During DMA transfer, it stores the next
DMA transfer destination address. This setting is ignored during flyby transfer.
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DMA FUNCTIONS (DMA CONTROLLER)
6.3.3 DMA byte count registers 0 to 3 (DBC0 to DBC3)
These 16-bit registers are used to set the byte transfer count for DMA channel n (n = 0 to 3). They store the
remaining transfer count during DMA transfer.
Since these registers are configured as 2-stage FIFO buffer registers, a new DMA byte transfer count for DMA
transfer can be specified during DMA transfer. (Refer to 6.9 Next Address Setting Function.)
These registers are decremented by 1 for each transfer, and transfer ends when a borrow occurs.
These registers can be read/written in 16-bit units.
Remark
If the DBCn register is read during DMA transfer after a terminal count has occurred without the
register being overwritten, the value set immediately before the DMA transfer will be read out (0000H
will not be read, even if DMA transfer has ended).
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DBC0
BC15 BC14 BC13 BC12 BC11 BC10 BC9 BC8 BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0
Address
FFFFF0C0H
After reset
Undefined
DBC1
BC15 BC14 BC13 BC12 BC11 BC10 BC9 BC8 BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0
FFFFF0C2H
Undefined
DBC2
BC15 BC14 BC13 BC12 BC11 BC10 BC9 BC8 BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0
FFFFF0C4H
Undefined
DBC3
BC15 BC14 BC13 BC12 BC11 BC10 BC9 BC8 BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0
FFFFF0C6H
Undefined
Bit position
Bit name
15 to 0
BC15 to BC0
Function
Byte Count
Sets the byte transfer count and stores the remaining byte transfer count during
DMA transfer.
DBCn (n = 0 to 3)
States
0000H
Byte transfer count 1 or remaining byte transfer count
0001H
Byte transfer count 2 or remaining byte transfer count
:
:
FFFFH
Byte transfer count 65,536 (2 ) or remaining byte transfer
count
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DMA FUNCTIONS (DMA CONTROLLER)
6.3.4 DMA addressing control registers 0 to 3 (DADC0 to DADC3)
These 16-bit registers are used to control the DMA transfer mode for DMA channel n (n = 0 to 3). These registers
cannot be accessed during DMA operation.
They can be read/written in 16-bit units.
(1/2)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DADC0
DS1 DS0
0
0
0
0
0
0
SAD1 SAD0 DAD1 DAD0 TM1 TM0 TTYP TDIR
Address
FFFFF0D0H
After reset
0000H
DADC1
DS1 DS0
0
0
0
0
0
0
SAD1 SAD0 DAD1 DAD0 TM1 TM0 TTYP TDIR
FFFFF0D2H
0000H
DADC2
DS1 DS0
0
0
0
0
0
0
SAD1 SAD0 DAD1 DAD0 TM1 TM0 TTYP TDIR
FFFFF0D4H
0000H
DADC3
DS1 DS0
0
0
0
0
0
0
SAD1 SAD0 DAD1 DAD0 TM1 TM0 TTYP TDIR
FFFFF0D6H
0000H
Bit position
15, 14
7, 6
5, 4
212
Bit name
DS1, DS0
SAD1,
SAD0
DAD1,
DAD0
Function
Data Size
Sets the transfer data size for DMA transfer.
DS1
DS0
Transfer data size
0
0
8 bits
0
1
16 bits
1
0
Setting prohibited
1
1
Setting prohibited
Source Address count Direction
Sets the count direction of the source address for DMA channel n.
SAD1
SAD0
0
0
Increment
Count direction
0
1
Decrement
1
0
Fixed
1
1
Setting prohibited
Destination Address count Direction
Sets the count direction of the destination address for DMA channel n.
DAD1
DAD0
0
0
Increment
Count direction
0
1
Decrement
1
0
Fixed
1
1
Setting prohibited
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CHAPTER 6
DMA FUNCTIONS (DMA CONTROLLER)
(2/2)
Bit position
Bit name
3, 2
TM1, TM0
Function
Transfer Mode
Sets the transfer mode during DMA transfer.
TM1
TM0
Transfer mode
0
0
Single transfer mode
0
1
Single-step transfer mode
1
0
Setting prohibited
1
1
Block transfer mode
1
TTYP
Transfer Type
Sets the DMA transfer type.
0: 2-cycle transfer
1: Flyby transfer
0
TDIR
Transfer Direction
Sets the transfer direction during transfer between I/O and memory. The setting is valid
during flyby transfer only and ignored during 2-cycle transfer.
0: Memory → I/O (read)
1: I/O → memory (write)
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6.3.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3)
These 8-bit registers are used to control the DMA transfer operating mode for DMA channel n (n = 0 to 3).
These registers can be read/written in 8-bit or 1-bit units. (However, bit 7 is read only and bits 2 and 1 are write
only. If bits 2 and 1 are read, the read value is always 0.)
<7>
6
5
4
<3>
<2>
<1>
<0>
DCHC0
TC0
0
0
0
MLE0
INIT0
STG0
E00
Address
FFFFF0E0H
After reset
00H
DCHC1
TC1
0
0
0
MLE1
INIT1
STG1
E11
FFFFF0E2H
00H
DCHC2
TC2
0
0
0
MLE2
INIT2
STG2
E22
FFFFF0E4H
00H
DCHC3
TC3
0
0
0
MLE3
INIT3
STG3
E33
FFFFF0E6H
00H
214
Bit position
Bit name
Function
7
TCn
(n = 0 to 3)
Terminal Count
This status bit indicates whether DMA transfer through DMA channel n has ended or not.
This bit is read-only. It is set to 1 when DMA transfer ends and cleared (to 0) when it is
read.
0: DMA transfer has not ended.
1: DMA transfer has ended.
3
MLEn
(n = 0 to 3)
Multi Link Enable Bit
When this bit is set to 1 at terminal count output, the Enn bit is not cleared to 0 and the
DMA transfer enable state is retained. Moreover, the next DMA transfer request can be
acknowledged even when the TCn bit is not read.
When this bit is cleared to 0 at terminal count output, the Enn bit is cleared to 0 and the
DMA transfer disable state is entered. At the next DMA request, the Enn bit must be set to
1 and the TCn bit read.
2
INITn
(n = 0 to 3)
Initialize
When this bit is set to 1, DMA transfer is forcibly terminated.
1
STGn
(n = 0 to 3)
Software Trigger
If this bit is set to 1 in the DMA transfer enable state (TCn bit = 0, Enn bit = 1), DMA
transfer is started.
0
Enn
(n = 0 to 3)
Enable
Specifies whether DMA transfer through DMA channel n is to be enabled or disabled. This
bit is cleared to 0 when DMA transfer ends. It is also cleared to 0 when DMA transfer is
forcibly terminated by setting the INITn bit to 1 or by NMI input.
0: DMA transfer disabled
1: DMA transfer enabled
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DMA FUNCTIONS (DMA CONTROLLER)
6.3.6 DMA disable status register (DDIS)
This register holds the contents of the Enn bit of the DCHCn register during NMI input (n = 0 to 3).
This register is read-only in 8-bit units.
DDIS
7
6
5
4
3
2
1
0
0
0
0
0
CH3
CH2
CH1
CH0
Bit position
Bit name
3 to 0
CH3 to CH0
Address
FFFFF0F0H
After reset
00H
Function
NMI Interrupt Status
Reflects the contents of the Enn bit of the DCHCn register during NMI input. The
contents of this register are held until the next NMI input or until the system is reset.
6.3.7 DMA restart register (DRST)
This register is used to restart DMA transfer that has been forcibly interrupted by NMI input. The ENn bit of this
register and the Enn bit of the DCHCn register are linked to each other (n = 0 to 3). Following forcible interrupt by
NMI input, the DMA channel that was interrupted is confirmed from the contents of the DDIS register, and DMA
transfer is restarted by setting the ENn bit of the corresponding channel to 1.
This register can be read/written in 8-bit units.
DRST
7
6
5
4
3
2
1
0
0
0
0
0
EN3
EN2
EN1
EN0
Address
FFFFF0F2H
After reset
00H
Bit position
Bit name
Function
3 to 0
EN3 to EN0
Restart Enable
Specifies whether DMA transfer through DMA channel n is to be enabled or disabled.
This bit is cleared to 0 when DMA transfer is completed in accordance with the terminal
count output.
It is also cleared to 0 when DMA transfer is forcibly terminated by setting the INITn bit to
1 or by NMI input.
0: DMA transfer disabled
1: DMA transfer enabled
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DMA FUNCTIONS (DMA CONTROLLER)
6.3.8 DMA terminal count output control register (DTOC)
The DMA terminal count output control register (DTOC) is an 8-bit register that controls the terminal count output
from each DMA channel. Terminal count signals from each DMA channel can be brought together and output from
the TC0 pin.
This register can be read/written in 8-bit units.
DTOC
Bit position
3 to 0
7
6
5
4
3
2
1
0
0
0
0
0
TCO3
TCO2
TCO1
TCO0
Bit name
TCO3 to
TCO0
Address
FFFFF8A0H
Function
Terminal Count Output
Indicates the state of the TCn pin (n = 0 to 3).
0: Channel n terminal count signal not output from TC0 pin.
1: Channel n terminal count signal output from TC0 pin.
The following shows an example of the case when the DTOC register is set to 03H.
DMA0 DMA0
CPU
DMA channel 0
terminal count
DMA1 DMA1
DMA channel 1
terminal count
TC0 (output)
TC2 (output)
216
CPU
User’s Manual U14359EJ3V0UM
DMA2 DMA2
DMA channel 2
terminal count
After reset
01H
CHAPTER 6
DMA FUNCTIONS (DMA CONTROLLER)
6.3.9 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3)
These 8-bit registers are used to control the DMA transfer start trigger through interrupt requests from on-chip
peripheral I/O.
The interrupt requests set by these registers serve as DMA transfer startup factors.
These registers can be read/written in 8-bit units. However, only bit 7 (DFn) can be read/written in 1-bit units.
Caution
An interrupt request input in the standby mode (IDLE or software STOP mode) cannot be a DMA
transfer start factor.
(1/2)
<7>
6
5
4
3
2
1
0
DTFR0
DF0
0
IFC05
IFC04
IFC03
IFC02
IFC01
IFC00
Address
FFFFF810H
After reset
00H
DTFR1
DF1
0
IFC15
IFC14
IFC13
IFC12
IFC11
IFC10
FFFFF812H
00H
DTFR2
DF2
0
IFC25
IFC24
IFC23
IFC22
IFC21
IFC20
FFFFF814H
00H
DTFR3
DF3
0
IFC35
IFC34
IFC33
IFC32
IFC31
IFC30
FFFFF816H
00H
Bit position
Bit name
Function
7
DFn
DMA Request Flag
This is a DMA transfer request flag.
Only 0 can be written to this flag.
0: DMA transfer not requested
1: DMA transfer requested
If the interrupt specified as the DMA transfer startup trigger occurs and it is necessary to
clear the DMA transfer request while DMA transfer is disabled (including when it is aborted
by NMI or forcibly terminated by software), stop the operation of the source causing the
interrupt, and then clear the DFn bit to 0 (for example, disable reception in the case of
serial reception). If it is clear that the interrupt will not occur until DMA transfer is resumed
next, it is not necessary to stop the operation of the source causing the interrupt.
5 to 0
IFCn5 to
IFCn0
Interrupt Factor Code
This code is used to set the interrupt sources serving as DMA transfer startup factors.
IFCn5
IFCn4
IFCn3
IFCn2
IFCn1
IFCn0
0
0
0
0
0
0
DMA request from on-chip
peripheral I/O disabled
0
0
0
0
0
1
INTP000/INTM000
0
0
0
0
1
0
INTP001/INTM001
0
0
0
0
1
1
INTP010/INTM010
0
0
0
1
0
0
INTP011/INTM011
0
0
0
1
0
1
INTP020/INTM020
0
0
0
1
1
0
INTP021/INTM021
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Interrupt source
217
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DMA FUNCTIONS (DMA CONTROLLER)
(2/2)
Bit position
5 to 0
Bit name
IFCn5 to
IFCn0
Function
IFCn5
IFCn4
IFCn3
IFCn2
IFCn1
IFCn0
0
0
0
1
1
1
INTP030/INTM030
0
0
1
0
0
0
INTP031/INTM031
0
0
1
0
0
1
INTP100
0
0
1
0
1
0
INTP101
0
0
1
0
1
1
INTP102
0
0
1
1
0
0
INTP103
0
0
1
1
0
1
INTP110
0
0
1
1
1
0
INTP111
0
0
1
1
1
1
INTP112
0
1
0
0
0
0
INTP113
0
1
0
0
0
1
INTP120
0
1
0
0
1
0
INTP121
0
1
0
0
1
1
INTP122
0
1
0
1
0
0
INTP123
0
1
0
1
0
1
INTP130
0
1
0
1
1
0
INTP131
0
1
0
1
1
1
INTP132
0
1
1
0
0
0
INTP133
0
1
1
0
0
1
INTCMD0
0
1
1
0
1
0
INTCMD1
0
1
1
0
1
1
INTCMD2
0
1
1
1
0
0
INTCMD3
0
1
1
1
0
1
INTCSI0
0
1
1
1
1
0
INTSR0
0
1
1
1
1
1
INTST0
1
0
0
0
0
0
INTCSI1
1
0
0
0
0
1
INTSR1
1
0
0
0
1
0
INTST1
1
0
0
0
1
1
INTCSI2
1
0
0
1
0
0
INTSR2
1
0
0
1
0
1
INTST2
1
0
0
1
1
0
INTAD
Other than above
Remark
218
n = 0 to 3
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Interrupt source
Setting prohibited
CHAPTER 6
DMA FUNCTIONS (DMA CONTROLLER)
The relationship between the DMARQn signal and the interrupt source that serves as a DMA transfer trigger is as
follows (n = 0 to 3)
DMARQn
Selector
Interrupt source
Internal DMA request signal
IFCn0 to IFCn5
Remark
If an interrupt request is specified as the DMA transfer start factor, an interrupt request will be generated
if DMA transfer starts. To prevent an interrupt from being generated, mask the interrupt by setting the
interrupt request control register. DMA transfer starts even if an interrupt is masked.
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CHAPTER 6
6.4
DMA FUNCTIONS (DMA CONTROLLER)
DMA Bus States
6.4.1 Types of bus states
The DMAC bus states consist of the following 13 states.
(1) TI state
The TI state is an idle state, during which no access request is issued.
The DMARQ0 to DMARQ3 signals are sampled at the rising edge of the CLKOUT signal.
(2) T0 state
DMA transfer ready state (state in which a DMA transfer request has been issued and the bus mastership is
acquired for the first DMA transfer).
(3) T1R state
The bus enters the T1R state at the beginning of a read operation in the 2-cycle transfer mode.
Address driving starts. After entering the T1R state, the bus invariably enters the T2R state.
(4) T1RI state
The T1RI state is a state in which the bus waits for the acknowledge signal corresponding to an external
memory read request.
After entering the last T1RI state, the bus invariably enters the T2R state.
(5) T2R state
The T2R state corresponds to the last state of a read operation in the 2-cycle transfer mode, or to a wait
state.
In the last T2R state, read data is sampled. After entering the last T2R state, the bus invariably enters the
T1W state.
(6) T2RI state
State in which the bus is ready for DMA transfer to on-chip peripheral I/O or internal RAM (state in which the
bus mastership is acquired for DMA transfer to on-chip peripheral I/O or internal RAM).
After entering the last T2RI state, the bus invariably enters the T1W state.
(7) T1W state
The bus enters the T1W state at the beginning of a write operation in the 2-cycle transfer mode.
Address driving starts. After entering the T1W state, the bus invariably enters the T2W state.
(8) T1WI state
State in which the bus waits for the acknowledge signal corresponding to an external memory write request.
After entering the last T1WI state, the bus invariably enters the T2W state.
(9) T2W state
The T2W state corresponds to the last state of a write operation in the 2-cycle transfer mode, or to a wait
state.
In the last T2W state, the write strobe signal is made inactive.
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(10) T1FH state
The basic flyby transfer state, this state corresponds to the transfer execution cycle.
After entering the T1FH state, the bus enters the T2FH state.
(11) T1FHI state
The T1FHI state corresponds to the last state of a flyby transfer, during which the end of transfer is waited
for.
After entering the T1FHI state, the bus is released and enters the TE state.
(12) T2FH state
The T2FH state is the state during which it is judged whether flyby transfer is to be continued or not.
If the next transfer is executed in the block transfer mode, the bus enters the T1FH state after the T2FH
state.
Under other conditions, the bus enters the T1FHI state when a wait is issued. If no wait is issued, the bus is
released and enters the TE state.
(13) TE state
The TE state corresponds to DMA transfer completion. The DMAC generates the internal DMA transfer
completion signal (TCn) and various internal signals are initialized (n = 0 to 3). After entering the TE state,
the bus invariably enters the TI state.
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DMA FUNCTIONS (DMA CONTROLLER)
6.4.2 DMAC bus cycle state transition
Except for the block transfer mode, each time the processing for a DMA transfer is completed, the bus mastership
is released.
Figure 6-1. DMAC Bus Cycle State Transition
(a) 2-cycle transfer
(b) Flyby transfer
TI
TI
T0
T0
T1R
T1RI
T1FH
T2R
T2RI
T1W
T2FH
T1WI
T1FHI
T2W
222
TE
TE
TI
TI
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CHAPTER 6
6.5
DMA FUNCTIONS (DMA CONTROLLER)
Transfer Modes
6.5.1 Single transfer mode
In single transfer mode, the DMAC releases the bus at each byte/halfword transfer. If there is a subsequent DMA
transfer request, transfer is performed again once. This operation continues until a terminal count occurs.
When the DMAC has released the bus, if another higher priority DMA transfer request is issued, the higher priority
DMA request takes precedence. If a single transfer is executed, the internal DMA request is cleared each time one
DMA cycle has been completed. If any other channel requests DMA after completion of one DMA cycle, therefore,
the DMA transfer request with the highest priority is selected from the channels other than the one for which the DMA
cycle has just been completed.
The following shows an example of a single transfer. Figure 6-3 shows an example of a single transfer in which a
higher priority DMA request is issued. DMA channels 0 to 2 are in the block transfer mode and channel 3 is in the
single transfer mode.
Figure 6-2. Single Transfer Example 1
DMARQ3
(input)
Note
Note
Note
Note
CPU CPU DMA3 CPU DMA3 CPU DMA3 CPU CPU CPU CPU CPU CPU DMA3 CPU DMA3 CPU CPU CPU
DMA channel 3 terminal count
Note The bus is always released.
Figure 6-3. Single Transfer Example 2
DMARQ0
(input)
DMARQ1
(input)
DMARQ2
(input)
DMARQ3
(input)
Note
Note
Note
Note
CPU CPU CPU DMA3 CPU DMA0 DMA0 CPU DMA1 DMA1 CPU DMA2 DMA2 CPU DMA3 CPU DMA3
DMA channel 1
terminal count
DMA channel 0
terminal count
DMA channel 3
terminal count
DMA channel 2
terminal count
Note The bus is always released.
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DMA FUNCTIONS (DMA CONTROLLER)
6.5.2 Single-step transfer mode
In single-step transfer mode, the DMAC releases the bus at each byte/halfword transfer. If there is a subsequent
DMA transfer request signal (DMARQ0 to DMARQ3), transfer is performed again. This operation continues until a
terminal count occurs.
When the DMAC has released the bus, if another higher priority DMA transfer request is issued, the higher priority
DMA request always takes precedence.
The following shows an example of a single-step transfer. Figure 6-5 shows an example of single-step transfer
made in which a higher priority DMA request is issued. DMA channels 0 and 1 are in the single-step transfer mode.
Figure 6-4. Single-Step Transfer Example 1
DMARQ1
(input)
Note
Note
Note
CPU CPU CPU DMA1 CPU DMA1 CPU DMA1 CPU DMA1 CPU CPU CPU CPU CPU CPU CPU
DMA channel 1 terminal count
Note The bus is always released.
Figure 6-5. Single-Step Transfer Example 2
DMARQ0
(input)
DMARQ1
(input)
Note
Note
Note
Note
Note
Note
CPU CPU CPU DMA1 CPU DMA1 CPU DMA0 CPU DMA0 CPU DMA0 CPU DMA1 CPU DMA1 CPU
DMA channel 0
terminal count
Note The bus is always released.
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DMA channel 1
terminal count
CHAPTER 6
DMA FUNCTIONS (DMA CONTROLLER)
6.5.3 Block transfer mode
In the block transfer mode, once transfer starts, the DMAC continues the transfer operation without releasing the
bus until a terminal count occurs. No other DMA requests are acknowledged during block transfer.
After the block transfer ends and the DMAC releases the bus, another DMA transfer can be acknowledged.
The following shows an example of block transfer in which a higher priority DMA request is issued. DMA channels
2 and 3 are in the block transfer mode.
Figure 6-6. Block Transfer Example
DMARQ2
(input)
DMARQ3
(input)
CPU CPU CPU DMA3 DMA3 DMA3 DMA3 DMA3 DMA3 DMA3 DMA3 CPU DMA2 DMA2 DMA2 DMA2 DMA2
DMA channel 3
terminal count
User’s Manual U14359EJ3V0UM
The bus is always
released.
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CHAPTER 6
6.6
DMA FUNCTIONS (DMA CONTROLLER)
Transfer Types
6.6.1 2-cycle transfer
In 2-cycle transfer, data transfer is performed in two cycles, a read cycle (source to DMAC) and a write cycle
(DMAC to destination).
In the first cycle, the source address is output and reading is performed from the source to the DMAC. In the
second cycle, the destination address is output and writing is performed from the DMAC to the destination.
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Figure 6-7. Timing of Access to SRAM, External ROM, and External I/O During 2-Cycle DMA Transfer (1/2)
(a) SRAM → External I/O (BCC register setting for SRAM: BCn1, BCn0 = 00B)
(BCC register setting for external I/O: BCn1, BCn0 = 00B)
T1
T2
TINote
T1
T2
CLKOUT (output)
DMARQx (input)
DMAAKx (output)
Address
A0 to A25 (output)
Address
BCYST (output)
CSn/RASm (output)
of SRAM area
CSn/RASm (output)
of external I/O area
RD (output)
OE (output)
WE (output)
UWR/UCAS (output)
LWR/LCAS (output)
IORD (output)
IOWR (output)
LBE (output)
UBE (output)
Data
D0 to D15 (I/O)
Data
WAIT (input)
TCx (output)
Note This idle state (TI) is independent of the BCC register setting.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3
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DMA FUNCTIONS (DMA CONTROLLER)
Figure 6-7. Timing of Access to SRAM, External ROM, and External I/O During 2-Cycle DMA Transfer (2/2)
(b) SRAM → External I/O (BCC register setting for SRAM: BCn1, BCn0 = 11B)
(BCC register setting for external I/O: BCn1, BCn0 = 00B)
T1
T2
TINote 1 TINote 1 TINote 1 TINote 2
T1
T2
CLKOUT (output)
DMARQx (input)
DMAAKx (output)
Address
A0 to A25 (output)
Address
BCYST (output)
CSn/RASm (output)
of SRAM area
CSn/RASm (output)
of external I/O area
RD (output)
OE (output)
WE (output)
UWR/UCAS (output)
LWR/LCAS (output)
IORD (output)
IOWR (output)
LBE (output)
UBE (output)
Data
D0 to D15 (I/O)
WAIT (input)
TCx (output)
Notes 1.
2.
This idle state (TI) is inserted by means of a BCC register setting.
This idle state (TI) is independent of the BCC register setting.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3
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Data
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DMA FUNCTIONS (DMA CONTROLLER)
Figure 6-8. Timing of 2-Cycle DMA Transfer (External I/O → SRAM)
(a) Single-step transfer mode
TI
TI
TI
TI
TO
T1 T2
T1R T2R
TI
Note 1
T1 T2
T1W T2W
TI
TI
TI
T1 TW T2
TO T1R T2R T2R
TI
Note 1
T1 TW T2
T1W T2W T2W
CLKOUT (output)
DMARQx (input)
Internal DMA
request signal
DMAAKx (output)
TCx (output)
A0 to A25 (output)
Address
Address
Address
Address
D0 to D15 (I/O)
Data
Data
Data
Data
CSm (output) of
external I/O area
CSn (output) of
SRAM area
BCYST (output)
RD (output)
OE (output)
H
WE (output)
H
UWR/UCAS (output)
LWR/LCAS (output)
IORD (output)Note 2
IOWR (output)Note 2
WAIT (input)
Notes 1.
2.
This idle state (TI) is independent of the BCC register setting.
When the IOEN bit of the BCP register is set to 1.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 0 to 7, x = 0 to 3 (n ≠ m)
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Figure 6-9. Timing of 2-Cycle DMA Transfer (SRAM → EDO DRAM) (1/3)
(a) Single transfer mode
Note 2
TI
T1
T2
T1
T2
T1
T2
TI
TI
TI
TO
T1R
T2R
Note 1
TI
TRPW
Note 2
T1
T2
T1W T2W T2W
TE
T1
TW
T2
T1
TW
T2
T1
T2
TI
TI
TI
TI
TI
TO
T1R
T2R
Note 1
TI
TCPW TB
T1W T2W
TE
CLKOUT (output)
DMARQx (input)
Internal DMA
request signal
DMAAKx (output)
TCx (output)
Address
Address (output)
Row
address
Column
address
Address
Column address
BCYST (output)
Note 3
CSn (output) of
SRAM area
RASm (output) of
DRAM area
Note 4
CSn (output)
of other area
LCAS (output)
UCAS (output)
RD (output)
OE (output)
WE (output)
LBE (output)
UBE (output)
D0 to D15 (I/O)
Notes 1.
Data
Data
Data
Data
Data
Data
Data
This idle state (TI) is independent of the BCC register setting.
2.
TRPW and TCPW are always inserted for one or more cycles.
3.
When a bus cycle accessing another CS space or a read cycle accessing the same CS space
follows this write cycle.
4.
In the case of the RAS hold mode
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3
230
Data
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DMA FUNCTIONS (DMA CONTROLLER)
Figure 6-9. Timing of 2-Cycle DMA Transfer (SRAM → EDO DRAM) (2/3)
(b) Single-step transfer mode
Note 2
TI
T1
T2
T1
T2
T1
T2
TI
TI
TI
TO
T1R
T2R
Note 1
TI
TRPW
Note 2
T1
T2
T1W T2W T2W
TE
T1
T2
T1
T2
T1
T2
TI
TI
TI
TI
T1R
T2R
Note 1
TI
TCPW TB
T1W T2W
TE
CLKOUT (output)
DMARQx (input)
Internal DMA
request singal
DMAAKx (output)
TCx (output)
Address
Address (output)
Row
address
Column
address
Address
Column address
BCYST (output)
Note 3
CSn (output) of
SRAM area
RASm (output) of
DRAM area
Note 4
CSn (output) of
other area
LCAS (output)
UCAS (output)
RD (output)
OE (output)
WE (output)
LBE (output)
UBE (output)
D0 to D15 (I/O)
Notes 1.
Data
Data
Data
Data
Data
Data
Data
Data
This idle state (TI) is independent of the BCC register setting.
2.
TRPW and TCPW are always inserted for one or more cycles.
3.
When a bus cycle accessing another CS space or a read cycle accessing the same CS space
follows this write cycle.
4.
In the case of the RAS hold mode
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3
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Figure 6-9. Timing of 2-Cycle DMA Transfer (SRAM → EDO DRAM) (3/3)
(c) Block transfer mode
Note 2
TI
T1
T2
T1
T2
T1
T2
TI
TI
TI
TO
T1R
T2R
Note 1
TI
TRPW
Note 2
T1
T2
T1W T2W T2W
TE
T1
T2
T1R
T2R
Note 1
TI
TCPW TB
T1W T2W
TE
CLKOUT (output)
DMARQx (input)
Internal DMA
request signal
DMAAKx (output)
TCx (output)
Address
Address (output)
Row
address
Column
address
Address
Column address
BCYST (output)
Note 3
CSn (output) of
SRAM area
RASm (output) of
DRAM area
Note 4
CSn (output) of
other area
LCAS (output)
UCAS (output)
RD (output)
OE (output)
WE (output)
LBE (output)
UBE (output)
D0 to D15 (I/O)
Notes 1.
Data
Data
Data
Data
Data
This idle state (TI) is independent of the BCC register setting.
2.
TRPW and TCPW are always inserted for one or more cycles.
3.
When a bus cycle accessing another CS space or a read cycle accessing the same CS space
follows this write cycle.
4.
In the case of the RAS hold mode
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3
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DMA FUNCTIONS (DMA CONTROLLER)
Figure 6-10. Timing of 2-Cycle DMA Transfer (EDO DRAM → SRAM) (1/3)
(a) Single transfer mode
Note 1
TI
T1
T2
T1
T2
TRPW
TI
TI
TI
TO
T1R
T1
T2
T2R T2R
TE
T1
T2
T1
TW
T2
T1
TW
T2
TB
T1W
T2W
TI
TI
TI
TI
TI
TO
T1R
T1
TE
T2
T1W T2W
CLKOUT (output)
DMARQx (input)
Internal DMA
request signal
DMAAKx (output)
TCx (output)
Row
address
Address (output)
Column
address
Column
address
Address
Address
BCYST (output)
CSn (output) of
SRAM area
RASm (output) of
DRAM area
Note 2
CSn (output) of
other area
LCAS/LWR (output)
UCAS/UWR (output)
RD (output)
OE (output)
WE (output)
LBE (output)
UBE (output)
D0 to D15 (I/O)
Notes 1.
2.
Data
Data
Data
Data
Data
Data
Data
Data
TRPW is always inserted for one or more cycles.
In the case of the RAS hold mode
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3
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DMA FUNCTIONS (DMA CONTROLLER)
Figure 6-10. Timing of 2-Cycle DMA Transfer (EDO DRAM → SRAM) (2/3)
(b) Single-step transfer mode
Note 1
TI
T1
T2
T1
T2
TRPW
TI
TI
TI
TO
T1R
T1
T2
T2R T2R
TE
T1
T2
T1
T2
T1
T2
TB
T1W
T2W
TI
TI
TI
TI
T1R
T1
TE
T2
T1W T2W
CLKOUT (output)
DMARQx (input)
Internal DMA
request signal
DMAAKx (output)
TCx (output)
Row
address
Address (output)
Column
address
Column
address
Address
Address
BCYST (output)
CSn (output) of
SRAM area
RASm (output) of
DRAM area
Note 2
CSn (output) of
other area
LCAS/LWR (output)
UCAS/UWR (output)
RD (output)
OE (output)
WE (output)
LBE (output)
UBE (output)
D0 to D15 (I/O)
Notes 1.
2.
Data
Data
Data
Data
TRPW is always inserted for one or more cycles.
In the case of the RAS hold mode
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3
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Data
Data
Data
Data
CHAPTER 6
DMA FUNCTIONS (DMA CONTROLLER)
Figure 6-10. Timing of 2-Cycle DMA Transfer (EDO DRAM → SRAM) (3/3)
(c) Block transfer mode
Note 1
TI
T1
T2
T1
T2
TRPW
TI
TI
TI
TO
T1R
T1
T2
T2R T2R
TE
T1
T2
T1W
T2W
Note 2
TI
TB
T1R
T1
TE
T2
T1W T2W
CLKOUT (output)
DMARQx (input)
Input DMA
request signal
DMAAKx (output)
TCx (output)
Row
address
Address (output)
Column
address
Address
Column
address
Address
BCYST (output)
CSn (output) of
SRAM area
RASm (output) of
DRAM area
Note 3
CSn (output) of
other area
LCAS/LWR (output)
UCAS/UWR (output)
RD (output)
OE (output)
WE (output)
LBE (output)
UBE (output)
D0 to D15 (I/O)
Notes 1.
Data
Data
Data
Data
Data
Data
TRPW is always inserted for one or more cycles.
2.
This idle state (TI) is independent of the BCC register setting.
3.
In the case of the RAS hold mode
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3
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Figure 6-11. Timing of 2-Cycle DMA Transfer (SRAM → SDRAM) (1/3)
(a) Single transfer mode
TI
T1
T2
T1
T2
T1
T2
TI
TI
TI
TO
T1R
T2R
Note
TI
TW TACT TWR TWPRE TWE
T1
TW
T2
T1
TW
T2
T1
T2
T1W T2W T2W T2W T2W
TI
TI
TI
TI
TI
TO
T1R
T2R
Note
TI
TW
TWR TWPRE TWE
T1W T2W T2W T2W
SDCLK (output)
DMARQx (input)
Internal DMA
output signal
DMAAKx (output)
TCx (output)
Address
Address (output)
Row
address
Address
Column address
Column address
BCYST (output)
CSn (output) of
SRAM area
CSn (output) of
SDRAM area
CSn (output) of
other area
SDRAS (output)
SDCAS (output)
RD (output)
WE (output)
LDQM (output)
UDQM (output)
D0 to D15 (I/O)
SDCKE (output)
Data
Data
Data
Data
Data
H
Note This idle state (TI) is independent of the BCC register setting.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, x = 0 to 3
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Data
Data
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DMA FUNCTIONS (DMA CONTROLLER)
Figure 6-11. Timing of 2-Cycle DMA Transfer (SRAM → SDRAM) (2/3)
(b) Single-step transfer mode
TI
T1
T2
T1
T2
T1
T2
TI
TI
TI
TO
T1R
T2R
Note
TI
TW TACT TWR TWPRE TWE
T1
T2
T1
T2
T1
T2
T1W T2W T2W T2W T2W
TI
TI
TI
TI
T1R
T2R
Note
TI
TW TWR TWPRE TWE
T1W T2W T2W T2W
SDCLK (output)
DMARQx (input)
Internal DMA
request signal
DMAAKx (output)
TCx (output)
Address
Address (output)
Row
address
Address
Column address
Column address
BCYST (output)
CSn (output) of
SRAM area
CSn (output) of
SDRAM area
CSn (output) of
other area
SDRAS (output)
SDCAS (output)
RD (output)
WE (output)
LDQM (output)
UDQM (output)
D0 to D15 (I/O)
SDCKE (output)
Data
Data
Data
Data
Data
Data
Data
Data
H
Note This idle state (TI) is independent of the BCC register setting.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, x = 0 to 3
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Figure 6-11. Timing of 2-Cycle DMA Transfer (SRAM → SDRAM) (3/3)
(c) Block transfer mode
TI
T1
T2
T1
T2
T1
T2
TI
TI
TI
TO
T1R
T2R
Note
TI
TW TACT TWR TWPRE TWE
T1W T2W T2W T2W T2W
Note
TI
T1
T2
T1R
T2R
Note
TI
TW
TWR TWPRE TWE
T1W T2W T2W T2W
SDCLK (output)
DMARQx (input)
Internal DMA
request signal
DMAAKx (output)
TCx (output)
Address
Address (output)
Row
address
Column address
Address
Column address
BCYST (output)
CSn (output) of
SRAM area
CSn (output) of
SDRAM area
CSn (output) of
other area
SDRAS (output)
SDCAS (output)
RD (output)
WE (output)
LDQM (output)
UDQM (output)
D0 to D15 (I/O)
SDCKE (output)
Data
Data
Data
Data
H
Note This idle state (TI) is independent of the BCC register setting.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, x = 0 to 3
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Data
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DMA FUNCTIONS (DMA CONTROLLER)
Figure 6-12. Timing of 2-Cycle DMA Transfer (SDRAM → SRAM) (1/3)
(a) Single transfer mode
TI
T1
T2
T1
T2
TW TACT TREAD TLATE TLATE
TI
TI
TI
TO
T1R
T2R
T2R
T2R T2R
Note
TI
T1
T2
T1W T2W
T1
TW
T2
T1
TW
T2
TW TREAD TLATE TLATE
TI
TI
TI
TI
TI
TO
T1W T2W T2W T2W
Note
T1
T2
TI
T1R
T2R
SDCLK (output)
DMARQx (input)
Internal DMA
request signal
DMAAKx (output)
TCx (output)
Row
address
Address (output)
Column address
Column address
Address
Address
BCYST (output)
CSn (output) of
SRAM area
CSn (output) of
SDRAM area
CSn (output) of
other area
SDRAS (output)
SDCAS (output)
RD (output)
WE (output)
LDQM/LWR (output)
UDQM/UWR (output)
D0 to D15 (I/O)
SDCKE (output)
Data
Data
Data
Data
Data
Data
Data
Data
H
Note This idle state (TI) is independent of the BCC register setting.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, x = 0 to 3
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DMA FUNCTIONS (DMA CONTROLLER)
Figure 6-12. Timing of 2-Cycle DMA Transfer (SDRAM → SRAM) (2/3)
(b) Single-step transfer mode
TI
T1
T2
T1
T2
TW TACT TREAD TLATE TLATE
TI
TI
TI
TO
T1R
T2R
T2R
T2R T2R
Note
TI
T1
T2
T1W T2W
T1
T2
T1
T2
TI
TI
TI
TI
TW TREAD TLATE TLATE
T1W T2W T2W T2W
Note
TI
T1
T2
T1R
T2R
SDCLK (output)
DMARQx (input)
Internal DMA
request signal
DMAAKx (output)
TCx (output)
Row
address
Address (output)
Column address
Column address
Address
Address
BCYST (output)
CSn (output) of
SRAM area
CSn (output) of
SDRAM area
CSn (output) of
other area
SDRAS (output)
SDCAS (output)
RD (outpur)
WE (output)
LDQM/LWR (output)
UDQM/UWR (output)
D0 to D15 (I/O)
SDCKE (output)
Data
Data
Data
Data
H
Note This idle state (TI) is independent of the BCC register setting.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, x = 0 to 3
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Data
Data
Data
Data
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DMA FUNCTIONS (DMA CONTROLLER)
Figure 6-12. Timing of 2-Cycle DMA Transfer (SDRAM → SRAM) (3/3)
(c) Block transfer mode
TI
T1
T2
T1
T2
TW TACT TREAD TLATE TLATE
TI
TI
TI
TO
T1R
T2R
T2R
T2R T2R
T1
Note
TI
T2
T1W T2W
Note
TI
TW TREAD TLATE TLATE
T1W T2W T2W T2W
Note
T1
T2
TI
T1R
T2R
SDCLK (output)
DMARQx (input)
Internal DMA
request signal
DMAAKx (output)
TCx (output)
Row
address
Address (output)
Column address
Address
Column address
Address
BCYST (output)
CSn (output) of
SRAM area
CSn (output) of
SDRAM area
CSn (output) of
other area
SDRAS (output)
SDCAS (output)
RD (output)
WE (output)
LDQM/LWR (output)
UDQM/UWR (output)
D0 to D15 (I/O)
SDCKE (output)
Data
Data
Data
Data
Data
Data
H
Note This idle state (TI) is independent of the BCC register setting.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, x = 0 to 3
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6.6.2 Flyby transfer
Since data is transferred in 1 cycle during a flyby transfer, a memory address is always output irrespective whether
it is a source address or a destination address, and read/write signals of the memory and peripheral I/O become
active at the same time. Therefore, the external I/O is selected by the DMAAK0 to DMAAK3 signals.
To perform a normal access to the external I/O by means other than DMA transfer, externally AND the CSm and
DMAAKx signals (m = 0 to 7, x = 0 to 3), and connect the resultant signal to the chip select signal of the external I/O.
A circuit example of a normal access, other than DMA transfer, to external I/O is shown below.
Figure 6-13. Circuit Example When Flyby Transfer Is Performed Between External I/O and SRAM
Ax to Axx
Ax to Axx
D0 to D15
D0 to D7
RD
OE
LWR
WE
CSn
CSn
SRAM
Ax to Axx
D8 to D15
OE
UWR
WE
CSn
SRAM
D0 to D15
IORD
RD
IOWR
WR
DMAAKx
CS
CSm
V850E/MA1
Remark
External I/O
n = 0 to 7, m = 0 to 7 (n ≠ m)
x = 0 to 3
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DMA FUNCTIONS (DMA CONTROLLER)
Figure 6-14. Timing of Flyby Transfer (DRAM → External I/O) (1/3)
(a) Block transfer mode
TI
TI
TI
TI
TO
Note
T2
TRPW T1
T1FH T2FH T1FH
TF
TE
TB
TW
T1FH T1FH
TF
TE
CLKOUT (output)
DMARQx (input)
Internal DMA
request signal
DMAAKx (output)
TCx (output)
Row
address
A0 to A25 (output)
Column address
D0 to D15 (I/O)
Data
Column address
Data
RASm (output) of
DRAM area
CSn (output) of
external I/O area
H
BCYST (output)
RD (output)
H
OE (output)
WE (output)
H
UWR/UCAS (output)
LWR/LCAS (output)
IORD (output)
H
IOWR (output)
WAIT (input)
Note TRPW is always inserted for one or more cycles.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3 (n ≠ m)
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Figure 6-14. Timing of Flyby Transfer (DRAM → External I/O) (2/3)
(b) Single transfer mode
Note
TI
TI
TI
TI
Note
TRPW T1 T2
TO T1FH T2FH T1FH TF
TE
TI
TI
TI
TI
TI
TI
TRPW T1 T2
TO T1FH T2FH T2FH TF
TE
CLKOUT (output)
DMARQx (input)
Internal DMA
request signal
DMAAKx (output)
TCx (output)
Row
address
A0 to A25 (output)
Column address
Data
D0 to D15 (I/O)
RASm (output) of
DRAM area
CSn (output) of
external I/O area
BCYST (output)
RD (output)
OE (output)
WE (output)
UWR/UCAS (output)
LWR/LCAS (output)
IORD (output)
IOWR (output)
WAIT (input)
Note TRPW is always inserted for one or more cycles.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3 (n ≠ m)
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Row
address
Column address
Data
CHAPTER 6
DMA FUNCTIONS (DMA CONTROLLER)
Figure 6-14. Timing of Flyby Transfer (DRAM → External I/O) (3/3)
(c) Single-step transfer mode
Note
TI
TI
TI
TI
TRPW T1 T2
TO T1FH T2FH T1FH TF
TE
TI
TI
TI
TB
TO T1FH TF
TE
TI
TI
CLKOUT (output)
DMARQx (input)
Internal DMA
request signal
DMAAKx (output)
TCx (output)
A0 to A25 (output)
Row
address
Column address
Data
D0 to D15 (I/O)
Column address
Data
RASm (output) of
DRAM area
CSn (output) of
external I/O area
BCYST (output)
RD (output)
OE (output)
WE (output)
UWR/UCAS (output)
LWR/LCAS (output)
IORD (output)
IOWR (output)
WAIT (input)
Note TRPW is always inserted for one or more cycles.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3 (n ≠ m)
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Figure 6-15. Timing of Access to SRAM, External ROM, and External I/O During DMA Flyby Transfer (1/2)
(a) SRAM → external I/O
When TASW and TI are inserted
TASW
T1
T2
TF
TI
T1
TW
T2
CLKOUT (output)
A0 to A25 (output)
Address
Address
BCYST (output)
CSn/RASm (output)
RD (output)
OE (output)
WE (output)
UWR/UCAS/UDQM (output)
LWR/LCAS/LDQM (output)
IORD (output)
IOWR (output)
LBE (output)
UBE (output)
Data
D0 to D15 (I/O)
WAIT (input)
DMAAKx (output)
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3
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TF
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Figure 6-15. Timing of Access to SRAM, External ROM, and External I/O During DMA Flyby Transfer (2/2)
(b) External I/O → SRAM
When TASW is inserted
TASW
T2
T1
TF
T1
TW
T2
TF
CLKOUT (output)
A0 to A25 (output)
Address
Address
BCYST (output)
CSn/RASm (output)
RD (output)
OE (output)
WE (output)
UWR/UCAS/UDQM (output)
LWR/LCAS/LDQM (output)
IORD (output)
Note
IOWR (output)
LBE (output)
UBE (output)
Data
D0 to D15 (I/O)
Data
WAIT (input)
DMAAKx (output)
Note During DMA flyby transfer, the rise timing of this read cycle is different from that of other transfer
operations.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3
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Figure 6-16. Page ROM Access Timing During DMA Flyby Transfer
(a) Page ROM → external I/O
When TI is inserted
T1
T2
TF
TI
T1
TW
T2
CLKOUT (output)
Address
A0 to A25 (output)
Address
BCYST (output)
CSn/RASm (output)
RD (output)
OE (output)
H
WE (output)
H
UWR/UCAS (output)
H
LWR/LCAS (output)
H
IORD (output)
H
IOWR (output)
D0 to D15 (I/O)
Data
WAIT (input)
DMAAKx (output)
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3.
248
n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3
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TF
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DMA FUNCTIONS (DMA CONTROLLER)
Figure 6-17. DRAM Access Timing During DMA Flyby Transfer (1/4)
(a) DRAM → external I/O (when no wait is inserted)
TRPWNote 1
T1
T2
TF
TE
TB
TF
TE
CLKOUT (output)
A0 to A25 (output)
Row address
Column address
Column address
BCYST (output)
Note 3
CSn/RASm (output)
RD (output)
OE (output)
WE (output)
UWR/UCAS (output)
Note 4
Note 4
Note 4
Note 4
LWR/LCAS (output)
IORDNote 2 (output)
IOWR (output)
Data
D0 to D15 (I/O)
Data
WAIT (input)
DMAAKx (output)
Notes 1.
2.
TRPW is always inserted for 1 or more cycles.
During DMA flyby transfer, the rise timing of this read cycle is different from that of other transfer
operations.
3. When a bus cycle accessing another CS space or a write cycle accessing the same CS space
follows this cycle.
4. The rise timing of this write cycle is different from that of a normal EDO DRAM write cycle.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3
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Figure 6-17. DRAM Access Timing During DMA Flyby Transfer (2/4)
(b) DRAM → External I/O (when TRHW and TW are inserted)
TRPW
Note 1
T1
TRHW
T2
TW
T3
TE
TCPW
Note 1
TO1
TW
TO2
TE
CLKOUT (output)
A0 to A25 (output)
Row address
Column address
Column address
BCYST (output)
Note 3
CSn/RASm (output)
RD (output)
OE (output)
WE (output)
UWR/UCAS (output)
Note 4
Note 4
Note 4
Note 4
LWR/LCAS (output)
IORDNote 2 (output)
IOWR (output)
Data
D0 to D15 (I/O)
Data
WAIT (input)
DMAAKx (output)
Notes 1.
2.
TRPW and TCPW are always inserted for 1 or more cycles.
During DMA flyby transfer, the rise timing of this read cycle is different from that of other transfer
operations.
3.
When a bus cycle accessing another CS space or a write cycle accessing the same CS space
follows this cycle.
4.
The rise timing of this write cycle is different from that of a normal EDO DRAM write cycle.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3
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Figure 6-17. DRAM Access Timing During DMA Flyby Transfer (3/4)
(c) External I/O → DRAM (when no waits are inserted)
TRPWNote 1
T1
T2
TE
TCPWNote 1
TB
TE
CLKOUT (output)
A0 to A25 (output)
Row address
Column address
Column address
BCYST (output)
Note 3
CSn/RASm (output)
RD (output)
OE (output)
WE (output)
UWR/UCAS (output)
Note 4
Note 4
Note 4
Note 4
LWR/LCAS (output)
IORDNote 2 (output)
IOWR (output)
D0 to D15 (I/O)
Data
Data
WAIT (input)
DMAAKx (output)
Notes 1.
2.
TRPW and TCPW are always inserted for 1 or more cycles.
During DMA flyby transfer, the rise timing of this read cycle is different from that of other transfer
operations.
3.
When a bus cycle accessing another CS space or a write cycle accessing the same CS space
follows this cycle.
4.
The rise timing of this write cycle is different from that of a normal EDO DRAM write cycle.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3
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Figure 6-17. DRAM Access Timing During DMA Flyby Transfer (4/4)
(d) External I/O → DRAM (when TRHW and TW are inserted)
TRPWNote 1
T1
TRHW
T2
TE
TW
TCPWNote 1
TB
TW
TE
CLKOUT (output)
A0 to A25 (output)
Row address
Column address
Column address
BCYST (output)
Note 3
CSn/RASm (output)
RD (output)
OE (output)
WE (output)
UWR/UCAS (output)
Note 4
Note 4
Note 4
Note 4
LWR/LCAS (output)
IORDNote 2 (output)
IOWR (output)
D0 to D15 (I/O)
Data
Data
WAIT (input)
DMAAKx (output)
Notes 1.
2.
TRPW and TCPW are always inserted for 1 or more cycles.
During DMA flyby transfer, the rise timing of this read cycle is different from that of other transfer
operations.
3.
When a bus cycle accessing another CS space or a write cycle accessing the same CS space
follows this cycle.
4.
The rise timing of this write cycle is different from that of a normal EDO DRAM write cycle.
Remarks 1. The circle { indicates the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7, m = 1, 3, 4, 6, x = 0 to 3
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6.7
DMA FUNCTIONS (DMA CONTROLLER)
Transfer Object
6.7.1 Transfer type and transfer object
Table 6-1 lists the relationships between transfer type and transfer object. The mark “√” means “transfer possible”,
and the mark “−” means “transfer impossible”.
Table 6-1. Relationship Between Transfer Type and Transfer Object
Destination
2-Cycle Transfer
Internal
ROM
On-chip
Peripheral
External
I/O
Flyby Transfer
Internal
RAM
External
Memory
Internal
ROM
On-chip
Peripheral
I/O
External
I/O
Internal
RAM
External
Memory
I/O
−
√
√
√
√
−
−
−
−
−
External I/O
−
√
√
√
√
−
−
−
−
√Note
Internal RAM
−
√
√
−
√
−
−
−
−
−
Note
−
−
−
−
−
On-chip
Source
peripheral I/O
External
memory
−
√
√
√
√
−
−
Internal ROM
−
−
−
−
×
−
−
Note
√
In the case of flyby transfer, data cannot be transferred to/from SDRAM.
Cautions 1. The operation is not guaranteed for combinations of transfer destination and source marked
with “−
−” in Table 6-1.
2.
In the case of flyby transfer, make the data bus width the same for the source and
destination.
3.
Addresses between 3FFF000H and 3FFFFFFH cannot be specified for the source and
destination address of DMA transfer. Be sure to specify an address between FFFF000H and
FFFFFFFH.
Remarks 1. During 2-cycle DMA transfer, if the data bus width of the transfer source and that of the transfer
destination are different, the operation becomes as follows.
<16-bit transfer>
• Transfer from a 16-bit bus to an 8-bit bus
A read cycle (16 bits) is generated and then a write cycle (8 bits) is generated twice consecutively.
• Transfer from an 8-bit bus to a 16-bit bus
A read cycle (8 bits) is generated twice consecutively and then a write cycle (16 bits) is generated.
<8-bit transfer>
• Transfer from 16-bit bus to 8-bit bus
A read cycle (the higher 8 bits go into a high-impedance state) is generated and then a write cycle
(8 bits) is generated.
• Transfer from 8-bit bus to 16-bit bus
A read cycle (8 bits) is generated and then a write cycle is generated (the higher 8 bits go into a
high-impedance state). Data is written in the order from lower bits to higher bits to the transfer
destination in the case of little endian and in reverse order in the case of big endian.
2. Transfer between the little endian area and the big endian area is possible.
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6.7.2 External bus cycles during DMA transfer
The external bus cycles during DMA transfer are shown below.
Table 6-2. External Bus Cycles During DMA Transfer
Transfer Type
Transfer Object
2-cycle transfer
On-chip peripheral I/O, internal RAM
Flyby transfer
External Bus Cycle
Note
None
–
External I/O
Yes
SRAM cycle
External memory
Yes
Memory access cycle set by the BCT register
Between external memory and
external I/O
Yes
DMA flyby transfer cycle accessing memory that is
set as external memory by the BCT register
Note Other external cycles, such as a CPU-based bus cycle can be started.
6.8
DMA Channel Priorities
The DMA channel priorities are fixed as follows.
DMA channel 0 > DMA channel 1 > DMA channel 2 > DMA channel 3
These priorities are valid in the TI state only. In the block transfer mode, the channel used for transfer is never
switched.
In the single-step transfer mode, if a higher priority DMA transfer request is issued while the bus is released (in the
TI state), the higher priority DMA transfer request is acknowledged.
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6.9
DMA FUNCTIONS (DMA CONTROLLER)
Next Address Setting Function
The DMA source address registers (DSAnH, DSAnL), DMA destination address registers (DDAnH, DDAnL), and
DMA transfer count register (DBCn) are buffer registers with a 2-stage FIFO configuration (n = 0 to 3).
When the terminal count is issued, these registers are automatically rewritten with the value that was set immediately
before.
Therefore, during DMA transfer, transfer is automatically started when a new DMA transfer setting is made for
these registers and the MLEn bit of the DCHCn register is set to 1 (however, the DMA transfer end interrupt may be
issued even if DMA transfer is automatically started).
Figure 6-14 shows the configuration of the buffer register.
Figure 6-18. Buffer Register Configuration
Internal bus
Data read
Data write
Master
register
Slave
register
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count
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6.10 DMA Transfer Start Factors
There are 3 types of DMA transfer start factors, as shown below.
(1) Request from an external pin (DMARQn)
Requests from the DMARQn pin are sampled each time the CLKOUT signal rises (n = 0 to 3).
Hold the request from DMARQn pin until the corresponding DMAAKn signal becomes active.
If a state whereby the Enn bit of the DCHCn register = 1 and the TCn bit = 0 is set, the DMARQn signal in the
TI state becomes valid. If the DMARQn signal becomes active in the TI state, it changes to the T0 state and
DMA transfer is started.
(2) Request from software
If the STGn, Enn, and TCn bits of the DCHCn register are set as follows, DMA transfer starts (n = 0 to 3).
• STGn bit = 1
• Enn bit = 1
• TCn bit = 0
(3) Request from on-chip peripheral I/O
If, when the Enn and TCn bits of the DCHCn register are set as shown below, an interrupt request is issued
from the on-chip peripheral I/O that is set in the DTFRn register, DMA transfer starts (n = 0 to 3).
• Enn bit = 1
• TCn bit = 0
Remark
Since the DMARQn signal is level-sampled and not edge-detected, to enable edge detection of a DMA
request, set an external interrupt request for the DMA start trigger instead of using the DMARQn signal
(n = 0 to 3).
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6.11 Terminal Count Output upon DMA Transfer End
The terminal count signal (TCn) becomes active for one clock during the last DMA transfer cycle (n = 3 to 0).
The TCn signal becomes active in the clock following the clock in which the BCYST signal becomes active during
the last DMA transfer cycle. In 2-cycle transfer, the TCn signal becomes active in the write cycle of the last DMA
transfer.
Figure 6-19. Terminal Count Signal (TCn) Timing Example
DMARQn (input)
TCn (output)
CPU CPU
CPU DMAn DMAn DMAn CPU
DMA channel n terminal count
Remark
n = 0 to 3
6.12 Forcible Interruption
DMA transfer can be forcibly interrupted by NMI input during DMA transfer.
At such a time, the DMAC resets the Enn bit of the DCHCn register of all channels to 0 and the DMA transfer
disabled state is entered. An NMI request can then be acknowledged after the DMA transfer that was being executed
when the NMI was input is complete (n = 0 to 3).
In the single-step transfer mode or block transfer mode, the DMA transfer request is held in the DMAC. If the Enn
bit is set to 1, DMA transfer restarts from the point where it was interrupted.
In the single transfer mode, if the Enn bit is set to 1, the next DMA transfer request is received and DMA transfer
starts.
Figure 6-20. Example of Forcible Interrupt of DMA Transfer
NMI (input)
Forcible
interruption
DMA transfer DMA transfer stop
DDIS register
Transfer
restart
DMA transfer
Forcible
interruption
DMA transfer stop
01H
DRST register
01H
E00 bit of DCHC register
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6.13 Forcible Termination
DMA transfer can be forcibly terminated by the INITn bit of the DCHCn register, in addition to the forcible
interruption operation by means of NMI input (n = 0 to 3).
An example of forcible termination by the INITn bit of the DCHCn register is illustrated below (n = 0 to 3).
Figure 6-21. Example of Forcible Termination of DMA Transfer
(a) Block transfer through DMA channel 3 is started during block transfer through DMA channel 2
DSA2, DDA2, DBC2,
DADC2, DCHC2
DCHC2
(INIT2 bit = 1)
Register set
Register set
DMARQ2 (input)
E22 bit → 0
TC2 bit = 0
E22 bit = 1
TC2 bit = 0
DSA3, DDA3, DBC3,
DADC3, DCHC3
Register set
DMARQ3 (input)
E33 bit → 0
TC3 bit → 1
E33 bit = 1
TC3 bit = 0
CPU CPU CPU CPU DMA2 DMA2 DMA2 DMA2 DMA2 CPU DMA3 DMA3 DMA3 DMA3 CPU CPU CPU
DMA channel 3 terminal count
DMA channel 3 transfer start
Forcible termination of DMA channel 2 transfer, bus released
(b) When transfer is aborted during DMA channel 1 block transfer, and transfer under another condition
is executed
DSA1, DDA1, DBC1,
DADC1, DCHC1
Register set
DSA1, DDA1,
DBC1
DCHC1
(INIT1 bit = 1)
Register set
DADC1,
DCHC1
Register set
Register set
DMARQ1 (input)
E11 bit → 0
TC1 bit = 0
E11 bit = 1
TC1 bit = 0
E11 bit → 1
TC1 bit = 0
E11 bit → 0
TC1 bit → 1
CPU CPU CPU CPU DMA1 DMA1 DMA1 DMA1 DMA1 DMA1 CPU CPU CPU CPU DMA1 DMA1 DMA1 CPU
Forcible termination of DMA channel
1 transfer, bus released
Remark
During DMA transfer, the next condition can be set because the DSAn, DDAn, and DBCn registers
are buffer registers.
However, the setting to the DADCn register is invalid (refer to 6.9
Address Setting Function and 6.3.4
Next
DMA addressing control registers 0 to 3 (DADC to
DADC3 ).
258
DMA channel 1
terminal count
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6.14 Times Related to DMA Transfer
The overhead before and after DMA transfer and minimum execution clock for DMA transfer are shown below. In
the case of external memory access, the time depends on the type of external memory connected.
Table 6-3. Number of Minimum Execution Clocks in DMA Cycle
DMA Cycle
Number of Minimum Execution Clocks
From DMARQn signal acknowledgement to DMAAKn signal
rising
4 clocks
External memory access
Depends on the memory connected.
Internal RAM access
1 clock
Remark
n = 0 to 3
6.15 Maximum Response Time for DMA Transfer Request
The response time for a DMA transfer request becomes the longest under the following conditions (in the DRAM
refresh cycle enabled state). However, the case when a higher priority DMA transfer is generated is excluded.
(1) Condition 1
Condition
Instruction fetch from an external memory in 8-bit data bus width
Response time
Tinst × 4 + Tref
DMARQn (input)
DMAAKn (output)
D0 to D15 (I/O)
Fetch (1/4) Fetch (2/4) Fetch (3/4) Fetch (4/4)
Refresh
DMA cycle
(2) Condition 2
Condition
Word data access with an external memory in 8-bit data bus width
Response time
Tdata × 4 + Tref
DMARQn (input)
DMAAKn (output)
D0 to D15 (I/O)
Data (1/4)
Data (2/4)
Data (3/4)
Data (4/4)
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DMA cycle
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(3) Condition 3
Condition
Instruction fetch from an external memory in 8-bit data bus width
Execution of a bit manipulation instruction (SET1, CLR1, or NOT1)
Response time
Tinst × 4 + Tdata × 2 + Tref
DMARQn (input)
DMAAKn (output)
D0 to D15 (I/O)
Data read Fetch (1/4) Fetch (2/4) Fetch (3/4) Fetch (4/4) Data write
Remarks 1. Tinst:
Refresh
DMA cycle
Number of clocks per bus cycle during instruction fetch
Tdata: Number of clocks per bus cycle during data access
Tref:
Number of clocks per refresh cycle
2. n = 0 to 3
6.16 One-Time Transfer During Single Transfer via DMARQ0 to DMARQ3 Signals
To perform transfer only one time when single transfer is executed for an external memory via the DMARQn signal,
the DMARQn signal must be made inactive within 3 clocks from when the DMAAKn signal becomes inactive (n = 0 to
3).
Figure 6-22. Time to Perform Single Transfer One Time
DMA request sampling period
Period without sampling DMA request
CLKOUT (output)
DMARQn (input)
DMAAKn (output)
DMA transfer cycle
Remarks 1. The circle { indicates the sampling timing.
2. n = 0 to 3
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In the single transfer mode, the next
DMA transfer does not start if the DMARQn
signal rises within three clocks.
CHAPTER 6
DMA FUNCTIONS (DMA CONTROLLER)
6.17 Cautions
(1) Memory boundary
The transfer operation is not guaranteed if the source or the destination address exceeds the area of DMA
objects (external memory, internal RAM, or peripheral I/O) during DMA transfer.
(2) Transfer of misaligned data
DMA transfer of 16-bit bus width misaligned data is not supported. If the source or the destination address is
set to an odd address, the LSB of the address is forcibly handled as "0".
(3) Bus arbitration for CPU
When an external device is targeted for DMA transfer, the CPU can access the internal ROM and internal
RAM (if they are not subject to DMA transfer).
When DMA transfer is executed between the on-chip peripheral I/O and internal RAM, the CPU can access
the internal ROM.
(4) DMAAKn signal output
When the transfer object is internal RAM, the DMAAKn signal is not output during a DMA cycle for internal
RAM (for example, if 2-cycle transfer is performed from internal RAM to an external memory, the DMAAKn
signal is output only during a DMA write cycle for the external memory).
6.17.1 Interrupt factors
DMA transfer is interrupted if the following factors are issued.
• Bus hold
• Refresh cycle
If the factor that is interrupting DMA transfer disappears, DMA transfer promptly restarts.
6.18 DMA Transfer End
When DMA transfer ends and the TCn bit of the DCHCn register is set to 1, a DMA transfer end interrupt
(INTDMAn) is issued to the interrupt controller (INTC) (n = 0 to 3).
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CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION
The V850E/MA1 is provided with a dedicated interrupt controller (INTC) for interrupt servicing and can process a
total of 50 interrupt requests.
An interrupt is an event that occurs independently of program execution, and an exception is an event whose
occurrence is dependent on program execution. Generally, an exception takes precedence over an interrupt.
The V850E/MA1 can process interrupt requests from the on-chip peripheral hardware and external sources.
Moreover, exception processing can be started by the TRAP instruction (software exception) or by generation of an
exception event (i.e. fetching of an illegal opcode) (exception trap).
7.1
Features
{ Interrupts
• Non-maskable interrupts: 1 source
• Maskable interrupts: 49 sources
• 8 levels of programmable priorities (maskable interrupts)
• Multiple interrupt control according to priority
• Masks can be specified for each maskable interrupt request.
• Noise elimination, edge detection, and valid edge specification for external interrupt request signals.
{ Exceptions
• Software exceptions: 32 sources
• Exception traps: 2 sources (illegal opcode exception and debug trap)
Interrupt/exception sources are listed in Table 7-1.
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Table 7-1. Interrupt/Exception Source List (1/2)
Type
Classification
Interrupt/Exception Source
Name
Controlling
Generating Source
Default Exception
Generating Priority
Register
Reset
Interrupt
RESET
Non-maskable
Interrupt
NMI0
Software
Exception
TRAP0n
exception
Exception
Exception trap
Exception
Handler
Restored PC
Address
Unit
−
Reset input
−
−
0000H
00000000H Undefined
−
NMI input
−
−
0010H
Note
−
TRAP instruction
−
−
004nH
Note
00000040H nextPC
TRAP1n
Note
−
TRAP instruction
−
−
005nH
Note
00000050H nextPC
ILGOP/
−
Illegal opcode/
−
−
0060H
00000060H nextPC
00000080H nextPC
DBG0
Maskable
Code
00000010H nextPC
DBTRAP instruction
Interrupt
INTOV00
OVIC00
Timer 00 overflow
RPU
0
0080H
Interrupt
INTOV01
OVIC01
Timer 01 overflow
RPU
1
0090H
00000090H nextPC
Interrupt
INTOV02
OVIC02
Timer 02 overflow
RPU
2
00A0H
000000A0H nextPC
Interrupt
INTOV03
OVIC03
Timer 03 overflow
RPU
3
00B0H
000000B0H nextPC
Interrupt
INTP000/
P00IC0
Match of
Pin/RPU
4
00C0H
000000C0H nextPC
Pin/RPU
5
00D0H
000000D0H nextPC
Pin/RPU
6
00E0H
000000E0H nextPC
Pin/RPU
7
00F0H
000000F0H nextPC
Pin/RPU
8
0100H
00000100H nextPC
Pin/RPU
9
0110H
00000110H nextPC
Pin/RPU
10
0120H
00000120H nextPC
Pin/RPU
11
0130H
00000130H nextPC
INTM000
Interrupt
INTP001/
INTP000 pin/CCC00
P00IC1
INTM001
Interrupt
INTP010/
INTP001 pin/CCC01
P01IC0
INTM010
Interrupt
INTP011/
INTP020/
P01IC1
INTP021/
P02IC0
INTP030/
P02IC1
INTP031/
Match of
INTP021 pin/CCC21
P03IC0
INTM030
Interrupt
Match of
INTP020 pin/CCC20
INTM021
Interrupt
Match of
INTP011 pin/CCC11
INTM020
Interrupt
Match of
INTP010 pin/CCC10
INTM011
Interrupt
Match of
Match of
INTP030 pin/CCC30
P03IC1
INTM031
Match of
INTP031 pin/CCC31
Interrupt
INTP100
P10IC0
INTP100 pin
Pin
12
0140H
00000140H nextPC
Interrupt
INTP101
P10IC1
INTP101 pin
Pin
13
0150H
00000150H nextPC
Interrupt
INTP102
P10IC2
INTP102 pin
Pin
14
0160H
00000160H nextPC
Interrupt
INTP103
P10IC3
INTP103 pin
Pin
15
0170H
00000170H nextPC
Interrupt
INTP110
P11IC0
INTP110 pin
Pin
16
0180H
00000180H nextPC
Interrupt
INTP111
P11IC1
INTP111 pin
Pin
17
0190H
00000190H nextPC
Interrupt
INTP112
P11IC2
INTP112 pin
Pin
18
01A0H
000001A0H nextPC
Interrupt
INTP113
P11IC3
INTP113 pin
Pin
19
01B0H
000001B0H nextPC
Interrupt
INTP120
P12IC0
INTP120 pin
Pin
20
01C0H
000001C0H nextPC
Interrupt
INTP121
P12IC1
INTP121 pin
Pin
21
01D0H
000001D0H nextPC
Interrupt
INTP122
P12IC2
INTP122 pin
Pin
22
01E0H
000001E0H nextPC
Interrupt
INTP123
P12IC3
INTP123 pin
Pin
23
01F0H
000001F0H nextPC
Interrupt
INTP130
P13IC0
INTP130 pin
Pin
24
0200H
00000200H nextPC
Interrupt
INTP131
P13IC1
INTP131 pin
Pin
25
0210H
00000210H nextPC
Interrupt
INTP132
P13IC2
INTP132 pin
Pin
26
0220H
00000220H nextPC
Interrupt
INTP133
P13IC3
INTP133 pin
Pin
27
0230H
00000230H nextPC
Interrupt
INTCMD0
CMICD0
CMD0 match signal
RPU
28
0240H
00000240H nextPC
Interrupt
INTCMD1
CMICD1
CMD1 match signal
RPU
29
0250H
00000250H nextPC
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CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION
Table 7-1. Interrupt/Exception Source List (2/2)
Type
Classification
Interrupt/Exception Source
Name
Controlling
Generating Source
Default Exception
Generating Priority
Register
Maskable
Code
Handler
Restored PC
Address
Unit
Interrupt
INTCMD2
CMICD2
CMD2 match signal
RPU
30
0260H
00000260H nextPC
Interrupt
INTCMD3
CMICD3
CMD3 match signal
RPU
31
0270H
00000270H nextPC
Interrupt
INTDMA0
DMAIC0
End of DMA0 transfer
DMA
32
0280H
00000280H nextPC
Interrupt
INTDMA1
DMAIC1
End of DMA1 transfer
DMA
33
0290H
00000290H nextPC
Interrupt
INTDMA2
DMAIC2
End of DMA2 transfer
DMA
34
02A0H
000002A0H nextPC
Interrupt
INTDMA3
DMAIC3
End of DMA3 transfer
DMA
35
02B0H
000002B0H nextPC
Interrupt
INTCSI0
CSIIC0
CSI0 transmission/
SIO
36
02C0H
000002C0H nextPC
Interrupt
INTSER0
SEIC0
UART0 reception error
SIO
37
02D0H
000002D0H nextPC
Interrupt
INTSR0
SRIC0
UART0 reception
SIO
38
02E0H
000002E0H nextPC
SIO
39
02F0H
000002F0H nextPC
SIO
40
0300H
00000300H nextPC
reception completion
completion
Interrupt
INTST0
STIC0
UART0 transmission
completion
Interrupt
INTCSI1
CSIIC1
CSI1 transmission/
reception completion
Interrupt
INTSER1
SEIC1
UART1 reception error
SIO
41
0310H
00000310H nextPC
Interrupt
INTSR1
SRIC1
UART1 reception
SIO
42
0320H
00000320H nextPC
SIO
43
0330H
00000330H nextPC
SIO
44
0340H
00000340H nextPC
completion
Interrupt
INTST1
STIC1
UART1 transmission
completion
Interrupt
INTCSI2
CSIIC2
CSI2 transmission/
reception completion
Interrupt
INTSER2
SEIC2
UART2 reception error
SIO
45
0350H
00000350H nextPC
Interrupt
INTSR2
SRIC2
UART2 reception
SIO
46
0360H
00000360H nextPC
SIO
47
0370H
00000370H nextPC
ADC
48
0380H
00000380H nextPC
completion
Interrupt
INTST2
STIC2
UART2 transmission
completion
Interrupt
INTAD
ADIC
End of A/D conversion
Note n = 0 to FH
Remarks 1. Default Priority: The priority order when two or more maskable interrupt requests occur at the
same time. The highest priority is 0.
Restored PC:
The value of the PC saved to EIPC or FEPC when interrupt/exception processing
is started.
However, the value of the PC saved when an interrupt is
acknowledged during divide instruction (DIV, DIVH, DIVU, DIVHU) execution is
the value of the PC of the current instruction (DIV, DIVH, DIVU, DIVHU).
nextPC:
The PC value that starts the processing following interrupt/exception processing.
2. The execution address of the illegal instruction when an illegal opcode exception occurs is
calculated by (Restored PC – 4).
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7.2
Non-Maskable Interrupts
A non-maskable interrupt request is acknowledged unconditionally, even when interrupts are in the interrupt
disabled (DI) status. An NMI is not subject to priority control and takes precedence over all the other interrupts.
A non-maskable interrupt request is input from the NMI pin. When the valid edge specified by bit 0 (ESN0) of
external interrupt mode register 0 (INTM0) is detected at the NMI pin, the interrupt occurs.
While the service program of the non-maskable interrupt is being executed (PSW.NP = 1), the acknowledgement
of another non-maskable interrupt request is held pending. The pending NMI is acknowledged after the original
service program of the non-maskable interrupt under execution has been terminated (by the RETI instruction), or
when PSW.NP is cleared to 0 by the LDSR instruction. Note that if two or more NMI requests are input during the
execution of the service program for an NMI, the number of NMIs that will be acknowledged after PSW.NP is cleared
to 0 is only one.
Remark
PSW.NP: The NP bit of the PSW register.
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7.2.1 Operation
If a non-maskable interrupt is generated, the CPU performs the following processing, and transfers control to the
handler routine:
<1> Saves the restored PC to FEPC.
<2> Saves the current PSW to FEPSW.
<3> Writes exception code 0010H to the higher halfword (FECC) of ECR.
<4> Sets the NP and ID bits of the PSW and clears the EP bit.
<5> Sets the handler address (00000010H) corresponding to the non-maskable interrupt to the PC, and
transfers control.
The servicing configuration of a non-maskable interrupt is shown in Figure 7-1.
Figure 7-1. Servicing Configuration of Non-Maskable Interrupt
NMI input
INTC
acknowledged
Non-maskable interrupt request
CPU processing
PSW.NP
1
0
FEPC
FEPSW
ECR.FECC
PSW.NP
PSW.EP
PSW.ID
PC
Restored PC
PSW
0010H
1
0
1
00000010H
Interrupt servicing
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Interrupt request held pending
CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION
Figure 7-2. Acknowledging Non-Maskable Interrupt Request
(a) If a new NMI request is generated while an NMI service program is being executed
Main routine
(PSW.NP = 1)
NMI request
NMI request
NMI request held pending because
PSW.NP = 1
Pending NMI request serviced
(b) If a new NMI request is generated twice while an NMI service program is being executed
Main routine
NMI request
Held pending because NMI service program is being serviced
NMI request
Held pending because NMI service program is being serviced
NMI request
Only one NMI request is acknowledged even though
two NMI requests are generated
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7.2.2 Restore
Execution is restored from the non-maskable interrupt servicing by the RETI instruction.
When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the
address of the restored PC.
<1> Restores the values of the PC and the PSW from FEPC and FEPSW, respectively, because the EP bit of
the PSW is 0 and the NP bit of the PSW is 1.
<2> Transfers control back to the address of the restored PC and PSW.
Figure 7-3 illustrates how the RETI instruction is processed.
Figure 7-3. RETI Instruction Processing
RETI instruction
1
PSW.EP
0
PSW.NP
1
0
PC
PSW
EIPC
EIPSW
PC
PSW
FEPC
FEPSW
Original processing restored
Caution
Remark
268
When the PSW.EP bit and PSW.NP bit are changed by the LDSR instruction during nonmaskable interrupt servicing, in order to restore the PC and PSW correctly during recovery
by the RETI instruction, it is necessary to set PSW.EP back to 0 and PSW.NP back to 1 using
the LDSR instruction immediately before the RETI instruction.
The solid line shows the CPU processing flow.
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7.2.3 Non-maskable interrupt status flag (NP)
The NP flag is a status flag that indicates that non-maskable interrupt (NMI) servicing is under execution.
This flag is set when an NMI interrupt has been acknowledged, and masks all interrupt requests and exceptions to
prohibit multiple interrupts from being acknowledged.
8 7 6 5 4 3 2 1 0
31
PSW
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NP EP ID SAT CY OV S Z
Bit position
7
Bit name
After reset
00000020H
Function
NMI Pending
Indicates whether NMI interrupt servicing is in progress.
0: No NMI interrupt servicing
1: NMI interrupt currently being serviced
NP
7.2.4 Noise elimination
NMI pin noise is eliminated with analog delay. The delay time is 60 to 300 ns. A signal input that changes within
the delay time is not internally acknowledged.
7.2.5 Edge detection function
External interrupt mode register 0 (INTM0) is a register that specifies the valid edge of a non-maskable interrupt
(NMI). The NMI valid edge can be specified to be either the rising edge or the falling edge by the ESN0 bit.
This register can be read/written in 8-bit or 1-bit units.
INTM0
7
6
5
4
3
2
1
<0>
0
0
0
0
0
0
0
ESN0
Bit position
0
Bit name
ESN0
Address
FFFFF880H
After reset
00H
Function
Edge Select NMI
Specifies the NMI pin’s valid edge.
0: Falling edge
1: Rising edge
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CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION
7.3
Maskable Interrupts
Maskable interrupt requests can be masked by interrupt control registers. The V850E/MA1 has 49 maskable
interrupt sources.
If two or more maskable interrupt requests are generated at the same time, they are acknowledged according to
the default priority. In addition to the default priority, eight levels of priorities can be specified by using the interrupt
control registers (programmable priority control).
When an interrupt request has been acknowledged, the acknowledgement of other maskable interrupt requests is
disabled and the interrupt disabled (DI) status is set.
When the EI instruction is executed in an interrupt service routine, the interrupt enabled (EI) status is set, which
enables servicing of interrupts having a higher priority than the interrupt request in progress (specified by the
interrupt control register). Note that only interrupts with a higher priority will have this capability; interrupts with the
same priority level cannot be nested.
However, if multiple interrupts are executed, the following processing is necessary.
<1> Save EIPC and EIPSW in memory or a general-purpose register before executing the EI instruction.
<2> Execute the DI instruction before executing the RETI instruction, then reset EIPC and EIPSW with the values
saved in <1>.
7.3.1 Operation
If a maskable interrupt occurs by INT input, the CPU performs the following processing, and transfers control to a
handler routine:
<1> Saves the restored PC to EIPC.
<2> Saves the current PSW to EIPSW.
<3> Writes an exception code to the lower halfword of ECR (EICC).
<4> Sets the ID bit of the PSW and clears the EP bit.
<5> Sets the handler address corresponding to each interrupt to the PC, and transfers control.
The servicing configuration of a maskable interrupt is shown in Figure 7-4.
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Figure 7-4. Maskable Interrupt Servicing
INT input
INTC accepted
xxIF = 1
No
Yes
xxMK = 0
Yes
Priority higher than
that of interrupt currently
being serviced?
No
Is the interrupt
mask released?
No
Yes
Priority higher
than that of other interrupt
request?
No
Yes
Highest default
priority of interrupt requests
with the same priority?
No
Yes
Maskable interrupt request
Interrupt request held pending
CPU processing
PSW.NP
1
0
PSW.ID
1
0
EIPC
EIPSW
ECR.EICC
PSW.EP
PSW.ID
Corresponding
bit of ISPRNote
PC
Restored PC
PSW
Exception code
0
1
1
Interrupt request held pending
Handler address
Interrupt servicing
Note For the ISPR register, see 7.3.6 In-service priority register (ISPR).
The INT input masked by the interrupt controllers and the INT input that occurs while another interrupt is being
serviced (when PSW.NP = 1 or PSW.ID = 1) are held pending internally by the interrupt controller. In such case, if
the interrupts are unmasked, or when PSW.NP = 0 and PSW.ID = 0 as set by the RETI and LDSR instructions, input
of the pending INT starts the new maskable interrupt servicing.
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7.3.2 Restore
Recovery from maskable interrupt servicing is carried out by the RETI instruction.
When the RETI instruction is executed, the CPU performs the following steps, and transfers control to the address
of the restored PC.
<1> Restores the values of the PC and the PSW from EIPC and EIPSW because the EP bit of the PSW is 0 and
the NP bit of the PSW is 0.
<2> Transfers control to the address of the restored PC and PSW.
Figure 7-5 illustrates the processing of the RETI instruction.
Figure 7-5. RETI Instruction Processing
RETI instruction
1
PSW.EP
0
PSW.NP
1
0
PC
PSW
Corresponding
bit of ISPRNote
EIPC
EIPSW
0
PC
PSW
FEPC
FEPSW
Restores original processing
Note For the ISPR register, see 7.3.6 In-service priority register (ISPR).
Caution
Remark
272
When the PSW.EP bit and the PSW.NP bit are changed by the LDSR instruction during
maskable interrupt servicing, in order to restore the PC and PSW correctly during recovery
by the RETI instruction, it is necessary to set PSW.EP back to 0 and PSW.NP back to 0 using
the LDSR instruction immediately before the RETI instruction.
The solid line shows the CPU processing flow.
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7.3.3 Priorities of maskable interrupts
The V850E/MA1 provides multiple interrupt servicing in which an interrupt is acknowledged while another interrupt
is being serviced. Multiple interrupts can be controlled by priority levels.
There are two types of priority level control: control based on the default priority levels, and control based on the
programmable priority levels that are specified by the interrupt priority level specification bit (xxPRn) of the interrupt
control register (xxICn). When two or more interrupts having the same priority level specified by the xxPRn bit are
generated at the same time, interrupts are serviced in order depending on the priority level allocated to each interrupt
request type (default priority level) beforehand.
For more information, refer to Table 7-1
Interrupt/Exception
Source List. The programmable priority control customizes interrupt requests into eight levels by setting the priority
level specification flag.
Note that when an interrupt request is acknowledged, the ID flag of PSW is automatically set to 1. Therefore,
when multiple interrupts are to be used, clear the ID flag to 0 beforehand (for example, by placing the EI instruction in
the interrupt service program) to set the interrupt enable mode.
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Figure 7-6. Example of Processing in Which Another Interrupt Request Is Issued While an
Interrupt Is Being Serviced (1/2)
Main routine
Servicing of a
EI
Servicing of b
EI
Interrupt
request b
(level 2)
Interrupt request a
(level 3)
Interrupt request b is acknowledged because the
priority of b is higher than that of a and interrupts are
enabled.
Servicing of c
Interrupt request c
(level 3)
Interrupt request d
(level 2)
Although the priority of interrupt request d is higher
than that of c, d is held pending because interrupts
are disabled.
Servicing of d
Servicing of e
EI
Interrupt request e
(level 2)
Interrupt request f
(level 3)
Interrupt request f is held pending even if interrupts are
enabled because its priority is lower than that of e.
Servicing of f
Servicing of g
EI
Interrupt request g
(level 1)
Interrupt request h
(level 1)
Interrupt request h is held pending even if interrupts are
enabled because its priority is the same as that of g.
Servicing of h
Caution To perform multiple interrupt servicing, the values of the EIPC and EIPSW registers must be
saved before executing the EI instruction. When returning from multiple interrupt servicing,
restore the values of EIPC and EIPSW after executing the DI instruction.
Remarks 1. a to u in the figure are the temporary names of interrupt requests shown for the sake of
explanation.
2. The default priority in the figure indicates the relative priority between two interrupt requests.
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Figure 7-6. Example of Processing in Which Another Interrupt Request Is Issued While an
Interrupt Is Being Serviced (2/2)
Main routine
Servicing of i
EI
Interrupt request i
(level 2)
Servicing of k
EI
Interrupt
request j
(level 3)
Interrupt request k
(level 1)
Interrupt request j is held pending because its
priority is lower than that of i.
k that occurs after j is acknowledged because it
has the higher priority.
Servicing of j
Servicing of l
Interrupt request l
(level 2)
Interrupt requests m and n are held pending
because servicing of l is performed in the interrupt
disabled status.
Interrupt
request m
(level 3)
Interrupt request n
(level 1)
Servicing of n
Pending interrupt requests are acknowledged after
servicing of interrupt request l.
At this time, interrupt request n is acknowledged
first even though m has occurred first because the
priority of n is higher than that of m.
Servicing of m
Interrupt request o
(level 3)
Interrupt
request p
(level 2)
Servicing of o
Servicing of p
EI
Servicing of q
EI
Servicing of r
EI
Interrupt
request q
Interrupt
(level 1)
request r
(level 0)
If levels 3 to 0 are acknowledged
Servicing of s
Interrupt request s
(level 1)
Interrupt
request t
(level 2)
Interrupt request u
(level 2)
Note 1
Note 2
Pending interrupt requests t and u are
acknowledged after servicing of s.
Because the priorities of t and u are the same, u is
acknowledged first because it has the higher
default priority, regardless of the order in which the
interrupt requests have been generated.
Servicing of u
Servicing of t
Notes 1.
Lower default priority
2.
Higher default priority
Caution To perform multiple interrupt servicing, the values of the EIPC and EIPSW registers must be
saved before executing the EI instruction. When returning from multiple interrupt servicing,
restore the values of EIPC and EIPSW after executing the DI instruction.
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CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION
Figure 7-7. Example of Servicing Interrupt Requests Simultaneously Generated
Main routine
EI
Interrupt request a (level 2)
Interrupt request b (level 1)
Interrupt request c (level 1)
Default priority
a>b>c
NMI request
Servicing of interrupt request b
Servicing of interrupt request c
.
.
Interrupt request b and c are
acknowledged first according to
their priorities.
Because the priorities of b and c are
the same, b is acknowledged first
according to the default priority.
Servicing of interrupt request a
Caution
To perform multiple interrupt servicing, the values of the EIPC and EIPSW registers must be
saved before executing the EI instruction. When returning from multiple interrupt servicing,
restore the values of EIPC and EIPSW after executing the DI instruction.
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7.3.4 Interrupt control register (xxICn)
An interrupt control register is assigned to each interrupt request (maskable interrupt) and sets the control
conditions for each maskable interrupt request.
This register can be read/written in 8-bit or 1-bit units.
xxICn
<7>
<6>
5
4
3
2
1
0
xxIFn
xxMKn
0
0
0
xxPRn2
xxPRn1
xxPRn0
Bit position
Bit name
Address
FFFFF110H to
FFFF170H
Function
7
xxIFn
Interrupt Request Flag
This is an interrupt request flag.
0: Interrupt request not issued
1: Interrupt request issued
The flag xxlFn is reset automatically by the hardware if an interrupt request is
acknowledged.
6
xxMKn
Mask Flag
This is an interrupt mask flag.
0: Interrupt servicing enabled
1: Interrupt servicing disabled (pending)
xxPRn2 to
xxPRn0
Priority
8 levels of priority order are specified for each interrupt.
2 to 0
After reset
47H
xxPRn2
xxPRn1
xxPRn0
0
0
0
Specifies level 0 (highest).
Interrupt priority specification bit
0
0
1
Specifies level 1.
0
1
0
Specifies level 2.
0
1
1
Specifies level 3.
1
0
0
Specifies level 4.
1
0
1
Specifies level 5.
1
1
0
Specifies level 6.
1
1
1
Specifies level 7 (lowest).
Remark xx: Identification name of each peripheral unit (OV, P00 to P03, P10 to P13, CM, DMA, CSI, SE, SR,
ST, AD)
n: Peripheral unit number (None or 0 to 3).
The addresses and bits of the interrupt control registers are as follows:
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(1/2)
Address
Register
Bit
<7>
<6>
5
4
3
2
1
0
FFFFF110H
OVIC00
OVIF0
OVMK0
0
0
0
OVPR02
OVPR01
OVPR00
FFFFF112H
OVIC01
OVIF1
OVMK1
0
0
0
OVPR12
OVPR11
OVPR10
FFFFF114H
OVIC02
OVIF2
OVMK2
0
0
0
OVPR22
OVPR21
OVPR20
FFFFF116H
OVIC03
OVIF3
OVMK3
0
0
0
OVPR32
OVPR31
OVPR30
FFFFF118H
P00IC0
P00IF0
P00MK0
0
0
0
P00PR02
P00PR01
P00PR00
FFFFF11AH P00IC1
P00IF1
P00MK1
0
0
0
P00PR12
P00PR11
P00PR10
FFFFF11CH P01IC0
P01IF0
P01MK0
0
0
0
P01PR02
P01PR01
P01PR00
FFFFF11EH P01IC1
P01IF1
P01MK1
0
0
0
P01PR12
P01PR11
P01PR10
FFFFF120H
P02IC0
P02IF0
P02MK0
0
0
0
P02PR02
P02PR01
P02PR00
FFFFF122H
P02IC1
P02IF1
P02MK1
0
0
0
P02PR12
P02PR11
P02PR10
FFFFF124H
P03IC0
P03IF0
P03MK0
0
0
0
P03PR02
P03PR01
P03PR00
FFFFF126H
P03IC1
P03IF1
P03MK1
0
0
0
P03PR12
P03PR11
P03PR10
FFFFF128H
P10IC0
P10IF0
P10MK0
0
0
0
P10PR02
P10PR01
P10PR00
FFFFF12AH P10IC1
P10IF1
P10MK1
0
0
0
P10PR12
P10PR11
P10PR10
FFFFF12CH P10IC2
P10IF2
P10MK2
0
0
0
P10PR22
P10PR21
P10PR20
FFFFF12EH P10IC3
P10IF3
P10MK3
0
0
0
P10PR32
P10PR31
P10PR30
FFFFF130H
P11IC0
P11IF0
P11MK0
0
0
0
P11PR02
P11PR01
P11PR00
FFFFF132H
P11IC1
P11IF1
P11MK1
0
0
0
P11PR12
P11PR11
P11PR10
FFFFF134H
P11IC2
P11IF2
P11MK2
0
0
0
P11PR22
P11PR21
P11PR20
FFFFF136H
P11IC3
P11IF3
P11MK3
0
0
0
P11PR32
P11PR31
P11PR30
FFFFF138H
P12IC0
P12IF0
P12MK0
0
0
0
P12PR02
P12PR01
P12PR00
FFFFF13AH P12IC1
P12IF1
P12MK1
0
0
0
P12PR12
P12PR11
P12PR10
FFFFF13CH P12IC2
P12IF2
P12MK2
0
0
0
P12PR22
P12PR21
P12PR20
FFFFF13EH P12IC3
P12IF3
P12MK3
0
0
0
P12PR32
P12PR31
P12PR30
FFFFF140H
P13IC0
P13IF0
P13MK0
0
0
0
P13PR02
P13PR01
P13PR00
FFFFF142H
P13IC1
P13IF1
P13MK1
0
0
0
P13PR12
P13PR11
P13PR10
FFFFF144H
P13IC2
P13IF2
P13MK2
0
0
0
P13PR22
P13PR21
P13PR20
FFFFF146H
P13IC3
P13IF3
P13MK3
0
0
0
P13PR32
P13PR31
P13PR30
FFFFF148H
CMICD0
CMIF0
CMMK0
0
0
0
CMPR02
CMPR01
CMPR00
FFFFF14AH CMICD1
CMIF1
CMMK1
0
0
0
CMPR12
CMPR11
CMPR10
FFFFF14CH CMICD2
CMIF2
CMMK2
0
0
0
CMPR22
CMPR21
CMPR20
FFFFF14EH CMICD3
CMIF3
CMMK3
0
0
0
CMPR32
CMPR31
CMPR30
FFFFF150H
DMAIC0
DMAIF0
DMAMK0
0
0
0
DMAPR02
DMAPR01
DMAPR00
FFFFF152H
DMAIC1
DMAIF1
DMAMK1
0
0
0
DMAPR12
DMAPR11
DMAPR10
FFFFF154H
DMAIC2
DMAIF2
DMAMK2
0
0
0
DMAPR22
DMAPR21
DMAPR20
FFFFF156H
DMAIC3
DMAIF3
DMAMK3
0
0
0
DMAPR32
DMAPR31
DMAPR30
FFFFF158H
CSIIC0
CSIIF0
CSIMK0
0
0
0
CSIPR02
CSIPR01
CSIPR00
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(2/2)
Address
Register
Bit
<7>
<6>
5
4
3
2
1
0
FFFFF15AH SEIC0
SEIF0
SEMK0
0
0
0
SEPR02
SEPR01
SEPR00
FFFFF15CH SRIC0
SRIF0
SRMK0
0
0
0
SRPR02
SRPR01
SRPR00
FFFFF15EH STIC0
STIF0
STMK0
0
0
0
STPR02
STPR01
STPR00
FFFFF160H
CSIIC1
CSIIF1
CSIMK1
0
0
0
CSIPR12
CSIPR11
CSIPR10
FFFFF162H
SEIC1
SEIF1
SEMK1
0
0
0
SEPR12
SEPR11
SEPR10
FFFFF164H
SRIC1
SRIF1
SRMK1
0
0
0
SRPR12
SRPR11
SRPR10
FFFFF166H
STIC1
STIF1
STMK1
0
0
0
STPR12
STPR11
STPR10
FFFFF168H
CSIIC2
CSIIF2
CSIMK2
0
0
0
CSIPR22
CSIPR21
CSIPR20
FFFFF16AH SEIC2
SEIF2
SEMK2
0
0
0
SEPR22
SEPR21
SEPR20
FFFFF16CH SRIC2
SRIF2
SRMK2
0
0
0
SRPR22
SRPR21
SRPR20
FFFFF16EH STIC2
STIF2
STMK2
0
0
0
STPR22
STPR21
STPR20
FFFFF170H
ADIF
ADMK
0
0
0
ADPR2
ADPR1
ADPR0
ADIC
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7.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3)
These registers set the interrupt mask state for the maskable interrupts. The xxMKn bit of the IMR0 to IMR3
registers is equivalent to the xxMKn bit of the xxICn register.
The IMRm register (m = 0 to 3) can be read/written in 16-bit units.
If the higher 8 bits of the IMRm register are used as an IMRmH register and the lower 8 bits as an IMRmL register,
these registers can be read/written in 8-bit or 1-bit units.
Bits 15 to 1 of the IMR3 register (bits 7 to 0 of the IMR3H register and bits 7 to 1 of the IMR3L register) are fixed to
1. If these bits are not 1, the operation cannot be guaranteed.
<15>
IMR0
<14>
<13>
<12>
<11>
<9>
<8>
P10MK3 P10MK2 P10MK1 P10MK0 P03MK1 P03MK0 P02MK1 P02MK0
<7>
<6>
<5>
<4>
<3>
P01MK1 P01MK0 P00MK1 P00MK0 OVMK3
<15>
IMR1
<10>
<14>
CMMK3 CMMK2
<7>
<6>
<13>
<12>
<11>
<2>
<1>
<0>
OVMK2
OVMK1
OVMK0
<10>
<9>
<8>
CMMK1 CMMK0 P13MK3 P13MK2 P13MK1 P13MK0
<5>
<4>
<3>
<2>
<1>
Address
FFFFF100H
After reset
FFFFH
Address
FFFFF102H
After reset
FFFFH
Address
FFFFF104H
After reset
FFFFH
Address
FFFFF106H
After reset
FFFFH
<0>
P12MK3 P12MK2 P12MK1 P12MK0 P11MK3 P11MK2 P11MK1 P11MK0
IMR2
IMR3
<15>
<14>
<13>
<12>
<11>
<10>
<9>
<8>
STMK2
SRMK2
SEMK2
CSIMK2
STMK1
SRMK1
SEMK1
CSIMK1
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
STMK0
SRMK0
SEMK0
15
14
13
12
11
10
9
8
1
1
1
1
1
1
1
1
7
6
5
4
3
2
1
<0>
1
1
1
1
1
1
1
ADMK
Bit position
15 to 0
(IMR0 to 2),
0 (IMR3)
CSIMK0 DMAMK3 DMAMK2 DMAMK1 DMAMK0
Bit name
xxMKn
Function
Mask Flag
Interrupt mask flag
0: Interrupt servicing enabled
1: Interrupt servicing disabled (pending)
Remark xx: Identification name of each peripheral unit (OV, P00 to P03, P10 to P13, CM, DMA, CSI, SE, SR,
ST, and AD).
n: Peripheral unit number (None, or 0 to 3)
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7.3.6 In-service priority register (ISPR)
This register holds the priority level of the maskable interrupt currently acknowledged. When an interrupt request
is acknowledged, the bit of this register corresponding to the priority level of that interrupt request is set to 1 and
remains set while the interrupt is serviced.
When the RETI instruction is executed, the bit corresponding to the interrupt request having the highest priority is
automatically reset to 0 by hardware. However, it is not reset to 0 when execution is returned from non-maskable
interrupt servicing or exception processing.
This register is read-only in 8-bit or 1-bit units.
ISPR
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
ISPR7
ISPR6
ISPR5
ISPR4
ISPR3
ISPR2
ISPR1
ISPR0
Bit position
Bit name
7 to 0
ISPR7 to ISPR0
Remark
Address
FFFFF1FAH
After reset
00H
Function
In-Service Priority Flag
Indicates priority of interrupt currently acknowledged
0: Interrupt request with priority n not acknowledged
1: Interrupt request with priority n acknowledged
n = 0 to 7 (priority level)
7.3.7 Maskable interrupt status flag (ID)
The ID flag is bit 5 of the PSW and controls the maskable interrupt’s operating state, and stores control
information regarding enabling or disabling of interrupt requests.
8 7 6 5 4 3 2 1 0
31
PSW
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NP EP ID SAT CY OV S Z
Bit position
5
Bit name
ID
After reset
00000020H
Function
Interrupt Disable
Indicates whether maskable interrupt servicing is enabled or disabled.
0: Maskable interrupt request acknowledgement enabled
1: Maskable interrupt request acknowledgement disabled (pending)
This bit is set to 1 by the DI instruction and reset to 0 by the EI instruction. Its
value is also modified by the RETI instruction or LDSR instruction when
referencing the PSW.
Non-maskable interrupt requests and exceptions are acknowledged regardless
of this flag. When a maskable interrupt is acknowledged, the ID flag is
automatically set to 1 by hardware.
The interrupt request generated during the acknowledgement disabled period
(ID = 1) is acknowledged when the xxIFn bit of xxICn is set to 1, and the ID flag
is reset to 0.
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7.3.8 Noise elimination
The noise of the INTPn, INTPm, and TI000 to TI030 pins is eliminated with analog delay (n = 000, 001, 010, 011,
020, 021, 030, 031, m = 103 to 100, 113 to 110, 123 to 120, and 133 to 130). The delay time is about 60 to 220 ns.
A signal input that changes within the delay time is not internally acknowledged.
7.3.9 Interrupt trigger mode selection
The valid edge of pins INTP0n0, INTP0n1, INTP1nm, ADTRG, and TI0n0 can be selected by program. Moreover,
a level trigger can be selected for the INTP1nm pin (n = 0 to 3, m = 0 to 3). The edge that can be selected as the
valid edge is one of the following.
• Rising edge
• Falling edge
• Both the rising and falling edges
When the INTP0n0, INTP0n1, INTP1nm, ADTRG, and TI0n0 pins are edge-detected, they become interrupt
sources and capture trigger, A/D trigger, and timer external count inputs (n = 0 to 3, m = 0 to 3).
The valid edge is specified by external interrupt mode registers 1 to 4 (INTM1 to INTM4) and valid edge select
registers (SESC0 to SESC3). The level trigger is specified by external interrupt mode registers 1 to 4 (INTM1 to
INTM4).
(1) External interrupt mode registers 1 to 4 (INTM1 to INTM4)
These registers specify the trigger mode for external interrupt requests (INTP100 to INTP103, INTP110 to
INTP113, INTP120 to INTP122, INTP123/ADTRG, INTP130 to INTP133), input via external pins.
The
correspondence between each register and the external interrupt requests that register controls is shown
below.
• INTM1: INTP100 to INTP103
• INTM2: INTP110 to INTP113
• INTM3: INTP120 to INTP122, INTP123/ADTRG
• INTM4: INTP130 to INTP133
INTP123 is the alternate function pin of the A/D converter external trigger input (ADTRG). Therefore, when
INTP123/ADTRG is set to the external trigger mode by the TRG0 to TRG2 bits of the A/D converter mode
register (ADM), the ES1231 and ES1230 bits specify the valid edge of the external trigger input (ADTRG).
The valid edge can be specified independently for each pin (rising edge, falling edge, or both rising and
falling edges).
These registers can be read/written in 8-bit units.
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INTM1
7
6
5
4
3
2
1
0
ES1031
ES1030
ES1021
ES1020
ES1011
ES1010
ES1001
ES1000
INTP103
INTM2
INTP102
6
5
4
3
2
1
0
ES1131
ES1130
ES1121
ES1120
ES1111
ES1110
ES1101
ES1100
INTP112
INTM4
INTP111
6
5
4
3
2
1
0
ES1231
ES1230
ES1221
ES1220
ES1211
ES1210
ES1201
ES1200
INTP122
INTP121
6
5
4
3
2
1
0
ES1331
ES1330
ES1321
ES1320
ES1311
ES1310
ES1301
ES1300
Bit position
7 to 0
Notes 1.
INTP132
INTP131
Bit name
ES1nm1,
ES1nm0
(n = 0 to 3,
m = 0 to 3)
After reset
00H
Address
FFFFF886H
After reset
00H
Address
FFFFF888H
After reset
00H
INTP120
7
INTP133
Address
FFFFF884H
INTP110
7
INTP123/ADTRG
After reset
00H
INTP100
7
INTP113
INTM3
INTP101
Address
FFFFF882H
INTP130
Function
Edge Select
Specifies the valid edge of the INTP1nm and ADTRG pins.
ES1nm1
ES1nm0
Operation
0
0
Falling edge
0
1
Rising edge
1
0
Level detection (low-level detection)
1
1
Both rising and falling edges
Notes 1, 2, 3
The level of the INTP1nm pin is sampled at the interval of the system clock divided by two, and the
P1nIFm bit is latched as an interrupt request when a low level is detected. Therefore, even if the
P1nIFm bit of the interrupt control register (P1nICm) is automatically cleared to 0 when the CPU
acknowledges an interrupt, the P1nIFm bit is immediately set to 1, and an interrupt is generated
continuously. To avoid this, forcibly clear the P1nIFm bit to 0 after making the INTP1nm pin
inactive for an external device in the interrupt service routine (n = 0 to 3, m = 0 to 3).
2.
When a lower priority level-detection interrupt request (INTP1nm) occurs while another interrupt is
being serviced and this newly generated level-detection interrupt request becomes inactive before
the current interrupt service is complete, this new interrupt request (INTP1nm) is held pending. To
avoid acknowledging this INTP1nm interrupt request, clear the P1nIFm bit of the interrupt control
register (n = 0 to 3, m = 0 to 3).
3.
When this pin is used as the ADTRG pin, do not select this setting (level detection).
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(2) Valid edge select registers C0 to C3 (SESC0 to SESC3)
These registers specify the valid edge for external interrupt requests (INTP000, INTP001, INTP010,
INTP011, INTP020, INTP021, INTP030, INTP031, TI000 to TI030), input via external pins.
The
correspondence between each register and the external interrupt requests that register controls is shown
below.
• SESC0: TI000, INTP000, INTP001
• SESC1: TI010, INTP010, INTP011
• SESC2: TI020, INTP020, INTP021
• SESC3: TI030, INTP030, INTP031
The valid edge can be specified independently for each pin (rising edge, falling edge, or both rising and
falling edges).
These registers can be read/written in 8-bit units.
Caution When using the INTP0n0/TI0n0 or INTP0n1 pin as INTP0n0, INTP0n1, be sure to preset the
TMCCAEn bit of timer mode control register Cn0 (TMCCn0) to 1 (n = 0 to 3).
SESC0
7
6
5
4
TES01
TES00
0
0
3
INTP001
7
6
5
4
TES11
TES10
0
0
3
6
5
4
TES21
TES20
0
0
6
5
4
TES31
TES30
0
0
1
After reset
00H
Address
FFFFF629H
After reset
00H
Address
FFFFF639H
After reset
00H
0
INTP020
2
1
0
INTP031
Bit name
INTP030
Function
Edge Select
Specifies the valid edge of the INTPn and TI000 to TI030 pins.
7, 6
TESn1,
TESn0
(n = 0 to 3)
3, 2
IESn1, IESn0
(n = 001, 011,
021, 031)
xESn1
xESn0
0
0
Falling edge
0
1
Rising edge
IESn1, IESn0
(n = 000, 010,
020, 030)
1
0
RFU (reserved)
1
1
Both rising and falling edges
1, 0
Address
FFFFF619H
0
IES0311 IES0310 IES0301 IES0300
TI030
284
2
3
After reset
00H
INTP010
INTP021
7
Bit position
1
IES0211 IES0210 IES0201 IES0200
TI020
SESC3
2
3
Address
FFFFF609H
INTP000
INTP011
7
0
IES0111 IES0110 IES0101 IES0100
TI010
SESC2
1
IES0011 IES0010 ES0001 IES0000
TI000
SESC1
2
Operation
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CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION
7.4
Software Exception
A software exception is generated when the CPU executes the TRAP instruction, and can always be
acknowledged.
7.4.1 Operation
If a software exception occurs, the CPU performs the following processing, and transfers control to the handler
routine:
<1> Saves the restored PC to EIPC.
<2> Saves the current PSW to EIPSW.
<3> Writes an exception code to the lower 16 bits (EICC) of ECR (interrupt source).
<4> Sets the EP and ID bits of the PSW.
<5> Sets the handler address (00000040H or 00000050H) corresponding to the software exception to the PC,
and transfers control.
Figure 7-8 illustrates the processing of a software exception.
Figure 7-8. Software Exception Processing
TRAP instructionNote
CPU processing
EIPC
EIPSW
ECR.EICC
PSW.EP
PSW.ID
PC
Restored PC
PSW
Exception code
1
1
Handler address
Exception processing
Note TRAP instruction format: TRAP vector (the vector is a value from 0 to 1FH.)
The handler address is determined by the TRAP instruction’s operand (vector). If the vector is 0 to 0FH, it
becomes 00000040H, and if the vector is 10H to 1FH, it becomes 00000050H.
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7.4.2 Restore
Recovery from software exception processing is carried out by the RETI instruction.
By executing the RETI instruction, the CPU carries out the following processing and shifts control to the restored
PC’s address.
<1> Loads the restored PC and PSW from EIPC and EIPSW because the EP bit of the PSW is 1.
<2> Transfers control to the address of the restored PC and PSW.
Figure 7-9 illustrates the processing of the RETI instruction.
Figure 7-9. RETI Instruction Processing
RETI instruction
1
PSW.EP
0
PSW.NP
1
0
PC
PSW
EIPC
EIPSW
PC
PSW
FEPC
FEPSW
Original processing restored
Caution When the PSW.EP bit and the PSW.NP bit are changed by the LDSR instruction during the
software exception processing, in order to restore the PC and PSW correctly during
recovery by the RETI instruction, it is necessary to set PSW.EP back to 1 using the LDSR
instruction immediately before the RETI instruction.
Remark
286
The solid line shows the CPU processing flow.
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7.4.3 Exception status flag (EP)
The EP flag is bit 6 of the PSW, and is a status flag used to indicate that exception processing is in progress. It is
set when an exception occurs.
31
PSW
8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NP EP ID SAT CY OV S Z
Bit Position
6
Bit Name
EP
After reset
00000020H
Function
Exception Pending
Shows that exception processing is in progress.
0: Exception processing not in progress.
1: Exception processing in progress.
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CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION
7.5
Exception Trap
An exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. In the
V850E/MA1, an illegal opcode exception (ILGOP: Illegal Opcode Trap) is considered as an exception trap.
7.5.1 Illegal opcode definition
The illegal instruction has an opcode (bits 10 to 5) of 111111B, a sub-opcode (bits 26 to 23) of 0111B to 1111B,
and a sub-opcode (bit 16) of 0B. An exception trap is generated when an instruction applicable to this illegal
instruction is executed.
15
11 10
×××××
5 4
0 31
27 26
××××××××××
1 1 1 1 1 1
23 22
0 1 1 1
to
1 1 1 1
××××××
16
0
× : Arbitrary
Caution
Since it is possible to assign this instruction to an illegal opcode in the future, it is
recommended that it not be used.
(1) Operation
If an exception trap occurs, the CPU performs the following processing, and transfers control to the handler
routine:
<1> Saves the restored PC to DBPC.
<2> Saves the current PSW to DBPSW.
<3> Sets the NP, EP, and ID bits of the PSW.
<4> Sets the handler address (00000060H) corresponding to the exception trap to the PC, and transfers
control.
Figure 7-10 illustrates the processing of the exception trap.
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Figure 7-10. Exception Trap Processing
Exception trap (ILGOP) occurs
CPU processing
DBPC
DBPSW
PSW.NP
PSW.EP
PSW.ID
PC
Restored PC
PSW
1
1
1
00000060H
Exception processing
(2) Restore
Recovery from an exception trap is carried out by the DBRET instruction.
By executing the DBRET
instruction, the CPU carries out the following processing and controls the address of the restored PC.
<1> Loads the restored PC and PSW from DBPC and DBPSW.
<2> Transfers control to the address indicated by the restored PC and PSW.
Figure 7-11 illustrates the restore processing from an exception trap.
Figure 7-11. Restore Processing from Exception Trap
DBRET instruction
PC
PSW
DBPC
DBPSW
Jump to address of restored PC
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CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION
7.5.2 Debug trap
The debug trap is an exception that can be acknowledged every time and is generated by execution of the
DBTRAP instruction.
When the debug trap is generated, the CPU performs the following processing.
(1) Operation
<1> Saves the restored PC to DBPC.
<2> Saves the current PSW to DBPSW.
<3> Sets the NP, EP and ID bits of the PSW.
<4> Sets the handler address (00000060H) corresponding to the debug trap to the PC and transfers control.
Figure 7-12 illustrates the processing of the debug trap.
Figure 7-12. Debug Trap Processing
DBTRAP instruction
CPU processing
DBPC
DBPSW
PSW.NP
PSW.EP
PSW.ID
PC
Restored PC
PSW
1
1
1
00000060H
Exception processing
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CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION
(2) Restore
Recovery from a debug trap is carried out by the DBRET instruction. By executing the DBRET instruction,
the CPU carries out the following processing and controls the address of the restored PC.
<1> Loads the restored PC and PSW from DBPC and DBPSW.
<2> Transfers control to the address indicated by the restored PC and PSW.
Figure 7-13 illustrates the restore processing from a debug trap.
Figure 7-13. Restore Processing from Debug Trap
DBRET instruction
PC
PSW
DBPC
DBPSW
Jump to address of restored PC
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CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION
7.6
Multiple Interrupt Servicing Control
Multiple interrupt servicing control is a process by which an interrupt request that is currently being serviced can
be interrupted during servicing if there is an interrupt request with a higher priority level, and the higher priority
interrupt request is acknowledged and serviced first.
If there is an interrupt request with a lower priority level than the interrupt request currently being serviced, that
interrupt request is held pending.
Multiple interrupt servicing control of maskable interrupts is executed when interrupts are enabled (ID = 0). Thus,
to execute multiple interrupts, it is necessary to set the interrupt enabled state (ID = 0) even for an interrupt service
routine.
If maskable interrupts are enabled or a software exception is generated in a maskable interrupt or software
exception service program, it is necessary to save EIPC and EIPSW.
This is accomplished by the following procedure.
(1) Acknowledgement of maskable interrupts in service program
Service program of maskable interrupt or exception
...
...
• EIPC saved to memory or register
• EIPSW saved to memory or register
• EI instruction (interrupt acknowledgement enabled)
...
← Maskable interrupt acknowledgement
...
...
...
• DI instruction (interrupt acknowledgement disabled)
• Saved value restored to EIPSW
• Saved value restored to EIPC
• RETI instruction
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(2) Generation of exception in service program
Service program of maskable interrupt or exception
...
...
• EIPC saved to memory or register
• EIPSW saved to memory or register
...
• TRAP instruction
← Exception such as TRAP instruction acknowledged.
...
• Saved value restored to EIPSW
• Saved value restored to EIPC
• RETI instruction
The priority order for multiple interrupt servicing control has 8 levels, from 0 to 7 for each maskable interrupt
request (0 is the highest priority), but it can be set as desired via software. The priority order is set using the
xxPRn0 to xxPRn2 bits of the interrupt control request register (xxlCn), provided for each maskable interrupt
request. After system reset, an interrupt request is masked by the xxMKn bit and the priority order is set to
level 7 by the xxPRn0 to xxPRn2 bits.
The priority order of maskable interrupts is as follows.
(High)
Level 0 > Level 1 > Level 2 > Level 3 > Level 4 > Level 5 > Level 6 > Level 7
(Low)
Interrupt servicing that has been suspended as a result of multiple servicing control is resumed after the
servicing of the higher priority interrupt has been completed and the RETI instruction has been executed.
A pending interrupt request is acknowledged after the current interrupt servicing has been completed and
the RETI instruction has been executed.
Caution
In a non-maskable interrupt service routine (time until the RETI instruction is executed),
maskable interrupts are suspended and not acknowledged.
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7.7
Interrupt Latency Time
The V850E/MA1 interrupt latency time (from interrupt generation to start of interrupt servicing) is described below.
Figure 7-14. Pipeline Operation at Interrupt Request Acknowledgement (Outline)
4 system clocks
Internal clock
Interrupt request
Instruction 1
IF
ID
EX MEM WB
IF× ID×
Instruction 2
Interrupt acknowledgement operation
INT1 INT2 INT3 INT4
IF
Instruction (start instruction of
interrupt service routine)
ID
EX
INT1 to INT4: Interrupt acknowledgement processing
IF×:
Invalid instruction fetch
ID×:
Invalid instruction decode
Condition
Interrupt latency time (internal system clock)
Internal
interrupt
INTP0nm
INTP1nm
Minimum
4
7+
Analog delay time
4+
Analog delay time
Maximum
10
13 +
Analog delay time
10 +
Analog delay time
Remark
294
External interrupt
The following cases are exceptions.
• In IDLE/software STOP mode
• External bus access
• Two or more interrupt request non-sample
instructions are executed in succession
• Access to interrupt control register
n = 0 to 3, m = 0, 1
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CHAPTER 7 INTERRUPTION/EXCEPTION PROCESSING FUNCTION
7.8
Periods in Which Interrupts Are Not Acknowledged
An interrupt is acknowledged while an instruction is being executed. However, no interrupt will be acknowledged
between an interrupt non-sample instruction and the next instruction.
The interrupt request non-sample instructions are as follows.
• EI instruction
• DI instruction
• LDSR reg2, 0x5 instruction (for PSW)
• The store instruction for the following registers.
• Command register (PRCMD)
• Interrupt-related registers:
Interrupt control register (xxICn), interrupt mask registers 0 to 3 (IMR0 to IMR3), in-service priority
register (ISPR)
• CSI-related registers:
Clocked serial interface clock selection registers 0 to 2 (CSIC0 to CSIC2),
clocked serial interface mode registers 0 to 2 (CSIM0 to CSIM2),
serial I/O shift registers 0 to 2 (SIO0 to SIO2),
receive-only serial I/O shift registers 0 to 2 (SIOE0 to SIOE2),
clocked serial interface transmit buffer registers 0 to 2 (SOTB0 to SOTB2)
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CHAPTER 8 PRESCALER UNIT (PRS)
The prescaler divides the internal system clock and supplies the divided clock to internal peripheral units. The
divided clock differs depending on the unit.
For the timer units and A/D converter, a 2-division clock is input.
For other units, the input clock is selected using that unit’s control register.
The CPU operates with the internal system clock.
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CHAPTER 9 CLOCK GENERATION FUNCTION
The clock generator (CG) generates and controls the internal system clock (φ) that is supplied to each internal unit,
such as the CPU.
9.1
Features
• Multiplication function using phase locked loop (PLL) synthesizer
• Clock sources
• Oscillation by connecting a resonator
• External clock
• Power-save control
• HALT mode
• IDLE mode
• Software STOP mode
• Internal system clock output function
9.2
Configuration
X1
(fXX)
X2
Clock
generator
(CG)
CPU, on-chip peripheral I/O
CLKOUT
Time base counter (TBC)
CKSEL
Remark
fXX: External resonator or external clock frequency
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CHAPTER 9 CLOCK GENERATION FUNCTION
9.3
Input Clock Selection
The clock generator consists of an oscillator and a PLL synthesizer. For example, connecting a 5.0 MHz crystal
resonator or ceramic resonator to pins X1 and X2 enables a 50 MHz internal system clock (φ) to be generated when
multiplied by 10.
Also, an external clock can be input directly to the oscillator. In this case, the clock signal should be input only to
the X1 pin (the X2 pin should be left open).
Two basic operation modes are provided for the clock generator. These are PLL mode and direct mode. The
operation mode is selected by the CKSEL pin. The input to this pin is latched on reset.
CKSEL
Operating Mode
0
PLL mode
1
Direct mode
Caution The input level for the CKSEL pin must be fixed. If it is switched during operation, malfunction
may occur.
9.3.1 Direct mode
In direct mode, an external clock with twice the frequency of the internal system clock is input. The maximum
frequency that can be input in direct mode is 50 MHz. The V850E/MA1 is mainly used in application systems in which
it is operated at relatively low frequencies. Taking EMI prevention into consideration, if the external clock frequency
(fXX) is 32 MHz (internal system clock (φ) = 16 MHz) or greater, PLL mode is recommended.
Caution In direct mode, an external clock must be input (an external resonator should not be
connected).
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9.3.2 PLL mode
In PLL mode, an external resonator is connected or an external clock is input and multiplied by the PLL
synthesizer. The multiplied PLL output is divided by the division ratio specified by the clock control register (CKC) to
generate a system clock that is 10, 5, 2.5, or 1 times the frequency of the external resonator or external clock (fXX).
After reset, an internal system clock (φ) that is the same frequency as the internal clock frequency (fXX) (1 × fXX) is
generated.
When a frequency that is 10 times the input clock frequency (fXX) (10 × fXX) is generated, a system with low noise
and low power consumption can be realized because a frequency of up to 50 MHz is obtained based on a 5 MHz
external resonator or external clock.
In PLL mode, if the clock supply from an external resonator or external clock source stops, operation of the internal
system clock (φ) based on the free-running frequency of the clock generator’s internal voltage controlled oscillator
(VCO) continues. However, do not devise an application method expecting to use this free-running frequency.
Example: Clock when PLL mode (φ = 10 × fXX) is used
System Clock Frequency (φ)
External Resonator or External Clock Frequency (fXX)
50.000 MHz
5.0000 MHz
40.000 MHz
4.0000 MHz
Caution When in PLL mode, only an fXX (4 to 5 MHz) value for which 10 × fXX does not exceed the system
clock maximum frequency (50 MHz) can be used for the oscillation frequency or external clock
frequency.
However, if any of 5 × fXX, 2.5 × fXX, or 1 × fXX is used, a frequency of 4 to 6.6 MHz can be used.
If the V850E/MA1 does not need to be operated at high frequency, when PLL mode is selected a
Remark
power consumption can be reduced by lowering the system clock frequency using software (φ = 5 × fXX,
φ = 2.5 × fXX, or φ = 1 × fXX).
9.3.3 Peripheral command register (PHCMD)
This is an 8-bit register that is used to set protection for writing to registers that can significantly affect the system
so that the application system is not halted unexpectedly due to an inadvertent program loop. This register is writeonly in 8-bit units (when it is read, undefined data is read out).
Writing to the first specific register (CKC or FLPMC register) is only valid after first writing to the PHCMD register.
Because of this, the register value can be overwritten only with the specified sequence, preventing an illegal write
operation from being performed.
PHCMD
7
6
5
4
3
2
1
0
REG7
REG6
REG5
REG4
REG3
REG2
REG1
REG0
Bit position
7 to 0
Bit name
REG7 to
REG0
Address
After reset
FFFFF800H Undefined
Function
Registration Code (arbitrary 8-bit data)
The specific registers targeted are as follows.
• Clock control register (CKC)
• Flash programming mode control register (FLPMC)
The generation of an illegal store operation can be checked with the PRERR bit of the peripheral status register
(PHS).
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CHAPTER 9 CLOCK GENERATION FUNCTION
9.3.4 Clock control register (CKC)
The clock control register is an 8-bit register that controls the internal system clock (φ) in PLL mode. It can be
written to only by a specific sequence combination so that it cannot easily be overwritten by mistake due to an
inadvertent program loop.
This register can be read or written in 8-bit units.
Caution Do not change bits CKDIV2 to CKDIV0 in direct mode.
CKC
7
6
5
4
3
2
1
0
0
TBCS
CESEL
0
CKDIV2
CKDIV1
Bit position
5
Bit name
TBCS
0
Address
CKDIV0 FFFFF822H
After reset
00H
Function
Time Base Count Select
Selects the time base counter clock.
8
0: fXX/2
9
1: fXX/2
For details, see 9.6.2 Time base counter (TBC).
4
2 to 0
CESEL
Crystal/External Select
Specifies the functions of the X1 and X2 pins.
0: A resonator is connected to the X1 and X2 pins
1: An external clock is connected to the X1 pin
When CESEL = 1, the oscillator feedback loop is disconnected to prevent current
leak in software STOP mode.
CKDIV2 to
CKDIV0
Clock Divide
Sets the internal system clock frequency (φ) when PLL mode is used.
Internal system clock (φ)
CKDIV2 CKDIV1 CKDIV0
0
0
0
fXX
0
0
1
2.5 × fXX
0
1
1
5 × fXX
1
1
1
10 × fXX
Other than above
Setting prohibited
To change the internal system clock frequency in the middle of an operation, be
sure to set it to fXX first, and then change the frequency as desired.
Example Clock generator settings
Operation
Mode
CKSEL Pin
Direct mode
PLL mode
CKC Register
Input Clock (fXX)
CKDIV2
CKDIV0
CKDIV0
High-level input
0
0
0
16 MHz
8 MHz
Low-level input
0
0
0
5 MHz
5 MHz
0
0
1
5 MHz
12.5 MHz
0
1
1
5 MHz
25 MHz
1
1
1
5 MHz
50 MHz
Setting prohibited
Setting prohibited
Other than above
300
Internal System
Clock (φ)
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CHAPTER 9 CLOCK GENERATION FUNCTION
Set data in the clock control register (CKC) in the following sequence.
<1>
Disable interrupts (set the NP bit of PSW to 1)
<2>
Prepare data in any one of the general-purpose registers to set in the specific register.
<3>
Write data to the peripheral command register (PHCMD)
<4>
Set the clock control register (CKC) (with the following instructions).
• Store instruction (ST/SST instruction)
• Bit manipulation instruction (SET1/CLR1/NOT1 instruction)
<5>
Assert the NOP instructions (5 instructions (<5> to <9>))
<10> Release the interrupt disabled state (set the NP bit of PSW to 0).
[Sample coding]
<1> LDSR
rX, 5
<2> MOV
0X07, r10
<3> ST.B
r10, PHCMD [r0]
<4> ST.B
r10, CKC [r0]
<5> NOP
<6> NOP
<7> NOP
<8> NOP
<9> NOP
<10> LDSR
Remark
rY, 5
rX: Value written to PSW
rY: Value returned to PSW
No special sequence is required to read the specific register.
Cautions 1. If an interrupt is acknowledged between the issuance of data to the PHCMD (<3>) and
writing to the specific register immediately after (<4>), the write operation to the specific
register is not performed and a protection error (the PRERR bit of the PHS register = 1) may
occur. Therefore, set the NP bit of the PSW to 1 (<1>) to disable interrupt acknowledgement.
Also disable interrupt acknowledgement when selecting a bit manipulation instruction for
the specific register setting.
2. Although the data written to the PHCMD register is dummy data, use the same register as
the general-purpose register used in specific register setting (<4>) for writing to the PHCMD
register (<3>). The same method should be applied when using a general-purpose register
for addressing.
3. Be sure to terminate all DMA transfers prior to the execution of the above sequence.
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9.3.5 Peripheral status register (PHS)
If a write operation to the protection-targeted internal registers is not performed in the correct sequence, including
access to the command register, writing is not performed and a protection error is generated, setting the status flag
(PRERR) to 1. This flag is a cumulative flag. After checking the PRERR flag, it is cleared to 0 by an instruction.
This register can be read or written in 8-bit or 1-bit units.
PHS
7
6
5
4
3
2
1
<0>
Address
After reset
0
0
0
0
0
0
0
PRERR
FFFFF802H
00H
Bit position
0
Bit name
PRERR
Function
Protection Error
0: Protection error has not occurred
1: Protection error occurred
The operating conditions of the PRERR flag are as follows.
Set conditions:
<1> If the operation of the relevant store instruction for the peripheral I/O is not a write
operation for the PHCMD register, but the peripheral specific register is written to.
<2> If the first store instruction operation after the write operation to the PHCMD register is for
memory other than the specific registers and peripheral I/O.
Reset conditions: <1> If the PRERR flag of the PHS register is set to 0.
<2> If the system is reset
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9.4
PLL Lockup
The lockup time (frequency stabilization time) is the time from when the power is turned on or software STOP
mode is released until the phase locks at the prescribed frequency. The state until this stabilization occurs is called
the unlocked state, and the stabilized state is called the locked state.
The lock register (LOCKR) has a lock flag that reflects the stabilized state of the PLL frequency.
This register is read-only in 8-bit or 1-bit units.
Caution If the phase is locked, the LOCK flag is cleared to 0. If it is unlocked later because of a standby
status, the LOCK flag is set to 1. If the phase is unlocked by a cause other than the standby
status, however, the LOCK flag is not affected (LOCK = 0).
LOCKR
7
6
5
4
3
2
1
<0>
0
0
0
0
0
0
0
LOCK
Bit position
0
Bit name
LOCK
Address
After reset
FFFFF824H 0000000xB
Function
Lock Status Flag
This is a read-only flag that indicates the PLL lock state. This flag holds the value
0 as long as a lockup state is maintained and is not initialized by a system reset.
0: Indicates that the PLL is locked.
1: Indicates that the PLL is not locked (unlock state).
If the clock stops, the power fails, or some other factor operates to cause an unlock state to occur, for control
processing that depends on software execution speed, such as real-time processing, be sure to judge the LOCK flag
by software immediately after operation begins so that processing does not begin until after the clock stabilizes.
On the other hand, static processing such as the setting of internal hardware or the initialization of register data or
memory data can be executed without waiting for the LOCK flag to be reset.
The relationship between the oscillation stabilization time (the time from when the resonator starts to oscillate until
the input waveform stabilizes) when a resonator is used, and the PLL lockup time (the time until frequency stabilizes)
is shown below.
Oscillation stabilization time < PLL lockup time.
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9.5
Power-Save Control
9.5.1 Overview
The power-save function has the following three modes.
(1) HALT mode
In this mode, the clock generator (oscillator and PLL synthesizer) continues to operate, but the CPU’s
operation clock stops.
Since the supply of clocks to on-chip peripheral functions other than the CPU
continues, operation continues. The power consumption of the overall system can be reduced by intermittent
operation using a combination of the HALT mode and the normal operation mode.
The system is switched to HALT mode by a specific instruction (the HALT instruction).
(2) IDLE mode
In this mode, the clock generator (oscillator and PLL synthesizer) continues to operate, but the supply of
internal system clocks is stopped, which causes the overall system to stop.
When the system is released from IDLE mode, it can be switched to normal operation mode quickly because
the oscillator’s oscillation stabilization time does not need to be secured.
The system is switched to IDLE mode by a PSMR register setting.
IDLE mode is located midway between software STOP mode and HALT mode in relation to the clock
stabilization time and current consumption. It is used for situations in which a low-current-consumption mode
is to be used and the clock stabilization time is to be eliminated after the mode is released.
(3) Software STOP mode
In this mode, the overall system is stopped by stopping the clock generator (oscillator and PLL synthesizer).
The system enters an ultra-low-power-consumption state in which only leakage current is lost.
The system is switched to software STOP mode by a PSMR register setting.
(a) PLL mode
The system is switched to software STOP mode by setting the register using software.
The PLL
synthesizer’s clock output is stopped at the same time the oscillator is stopped. After software STOP
mode is released, the oscillator’s oscillation stabilization time must be secured until the system clock
stabilizes. Also, PLL lockup time may be required depending on the program. When a resonator or
external clock is connected, following the release of the software STOP mode, execution of the program
is started after the count time of the time base counter has elapsed.
(b) Direct mode
To stop the clock, set the X1 pin to low level. After the release of software STOP mode, execution of the
program is started after the count time of the time base counter has elapsed.
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Figure 9-1 shows the operation of the clock generator in normal operation mode, HALT mode, IDLE mode, and
software STOP mode.
An effective low power consumption system can be realized by combining these modes and switching modes
according to the required use.
Figure 9-1. Power-Save Mode State Transition Diagram
Release according to RESET,
NMI, or maskable interrupt
Normal operation mode
Set HALT mode
Release according to RESET,
NMI, or maskable interruptNote
Release according to RESET,
NMI, or maskable interruptNote
Set STOP mode
HALT mode
Set IDLE mode
Software STOP mode
IDLE mode
Note INTP1nn (n = 0 to 3)
When level detection is specified for the INTP1nn pin, software STOP mode and IDLE mode cannot
be released.
Table 9-1. Clock Generator Operation Using Power-Save Control
Clock Source
PLL mode
Oscillation with
resonator
External clock
Direct mode
Remark
External clock
Power-Save Mode
Oscillator
PLL
Synthesizer
Clock Supply
to Peripheral
I/O
Clock Supply
to CPU
Normal operation
√
√
√
√
HALT mode
√
√
√
−
IDLE mode
√
√
−
−
Software STOP mode
−
−
−
−
Normal operation
−
√
√
√
HALT mode
−
√
√
−
IDLE mode
−
√
−
−
Software STOP mode
−
−
−
−
Normal operation
−
−
√
√
HALT mode
−
−
√
−
IDLE mode
−
−
−
−
Software STOP mode
−
−
−
−
√: Operating
−: Stopped
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9.5.2 Control registers
(1) Power-save mode register (PSMR)
This is an 8-bit register that controls power-save mode. It is effective only when the STB bit of the PSC
register is set to 1.
Writing to the PSMR register is executed by the store instruction (ST/SST instruction) and a bit manipulation
instruction (SET1/CLR1/NOT1 instruction).
This register can be read or written in 8-bit or 1-bit units.
PSMR
7
6
5
4
3
2
1
<0>
Address
After reset
0
0
0
0
0
0
0
PSM
FFFFF820H
00H
Bit position
0
Bit name
Function
PSM
Power Save Mode
Specifies IDLE mode or software STOP mode.
0: Switches the system to IDLE mode
1: Switches the system to software STOP mode
(2) Command register (PRCMD)
This is an 8-bit register that is used to set protection for write operations to registers that can significantly
affect the system so that the application system is not halted unexpectedly due to an inadvertent program
loop.
Writing to the first specific register (power-save control register (PSC)) is only valid after first writing to the
PRCMD register. Because of this, the register value can be overwritten only by the specified sequence,
preventing an illegal write operation from being performed.
This register is write-only in 8-bit units. When it is read, undefined data is read out.
PRCMD
7
6
5
4
3
2
1
0
REG7
REG6
REG5
REG4
REG3
REG2
REG1
REG0
Bit position
7 to 0
306
Bit name
REG7 to
REG0
Address
FFFFF1FCH Undefined
Function
Registration Code (arbitrary 8-bit data)
The specific register targeted is the power-save control register (PSC).
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(3) Power-save control register (PSC)
This is an 8-bit register that controls the power-save function. This register, which is one of the specific
registers, is valid only when accessed in a specific sequence during a write operation.
This register can be read or written in 8-bit or 1-bit units. If bit 7 or 6 is set to 1, operation cannot be
guaranteed.
Caution
It is impossible to set the STB bit and the NMIM or INTM bit at the same time. Be sure to set
the STB bit after setting the NMIM or INTM bit.
PSC
7
6
<5>
<4>
3
2
<1>
0
Address
After reset
0
0
NMIM
INTM
0
0
STB
0
FFFFF1FEH
00H
Bit position
Bit name
Function
5
NMIM
NMI Mode
This is the enable/disable setting bit for standby mode release using the valid edge
input of NMI.
0: Release by NMI enabled
1: Release by NMI disabled
4
INTM
INT Mode
This is the enable/disable setting for standby mode release using an unmasked
maskable interrupt (INTP1nn) (n = 0 to 3).
0: Release by maskable interrupt enabled
1: Release by maskable interrupt disabled
1
STB
Standby Mode
Indicates the standby mode status.
If 1 is written to this bit, the system enters IDLE or software STOP mode (set by
the PSM bit of the PSMR register). When standby mode is released, this bit is
automatically reset to 0.
0: Standby mode is released
1: Standby mode is in effect
Set data in the power-save control register (PSC) in the following sequence.
<1> Set the power-save mode register (PSMR) (with the following instructions).
• Store instruction (ST/SST instruction)
• Bit manipulation instruction (SET1/CLR1/NOT1 instruction)
<2> Prepare data in any one of the general-purpose registers to set to the specific register.
<3> Write data to the command register (PRCMD).
<4> Set the power-save control register (PSC) (with the following instructions).
• Store instruction (ST/SST instruction)
• Bit manipulation instruction (SET1/CLR1/NOT1 instruction)
<5> Assert the NOP instructions (5 instructions (<5> to <9>).
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Sample coding
<1> ST.B
r11, PSMR [r0]
; Set PSMR register
<2> MOV
0×02, r10
<3> ST.B
r10, PRCMD [r0]
; Write PRCMD register
<4> ST.B
r10, PSC [r0]
; Set PSC register
<5> NOP
; Dummy instruction
<6> NOP
; Dummy instruction
<7> NOP
; Dummy instruction
<8> NOP
; Dummy instruction
<9> NOP
; Dummy instruction
(next instruction)
; Execution routine after software STOP mode and IDLE mode release
No special sequence is required to read the specific register.
Cautions 1. A store instruction for the command register does not acknowledge interrupts. This coding
is made on assumption that <3> and <4> above are executed by the program with
consecutive store instructions. If another instruction is set between <3> and <4>, the above
sequence may become ineffective when the interrupt is acknowledged by that instruction,
and a malfunction of the program may result.
2. Although the data written to the PRCMD register is dummy data, use the same register as
the general-purpose register used in specific register setting (<4>) for writing to the PRCMD
register (<3>). The same method should be applied when using a general-purpose register
for addressing.
3. At least 5 NOP instructions must be inserted after executing a store instruction to the PSC
register to set software STOP or IDLE mode.
4. Be sure to terminate all DMA transfers prior to the execution of the above sequence.
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9.5.3 HALT mode
(1) Setting and operation status
In HALT mode, the clock generator (oscillator and PLL synthesizer) continues to operate, but the operation
clock of the CPU is stopped. Since the supply of clocks to on-chip peripheral I/O units other than the CPU
continues, operation continues. The power consumption of the overall system can be reduced by setting the
system to HALT mode while the CPU is idle.
The system is switched to HALT mode by the HALT instruction.
Although program execution stops in HALT mode, the contents of all registers, internal RAM, and ports are
maintained in the state they were in immediately before HALT mode began. Also, operation continues for all
on-chip peripheral I/O units (other than ports) that do not depend on CPU instruction processing. Table 9-2
shows the status of each hardware unit in HALT mode.
Caution
If the HALT instruction is executed while an interrupt is being held pending, the HALT mode
is set once but it is immediately released by the pending interrupt request.
Table 9-2. Operation Status in HALT Mode
Function
Operation Status
Clock generator
Operating
Internal system clock
Operating
CPU
Stopped
Ports
Maintained
On-chip peripheral I/O (excluding ports)
Operating
Internal data
All internal data such as CPU registers, statuses, data, and
the contents of internal RAM are maintained in the state
they were in immediately before HALT mode began.
D0 to D15
Operating
A0 to A25
RD, WE, OE, BCYST
UWR, LWR, IORD, IOWR
LDQM, UDQM
CS0 to CS7
LCAS, UCAS
RAS1, RAS3, RAS4, RAS6
SDRAS
SDCAS
REFRQ
HLDAK
HLDRQ
WAIT
SELFREF
SDCKE
SDCLK
Clock output
CLKOUT
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(2) Release of HALT mode
HALT mode is released by a non-maskable interrupt request, an unmasked maskable interrupt request, or
RESET pin input.
(a) Release according to a non-maskable interrupt request or an unmasked maskable interrupt
request
HALT mode is released by a non-maskable interrupt request or by an unmasked maskable interrupt
request regardless of the priority. However, if the system is set to HALT mode during an interrupt
servicing routine, operation will differ as follows.
(i)
If an interrupt request is generated with a lower priority than that of the interrupt request that is
currently being serviced, HALT mode is released, but the newly generated interrupt request is not
acknowledged. The new interrupt request is held pending.
(ii) If an interrupt request (including non-maskable interrupt requests) is generated with a higher priority
than that of the interrupt request that is currently being serviced, HALT mode is released and the
newly generated interrupt request is acknowledged.
Table 9-3. Operation After HALT Mode Is Released by Interrupt Request
Release Source
Enable Interrupt (EI) Status
Non-maskable interrupt request
Branch to handler address
Maskable interrupt request
Branch to handler address or
execute next instruction
(b) Release according to RESET pin input
This is the same as a normal reset operation.
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Disable Interrupt (DI) Status
Execute next instruction
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9.5.4 IDLE mode
(1) Setting and operation status
In IDLE mode, the clock generator (oscillator and PLL synthesizer) continues to operate, but the supply of
internal system clocks is stopped which causes the overall system to stop.
When IDLE mode is released, the system can be switched to normal operation mode quickly because the
oscillator's oscillation stabilization time or the PLL lockup time does not need to be secured.
The system is switched to IDLE mode by setting the PSC or PSMR register using a store instruction (ST or
SST instruction) or a bit manipulation instruction (SET1, CLR1, or NOT1 instruction) (see 9.5.2 Control
registers).
In IDLE mode, program execution is stopped, and the contents of all registers, internal RAM, and ports are
maintained in the state they were in immediately before execution stopped.
The operation of on-chip
peripheral I/O units (excluding ports) also is stopped.
Table 9-4 shows the status of each hardware unit in IDLE mode.
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Table 9-4. Operation Status in IDLE Mode
Function
Operation Status
Clock generator
Operating
Internal system clock
Stopped
CPU
Stopped
Ports
Maintained
On-chip peripheral I/O (excluding ports)
Stopped
Internal data
All internal data such as CPU registers, statuses, data,
and the contents of internal RAM are maintained in the
state they were in immediately before IDLE mode
began.
D0 to D15
High impedance
A0 to A25
RD, WE, OE, BCYST
High-level output
UWR, LWR, IORD, IOWR
LDQM, UDQM
CS0 to CS7
LCAS, UCAS
Operating
RAS1, RAS3, RAS4, RAS6
SDRAS
SDCAS
REFRQ
HLDAK
High-level output
HLDRQ
Input (no sampling)
WAIT
SELFREF
SDCKE
Low-level output
SDCLK
CLKOUT
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(2) Release of IDLE mode
IDLE mode is released by a non-maskable interrupt request, an unmasked maskable interrupt request
(INTP1nn), or RESET pin input.
(a) Release according to a non-maskable interrupt request or an unmasked maskable interrupt
request
IDLE mode is released by a non-maskable interrupt request or by an unmasked maskable interrupt
request (INTP1nn) regardless of the priority. However, if the system is set to IDLE mode during a
maskable interrupt servicing routine, operation will differ as follows (n = 0 to 3).
(i)
If an interrupt request is generated with a lower priority than that of the interrupt request that is
currently being serviced, IDLE mode is released, but the newly generated interrupt request is not
acknowledged. The new interrupt request is held pending.
(ii) If an interrupt request (including non-maskable interrupt requests) is generated with a higher priority
than that of the interrupt request that is currently being serviced, IDLE mode is released and the
newly generated interrupt request is acknowledged.
Table 9-5. Operation After IDLE Mode Is Released by Interrupt Request
Release Source
Enable Interrupt (EI) Status
Non-maskable interrupt request
Branch to handler address
Maskable interrupt request
Branch to handler address or
execute next instruction
Disable Interrupt (DI) Status
Execute next instruction
If the system is set to IDLE mode during an NMI servicing routine, IDLE mode is released, but the
interrupt is not acknowledged (interrupt is held pending).
Interrupt servicing that is started when IDLE mode is released by NMI pin input is handled in the same
way as normal NMI interrupt servicing that occurs during an emergency (because the NMI interrupt
handler address is unique). Therefore, when a program must be able to distinguish between these two
situations, a software status must be prepared in advance and that status must be set before setting the
PSMR register using a store instruction or a bit manipulation instruction. By checking for this status
during NMI interrupt servicing, an ordinary NMI can be distinguished from the processing that is started
when IDLE mode is released by NMI pin input.
(b) Release according to RESET pin input
This is the same as a normal reset operation.
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9.5.5 Software STOP mode
(1) Setting and operation status
In software STOP mode, the clock generator (oscillator and PLL synthesizer) is stopped. The overall system
is stopped, and ultra-low power consumption is achieved in which only leakage current is lost.
The system is switched to software STOP mode by using a store instruction (ST or SST instruction) or bit
manipulation instruction (SET1, CLR1, or NOT1 instruction) to set the PSC and PSMR registers (see 9.5.2
Control registers).
When PLL mode and resonator connection mode (CESEL bit of CKC register = 1) are used, the oscillator's
oscillation stabilization time must be secured after software STOP mode is released.
In both PLL and direct mode, following the release of software STOP mode, execution of the program is
started after the count time of the time base counter has elapsed.
Although program execution stops in software STOP mode, the contents of all registers, internal RAM, and
ports are maintained in the state they were in immediately before software STOP mode began.
operation of all on-chip peripheral I/O units (excluding ports) is also stopped.
Table 9-6 shows the status of each hardware unit in software STOP mode.
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Table 9-6. Operation Status in Software STOP Mode
Function
Operation Status
Clock generator
Stopped
Internal system clock
Stopped
CPU
Stopped
Ports
Maintained
On-chip peripheral I/O (excluding ports)
Stopped
Internal data
All internal data such as CPU registers, statuses,
data, and the contents of internal RAM are maintained
in the state they were in immediately before software
STOP mode began.
D0 to D15
High impedance
Note
A0 to A25
RD, WE, OE, BCYST
High-level output
UWR, LWR, IORD, IOWR
LDQM, UDQM
CS0 to CS7
Operating
LCAS, UCAS
RAS1, RAS3, RAS4, RAS6
SDRAS
SDCAS
REFRQ
HLDAK
High-level output
HLDRQ
Input (no sampling)
WAIT
SELFREF
Low-level output
SDCKE
SDCLK
CLKOUT
Note When the VDD value is within the operable range. However, even if it drops below the minimum
operable voltage, as long as the data retention voltage VDDDR is maintained, the contents of only the
internal RAM will be maintained.
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(2) Release of software STOP mode
Software STOP mode is released by a non-maskable interrupt request, an unmasked maskable interrupt
request (INTP1nn), or RESET pin input. Also, to release software STOP mode when PLL mode (CKSEL pin
= low level) and resonator connection mode (CESEL bit of CKC register = 0) are used, the oscillator’s
oscillation stabilization time must be secured.
Moreover, the oscillation stabilization time must be secured even when an external clock is connected
(CESEL bit = 1). See 9.4 PLL Lockup for details.
(a) Release according to a non-maskable interrupt request or an unmasked maskable interrupt
request
Software STOP mode is released by a non-maskable interrupt request or by an unmasked maskable
interrupt request (INTP1nn) regardless of the priority. However, if the system is set to software STOP
mode during an interrupt servicing routine, operation will differ as follows (n = 0 to 3).
(i)
If an interrupt request is generated with a lower priority than that of the interrupt request that is
currently being servicing, software STOP mode is released, but the newly generated interrupt
request is not acknowledged. The new interrupt request is held pending.
(ii) If an interrupt request (including non-maskable interrupt requests) is generated with a higher priority
than that of the interrupt request that is currently being serviced, software STOP mode is released
and the newly generated interrupt request is acknowledged.
Table 9-7. Operation After Software STOP Mode Is Released by Interrupt Request
Cancellation Source
Enable Interrupt (EI) Status
Non-maskable interrupt request
Branch to handler address
Maskable interrupt request
Branch to handler address or
execute next instruction
Disable Interrupt (DI) Status
Execute next instruction
If the system is set to software STOP mode during an NMI servicing routine, software STOP mode is
released, but the interrupt is not acknowledged (interrupt is held pending).
Interrupt servicing that is started when software STOP mode is released by NMI pin input is handled in
the same way as normal NMI interrupt servicing that occurs during an emergency (because the NMI
interrupt handler address is unique). Therefore, when a program must be able to distinguish between
these two situations, a software status must be prepared in advance and that status must be set before
setting the PSMR register using a store instruction or a bit manipulation instruction.
By checking for this status during NMI interrupt servicing, an ordinary NMI can be distinguished from the
servicing that is started when software STOP mode is released by NMI pin input.
(b) Release according to RESET pin input
This is the same as a normal reset operation.
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9.6
Securing Oscillation Stabilization Time
9.6.1 Oscillation stabilization time security specification
Two specification methods can be used to secure the time from when software STOP mode is released until the
stopped oscillator stabilizes.
(1) Securing the time using an on-chip time base counter
Software STOP mode is released when a valid edge is input to the NMI pin or a maskable interrupt request is
input (INTP1nn). Valid edge input to the pin causes the time base counter (TBC) to start counting, and the
time until the clock output from the oscillator stabilizes is secured during that counting time.
Oscillation stabilization time = TBC counting time
After a fixed time, internal system clock output begins, and processing branches to the NMI interrupt or
maskable interrupt handler address.
Set software STOP mode
Oscillation waveform
Internal main clock
CLKOUT (output)
STOP state
NMI (input)Note
Oscillator is stopped
Time base counter's
counting time
Note Valid edge: When specified as the rising edge.
The NMI pin should usually be set to an inactive level (for example, high level when the valid edge is
specified as the falling edge) in advance.
Software STOP mode is immediately released if STOP mode is set by NMI valid edge input or maskable
interrupt request input (INTP1nn) before the CPU acknowledges the interrupt.
If direct mode or external clock connection mode (CESEL bit of CKC register = 1) is used, program execution
begins after the count time of the time base counter has elapsed.
Also, even if PLL mode and resonator connection mode (CESEL bit of CKC register = 0) are used, program
execution begins after the oscillation stabilization time is secured according to the time base counter.
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(2) Securing the time according to the signal level width (RESET pin input)
Software STOP mode is released due to falling edge input to the RESET pin.
The time until the clock output from the oscillator stabilizes is secured according to the low-level width of the
signal that is input to the pin.
The supply of internal system clocks begins after a rising edge is input to the RESET pin, and processing
branches to the handler address used for a system reset.
Set software STOP mode
Oscillation waveform
Internal main clock
Undefined
CLKOUT (output)
Undefined
STOP state
RESET (input)
Internal system
reset signal
Oscillation stabilization
time secured by RESET
Oscillator is stopped
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9.6.2 Time base counter (TBC)
The time base counter (TBC) is used to secure the oscillator's oscillation stabilization time when software STOP
mode is released.
When an external clock is connected (CESEL bit of CKC register = 1) or a resonator is connected (PLL mode and
CESEL bit of CKC register = 0), the TBC counts the oscillation stabilization time after software STOP mode is
released, and program execution begins after the count is completed.
The TBC count clock is selected according to the TBCS bit of the CKC register, and the next counting time can be
set (reference).
Table 9-8. Counting Time Examples (φ = 10 × fXX)
TBCS Bit
0
1
Count Clock
Counting Time
fXX = 4.0000 MHz
fXX = 5.0000 MHz
φ = 40.000 MHz
φ = 50.000 MHz
8
16.3 ms
13.1 ms
9
32.6 ms
26.2 ms
fXX/2
fXX/2
fXX: External oscillation frequency
φ:
Internal system clock frequency
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CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
10.1 Timer C
10.1.1 Features (timer C)
Timer C is a 16-bit timer/counter that can perform the following operations.
• Interval timer function
• PWM output
• External signal cycle measurement
10.1.2 Function overview (timer C)
• 16-bit timer/counter
• Capture/compare common registers: 8
• Interrupt request sources
• Capture/match interrupt requests: 8
• Overflow interrupt requests: 4
• Timer/counter count clock sources: 2
(Selection of external pulse input or internal system clock division)
• Either free-running mode or overflow stop mode can be selected as the operation mode when the
timer/counter overflows
• Timer/counter can be cleared by a match of the timer/counter and a compare register
• External pulse outputs: 4
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10.1.3 Basic configuration of timer C
Table 10-1. Timer C Configuration
Timer
Count Clock
Timer C
Register
φ/4, φ/8,
φ/16, φ/32,
φ/64, φ/128,
φ/256, φ/512,
Remarks φ:
Read/Write
Generated
Interrupt Signal
Capture
Trigger
Timer Output
S/R
Other Functions
–
–
–
TMC0
Read
INTOV00
CCC00
Read/write
INTM000
INTP000
TO00 (S)
A/D conversion
start trigger
CCC01
Read/write
INTM001
INTP001
TO00 (R)
A/D conversion
start trigger
TMC1
Read
INTOV01
CCC10
Read/write
INTM010
INTP010
TO01 (S)
A/D conversion
start trigger
CCC11
Read/write
INTM011
INTP011
TO01 (R)
A/D conversion
start trigger
TMC2
Read
INTOV02
CCC20
Read/write
INTM020
INTP020
TO02 (S)
–
CCC21
Read/write
INTM021
INTP021
TO02 (R)
–
TMC3
Read
INTOV03
CCC30
Read/write
INTM030
INTP030
TO03 (S)
–
CCC31
Read/write
INTM031
INTP031
TO03 (R)
–
–
–
–
–
–
–
–
–
–
Internal system clock
S/R: Set/reset
(1) Timer C (16-bit timer/counter)
TI0n0/INTP0n0
INTP0n1
Clear & start
TMCn (16 bits)
CCCn0
CCCn1
INTOV0n
S
Q
RNote Q
Selector
φm
Selector
φ /2
φ m/2
φ m/4
φ m/8
φ m/16
φ m/32
φ m/64
φ m/128
φ m/256
TO0n
INTM0n0
INTM0n1
Note Reset priority
Remark
n = 0 to 3
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CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
10.1.4 Timer C
(1) Timers C0 to C3 (TMC0 to TMC3)
TMCn functions as a 16-bit free-running timer or as an event counter for an external signal. Besides being
mainly used for cycle measurement, TMCn can be used as pulse output (n = 0 to 3).
TMCn is read-only in 16-bit units.
Cautions 1. The TMCn register can only be read. If the TMCn register is written, the subsequent
operation is undefined.
2. If the TMCCAEn bit of the TMCCn register is cleared (0), a reset is performed
asynchronously.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Address
After reset
TMC0
FFFFF600H
0000H
TMC1
FFFFF610H
0000H
TMC2
FFFFF620H
0000H
TMC3
FFFFF630H
0000H
TMCn performs the count-up operations of an internal count clock or external count clock. Timer start and stop are
controlled by the TMCCEn bit of timer mode control register Cn0 (TMCCn0) (n = 0 to 3).
The internal or external count clock is selected by the ETIn bit of timer mode control register Cn1 (TMCCn1) (n = 0
to 3).
(a) Selection of the external count clock
TMCn operates as an event counter.
When the ETIn bit of timer mode control register Cn1 (TMCCn1) is set (1), TMCn counts the valid edges
of the external clock input (TI0n0), synchronized with the internal count clock. The valid edge is specified
by valid edge select register Cn (SESCn) (n = 0 to 3).
Caution
When the INTP0n0/TI0n0 pin is used as TI0n0 (external clock input pin), disable the
INTP0n0 interrupt or set CCCn0 to compare mode (n = 0 to 3).
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CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
(b) Selection of the internal count clock
TMCn operates as a free-running timer.
When an internal clock is specified as the count clock by timer mode control register Cn1 (TMCCn1),
TMCn is counted up for each input clock cycle specified by the CSn0 to CSn2 bits of the TMCCn0
register (n = 0 to 3).
Division by the prescaler can be selected for the count clock from among φ/4, φ/8, φ/16, φ/32, φ/64, φ/128,
φ/256, and φ/512 by the TMCCn0 register.
An overflow interrupt can be generated if the timer overflows. Also, the timer can be stopped following an
overflow by setting the OSTn bit of the TMCCn1 register to 1.
Caution
The count clock cannot be changed while the timer is operating.
The conditions when the TMCn register becomes 0000H are shown below.
(a) Asynchronous reset
• TMCCAEn bit of TMCCn0 register = 0
• Reset input
(b) Synchronous reset
• TMCCEn bit of TMCCn0 register = 0
• The CCCn0 register is used as a compare register, and the TMCn and CCCn0 registers match when
clearing the TMCn register is enabled (CCLRn bit of the TMCCn1 register = 1)
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CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
(2) Capture/compare registers Cn0 and Cn1 (CCCn0 and CCCn1) (n = 0 to 3)
These capture/compare registers are 16-bit registers.
They can be used as capture registers or compare registers according to the CMSn0 and CMSn1 bit
specifications of timer mode control register Cn1 (TMCCn1) (n = 0 to 3).
These registers can be read or written in 16-bit units. (However, write operations can only be performed in
compare mode.)
CCC0n
Address
FFFFF602H,
FFFFF604H
CCC1n
FFFFF612H,
FFFFF614H
0000H
CCC2n
FFFFF622H,
FFFFF624H
0000H
CCC3n
FFFFF632H,
FFFFF634H
0000H
15
Remark
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
After reset
0000H
n = 0 and 1
(a) Setting these registers as capture registers (CMSn0 and CMSn1 of TMCCn1 = 0)
When these registers are set as capture registers, the valid edges of the corresponding external interrupt
signals INTP0n0 and INTP0n1 are detected as capture triggers. The timer TMCn is synchronized with
the capture trigger, and the value of TMCn is latched in the CCCn0 and CCCn1 registers (capture
operation).
The valid edge of the INTP0n0 pin is specified (rising, falling, or both rising and falling edges) according
to the IES0n01 and IES0n00 bits of the SESCn register, and the valid edge of the INTP0n1 pin is
specified according to the IES0n11 and IES0n10 bits of the SESCn register (n = 0 to 3).
The capture operation is performed asynchronously to the count clock. The latched value is held in the
capture register until another capture operation is performed (n = 0 to 3).
When the TMCCAEn bit of timer mode control register Cn0 (TMCCn0) is 0, 0000H is read (n = 0 to 3).
If these registers are specified as capture registers, an interrupt is generated by detecting the valid edge
of signals INTP0n0 and INTP0n1 (n = 0 to 3).
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CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
(b) Setting these registers as compare registers (CMSn0 and CMSn1 of TMCCn1 = 1)
When these registers are set as compare registers, the TMCn and register values are compared for each
timer count clock, and an interrupt is generated by a match. If the CCLRn bit of timer mode control
register Cn1 (TMCCn1) is set (1), the TMCn value is cleared (0) at the same time as a match with the
CCCn0 register (it is not cleared (0) by a match with the CCCn1 register) (n = 0 to 3).
A compare register is equipped with a set/reset function. The corresponding timer output (TO0n) is set or
reset, in synchronization with the generation of a match signal (n = 0 to 3).
The interrupt selection source differs according to the function of the selected register.
Cautions 1. To write to capture/compare registers Cn0 and Cn1, always set the TMCCAEn bit to
1 first. If the TMCCAEn bit is 0, the data that is written will be invalid.
2. Write to capture/compare registers Cn0 and Cn1 after setting them as compare
registers via TMCCn0 and TMCCn1 register settings.
If they are set as capture
registers (CMSn0 and CMSn1 bits of TMCCn1 register = 0), no data is written even if
a write operation is performed to CCCn0 and CCCn1.
3. When these registers are set as compare registers, INTP0n0 and INTP0n1 cannot be
used (n = 0 to 3).
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CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
10.1.5 Timer C control registers
(1) Timer mode control registers C00 to C30 (TMCC00 to TMCC30)
The TMCCn0 registers control the operation of TMCn (n = 0 to 3). These registers can be read or written in
8-bit or 1-bit units.
Cautions 1. The TMCCAEn and other bits cannot be set at the same time. The other bits and the
registers of the other TMCn unit should always be set after the TMCCAEn bit has been
set. Also, to use external pins related to the timer function when timer C is used, be
sure to set (1) the TMCCAEn bit after setting the external pins to control mode.
2. When conflict occurs between an overflow and a TMCCn0 register write, the OVFn bit
value becomes the value written during the TMCCn0 register write (n = 0 to 3).
3. The operation of the system is not guaranteed when bits 2 and 3 are set to a value other
than 0.
(1/2)
<7>
6
5
4
3
2
TMCC00
OVF0
CS02
CS01
CS00
0
0
TMCCE0 TMCCAE0 FFFFF606H
00H
TMCC10
OVF1
CS12
CS11
CS10
0
0
TMCCE1 TMCCAE1 FFFFF616H
00H
TMCC20
OVF2
CS22
CS21
CS20
0
0
TMCCE2 TMCCAE2 FFFFF626H
00H
TMCC30
OVF3
CS32
CS31
CS30
0
0
TMCCE3 TMCCAE3 FFFFF636H
00H
Bit position
7
326
Bit name
OVFn
(n = 0 to 3)
<1>
<0>
Address
After reset
Function
Overflow
This is a flag that indicates TMCn overflow (n = 0 to 3).
0: No overflow occurs
1: Overflow occurs
When TMCn has counted up from FFFFH to 0000H, the OVFn bit becomes 1 and
an overflow interrupt request (INTOV0n) is generated at the same time. However,
if TMCn is cleared to 0000H after a match at FFFFH when the CCCn0 register is
set to compare mode (CMSn0 bit of TMCCn1 register = 1) and clearing is enabled
for a match when TMCn and CCCn0 are compared (CCLRn bit of TMCCn1
register = 1), then TMCn is considered to be cleared and the OVFn bit does not
become 1. Also, no INTOV0n interrupt is generated.
The OVFn bit retains the value 1 until 0 is written directly or until an asynchronous
reset is performed because the TMCCAEn bit is 0. An interrupt operation due to
an overflow is independent of the OVFn bit, and the interrupt request flag (OVIFn)
for INTOV0n is not affected even if the OVFn bit is manipulated. If an overflow
occurs while the OVFn bit is being read, the flag value changes, and the change is
reflected when the next read operation occurs.
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CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
(2/2)
Bit position
6 to 4
Bit name
CSn2 to
CSn0
(n = 0 to 3)
Function
Count Enable Select
Selects the TMCn internal count clock (n = 0 to 3).
CSn2
CSn1
CSn0
Count cycle
0
0
0
φ/4
0
0
1
φ/8
0
1
0
φ/16
0
1
1
φ/32
1
0
0
φ/64
1
0
1
φ/128
1
1
0
φ/256
1
1
1
φ/512
Caution The CSn2 to CSn0 bits must not be changed during timer
operation. If they are to be changed, they must be changed after
setting the TMCCEn bit to 0. If these bits are overwritten during
timer operation, operation cannot be guaranteed.
1
TMCCEn
(n = 0 to 3)
Count Enable
Controls the operation of TMCn (n = 0 to 3).
0: Count disabled (stops at 0000H and does not operate)
1: Counting operation is performed
Caution When TMCCEn = 0, the external pulse output (TO0n) becomes
inactive (the active level of TO0n output is set by the ALVn bit of
the TMCCn1 register).
0
TMCCAEn
(n = 0 to 3)
Clock Action Enable
Controls the internal count clock (n = 0 to 3).
0: The entire TMCn unit is asynchronously reset. The supply of clocks to
the TMCn unit stops.
1: Clocks are supplied to the TMCn unit
Cautions 1. When the TMCCAEn bit is set to 0, the TMCn unit can be
asynchronously reset.
2. When TMCCAEn = 0, the TMCn unit is in a reset state.
Therefore, to operate TMCn, the TMCCAEn bit must be set to 1.
3. When the TMCCAEn bit is changed from 1 to 0, all registers of
the TMCn unit are initialized. When TMCCAEn is set to 1 again,
the TMCn unit registers must be set again.
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CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
(2) Timer mode control registers C01 to C31 (TMCC01 to TMCC31)
The TMCCn1 registers control the operation of TMCn (n = 0 to 3).
These registers can be read or written in 8-bit units.
Cautions 1. The various bits of the TMCCn1 register must not be changed during timer operation. If
they are to be changed, they must be changed after setting the TMCCEn bit of the
TMCCn0 register to 0. If these bits are overwritten during timer operation, operation
cannot be guaranteed (n = 0 to 3).
2. If the ENTn1 and ALVn bits are changed at the same time, a glitch (spike shaped noise)
may be generated in the TO0n pin output. Either create a circuit configuration that will
not malfunction even if a glitch is generated or make sure that the ENTn1 and ALVn bits
do not change at the same time (n = 0 to 3).
3. TO0n output is not changed by an external interrupt signal (INTP0n0 or INTP0n1). To
use the TO0n signal, specify that the capture/compare registers are compare registers
(CMSn0 and CMSn1 bits of TMCCn1 register = 1) (n = 0 to 3).
(1/2)
7
6
5
4
3
2
1
0
Address
After reset
TMCC01
OST0
ENT01
ALV0
ETI0
CCLR0
0
CMS01
CMS00
FFFFF608H
20H
TMCC11
OST1
ENT11
ALV1
ETI1
CCLR1
0
CMS11
CMS10
FFFFF618H
20H
TMCC21
OST2
ENT21
ALV2
ETI2
CCLR2
0
CMS21
CMS20
FFFFF628H
20H
TMCC31
OST3
ENT31
ALV3
ETI3
CCLR3
0
CMS31
CMS30
FFFFF638H
20H
Bit position
Bit name
Function
7
OSTn
(n = 0 to 3)
Overflow Stop
Sets the operation when TMCn has overflowed (n = 0 to 3).
0: After the overflow, counting continues (free-running mode)
1: After the overflow, the timer maintains the value 0000H, and counting stops
(overflow stop mode). At this time, the TMCCEn bit of TMCCn0 remains at 1.
Counting is restarted by writing 1 to the TMCCEn bit.
6
ENTn1
(n = 0 to 3)
Enable To Pin
External pulse output is enabled/disabled (TO0n) (n = 0 to 3).
0: External pulse output is disabled. Output of the ALVn bit inactive level to the
TO0n pin is fixed. The TO0n pin level is not changed even if a match signal
from the corresponding compare register is generated.
1: External pulse output is enabled. A compare register match causes TO0n
output to change. However, if capture mode is set, TO0n output does not
change. The ALVn bit inactive level is output from the time when timer output
is enabled until a match signal is first generated.
Caution If either CCCn0 or CCCn1 is specified as a capture register, the
ENTn1 bit must be set to 0.
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(2/2)
Bit position
5
Bit name
ALVn
(n = 0 to 3)
Function
Active Level
Specifies the active level for external pulse output (TO0n) (n = 0 to 3).
0: Active level is low level
1: Active level is high level
Caution The initial value of the ALVn bit is 1.
4
ETIn
(n = 0 to 3)
External Input
Specifies a switch between the external and internal count clock.
0: Specifies the input clock (internal). The count clock can be selected
according to the CSn2 to CSn0 bits of TMCCn0 (n = 0 to 3).
1: Specifies the external clock (TI0n0). The valid edge can be selected
according to the TESn1 and TESn0 bit specifications of SESCn (n = 0 to 3).
3
CCLRn
(n = 0 to 3)
Compare Clear Enable
Sets whether the clearing of TMCn is enabled or disabled during a compare
operation (n = 0 to 3).
0: Clearing is disabled
1: Clearing is enabled (if CCCn0 and TMCn match during a compare operation,
TMCn is cleared).
1
CMSn1
(n = 0 to 3)
Capture/Compare Mode Select
Selects the operation mode of the capture/compare register (CCCn1) (n = 0 to 3).
0: The register operates as a capture register
1: The register operates as a compare register
0
CMSn0
(n = 0 to 3)
Capture/Compare Mode Select
Selects the operation mode of the capture/compare register (CCCn0) (n = 0 to 3).
0: The register operates as a capture register
1: The register operates as a compare register
Remarks 1. A reset takes precedence for the flip-flop of the TO0n output (n = 0 to 3).
2. When the A/D converter is set to timer trigger mode, the match interrupt of the compare registers
becomes a start trigger for A/D conversion, and the conversion operation begins. At this time, the
compare register match interrupt also functions as a compare register match interrupt for the
CPU. To prevent the generation of a compare register match interrupt for the CPU, disable
interrupts using the interrupt mask bits (P00MK0, P00MK1, P01MK0, and P01MK1) of the
interrupt control registers (P00IC0, P00IC1, P01IC0, and P01IC1).
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CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
(3) Valid edge select registers C0 to C3 (SESC0 to SESC3)
These registers specify the valid edge of an external interrupt request (INTP000, INTP001, INTP010,
INTP011, INTP020, INTP021, INTP030, INTP031, and TI000 to TI030) from an external pin.
The rising edge, the falling edge, or both rising and falling edges can be specified as the valid edge
independently for each pin.
Each of these registers can be read or written in 8-bit units.
Cautions 1. The various bits of the SESCn register must not be changed during timer operation. If
they are to be changed, they must be changed after setting the TMCCEn bit of the
TMCCn0 register to 0.
If the SESCn register is overwritten during timer operation,
operation cannot be guaranteed.
2. The operation of the system is not guaranteed if bits 5 and 4 are set to a value other
than 0.
SESC0
7
6
5
4
TES01
TES00
0
0
3
INTP001
7
6
5
4
TES11
TES10
0
0
TI010
SESC2
6
5
4
TES21
TES20
0
0
5
4
TES31
TES30
0
0
TI030
330
3
2
3
3, 2
IESn1, IESn0
(n = 001, 011,
021, 031)
IESn1, IESn0
(n = 000, 010,
020, 030)
After reset
00H
0
Address
After reset
00H
INTP010
1
0
Address
After reset
00H
INTP020
2
1
0
Address
IES0311 IES0310 IES0301 IES0300 FFFFF639H
INTP031
Bit name
TESn1,
TESn0
(n = 0 to 3)
1
IES0211 IES0210 IES0201 IES0200 FFFFF629H
TCLR3
7, 6
1, 0
2
INTP021
6
Address
IES0111 IES0110 IES0101 IES0100 FFFFF619H
TCLR2
7
0
INTP000
INTP011
7
Bit position
3
TCLR1
TI020
SESC3
1
IES0011 IES0010 IES0001 IES0000 FFFFF609H
TI000
SESC1
2
INTP030
Function
Edge Select
Specifies the valid edge of the INTPn and TI000 to TI030 pins.
xESn1
xESn0
Operation
0
0
Falling edge
0
1
Rising edge
1
0
RFU (reserved)
1
1
Both edges
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After reset
00H
CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
10.1.6 Timer C operation
(1) Count operation
Timer C can function as a 16-bit free-running timer or as an external signal event counter. The setting for the
type of operation is specified by timer mode control registers Cn0 and Cn1 (TMCCn0 and TMCCn1) (n = 0 to
3).
When it operates as a free-running timer, if the CCCn0 or CCCn1 register and the TMCn count value match,
an interrupt signal is generated and the timer output signal (TO0n) can be set or reset. Also, a capture
operation that holds the TMCn count value in the CCCn0 or CCCn1 register is performed, in synchronization
with the valid edge that was detected from the external interrupt request input pin as an external trigger. The
capture value is held until the next capture trigger is generated.
Caution
When using the INTP0n0/TI0n0 pin as an external clock input pin (TI0n0), be sure to disable
the INTP0n0 interrupt or set CCCn0 to compare mode (n = 0 to 3).
Figure 10-1. Basic Operation of Timer C
Count clock
TMCn
0000H 0001H 0002H 0003H
FBFEH FBFFH
∆
Count start
TMCCEn←1
Remark
0000H
∆
Count disabled
TMCCEn←0
0001H 0002H
∆
Count start
TMCCEn←1
n = 0 to 3
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CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
(2) Overflow
When the TMCn register has counted the count clock from FFFFH to 0000H, the OVFn bit of the TMCCn0
register is set (1), and an overflow interrupt (INTOV0n) is generated at the same time (n = 0 to 3). However,
if the CCCn0 register is set to compare mode (CMSn0 bit = 1) and to the value FFFFH when match clearing
is enabled (CCLRn bit = 1), then the TMCn register is considered to be cleared and the OVFn bit is not set (1)
when the TMCn register changes from FFFFH to 0000H. Also, the overflow interrupt (INTOV0n) is not
generated .
When the TMCn register is changed from FFFFH to 0000H because the TMCCEn bit changes from 1 to 0,
the TMCn register is considered to be cleared, but the OVFn bit is not set (1) and no INTOV0n interrupt is
generated.
Also, timer operation can be stopped after an overflow by setting the OSTn bit of the TMCCn1 register to 1.
When the timer is stopped due to an overflow, the count operation is not restarted until the TMCCEn bit of the
TMCCn0 register is set (1).
Operation is not affected even if the TMCCEn bit is set (1) during a count operation.
Remark
n = 0 to 3
Figure 10-2. Operation After Overflow (When OSTn = 1)
Overflow
FFFFH
Count
start
TMCn
0
OSTn ← 1
TMCCEn ← 1
TMCCEn ← 1
INTOV0n
Remark
332
n = 0 to 3
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Overflow
FFFFH
CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
(3) Capture operation
The TMCn register has two capture/compare registers. These are the CCCn0 register and the CCCn1
register. A capture operation or a compare operation is performed according to the settings of both the
CMSn1 and CMSn0 bits of the TMCCn1 register. If the CMSn1 and CMSn0 bits of the TMCCn1 register are
set to 0, the register operates as a capture register.
A capture operation that captures and holds the TMCn count value asynchronously relative to the count clock
is performed in synchronization with an external trigger. The valid edge that is detected from an external
interrupt request input pin (INTP0n0 or INTP0n1) is used as an external trigger (capture trigger). The TMCn
count value during counting is captured and held in the capture register, in synchronization with that capture
trigger signal. The capture register value is held until the next capture trigger is generated.
Also, an interrupt request (INTM0n0 or INTM0n1) is generated by INTP0n0 or INTP0n1 signal input.
The valid edge of the capture trigger is set by valid edge select register Cn (SESCn).
If both the rising and falling edges are set as capture triggers, the input pulse width from an external source
can be measured. Also, if only one of the edges is set as the capture trigger, the input pulse cycle can be
measured.
Remark
n = 0 to 3
Figure 10-3. Capture Operation Example
n
TMC1
0
TMCCE1
CCC11
(Capture register)
n
INTP011
(Capture trigger)
(Capture trigger)
Remarks 1. When the TMCCE1 bit is 0, no capture operation is performed even if INTP011 is input.
2. Valid edge of INTP011: Rising edge
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Figure 10-4. TMC1 Capture Operation Example (When Both Edges Are Specified)
(TMC1 count values)
D1
D0
TMC1
D2
∆
Count start
TMCCE1←1
∆
Overflow
OVF1←1
Interrupt request (INTP011)
D0
Capture register (CCC11)
Remark
334
D0 to D2: TMC1 count values
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CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
(4) Compare operation
The TMCn register has two capture/compare registers. These are the CCCn0 register and the CCCn1
register. A capture operation or a compare operation is performed according to the settings of both the
CMSn1 and CMSn0 bits of the TMCCn1 register. If the CMSn1 and CMSn0 bits of the TMCCn1 register are
set to 1, the register operates as a compare register.
A compare operation that compares the value that was set in the compare register and the TMCn count value
is performed.
If the TMCn count value matches the value of the compare register, which had been set in advance, a match
signal is sent to the output controller. The match signal causes the timer output pin (TO0n) to change and an
interrupt request signal (INTCCn) to be generated at the same time.
If the CCCn0 register is set to 0000H, the 0000H after the TMCn register counts up from FFFFH to 0000H is
judged as a match. In this case, the TMCn register value is cleared (0) at the next count timing, however, this
0000H is not judged as a match. Also, the 0000H when the TMCn register begins counting is not judged as a
match.
If match clearing is enabled (CCLRn bit = 1) for the CCCn0 register, the TMCn register is cleared when a
match with the TMCn register occurs during a compare operation.
Remark
n = 0 to 3
Figure 10-5. Compare Operation Example (1/2)
(a) When CCLR1 = 1 and CCC11 is other than 0000H
Count up
TMC1
n−1
Compare register
(CCC11)
n
0000H
0001H
n
Match detection
(INTM011)
Remarks 1. The match is detected immediately after the count-up, and the match detection signal is
generated.
2. n ≠ 0000H
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CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
Figure 10-5. Compare Operation Example (2/2)
(b) When CCLR1 = 1 and CCC11 is 0000H
Count up
TMC1
FFFFH
Compare register
(CCC11)
0000H
0000H
0001H
0000H
INTOV01
Match detection
(INTM011)
Remark
The match is detected immediately after the count-up, and the match detection signal is
generated.
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(5) External pulse output
Timer C has four timer output pins (TO0n).
An external pulse output (TO0n) is generated when a match of the two compare registers (CCCn0 and
CCCn1) and the TMCn register is detected.
If a match is detected when the TMCn count value and the CCC0n0 value are compared, the output level of
the TO0n pin is set. Also, if a match is detected when the TMCn count value and the CCC0n1 value are
compared, the output level of the TO0n pin is reset.
The output level of the TO0n pin can be specified by the TMCCn1 register.
Remark
n = 0 to 3
Table 10-2. TO0n Output Control
ENTn1
ALVn
0
0
1
0
1
0
1
0
When the CCCn0 register is matched: 0
When the CCCn1 register is matched: 1
1
1
When the CCCn0 register is matched: 1
When the CCCn1 register is matched: 0
Remark
TO0n Output
n = 0 to 3
Figure 10-6. TMC1 Compare Operation Example (Set/Reset Output Mode)
FFFFH
FFFFH
CCC11
CCC11
CCC10
CCC10
CCC10
TMC1 count value
0
∆
Count start
TMCCE1 ← 1
∆
Overflow
OVF1 ← 1
∆
Overflow
OVF1 ← 1
Interrupt request
(INTM010)
Interrupt request
(INTM011)
TO01 pin
ENT11 ← 1
ALV1 ← 1
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CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
10.1.7 Application examples (timer C)
(1) Interval timer
By setting the TMCCn0 and TMCCn1 registers as shown in Figure 10-7, timer C operates as an interval timer
that repeatedly generates interrupt requests with the value that was preset in the CCCn0 register as the
interval.
When the counter value of the TMCn register matches the setting value of the CCCn0 register, the TMCn
register is cleared (0000H) and an interrupt request signal (INTM0n0) is generated at the same time that the
count operation resumes.
Remark
n = 0 to 3
Figure 10-7. Contents of Register Settings When Timer C Is Used as Interval Timer
TMCCEn TMCCAEn
OVFn CSn2 CSn1 CSn0
TMCCn0
0/1
0/1
0/1
0/1
0
0
1
1
Supply input clocks to internal units
Enable count operation
OSTn ENTn ALVn
TMCCn1
0
0/1
0/1
ETIn CCLRn
0/1
1
CMSn1 CMSn0
0
0/1
1
Use CCCn0 register as compare register
Clear TMCn register due to match with
CCCn0 register
Continue counting after TMCn register
overflows
Remarks 1. 0/1: Set to 0 or 1 as necessary
2. n = 0 to 3
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Figure 10-8. Interval Timer Operation Timing Example
t
Count clock
TMCn register
0000H 0001H
Count start
CCCn0 register
p
p
0000H 0001H
Clear
p
0000H 0001H
p
Clear
p
p
p
INTM0n0
interrupt
Interval time
Interval time
Interval time
Remarks 1. p: Setting value of CCCn0 register (0000H to FFFFH)
t: Count clock cycle
Interval time = (p + 1) × t
2. n = 0 to 3
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CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
(2) PWM output
By setting the TMCCn0 and TMCCn1 registers as shown in Figure 10-9, timer C can output PWM of an
arbitrary frequency with the values that were preset in the CCCn0 and CCCn1 registers determining the
intervals.
When the counter value of the TMCn register matches the setting value of the CCCn0 register, the TO0n
output becomes active. Then, when the counter value of the TMCn register matches the setting value of the
CCCn1 register, the TO0n output becomes inactive. This enables PWM of an arbitrary frequency to be
output. When the setting value of the CCCn0 register and the setting value of the CCCn1 register are the
same, the TO0n output remains inactive and does not change.
The active level of the TO0n output can be set by the ALVn bit of the TMCCn1 register.
Remark
n = 0 to 3
Figure 10-9. Contents of Register Settings When Timer C Is Used for PWM Output
TMCCEn TMCCAEn
OVFn CSn2 CSn1 CSn0
TMCCn0
0/1
0/1
0/1
0/1
0
0
1
1
Supply input clocks to internal units
Enable count operation
OSTn ENTn ALVn
TMCCn1
0
1
0/1
ETIn CCLRn
0/1
0
CMSn1 CMSn0
0
1
1
Use CCCn0 register as compare register
Use CCCn1 register as compare register
Disable clearing of TMCn register due to
match with CCCn0 register
Enable external pulse output (TO0n)
Continue counting after TMCn register
overflows
Remarks 1. 0/1: Set to 0 or 1 as necessary
2. n = 0 to 3
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Figure 10-10. PWM Output Timing Example
Count
clock
TMCn
register
0000H 0001H
p
q
Count start
FFFFH 0000H 0001H
p
q
Clear
CCCn0
register
p
p
p
p
p
CCCn1
register
q
q
q
q
q
INTM0n0
interrupt
INTM0n1
interrupt
TO0n
(output)
Remarks 1. p: Setting value of CCCn0 register (0000H to FFFFH)
q: Setting value of CCCn1 register (0000H to FFFFH)
p≠q
2. In this example, the active level of the TO0n output is set to high level.
3. n = 0 to 3
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(3) Cycle measurement
By setting the TMCCn0 and TMCCn1 registers as shown in Figure 10-11, timer C can measure the cycle of
signals input to the INTP0n0 or INTP0n1 pin.
The valid edge of the INTP0n0 pin is selected according to the IES0n01 and IES0n00 bits of the SESCn
register, and the valid edge of the INTP0n1 pin is selected according to the IES0n11 and IES0n10 bits of the
SESCn register. Either the rising edge, the falling edge, or both edges can be selected as the valid edges of
both pins.
If the CCCn0 register is set as a capture register, the valid edge input of the INTP0n0 pin is set as the trigger
for capturing the TMCn register value in the CCCn0 register. When this value is captured, an INTM0n0
interrupt is generated.
Similarly, if the CCCn1 register is set as a capture register, the valid edge input of the INTP0n1 pin is set as
the trigger for capturing the TMCn register value in the CCCn1 register. When this value is captured, an
INTM0n1 interrupt is generated.
The cycle of signals input to the INTP0n0 pin is calculated by obtaining the difference between the TMCn
register’s count value (Dx) that was captured in the CCCn0 register according to the x-th valid edge input of
the INTP0n0 pin and the TMCn register’s count value (D(x+1)) that was captured in the CCCn0 register
according to the (x+1)-th valid edge input of the INTP0n0 pin and multiplying the value of this difference by
the cycle of the clock control signal.
The cycle of signals input to the INTP0n1 pin is calculated by obtaining the difference between the TMCn
register’s count value (Dx) that was captured in the CCCn1 register according to the x-th valid edge input of
the INTP0n1 pin and the TMCn register’s count value (D(x+1)) that was captured in the CCCn1 register
according to the (x+1)-th valid edge input of the INTP0n1 pin and multiplying the value of this difference by
the cycle of the clock control signal.
Remark
342
n = 0 to 3
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CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
Figure 10-11. Contents of Register Settings When Timer C Is Used for Cycle Measurement
TMCCEn TMCCAEn
OVFn CSn2 CSn1 CSn0
TMCCn0
0/1
0/1
0/1
0/1
0
0
1
1
Supply input clocks to internal units
Enable count operation
OSTn ENTn ALVn
TMCCn1
0
0/1
0/1
ETIn CCLRn
0/1
0/1
CMSn1 CMSn0
0
0
0
Use CCCn0 register as capture register
(when measuring the cycle of INTP0n0 input)
Use CCCn1 register as capture register
(when measuring the cycle of INTP0n1 input)
Continue counting after TMCn register
overflows
Remarks 1. 0/1: Set to 0 or 1 as necessary
2. n = 0 to 3
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CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
Figure 10-12. Cycle Measurement Operation Timing Example
t
Count
clock
TMCn
register
0000H 0001H
D0
D1
Count start
FFFFH 0000H 0001H
D2
D3
Clear
INTP0n0
(input)
CCCn0
register
D0
D1
D2
D3
INTM0n0
interrupt
INTOV0n
interrupt
(D1 − D0) × t
No overflow
{(10000H − D1) + D2} × t
Overflow occurs
(D3 − D2) × t
No overflow
Caution An overflow must not be generated more than once between the 1st and 2nd INTM0n0
interrupts.
Remarks 1. D0 to D3: TMCn register count values
t: Count clock cycle
2. In this example, the valid edge of the INTP0n0 input has been set to both edges (rising and
falling).
3. n = 0 to 3
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10.1.8 Cautions (timer C)
Various cautions concerning timer C are shown below.
(1) If a conflict occurs between the reading of the CCCn0 register and a capture operation when the CCCn0
register is used in capture mode, an external trigger (INTP0n0) valid edge is detected and an external
interrupt request signal (INTM0n0) is generated, however, the timer value is not stored in the CCCn0 register.
(2) If a conflict occurs between the reading of the CCCn1 register and a capture operation when the CCCn1
register is used in capture mode, an external trigger (INTP0n1) valid edge is detected and an external
interrupt request signal (INTM0n1) is generated, however, the timer value is not stored in the CCCn1 register.
(3) The following bits and registers must not be rewritten during operation (TMCCEn = 1).
• CSn2 to CSn0 bits of TMCCn0 register
• TMCCn1 register
• SESCn register
(4) The TMCCAEn bit of the TMCCn0 register is a TMCn reset signal. To use TMCn, first set (1) the TMCCAEn
bit.
(5) The analog noise elimination time + two cycles of the input clock are required to detect the valid edge of the
external interrupt request signal (INTP0n0 or INTP0n1). Therefore, edge detection will not be performed
normally for changes that are less than the analog noise elimination time + two cycles of the input clock. For
details of analog noise elimination, refer to 7.3.8 Noise elimination.
(6) The operation of an external interrupt request signal (INTM0n0 or INTM0n1) is automatically determined
according to the operating state of the capture/compare register. When the capture/compare register is used
for a capture operation, the external interrupt request signal is used for valid edge detection. When the
capture/compare register is used for a compare operation, the external interrupt request signal is used for an
interrupt indicating a match with the TMCn register.
(7) If the ENTn1 and ALVn bits are changed at the same time, a glitch (spike shaped noise) may be generated in
the TO0n pin output. Either create a circuit configuration that will not malfunction even if a glitch is generated
or make sure that the ENTn1 and ALVn bits are not changed at the same time.
Remark
n = 0 to 3
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10.2 Timer D
10.2.1 Features (timer D)
Timer D functions as a 16-bit interval timer.
10.2.2 Function overview (timer D)
• 16-bit interval timer
• Compare registers: 4
• Interrupt request sources: 4 sources
• Count clock selected from divisions of internal system clock
10.2.3 Basic configuration of timer D
Table 10-3. Timer D Configuration
Timer
Count Clock
Timer D
φ/4, φ/8,
φ/16, φ/32,
φ/64, φ/128,
φ/256, φ/512
Remark φ:
Register
Read/Write
TMD0
Read
CMD0
Read/write
TMD1
Read
CMD1
Read/write
TMD2
Read
CMD2
Read/write
TMD3
Read
CMD3
Read/write
Generated
Interrupt
Signal
Capture
Trigger
Timer Output
S/R
Other
Functions
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
INTCMD0
–
INTCMD1
–
INTCMD2
–
INTCMD3
Internal system clock
S/R: Set/reset
(1) Timer D (16-bit timer/counter)
φ /2
φm
φ m/2
φ m/4
φ m/8
φ m/16
φ m/32
φ m/64
φ m/128
φ m/256
TMDn (16 bits)
Clear & start
CMDn
Remark
346
n = 0 to 3
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CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
10.2.4 Timer D
(1) Timers D0 to D3 (TMD0 to TMD3)
TMDn is a 16-bit timer. It is mainly used as an interval timer for software (n = 0 to 3).
Starting and stopping TMDn is controlled by the TMDCEn bit of the timer mode control register Dn (TMCDn)
(n = 0 to 3).
Division by the prescaler can be selected for the count clock from among φ/4, φ/8, φ/16, φ/32, φ/64, φ/128,
φ/256, and φ/512 by the CSn0 to CSn2 bits of the TMCDn register.
TMDn is read-only in 16-bit units.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Address
After reset
TMD0
FFFFF540H
0000H
TMD1
FFFFF550H
0000H
TMD2
FFFFF560H
0000H
TMD3
FFFFF570H
0000H
The conditions for which the TMDn register becomes 0000H are shown below (n = 0 to 3).
• Reset input
• TMDCAEn bit = 0
• TMDCEn bit = 0
• Match of TMDn register and CMDn register
• Overflow
Cautions 1. If the TMDCAEn bit of the TMCDn register is cleared (0), a reset is performed
asynchronously.
2. If the TMDCEn bit of the TMCDn register is cleared (0), a reset is performed, in
synchronization with the internal clock. Similarly, a synchronized reset is performed
after a match with the CMDn register and after an overflow.
3. The count clock must not be changed during a timer operation. If it is to be overwritten,
it should be overwritten after the TMDCEn bit is cleared (0).
4. Up to φ/4 clocks are required after a value is set in the TMDCEn bit until the set value is
transferred to internal units. When a count operation begins, the count cycle from
0000H to 0001H differs from subsequent cycles.
5. After a compare match is generated, the timer is cleared at the next count clock.
Therefore, if the division ratio is large, the timer value may not be zero even if the timer
value is read immediately after a match interrupt is generated.
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(2) Compare registers D0 to D3 (CMD0 to CMD3)
CMDn and the TMDn register count value are compared, and an interrupt request signal (INTCMDn) is
generated when a match occurs. TMDn is cleared, in synchronization with this match. If the TMDCAEn bit of
the TMCDn register is set to 0, a reset is performed asynchronously, and the registers are initialized (n = 0 to
3).
The CMDn registers are configured with a master/slave configuration. When a CMDn register is written, data
is first written to the master register and then the master register data is transferred to the slave register. In a
compare operation, the slave register value is compared with the count value of the TMDn register. When a
CMDn register is read, data in the master side is read out.
CMDn can be read or written in 16-bit units.
Cautions 1. A write operation to a CMDn register requires φ/4 clocks until the value that was set in
the CMDn register is transferred to internal units. When writing continuously to the
CMDn register, be sure to reserve a time interval of at least φ/4 clocks.
2. The CMDn register can be overwritten only once in a single TMDn register cycle (from
0000H until an INTCMDn interrupt is generated due to a match of the TMDn register and
CMDn register). If this cannot be secured by the application, make sure that the CMDn
register is not overwritten during timer operation.
3. Note that a match signal will be generated after an overflow if a value less than the
counter value is written in the CMDn register during TMDn register operation (Figure 1013).
15
348
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Address
After reset
CMD0
FFFFF542H
0000H
CMD1
FFFFF552H
0000H
CMD2
FFFFF562H
0000H
CMD3
FFFFF572H
0000H
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CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
Figure 10-13. Example of Timing During TMDn Operation
(a) When CMDn < FFFFH
TMDn
m
n
n
TMDCAEn
TMDCEn
n
CMDn
INTCMDn
(b) When TMDn > CMDn
TMDn
FFFFH
m
n
n
TMDCAEn
TMDCEn
n
CMDn
INTCMDn
Remark
m = TMDn value when overwritten
n = CMDn value when overwritten
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CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
10.2.5 Timer D control registers
(1) Timer mode control registers D0 to D3 (TMCD0 to TMCD3)
The TMCDn registers control the operation of timer Dn (n = 0 to 3).
These registers can be read or written in 8-bit or 1-bit units.
Caution
The TMDCAEn and other bits cannot be set at the same time.
The other bits and the
registers of the other TMDn units should always be set after the TMDCAEn bit has been set.
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7
6
5
4
3
2
TMCD0
0
CS02
CS01
CS00
0
0
TMDCE0 TMDCAE0 FFFFF544H
00H
TMCD1
0
CS12
CS11
CS10
0
0
TMDCE1 TMDCAE1 FFFFF554H
00H
TMCD2
0
CS22
CS21
CS20
0
0
TMDCE2 TMDCAE2 FFFFF564H
00H
TMCD3
0
CS32
CS31
CS30
0
0
TMDCE3 TMDCAE3 FFFFF574H
00H
Bit position
6 to 4
<1>
Bit name
CSn2 to
CSn0
(n = 0 to 3)
<0>
Address
After reset
Function
Count Enable Select
Selects the TMDn internal count clock cycle (n = 0 to 3).
CS2
CS1
CS0
Count cycle
0
0
0
φ/4
0
0
1
φ/8
0
1
0
φ/16
0
1
1
φ/32
1
0
0
φ/64
1
0
1
φ/128
1
1
0
φ/256
1
1
1
φ/512
Caution The CSn2 to CSn0 bits must not be changed during timer
operation. If they are to be changed, they must be changed after
setting the TMDCEn bit to 0. If these bits are overwritten during
timer operation, operation cannot be guaranteed.
1
TMDCEn
(n = 0 to 3)
Count Enable
Controls the operation of TMDn (n = 0 to 3).
0: Count disabled (stops at 0000H and does not operate)
1: Counting operation is performed
Caution TMDCEn bit is not cleared even if a match is detected by the
compare operation. To stop the count operation, clear the
TMDCEn bit.
0
TMDCAEn
(n = 0 to 3)
Clock Action Enable
Controls the internal count clock (n = 0 to 3).
0: The entire TMDn unit is reset asynchronously. The supply of input clocks to
the TMDn unit stops.
1: Input clocks are supplied to the TMDn unit
Cautions 1. When the TMDCAEn bit is set to 0, the TMDn unit can be
asynchronously reset.
2. When TMDCAEn = 0, the TMDn unit is in a reset state.
Therefore, to operate TMDn, the TMDCAEn bit must be set to 1.
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10.2.6 Timer D operation
(1) Compare operation
TMDn can be used for a compare operation in which the value that was set in a compare register (CMDn) is
compared with the TMDn count value (n = 0 to 3).
If a match is detected by the compare operation, an interrupt (INTCMDn) is generated. The generation of the
interrupt causes TMDn to be cleared (0) at the next count timing. This function enables timer D to be used as
an interval timer.
CMDn can also be set to 0. In this case, when an overflow occurs and TMDn becomes 0, a match is
detected and INTCMDn is generated. Although the TMDn value is cleared (0) at the next count timing,
INTCMDn is not generated by this match.
Figure 10-14. TMD0 Compare Operation Example (1/2)
(a) When CMD0 is set to n (non-zero)
Count clock
Count up
TMD0 clear
Clear
TMD0
n
CMD0
0
n
Match detected
(INTCMD0)
Remark
Interval time = (n + 1) × (Count clock cycle)
n = 1 to 65,536 (FFFFH)
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Figure 10-14. TMD0 Compare Operation Example (2/2)
(b) When CMD0 is set to 0
Count clock
Count up
TMD0 clear
Clear
TMD0
CMD0
FFFFH
0
0
1
0
Match detected
(INTCMD0)
Overflow
Remark
Interval time = (FFFFH + 2) × (Count clock cycle)
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CHAPTER 10 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
10.2.7 Application examples (timer D)
(1) Interval timer
This section explains an example in which timer D is used as an interval timer with 16-bit precision.
Interrupt requests (INTCMDn) are output at equal intervals (see Figure 10-14 TMD0 Compare Operation
Example). The setup procedure is shown below (n = 0 to 3).
<1> Set (1) the TMDCAEn bit.
<2> Set each register.
• Select the count clock using the CSn0 to CSn2 bits of the TMCDn register.
• Set the compare value in the CMDn register.
<3> Start counting by setting (1) the TMDCEn bit.
<4> If the TMDn register and CMDn register values match, an INTCMDn interrupt is generated.
<5> INTCMDn interrupts are generated thereafter at equal intervals.
Remark
n = 0 to 3
10.2.8 Cautions (timer D)
Various cautions concerning timer D are shown below.
(1) To operate TMDn, first set (1) the TMDCAEn bit.
(2) Up to 4 clocks are required after a value is set in the TMDCEn bit until the set value is transferred to internal
units. When a count operation begins, the count cycle from 0000H to 0001H differs from subsequent cycles.
(3) To initialize the TMDn register status and start counting again, clear (0) the TMDCEn bit and then set (1) the
TMDCEn bit after an interval of 4 clocks has elapsed.
(4) Up to 4 clocks are required until the value that was set in the CMDn register is transferred to internal units.
When writing continuously to the CMDn register, be sure to secure a time interval of at least 4 clocks.
(5) The CMDn register can be overwritten only once during a timer/counter operation (from 0000H until an
INTCMDn interrupt is generated due to a match of the TMDn register and CMDn register). If this cannot be
secured, make sure that the CMDn register is not overwritten during a timer/counter operation.
(6) The count clock must not be changed during a timer operation.
If it is to be overwritten, it should be
overwritten after the TMDCEn bit is cleared (0). If the count clock is overwritten during a timer operation,
operation cannot be guaranteed.
(7) A match signal will be generated after an overflow if a value less than the counter value is written in the
CMDn register during TMDn register operation.
Remark
354
n = 0 to 3
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CHAPTER 11 SERIAL INTERFACE FUNCTION
11.1 Features
The serial interface function provides two types of serial interfaces equipped with six transmit/receive channels of
which four channels can be used simultaneously.
The following two interface formats are available.
(1) Asynchronous serial interface (UART0 to UART2): 3 channels
(2) Clocked serial interface (CSI0 to CSI2): 3 channels
UART0 to UART2, which use the method of transmitting/receiving one byte of serial data following a start bit,
enable full-duplex communication to be performed.
CSI0 to CSI2 transfer data according to three types of signals (3-wire serial I/O). These signals are the serial clock
(SCK0 to SCK2), serial input (SI0 to SI2), and serial output (SO0 to SO2) signals.
11.1.1 Switching between UART and CSI modes
In the V850E/MA1, since UART0 and CSI0 pin and the UART1 and CSI1 pin are alternate function pins, they
cannot be used at the same time. The PMC4 and PFC4 registers must be set in advance (see 14.3.5 Port 4).
Also, since UART2 and CSI2 have alternate functions as external interrupt request input pins (INTP120 and
INTP130 to INTP133), the PMC3 and PFC3 registers must be set in advance (see 14.3.4 Port 3).
If the mode is switched during a transmit or receive operation in UARTn or CSIn, operation cannot be guaranteed.
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11.2 Asynchronous Serial Interfaces 0 to 2 (UART0 to UART2)
11.2.1 Features
• Transfer rate: 300 bps to 1,562.5 Kbps (using a dedicated baud rate generator and an internal system clock of
50 MHz)
• Full-duplex communications
On-chip receive buffer (RXBn)
On-chip transmit buffer (TXBn)
• Two-pin configuration
TXDn: Transmit data output pin
RXDn: Receive data input pin
• Reception error detection function
• Parity error
• Framing error
• Overrun error
• Interrupt sources: 3 types
• Reception error interrupt (INTSERn):
Interrupt is generated according to the logical OR of the
three types of reception errors
• Reception completion interrupt (INTSRn):
Interrupt is generated when receive data is transferred from
the shift register to the receive buffer after serial transfer is
completed during a reception enabled state
• Transmission completion interrupt (INTSTn):
Interrupt is generated when the serial transmission of
transmit data (8 or 7 bits) from the shift register is completed
• The character length of transmit/receive data is specified according to the ASIM0 to ASIM2 registers
• Character length: 7 or 8 bits
• Parity functions: Odd, even, 0, or none
• Transmission stop bits: 1 or 2 bits
• On-chip dedicated baud rate generator
Remark
356
n = 0 to 2
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11.2.2 Configuration
UARTn is controlled by the asynchronous serial interface mode register (ASIMn), asynchronous serial interface
status register (ASISn), and asynchronous serial interface transmission status register (ASIFn) (n = 0 to 2). Receive
data is held in the receive buffer (RXBn), and transmit data is written to the transmit buffer (TXBn).
Figure 11-1 shows the configuration of the asynchronous serial interface.
(1) Asynchronous serial interface mode registers 0 to 2 (ASIM0 to ASIM2)
The ASIMn register is an 8-bit register for specifying the operation of the asynchronous serial interface.
(2) Asynchronous serial interface status registers 0 to 2 (ASIS0 to ASIS2)
The ASISn register consists of a set of flags that indicate the error contents when a reception error occurs.
The various reception error flags are set (1) when a reception error occurs and are reset (0) when the ASISn
register is read.
(3) Asynchronous serial interface transmission status registers 0 to 2 (ASIF0 to ASIF2)
The ASIFn register is an 8-bit register that indicates the status when a transmit operation is performed.
This register consists of a transmit buffer data flag, which indicates the hold status of TXBn data, and the
transmit shift register data flag, which indicates whether transmission is in progress.
(4) Reception control parity check
Receive operations are controlled according to the contents set in the ASIMn register. A check for parity
errors is also performed during a receive operation, and if an error is detected, the value corresponding to the
error contents is set in the ASISn register.
(5) Receive shift register
This is a shift register that converts the serial data that was input to the RXDn pin to parallel data. One byte
of data is received, and if a stop bit is detected, the receive data is transferred to the receive buffer.
This register cannot be directly manipulated.
(6) Receive buffer (RXBn)
RXBn is an 8-bit buffer register for holding receive data. When 7 characters are received, 0 is stored in the
MSB.
During a reception enabled state, receive data is transferred from the receive shift register to the receive
buffer, in synchronization with the end of the shift-in processing of one frame.
Also, the reception completion interrupt request (INTSRn) is generated by the transfer of data to the receive
buffer.
(7) Transmit shift register
This is a shift register that converts the parallel data that was transferred from the transmit buffer to serial
data.
When one byte of data is transferred from the transmit buffer, the shift register data is output from the TXDn
pin.
This register cannot be directly manipulated.
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(8) Transmit buffer (TXBn)
TXBn is an 8-bit buffer for transmit data. A transmit operation is started by writing transmit data to TXBn.
The transmission completion interrupt request (INTSTn) is generated in synchronization with the completion
of transmission of one frame.
(9) Addition of transmission control parity
Transmit operations are controlled by adding a start bit, parity bit, or stop bit to the data that is written to the
TXBn register, according to the contents that were set in the ASIMn register.
Figure 11-1. Asynchronous Serial Interface Block Diagram
Internal bus
Asynchronous serial interface
mode register n (ASIMn)
RXDn
Receive
buffer (RXBn)
Transmit
buffer (TXBn)
Receive
shift register
Transmit
shift register
Reception control
parity check
Addition of transmission
control parity
TXDn
INTSTn
INTSRn
Parity
Framing
Overrun
INTSERn
BRGn
Remark
358
n = 0 to 2
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11.2.3 Control registers
(1) Asynchronous serial interface mode registers 0 to 2 (ASIM0 to ASIM2)
These are 8-bit registers for controlling the transfer operations of UART0 to UART2.
These registers can be read or written in 8-bit or 1-bit units.
Caution
To use UARTn, set clock select register n (CKSRn) and baud rate generator control register
n (BRGCn). Then set the UARTCAEn bit to 1 before setting the other bits.
(1/3)
<7>
<6>
<5>
4
3
2
1
0
Address
After reset
ASIM0
UARTCAE0
TXE0
RXE0
PS01
PS00
CL0
SL0
ISRM0
FFFFFA00H
01H
ASIM1
UARTCAE1
TXE1
RXE1
PS11
PS10
CL1
SL1
ISRM1
FFFFFA10H
01H
ASIM2
UARTCAE2
TXE2
RXE2
PS21
PS20
CL2
SL2
ISRM2
FFFFFA20H
01H
Bit position
7
Bit name
UARTCAEn
(n = 0 to 2)
Function
Clock Enable
Controls the operation clock (n = 0 to 2).
0: Stops supply of clocks to UARTn unit
1: Supplies clocks to UARTn unit
Cautions 1. When the UARTCAEn bit is set to 0, the UARTn unit can be
asynchronously reset.
2. When UARTCAEn = 0, the UARTn unit is in a reset state.
Therefore, to operate UARTn, the UARTCAEn bit must be set to
1.
3. When the UARTCAEn bit is changed from 1 to 0, all registers of
the UARTn unit are initialized. When the UARTCAEn is set to 1
again, the UARTn unit registers must be set again.
The TXDn pin output is always high level in the transmission disable state,
irrespective of the setting of the UARTCAEn bit.
6
TXEn
(n = 0 to 2)
Transmit Enable
Specifies whether transmission is enabled or disabled.
0: Transmission is disabled
1: Transmission is enabled
Cautions 1. On startup, set UARTCAEn to 1 and then set TXEn to 1. Also,
always set UARTCAEn to 0 after setting TXEn to 0.
2. When the transmission unit status is to be initialized, the
transmission status may not be able to be initialized unless the
TXEn bit is set (1) again after an interval of two cycles of the
basic clock has elapsed since the TXEn bit was cleared (0) (For
the basic clock, see 11.2.6 (1) (a) Basic clock (Clock)).
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(2/3)
Bit position
5
Bit name
RXEn
(n = 0 to 2)
Function
Receive Enable
Specifies whether reception is enabled or disabled.
0: Reception is disabled
1: Reception is enabled
Cautions 1. On startup, set UARTCAEn to 1 and then set RXEn to 1. Also,
always set UARTCAEn to 0 after setting RXEn to 0.
2. When the reception unit status is to be initialized, the reception
status may not be able to be initialized unless the RXEn bit is
set (1) again after an interval of two cycles of the basic clock
has elapsed since the RXEn bit was cleared (0) (For the basic
clock, see 11.2.6 (1) (a) Basic clock (Clock)) .
4, 3
PSn1, PSn0
(n = 0 to 2)
Parity Select
Controls the parity bit.
PSn1
PSn0
Transmit operation
Receive operation
0
0
Do not output a parity bit
Receive with no parity
0
1
Output 0 parity
Receive as 0 parity
1
0
Output odd parity
Judge as odd parity
1
1
Output even parity
Judge as even parity
Cautions 1. To overwrite the PSn1 and PSn0 bits, first clear (0) the TXEn and
RXEn bits.
2. If “0 parity” is selected for reception, no parity judgement is
made. Therefore, no error interrupt is generated because the
PEn bit of the ASISn register is not set.
• Even parity
If the transmit data contains an odd number of bits with the value “1”, the parity
bit is set (1). If it contains an even number of bits with the value “1”, the parity
bit is cleared (0). This controls the number of bits with the value “1” contained
in the transmit data and the parity bit so that it is an even number.
During reception, the number of bits with the value “1” contained in the receive
data and the parity bit is counted, and if the number is odd, a parity error is
generated.
• Odd parity
In contrast to even parity, odd parity controls the number of bits with the value
“1” contained in the transmit data and the parity bit so that it is an odd number.
During reception, the number of bits with the value “1” contained in the receive
data and the parity bit is counted, and if the number is even, a parity error is
generated.
• 0 parity
During transmission, the parity bit is cleared (0) regardless of the transmit data.
During reception, no parity error is generated because no parity bit is checked.
• No parity
No parity bit is added to transmit data.
During reception, the receive data is considered to have no parity bit. No parity
error is generated because there is no parity bit.
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(3/3)
Bit position
2
Bit name
CLn
(n = 0 to 2)
Function
Character Length
Specifies the character length of the transmit/receive data.
0: 7 bits
1: 8 bits
Caution To overwrite the CLn bit, first clear (0) the TXEn and RXEn bits.
1
SLn
(n = 0 to 2)
Stop Bit Length
Specifies the stop bit length of the transmit data.
0: 1 bit
1: 2 bits
Cautions 1. To overwrite the SLn bit, first clear (0) the TXEn bit.
2. Since reception always operates by using a single stop bit, the
SLn bit setting does not affect receive operations.
0
ISRMn
(n = 0 to 2)
Interrupt Serial Receive Mode
Specifies whether the generation of reception completion interrupt requests when
an error occurs is enable or disabled.
0: An error interrupt request (INTSERn) is generated when an error occurs. In
this case, no reception completion interrupt request (INTSRn) is generated.
1: A reception completion interrupt request (INTSRn) is generated when an
error occurs. In this case, no error interrupt request (INTSERn) is generated.
Caution To overwrite the ISRMn bit, first clear (0) the RXEn bit.
Remark
When reception is disabled, the receive shift register does not detect a start bit.
No shift-in
processing or transfer processing to the receive buffer is performed, and the contents of the receive
buffer are retained.
When reception is enabled, the receive shift operation starts, in synchronization with the detection of
the start bit, and when the reception of one frame is completed, the contents of the receive shift
register are transferred to the receive buffer. A reception completion interrupt (INTSRn) is also
generated, in synchronization with the transfer to the receive buffer.
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(2) Asynchronous serial interface status registers 0 to 2 (ASIS0 to ASIS2)
These registers, which consist of 3-bit error flags (PEn, FEn, and OVEn), indicate the error status when
UARTn reception is completed (n = 0 to 2).
The status flag, which indicates a reception error, always indicates the status of the error that occurred most
recently. That is, if the same error occurred several times before the receive data was read, this flag would
hold only the status of the error that occurred last.
The ASISn register is cleared to 00H by a read operation. When a reception error occurs, the receive buffer
(RXBn) should be read after the ASISn register is read.
These registers are read-only in 8-bit units.
Caution
When the UARTCAEn bit or RXEn bit of the ASIMn register is set to 0, or when the ASISn
register is read, the PEn, FEn, and OVEn bits of the ASISn register are cleared (0).
7
6
5
4
3
2
1
0
Address
After reset
ASIS0
0
0
0
0
0
PE0
FE0
OVE0
FFFFFA03H
00H
ASIS1
0
0
0
0
0
PE1
FE1
OVE1
FFFFFA13H
00H
ASIS2
0
0
0
0
0
PE2
FE2
OVE2
FFFFFA23H
00H
Bit position
2
Bit name
PEn
(n = 0 to 2)
Function
Parity Error
This is a status flag that indicates a parity error.
0: When reception was completed, the transmit data parity matched the
parity bit
1: When reception was completed, the transmit data parity did not match
the parity bit
Caution The operation of the PEn bit differs according to the settings of the
PSn1 and PSn0 bits of the ASIMn register.
1
FEn
(n = 0 to 2)
Framing Error
This is a status flag that indicates a framing error.
0: When reception was completed, a stop bit was detected
1: When reception was completed, no stop bit was detected
Caution For receive data stop bits, only the first bit is checked regardless
of the number of stop bits.
0
OVEn
(n = 0 to 2)
Overrun Error
This is a status flag that indicates an overrun error.
0: The receive operation of one receive data value was completed or the
receive operation of the next receive data value was in progress.
1: UARTn completed the next receive operation before reading the RXBn
receive data.
Caution When an overrun error occurs, the next receive data value is not
written to the RXBn register and the data is discarded.
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(3) Asynchronous serial interface transmission status registers 0 to 2 (ASIF0 to ASIF2)
These registers, which consist of 2-bit status flags, indicate the status during transmission.
By writing the next data to the TXBn register after data is transferred from the TXBn register to the TXSn
register, transmit operations can be performed continuously without suspension even during an interrupt
interval. When transmission is performed continuously, data should be written after referencing the ASIFn
register to prevent writing to the TXBn register by mistake.
These registers are read-only in 8-bit or 1-bit units.
n = 0 to 2
Remark
7
6
5
4
3
2
<1>
<0>
Address
After reset
ASIF0
0
0
0
0
0
0
TXBF0
TXSF0
FFFFFA05H
00H
ASIF1
0
0
0
0
0
0
TXBF1
TXSF1
FFFFFA15H
00H
ASIF2
0
0
0
0
0
0
TXBF2
TXSF2
FFFFFA25H
00H
Bit position
Bit name
1
TXBFn
(n = 0 to 2)
Function
Transmit Buffer Flag
This is a transmit buffer data flag.
0: No data exists in TXBn
1: Data exists in TXBn
Caution When UARTCAEn = 0 and TXEn = 0 in the ASIMn register, the
TXBFn bit is cleared (0).
0
TXSFn
(n = 0 to 2)
Transmit Shift Flag
This is a transmit shift register data flag. It indicates the transmission status of
UARTn.
0: Transmission completed or awaiting transmission
1: Transmission in progress
Caution When UARTCAEn = 0 and TXEn = 0 in the ASIMn register, the
TXSFn bit is cleared (0).
The following table shows relationship between the transmission status and write operations to TXBn.
TXBFn
TXSFn
0
0
Initial status or transmission completed
Writing is permitted
0
1
Transmission in progress (no data is in TXBn)
Writing is permitted
1
0
Awaiting transmission (data is in TXBn)
Writing is not permitted
1
1
Transmission in progress (data is in TXBn)
Writing is not permitted
Caution
Transmission Status
Write Operation to TXBn
When transmission is performed continuously, data should be written to TXBn after
confirming the TXBFn value. If writing is not enabled, operation cannot be guaranteed
when data is written to TXBn.
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(4) Receive buffer registers 0 to 2 (RXB0 to RXB2)
These are 8-bit buffer registers for storing parallel data that had been converted by the receive shift register.
When reception is enabled (RXEn = 1 in the ASIMn register), receive data is transferred from the receive shift
register to the receive buffer, in synchronization with the completion of the shift-in processing of one frame.
Also, a reception completion interrupt request (INTSRn) is generated by the transfer to the receive buffer.
For information about the timing for generating these interrupt requests, see 11.2.5 (4) Receive operation.
If reception is disabled (RXEn = 0 in the ASIMn register), the contents of the receive buffer are retained, and
no processing is performed for transferring data to the receive buffer even when the shift-in processing of one
frame is completed. Also, no reception completion interrupt is generated.
When 7 bits is specified for the data length, bits 6 to 0 of the RXBn register are transferred for the receive
data and the MSB (bit 7) is always 0. However, if an overrun error occurs, the receive data at that time is not
transferred to the RXBn register.
Except when a reset is input, the RXBn register becomes FFH even when UARTCAEn = 0 in the ASIMn
register.
These registers are read-only in 8-bit units.
Remark
n = 0 to 2
7
6
5
4
3
2
1
0
Address
After reset
RXB0
RXB07
RXB06
RXB05
RXB04
RXB03
RXB02
RXB01
RXB00
FFFFFA02H
FFH
RXB1
RXB17
RXB16
RXB15
RXB14
RXB13
RXB12
RXB11
RXB10
FFFFFA12H
FFH
RXB2
RXB27
RXB26
RXB25
RXB24
RXB23
RXB22
RXB21
RXB20
FFFFFA22H
FFH
Bit position
7 to 0
364
Bit name
RXBn7 to
RXBn0
(n = 0 to 2)
Function
Receive Buffer
Stores receive data.
0 can be read for RXBn7 when 7-bit character data is received.
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(5) Transmit buffer registers 0 to 2 (TXB0 to TXB2)
These are 8-bit buffer registers for setting transmit data.
When transmission is enabled (TXEn = 1 in the ASIMn register), the transmit operation is started by writing
data to TXBn.
When transmission is disabled (TXEn = 0 in the ASIMn register), even if data is written to TXBn, the value is
ignored.
The TXBn data is transferred to the transmit shift register, and a transmission completion interrupt request
(INTSTn) is generated, in synchronization with the completion of the transmission of one frame from the
transmit shift register. For information about the timing for generating these interrupt requests, see 11.2.5 (2)
Transmit operation.
When TXBFn = 1 in the ASIFn register, writing must not be performed to TXBn.
These registers can be read or written in 8-bit units.
Remark
n = 0 to 2
7
6
5
4
3
2
1
0
Address
After reset
TXB0
TXB07
TXB06
TXB05
TXB04
TXB03
TXB02
TXB01
TXB00
FFFFFA04H
FFH
TXB1
TXB17
TXB16
TXB15
TXB14
TXB13
TXB12
TXB11
TXB10
FFFFFA14H
FFH
TXB2
TXB27
TXB26
TXB25
TXB24
TXB23
TXB22
TXB21
TXB20
FFFFFA24H
FFH
Bit position
7 to 0
Bit name
TXBn7 to
TXBn0
(n = 0 to 2)
Function
Transmit Buffer
Writes transmit data.
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11.2.4 Interrupt requests
The following three types of interrupt requests are generated from UARTn (n = 0 to 2).
• Reception error interrupt (INTSERn)
• Reception completion interrupt (INTSRn)
• Transmission completion interrupt (INTSTn)
The default priorities among these three types of interrupt requests is, from high to low, reception error interrupt,
reception completion interrupt, and transmission completion interrupt.
Table 11-1. Generated Interrupts and Default Priorities
Interrupt
Priority
Reception error
1
Reception completion
2
Transmission completion
3
(1) Reception error interrupt (INTSERn)
When reception is enabled, a reception error interrupt is generated according to the logical OR of the three
types of reception errors explained for the ASISn register. Whether a reception error interrupt (INTSERn) or
a reception completion interrupt (INTSRn) is generated when an error occurs can be specified using the
ISRMn bit of the ASIMn register.
When reception is disabled, no reception error interrupt is generated.
(2) Reception completion interrupt (INTSRn)
When reception is enabled, a reception completion interrupt is generated when data is shifted in to the
receive shift register and transferred to the receive buffer.
A reception completion interrupt request can be generated in place of a reception error interrupt according to
the ISRMn bit of the ASIMn register even when a reception error has occurred.
When reception is disabled, no reception completion interrupt is generated.
(3) Transmission completion interrupt (INTSTn)
A transmission completion interrupt is generated when one frame of transmit data containing 7-bit or 8-bit
characters is shifted out from the transmit shift register.
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11.2.5 Operation
(1) Data format
Full-duplex serial data transmission and reception can be performed.
The transmit/receive data format consists of one data frame containing a start bit, character bits, a parity bit,
and stop bits as shown in Figure 11-2.
The character bit length within one data frame, the type of parity, and the stop bit length are specified by the
asynchronous serial interface mode register n (ASIMn) (n = 0 to 2).
Also, data is transferred with the least significant bit (LSB) first.
Figure 11-2. Asynchronous Serial Interface Transmit/Receive Data Format
1 data frame
Start
bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity
bit
Stop bits
Character bits
• Start bit ··· 1 bit
• Character bits ··· 7 bits or 8 bits
• Parity bit ··· Even parity, odd parity, 0 parity, or no parity
• Stop bits ··· 1 bit or 2 bits
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(2) Transmit operation
When UARTCAEn is set to 1 in the ASIMn register, a high level is output to the TXDn pin.
Then, when TXEn is set to 1 in the ASIMn register, transmission is enabled, and the transmit operation is
started by writing transmit data to transmit buffer register n (TXBn) (n = 0 to 2).
(a) Transmission enabled state
This state is set by the TXEn bit in the ASIMn register (n = 0 to 2).
• TXEn = 1: Transmission enabled state
• TXEn = 0: Transmission disabled state
However, when the transmission enabled state is set, to use UART0 and UART1, which share pins with
clocked serial interfaces 0 and 1 (CSI0 and CSI1), the CSICAEn bit of clocked serial interface mode
registers 0 and 1 (CSIM0 and CSIM1) should be set to 0.
Since UARTn does not have a CTS (transmission enabled signal) input pin, a port should be used to
confirm whether the destination is in a reception enabled state.
(b) Starting a transmit operation
In the transmission enabled state, a transmit operation is started by writing transmit data to transmit
buffer register n (TXBn). When a transmit operation is started, the data in TXBn is transferred to transmit
shift register n (TXSn). Then, the TXSn register outputs data to the TXDn pin sequentially beginning with
the LSB (the transmit data is transferred sequentially starting with the start bit). The start bit, parity bit,
and stop bits are added automatically (n = 0 to 2).
(c) Transmission interrupt request
When the transmit shift register (TXSn) becomes empty, a transmission completion interrupt request
(INTSTn) is generated.
The timing for generating the INTSTn interrupt differs according to the
specification of the number of stop bits. The INTSTn interrupt is generated at the same time that the last
stop bit is output (n = 0 to 2).
If the data to be transmitted next has not been written to the TXBn register, the transmit operation is
suspended.
Caution
Normally, when transmit shift register n (TXSn) becomes empty, a transmission
completion interrupt (INTSTn) is generated.
However, no transmission completion
interrupt (INTSTn) is generated if transmit shift register n (TXSn) becomes empty due to
the input of a RESET.
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Figure 11-3. Asynchronous Serial Interface Transmission Completion Interrupt Timing
(a) Stop bit length: 1
Start
TXDn (output)
D0
D1
D2
D6
D7
Parity
D6
D7
Parity
Stop
INTSTn (output)
(b) Stop bit length: 2
TXDn (output)
Start
D0
D1
D2
Stop
INTSTn (output)
Remark
n = 0 to 2
(3) Continuous transmission operation
UARTn can write the next data to the TXBn register at the time that the TXSn register starts the shift
operation. This enables an efficient transmission rate to be realized by continuously transmitting data even
during interrupt servicing after the transmission of one data frame (n = 0 to 2).
When continuous transmission is performed, data should be written after referencing the ASIFn register to
confirm the transmission status and whether or not data can be written to the TXBn register (n = 0 to 2).
Caution
Transmit data should be written when the TXBFn bit is 0. The transmission unit should be
initialized when the TXSFn bit is 0.
If these actions are performed at other times, the
transmit data cannot be guaranteed.
Table 11-2. Transmission Status and Whether or Not Writing Is Enabled
TXBFn
TXSFn
0
0
Initial status or transmission completed
Writing is enabled
0
1
Transmission in progress (no data is in TXBn register)
Writing is enabled
1
0
Awaiting transmission (data is in TXBn register)
Writing is not enabled
1
1
Transmission in progress (data is in TXBn register)
Writing is not enabled
Remark
Transmission Status
Whether or Not Write Operation
to TXBn Is Enabled
n = 0 to 2
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CHAPTER 11 SERIAL INTERFACE FUNCTION
(a) Starting procedure
The procedure for starting continuous transmission is shown below.
Figure 11-4. Continuous Transmission Starting Procedure
Start
bit
TXDn (output)
<1>
Stop
bit
<3>
Data (1)
<2>
Start
bit
Data (2)
<4>
Stop
bit
<5>
INTSTn (output)
TXBn register
TXSn register
ASIFn register
(TXBFn and TXSFn bits)
Remark
Data (1)
FFH
Data (3)
Data (1)
FFH
00
Data (2)
10
01
Data (2)
11
01
Data (3)
11
01
11
n = 0 to 2
Transmission starting procedure
Internal operation
• Set transmission mode
<1> Start transmission unit
• Write data (1)
<2> Generate start bit
Start data (1) transmission
ASIFn register
TXBFn
TXSFn
0
0
1
0
0
1
1
1
0
1
1
1
0
1
1
1
• Read ASIFn register (confirm that TXBFn bit = 0)
• Write data (2)
<<Transmission in progress>>
<3> Generate INTSTn interrupt
• Read ASIFn register (confirm that TXBFn bit = 0)
• Write data (3)
<4> Generate start bit
Start data (2) transmission
<<Transmission in progress>>
<5> Generate INTSTn interrupt
• Read ASIFn register (confirm that TXBFn bit = 0)
• Write data (4)
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(b) Ending procedure
The procedure for ending continuous transmission is shown below.
Figure 11-5. Continuous Transmission Ending Procedure
Start
bit
TXDn (output)
<6>
<7>
Stop
bit
<9>
Data (m – 1)
<8>
Start
bit
Data (m)
<10>
Stop
bit
<11>
INTSTn (output)
TXBn register
TXSn register
ASIFn register
(TXBFn and TXSFn bits)
Data (m)
Data (m – 1)
Data (m – 1)
11
01
Data (m)
11
FFH
01
00
UARTCAEn bit or TXEn bit
Remark
n = 0 to 2
Transmission ending procedure
Internal operation
ASIFn register
TXBFn
TXSFn
<6> Transmission of data (m − 2) is in progress
1
1
<7> Generate INTST interrupt
0
1
1
1
0
1
0
0
• Read ASIFn register (confirm that the TXBFn bit = 0)
• Write data (n)
<8> Generate start bit
Start data (m − 1) transmission
<<Transmission in progress>>
<9> Generate INTSTn interrupt
• Read ASIFn register (confirm that the TXSFn bit = 1)
There is no write data
<10> Generate start bit
Start data (m) transmission
<<Transmission in progress>>
<11> Generate INTSTn interrupt
• Read ASIFn register (confirm that the TXSFn bit = 0)
• Clear (0) the UARTCAEn bit or TXEn bit
Initialize internal circuits
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(4) Receive operation
The awaiting reception state is set by setting UARTCAEn to 1 in the ASIMn register and then setting RXEn to
1 in the ASIMn register. RXDn pin sampling begins and a start bit is detected. When the start bit is detected,
the receive operation begins, and data is stored sequentially in the receive shift register according to the baud
rate that was set. A reception completion interrupt (INTSRn) is generated each time the reception of one
frame of data is completed. Normally, the receive data is transferred from the receive buffer (RXBn) to
memory by this interrupt servicing (n = 0 to 2).
(a) Reception enabled state
The receive operation is set to the reception enabled state by setting the RXEn bit in the ASIMn register
to 1 (n = 0 to 2).
• RXEn = 1: Reception enabled state
• RXEn = 0: Reception disabled state
However, when the reception enabled state is set, to use UART0 and UART1, which share pins with
clocked serial interfaces 0 and 1 (CSI0 and CSI1), the operation of CSIn must be disabled by setting the
CSICAEn bit of clocked serial interface mode registers 0 and 1 (CSIM0 and CSIM1) to 0 (n = 0 to 2).
In the reception disabled state, the reception hardware stands by in the initial state. At this time, the
contents of the receive buffer are retained, and no reception completion interrupt or reception error
interrupt is generated.
(b) Starting a receive operation
A receive operation is started by the detection of a start bit.
The RXDn pin is sampled using the serial clock from the baud rate generator (BRGn) (n = 0 to 2).
(c) Reception completion interrupt
When RXEn = 1 in the ASIMn register and the reception of one frame of data is completed (the stop bit is
detected), a reception completion interrupt (INTSRn) is generated and the receive data within the receive
shift register is transferred to RXBn at the same time (n = 0 to 2).
Also, if an overrun error occurs, the receive data at that time is not transferred to the receive buffer
(RXBn), and either a reception completion interrupt (INTSRn) or a reception error interrupt (INTSERn) is
generated (the receive data within the receive shift register is transferred to RXBn) according to the
ISRMn bit setting in the ASIMn register.
Even if a parity error or framing error occurs during a reception operation, the receive operation
continues, and after reception is completed, either a reception completion interrupt (INTSRn) or a
reception error interrupt (INTSERn) is generated according to the ISRMn bit setting in the ASIMn register.
If the RXEn bit is reset (0) during a receive operation, the receive operation is immediately stopped. The
contents of the receive buffer (RXBn) and of the asynchronous serial interface status register (ASISn) at
this time do not change, and no reception completion interrupt (INTSRn) or reception error interrupt
(INTSERn) is generated.
No reception completion interrupt is generated when RXEn = 0 (reception is disabled).
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Figure 11-6. Asynchronous Serial Interface Reception Completion Interrupt Timing
Start
RXDn (input)
D0
D1
D2
D6
D7
Parity
Stop
INTSRn (output)
RXBn register
Remark
n = 0 to 2
(5) Reception error
The three types of errors that can occur during a receive operation are a parity error, framing error, and
overrun error. The data reception result is that the various flags of the ASISn register are set (1), and a
reception error interrupt (INTSERn) or a reception completion interrupt (INTSRn) is generated at the same
time. The ISRMn bit of the ASIMn register specifies whether INTSERn or INTSRn is generated.
The type of error that occurred during reception can be ascertained by reading the contents of the ASISn
register during the INTSERn or INTSRn interrupt servicing.
The contents of the ASISn register are reset (0) by reading the ASISn register (if the next reception data
contains an error, the corresponding error flag is set (1)).
Table 11-3. Reception Error Causes
Error Flag
Reception Error
Cause
PEn
Parity error
The parity specification during transmission did not match
the parity of the reception data
FEn
Framing error
No stop bit was detected
OVEn
Overrun error
The reception of the next data was completed before data
was read from the receive buffer
Remark
n = 0 to 2
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CHAPTER 11 SERIAL INTERFACE FUNCTION
(a) Separation of reception error interrupt
A reception error interrupt can be separated from the INTSRn interrupt and generated as an INTSERn
interrupt by clearing the ISRMn bit of the ASIMn register (n = 0 to 2) to 0.
Figure 11-7. When Reception Error Interrupt Is Separated from INTSRn Interrupt (ISRMn Bit = 0)
(a) No error occurs during reception
(b) An error occurs during reception
INTSRn (output)
(Reception completion
interrupt)
INTSRn (output)
(Reception completion
interrupt)
INTSERn (output)
(Reception error
interrupt)
INTSERn (output)
(Reception error
interrupt)
Remark
n = 0 to 2
Figure 11-8. When Reception Error Interrupt Is Included in INTSRn Interrupt (ISRMn Bit = 1)
(a) No error occurs during reception
INTSRn (output)
(Reception completion
interrupt)
INTSRn (output)
(Reception completion
interrupt)
INTSERn (output)
(Reception error
interrupt)
INTSERn (output)
(Reception error
interrupt)
Remark
374
(b) An error occurs during reception
n = 0 to 2
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CHAPTER 11 SERIAL INTERFACE FUNCTION
(6) Parity types and corresponding operation
A parity bit is used to detect a bit error in communication data. Normally, the same type of parity bit is used at
the transmission and reception sides.
(a) Even parity
(i) During transmission
The parity bit is controlled so that the number of bits with the value “1” within the transmit data
including the parity bit is even. The parity bit value is as follows.
• If the number of bits with the value “1” within the transmit data is odd: 1
• If the number of bits with the value “1” within the transmit data is even: 0
(ii) During reception
The number of bits with the value “1” within the receive data including the parity bit is counted, and a
parity error is generated if this number is odd.
(b) Odd parity
(i) During transmission
In contrast to even parity, the parity bit is controlled so that the number of bits with the value “1”
within the transmit data including the parity bit is odd. The parity bit value is as follows.
• If the number of bits with the value “1” within the transmit data is odd: 0
• If the number of bits with the value “1” within the transmit data is even: 1
(ii) During reception
The number of bits with the value “1” within the receive data including the parity bit is counted, and a
parity error is generated if this number is even.
(c) 0 parity
During transmission the parity bit is set to “0” regardless of the transmit data.
During reception, no parity bit check is performed. Therefore, no parity error is generated regardless of
whether the parity bit is “0” or “1”.
(d) No parity
No parity bit is added to the transmit data.
During reception, the receive operation is performed as if there were no parity bit. Since there is no
parity bit, no parity error is generated.
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CHAPTER 11 SERIAL INTERFACE FUNCTION
(7) Receive data noise filter
The RXDn signal is sampled at the rising edge of the prescaler output clock. If the same sampling value is
obtained twice, the match detector output changes, and this output is sampled as input data. Therefore, data
not exceeding one clock width is judged to be noise and is not delivered to the internal circuit (see Figure 1110). See 11.2.6 (1) (a) Basic clock (Clock) regarding the basic clock.
Also, since the circuit is configured as shown in Figure 11-9, internal processing during a receive operation is
delayed by up to 2 clocks according to the external signal status.
Figure 11-9. Noise Filter Circuit
Clock
In
RXDn
Q
Internal signal A
Match detector
Remark
In
Q
Internal signal B
LD_EN
n = 0 to 2
Figure 11-10. Timing of RXDn Signal Judged as Noise
Clock
RXDn (input)
Internal signal A
Match
Mismatch
(judged as noise)
Internal signal B
Remark
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Match
Mismatch
(judged as noise)
CHAPTER 11 SERIAL INTERFACE FUNCTION
11.2.6 Dedicated baud rate generators 0 to 2 (BRG0 to BRG2)
A dedicated baud rate generator, which consists of a source clock selector and an 8-bit programmable counter,
generates serial clocks during transmission/reception in UARTn. The dedicated baud rate generator output can be
selected as the serial clock for each channel.
Separate 8-bit counters exist for transmission and for reception.
(1) Baud rate generator configuration
Figure 11-11. Baud Rate Generator Configuration
UARTCAEn
φ
φ /2
φ /4
UARTCAEn and TXEn (or RXEn)
φ /8
φ /16
φ /32
φ /64
Selector
Clock
8-bit counter
(fXCLK)
φ /128
φ /256
φ /512
φ /1,024
φ /2,048
Match detector
CKSRn: TPSn3 to TPSn0
1/2
Baud rate
BRGCn: BRGn7 to BRGn0
(a) Basic clock (Clock)
When UARTCAEn = 1 in the ASIMn register, the clock selected according to the TPSn3 to TPSn0 bits of
the CKSRn register is supplied to the transmission/reception unit. This clock is called the basic clock,
and its frequency is referred to as fXCLK. When UARTCAEn = 0, the clock signal is fixed at low level.
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CHAPTER 11 SERIAL INTERFACE FUNCTION
(2) Serial clock generation
A serial clock can be generated according to the settings of the CKSRn and BRGCn registers (n = 0 to 2).
The clock input to the 8-bit counter is selected according to the TPSn3 to TPSn0 bits of the CKSRn register.
The 8-bit counter divisor value can be selected according to the BRGn7 to BRGn0 bits of the BRGCn
register.
(a) Clock select registers 0 to 2 (CKSR0 to CKSR2)
The CKSRn register is an 8-bit register for selecting the input block according to the TPSn3 to TPSn0
bits. The clock selected by the TPSn3 to TPSn0 bits becomes the basic clock of the transmission/
reception module. Its frequency is referred to as fXCLK.
These registers can be read or written in 8-bit units.
Caution
The maximum allowable frequency of the basic clock (fXCLK) is 25 MHz. Therefore,
when the system clock’s frequency is 50 MHz, bits TPSn3 to TPSn0 cannot be set to
0000B (n = 0 to 2).
If the system clock frequency is 50 MHz, set the TPSn3 to TPSn0 bits to a value other
than 0000B and set the UARTCAEn bit of the ASIMn register to 1.
7
6
5
4
3
2
1
0
Address
After reset
CKSR0
0
0
0
0
TPS03
TPS02
TPS01
TPS00
FFFFFA06H
00H
CKSR1
0
0
0
0
TPS13
TPS12
TPS11
TPS10
FFFFFA16H
00H
CKSR2
0
0
0
0
TPS23
TPS22
TPS21
TPS20
FFFFFA26H
00H
Bit position
3 to 0
378
Bit name
TPSn3 to
TPSn0
(n = 0 to 2)
Function
Specifies the basic clock
TPSn3
TPSn2
TPSn1
TPSn0
Basic clock (fXCLK)
0
0
0
0
φ
0
0
0
1
φ/2
0
0
1
0
φ/4
0
0
1
1
φ/8
0
1
0
0
φ/16
0
1
0
1
φ/32
0
1
1
0
φ/64
0
1
1
1
φ/128
1
0
0
0
φ/256
1
0
0
1
φ/512
1
0
1
0
φ/1,024
1
0
1
1
φ/2,048
1
1
Arbitrary Arbitrary Setting prohibited
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CHAPTER 11 SERIAL INTERFACE FUNCTION
(b) Baud rate generator control registers 0 to 2 (BRGC0 to BRGC2)
The BRGCn register is an 8-bit register that controls the baud rate (serial transfer speed) of UARTn.
These registers can be read or written in 8-bit units.
Caution
If the BRGn7 to BRGn0 bits are to be overwritten, TXEn and RXEn should be set to 0
in the ASIMn register first (n = 0 to 2).
7
6
5
4
3
2
1
0
Address
After reset
BRGC0
MDL07
MDL06
MDL05
MDL04
MDL03
MDL02
MDL01
MDL00
FFFFFA07H
FFH
BRGC1
MDL17
MDL16
MDL15
MDL14
MDL13
MDL12
MDL11
MDL10
FFFFFA17H
FFH
BRGC2
MDL27
MDL26
MDL25
MDL24
MDL23
MDL22
MDL21
MDL20
FFFFFA27H
FFH
Bit position
7 to 0
Bit name
BRGn7 to
BRGn0
(n = 0 to 2)
Function
Specifies the 8-bit counter’s divisor value.
BRG n7 BRG n6 BRG n5 BRG n4 BRG n3 BRG n2 BRG n1 BRG n0
Divisor
value (k)
Serial clock
0
0
0
0
0
x
x
x
–
Setting
prohibited
0
0
0
0
1
0
0
0
8
fXCLK/8
0
0
0
0
1
0
0
1
9
fXCLK/9
0
0
0
0
1
0
1
0
10
fXCLK/10
…
…
…
…
…
…
…
…
…
…
1
1
1
1
1
0
1
0
250
fXCLK/250
1
1
1
1
1
0
1
1
251
fXCLK/251
1
1
1
1
1
1
0
0
252
fXCLK/252
1
1
1
1
1
1
0
1
253
fXCLK/253
1
1
1
1
1
1
1
0
254
fXCLK/254
1
1
1
1
1
1
1
1
255
fXCLK/255
Remarks 1. fXCLK: Frequency of clock selected according to TPSn3 to TPSn0 bits of CKSRn register.
2. k: Value set according to BRGn7 to BRGn0 bits (k = 8, 9, 10, ..., 255)
3. x: don’t care
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CHAPTER 11 SERIAL INTERFACE FUNCTION
(c) Baud rate
The baud rate is the value obtained according to the following formula.
Baud rate =
fXCLK
2 ×k
[bps]
fXCLK = Frequency of basic clock selected according to TPSn3 to TPSn0 bits of CKSRn register.
k = Value set according to BRGn7 to BRGn0 bits of BRGCn register (k = 8, 9, 10, ..., 255)
(d) Baud rate error
The baud rate error is obtained according to the following formula.
Error (%) =
 Actual baud rate (baud rate with

 Desired baud rate (normal baud
error)
rate)

− 1
 × 100 [%]

Cautions 1. Make sure that the baud rate error during transmission does not exceed the allowable
error of the reception destination.
2. Make sure that the baud rate error during reception is within the allowable baud rate
range during reception, which is described in paragraph (4).
Example: Basic clock frequency = 20 MHz = 20,000,000 Hz
Settings of BRGn7 to BRGn0 bits in BRGCn register = 01000001B (k = 65)
Target baud rate = 153,600 bps
Baud rate = 20 M/(2 × 65)
= 20,000,000/(2 × 65) = 153,846 [bps]
Error = (153,846/153,600 − 1) × 100
= 0.160 [%]
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(3) Baud rate setting example
Table 11-4. Baud Rate Generator Setting Data
Baud Rate
(bps)
φ = 50 MHz
fXCLK
k
φ = 40 MHz
ERR
fXCLK
0.15
φ/2
0.15
φ/2
0.15
φ/2
0.15
φ/2
0.15
φ/2
k
φ = 33 MHz
ERR
fXCLK
0.16
φ/2
0.16
φ/2
0.16
φ/2
0.16
φ/2
0.16
φ/2
k
φ = 10 MHz
ERR
fXCLK
k
ERR
–0.07
φ/2
130
0.16
–0.07
φ/2
130
0.16
–0.07
φ/2
130
0.16
–0.07
φ/2
130
0.16
–0.07
φ/2
130
0.16
300
φ/2
600
φ/2
1,200
φ/2
2,400
φ/2
4,800
φ/2
9,600
φ/2
163
0.15
φ/2
65
0.16
φ/2
215
–0.07
φ/2
130
0.16
19,200
φ/23
163
0.15
φ/24
80
0.16
φ/22
215
–0.07
φ/21
130
0.16
31,250
φ/2
0
φ/2
0
φ/2
0
φ/2
80
0
38,400
φ/2
0.15
φ/2
0.16
φ/2
–0.07
φ/2
130
0.16
76,800
φ/2
0.47
φ/2
0.16
φ/2
0.39
φ/2
65
0.16
153,600
φ/2
81
0.47
φ/2
65
0.16
φ/2
54
–0.54
φ/2
33
–1.36
312,500
φ/21
40
0
φ/21
32
0
φ/21
26
1.54
φ/20
16
0
9
8
7
6
5
4
3
2
2
1
163
163
163
163
163
100
163
81
10
9
8
7
6
5
3
3
2
1
65
65
65
65
65
65
65
65
8
7
6
5
4
3
2
1
1
1
215
215
215
215
215
132
215
107
7
6
5
4
3
2
1
0
0
0
Caution The maximum allowable frequency of the basic clock (fXCLK) is 25 MHz.
Remarks φ:
System clock frequency
Clock: Input clock
k:
Settings of BRGn7 to BRGn0 bits in BRGCn register (n = 0 to 2)
ERR:
Baud rate error [%]
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(4) Allowable baud rate range during reception
The degree to which a discrepancy from the transmission destination’s baud rate is allowed during reception
is shown below.
Caution
The equations described below should be used to set the baud rate error during reception
so that it always is within the allowable error range.
Figure 11-12. Allowable Baud Rate Range During Reception
Latch timing
UARTn
transfer rate
Start bit
Bit 0
Bit 1
Bit 7
Parity bit
Stop bit
FL
1 data frame (11 × FL)
Minimum allowable
transfer rate
Start bit
Bit 0
Bit 1
Bit 7
Parity bit
Stop bit
FLmin
Maximum allowable
transfer rate
Start bit
Bit 0
Bit 1
Bit 7
Parity bit
Stop bit
FL
FLmax
n = 0 to 2
Remark
As shown in Figure 11-12, after the start bit is detected, the receive data latch timing is determined according
to the counter that was set by the BRGCn register. If all data up to the final data (stop bit) is in time for this
latch timing, the data can be received normally.
Applying this to 11-bit reception is, theoretically, as follows.
FL = (Brate)–1
Brate: UARTn baud rate (n = 0 to 2)
k:
BRGCn setting value (n = 0 to 2)
FL:
1-bit data length
Latch timing margin: 2 clocks
Minimum allowable transfer rate: FLmin = 11 × FL −
382
k−2
2k
User’s Manual U14359EJ3V0UM
× FL =
21k + 2
2k
FL
CHAPTER 11 SERIAL INTERFACE FUNCTION
Therefore, the maximum baud rate that can be received at the transfer destination is as follows.
BRmax = (FLmin/11)
−1
=
22 k
Brate
21k + 2
Similarly, the maximum allowable transfer rate can be obtained as follows.
10
11
k+2
× FLmax = 11 × FL −
FLmax =
21k − 2
2×k
× FL =
21k − 2
2×k
FL
FL × 11
20 k
Therefore, the minimum baud rate that can be received at the transfer destination is as follows.
BRmin = (FLmax/11)
−1
=
22 k
21k − 2
Brate
The allowable baud rate error of UARTn and the transfer destination can be obtained as follows from the
expressions described above for computing the minimum and maximum baud rate values.
Table 11-5. Maximum and Minimum Allowable Baud Rate Error
Division Ratio (k)
Maximum Allowable
Baud Rate Error
Minimum Allowable
Baud Rate Error
8
+3.53%
–3.61%
20
+4.26%
–4.31%
50
+4.56%
–4.58%
100
+4.66%
–4.67%
255
+4.72%
–4.73%
Remarks 1. The reception precision depends on the number of bits in one frame, the input clock frequency,
and the division ratio (k). The higher the input clock frequency and the larger the division ratio
(k), the higher the precision.
2. k: BRGCn setting value (n = 0 to 2)
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(5) Transfer rate during continuous transmission
During continuous transmission, the transfer rate from a stop bit to the next start bit is extended two clocks
longer than normal. However, on the reception side, the transfer result is not affected since the timing is
initialized by the detection of the start bit.
Figure 11-13. Transfer Rate During Continuous Transmission
Start bit of
second byte
1 data frame
Start bit
FL
Bit 0
Bit 1
Bit 7
FL
FL
FL
Parity bit
FL
Stop bit
FLstp
Start bit
FL
Bit 0
FL
Representing the 1-bit data length by FL, the stop bit length by FLstp, and the basic clock frequency by fXCLK
yields the following equation.
FLstp = FL + 2/fXCLK
Therefore, the transfer rate during continuous transmission is as follows.
Transfer rate = 11 × FL + 2/fXCLK
11.2.7 Cautions
When the supply of clocks to UARTn is stopped (for example, IDLE or STOP mode), operation stops with each
register retaining the value it had immediately before the supply of clocks was stopped. The TXDn pin output also
holds and outputs the value it had immediately before the supply of clocks was stopped. However, operation is not
guaranteed after the supply of clocks is restarted. Therefore, after the supply of clocks is restarted, the circuits should
be initialized by setting UARTCAEn = 0, RXEn = 0, and TXEn = 0.
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11.3 Clocked Serial Interfaces 0 to 2 (CSI0 to CSI2)
11.3.1 Features
• Transfer rate: Master mode: Maximum 3.125 Mbps (when internal system clock operates at 50 MHz)
Slave mode:
Maximum 5 Mbps (when internal system clock operates at 50 MHz)
• Half-duplex communications
• Master mode and slave mode can be selected
• Transmission data length: 8 bits
• Transfer data direction can be switched between MSB first and LSB first
• Eight clock signals can be selected (7 master clocks and 1 slave clock)
• 3-wire method
SOn:
Serial data output
SIn:
Serial data input
SCKn:
Serial clock input/output
• Interrupt sources: 1 type
• Transmission/reception completion interrupt (INTCSIn)
• Transmission/reception mode or reception-only mode can be specified
• On-chip transmit buffer (SOTBn)
Remark
n = 0 to 2
11.3.2 Configuration
CSIn is controlled by the clocked serial interface mode register (CSIMn) (n = 0 to 2). Transmit/receive data can be
read from or written to the SIOn register.
(1) Clocked serial interface mode registers 0 to 2 (CSIM0 to CSIM2)
The CSIMn register is an 8-bit register for specifying the operation of CSIn.
(2) Clocked serial interface clock selection registers 0 to 2 (CSIC0 to CSIC2)
The CSICn register is an 8-bit register for controlling the transmit operation of CSIn.
(3) Serial I/O shift registers 0 to 2 (SIO0 to SIO2)
The SIOn register is an 8-bit register for converting between serial data and parallel data. SIOn is used for
both transmission and reception.
Data is shifted in (reception) or shifted out (transmission) beginning at either the MSB side or the LSB side.
Actual transmit/receive operations are controlled by reading or writing SIOn.
(4) Clocked serial interface transmit buffer registers 0 to 2 (SOTB0 to SOTB2)
The SOTBn register is an 8-bit buffer register for storing transmit data.
(5) Selector
The selector selects the serial clock to be used.
(6) Serial clock controller
The serial clock controller controls the supply of serial clocks to the shift register. When an internal clock is
used, it also controls the clocks that are output to the SCKn pin.
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(7) Serial clock counter
The serial clock counter counts serial clocks that are output or input during transmit and receive operations
and checks that 8-bit data has been transmitted or received.
(8) Interrupt controller
The interrupt controller controls whether or not an interrupt request is generated when the serial clock counter
has counted eight serial clocks.
Figure 11-14. Clocked Serial Interface Block Diagram
φ /215
Serial clock controller
φ /214
φ /212
φ /210
φ /28
Clock start/stop control
&
clock phase control
Selector
φ /2
φ /24
6
SCKn
Interrupt
controller
INTCSIn
SCKn
Transmission control
Transmit data control
SIn
Remark
386
Control signal
Transmit data buffer
register n (SOTBn)
SO selection
Shift register n
(SIOn)
SO latch
n = 0 to 2
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CHAPTER 11 SERIAL INTERFACE FUNCTION
11.3.3 Control registers
(1) Clocked serial interface mode registers 0 to 2 (CSIM0 to CSIM2)
The CSIMn register controls the operation of CSIn (n = 0 to 2).
These registers can be read or written in 8-bit or 1-bit units.
Caution
To use CSIn, be sure to set the external pins related to the CSIn function to control mode
and set the CSICn register. Then set the CSICAEn bit to 1 before setting the other bits.
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<7>
<6>
5
<4>
3
2
1
<0>
Address
After reset
CSIM0
CSICAE0 TRMD0
0
DIR0
0
0
0
CSOT0
FFFFF900H
00H
CSIM1
CSICAE1 TRMD1
0
DIR1
0
0
0
CSOT1
FFFFF910H
00H
CSIM2
CSICAE2 TRMD2
0
DIR2
0
0
0
CSOT2
FFFFF920H
00H
Bit position
7
Bit name
CSICAEn
(n = 0 to 2)
Function
CSI Operation Permission/Prohibition
Specifies whether CSIn operation is enabled or disabled (n = 0 to 2).
0: CSIn operation is disabled (SOn = low level, SCKn = high level)
1: CSIn operation is enabled
Cautions 1. If CSICAEn is set to 0, the CSIn unit can be reset
asynchronously.
2. If CSICAEn = 0, the CSIn unit is in a reset state. Therefore, to
operate CSIn, CSICAEn must be set to 1.
3. If the CSICAEn bit is changed from 1 to 0, all registers of the
CSIn unit are initialized. To set CSICAEn to 1 again, the
registers of the CSIn unit must be set again.
6
TRMDn
(n = 0 to 2)
Transmission/Reception Mode Control
Specifies the transmission/reception mode.
0: Reception-only mode
1: Transmission/reception mode
If TRMDn = 0, reception-only transfers are performed. In addition, the SOn pin
output is fixed at low level. Data reception is started by reading the SIOn register.
If TRMDn = 1, transmission/reception is started by writing data to the SOTBn
register.
Caution The TRMDn bit can be overwritten only when CSOTn = 0.
4
DIRn
(n = 0 to 2)
Transmit Direction Mode Control
Specifies the transfer direction mode (MSB or LSB).
0: The transfer data’s start bit is MSB
1: The transfer data’s start bit is LSB
Caution The DIRn bit can be overwritten only when CSOTn = 0.
0
CSOTn
(n = 0 to 2)
CSI Status of Transmission
This is a transfer status display flag.
0: Idle status
1: Transfer execution status
This flag is used to judge whether writing to the shift register (SIOn) is enabled or
not when starting serial data transmission in transmission/reception mode (TRMDn
= 1)
Caution The CSOTn bit is reset when the CSICAEn bit is cleared (0).
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CHAPTER 11 SERIAL INTERFACE FUNCTION
(2) Clocked serial interface clock selection registers 0 to 2 (CSIC0 to CSIC2)
The CSICn register is an 8-bit register that controls the transmit operation of CSIn.
These registers can be read or written in 8-bit units.
Caution
The CSIC2 to CSIC0 registers can be overwritten when CSICAEn = 0 in the CSIMn register.
(1/2)
7
6
5
4
3
2
1
0
Address
After reset
CSIC0
0
0
0
CKP0
DAP0
CKS02
CKS01
CKS00
FFFFF901H
00H
CSIC1
0
0
0
CKP1
DAP1
CKS12
CKS11
CKS10
FFFFF911H
00H
CSIC2
0
0
0
CKP2
DAP2
CKS22
CKS21
CKS20
FFFFF921H
00H
Bit position
Bit name
4, 3
CKPn, DAPn
(n = 0 to 2)
Function
Clock Phase Selection Bit, Data Phase Selection Bit
Specifies the data transmission/reception timing for SCKn.
CKPn
DAPn
0
0
Operation mode
SCKn
(I/O)
D7
SOn (output)
D6
D5
D4
D3
D2
D1
D0
SIn capture
0
1
SCKn
(I/O)
SOn (output)
D7
D6
D5
D4
D3
D2
D1
D0
SIn capture
1
0
SCKn
(I/O)
D7
SOn (output)
D6
D5
D4
D3
D2
D1
D0
SIn capture
1
1
SCKn
(I/O)
SOn (output)
D7
D6
D5
D4
D3
D2
D1
D0
SIn capture
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CHAPTER 11 SERIAL INTERFACE FUNCTION
(2/2)
Bit position
2 to 0
Bit name
CKSn2 to
CKSn0
(n = 0 to 2)
Function
Input Clock Selection
Specifies the input clock.
CKSn2
0
CKSn1
CKSn0
0
0
0
0
1
0
1
1
0
1
0
Input clock
Mode
0
φ/2
Master mode
1
φ/2
Master mode
0
φ/2
Master mode
1
φ/2
Master mode
0
φ/2
Master mode
1
φ/2
Master mode
15
14
12
10
8
6
1
1
0
φ/2
Master mode
1
1
1
External clock (SCKn)
Slave mode
4
Remark φ: Internal system clock frequency
(a) Baud rate
CKSn2
CKSn1
CKSn0
Baud rate (bps)
50 MHz
operation
390
40 MHz
operation
33 MHz
operation
25 MHz
operation
20 MHz
operation
0
0
0
1,526
1,221
1,007
763
610
0
0
1
3,052
2,441
2,014
1,526
1,221
0
1
0
12,207
9,766
8,057
6,104
4,883
0
1
1
48,828
39,063
32,227
24,414
19,531
1
0
0
195,313
156,250
128,906
97,656
78,125
1
0
1
781,250
625,000
515,625
390,625
312,500
1
1
0
3,125,000
2,500,000
2,062,500
1,562,500
1,250,000
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CHAPTER 11 SERIAL INTERFACE FUNCTION
(3) Serial I/O shift registers 0 to 2 (SIO0 to SIO2)
The SIOn register is an 8-bit shift register that converts parallel data to serial data. If TRMDn = 0 in the
CSIMn register, the transfer is started by reading SIOn.
Except when a reset is input, the SIOn register becomes 00H even when the CSICAEn bit of the CSIMn
register is cleared (0).
These registers are read-only in 8-bit units.
Caution
SIOn can be accessed only when the system is in an idle state (CSOTn = 0 in the CSIMn
register).
7
6
5
4
3
2
1
0
Address
After reset
SIO0
SIO07
SIO06
SIO05
SIO04
SIO03
SIO02
SIO01
SIO00
FFFFF902H
00H
SIO1
SIO17
SIO16
SIO15
SIO14
SIO13
SIO12
SIO11
SIO10
FFFFF912H
00H
SIO2
SIO27
SIO26
SIO25
SIO24
SIO23
SIO22
SIO21
SIO20
FFFFF922H
00H
Bit position
7 to 0
Bit name
SIOn7 to
SIOn0
(n = 0 to 2)
Function
Serial I/O
Shifts data in (reception) or shifts data out (transmission) beginning at the MSB or
the LSB side.
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(4) Receive-only serial I/O shift registers 0 to 2 (SIOE0 to SIOE2)
The SIOEn register is an 8-bit shift register that converts parallel data into serial data. A receive operation
does not start even if the SIOEn register is read while the TRMD bit of the CSIMn register is 0. Therefore this
register is used to read the value of the SIOn register (receive data) without starting a receive operation.
Except when a reset is input, the SIOEn register becomes 00H even when the CSICAEn bit of the CSIMn
register is cleared (0).
These registers are read-only in 8-bit units.
Caution
SIOEn can be accessed only when the system is in an idle state (CSOTn = 0 in the CSIMn
register).
7
6
5
4
3
2
1
0
Address
After reset
SIOE0
SIOE07
SIOE06
SIOE05
SIOE04
SIOE03
SIOE02
SIOE01
SIOE00
FFFFF903H
00H
SIOE1
SIOE17
SIOE16
SIOE15
SIOE14
SIOE13
SIOE12
SIOE11
SIOE10
FFFFF913H
00H
SIOE2
SIOE27
SIOE26
SIOE25
SIOE24
SIOE23
SIOE22
SIOE21
SIOE20
FFFFF923H
00H
Bit position
7 to 0
392
Bit name
SIOEn7 to
SIOEn0
(n = 0 to 2)
Function
Serial I/O
Shifts data in (reception) beginning at the MSB or the LSB side.
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CHAPTER 11 SERIAL INTERFACE FUNCTION
(5) Clocked serial interface transmit buffer registers 0 to 2 (SOTB0 to SOTB2)
The SOTBn register is an 8-bit buffer register for storing transmit data.
If transmission/reception mode is set (TRMDn = 1 in the CSIMn register), a transmit operation is started by
writing data to the SOTBn register.
RESET input sets the SOTBn register to 00H.
These registers can be read or written in 8-bit units.
Caution
SOTBn can be accessed only when the system is in an idle state (CSOTn = 0 in the CSIMn
register).
7
6
5
4
3
2
1
0
Address
After reset
SOTB0
SOTB07 SOTB06 SOTB05 SOTB04 SOTB03 SOTB02 SOTB01 SOTB00 FFFFF904H
00H
SOTB1
SOTB17 SOTB16 SOTB15 SOTB14 SOTB13 SOTB12 SOTB11 SOTB10 FFFFF914H
00H
SOTB2
SOTB27 SOTB26 SOTB25 SOTB24 SOTB23 SOTB22 SOTB21 SOTB20 FFFFF924H
00H
Bit position
7 to 0
Bit name
SOTBn7 to
SOTBn0
(n = 0 to 2)
Function
Serial I/O
Writes transmit data.
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11.3.4 Operation
(1) Transfer mode
CSIn transmits and receives data in three lines: 1 clock line and 2 data lines.
In reception-only mode (TRMDn = 0 in the CSIMn register), the transfer is started by reading the SIOn
register (n = 0 to 2).
In transmission/reception mode (TRMDn = 1 in the CSIMn register), the transfer is started by writing data to
the SOTBn register.
When an 8-bit transfer of CSIn ends, the CSOTn bit of the CSIMn register becomes 0, and transfer stops
automatically.
Also, when the transfer ends, a transmission/reception completion interrupt (INTCSIn) is
generated.
Cautions 1. When CSOTn = 1 in the CSIMn register, the control registers and data registers should
not be accessed.
2. If transmit data is written to the SOTBn register and the TRMDn bit of the CSIMn register
is changed from 0 to 1, serial transfer is not performed.
(2) Serial clock
(a) When internal clock is selected as the serial clock
If reception or transmission is started, a serial clock is output from the SCKn pin, and the data of the SIn
pin is taken into the SIOn register sequentially or data is output to the SOn pin sequentially from the SIOn
register at the timing when the data has been synchronized with the serial clock in accordance with the
setting of the CKPn and DAPn bits of the CSICn register (n = 0 to 2).
(b) When external clock is selected as the serial clock
If reception or transmission is started, the data of the SIn pin is taken into the SIOn register sequentially
or output to the SOn pin sequentially in synchronization with the serial clock that has been input to the
SCKn pin following transmission/reception startup in accordance with the setting of the CKPn and DAPn
bits of the CSICn register (n = 0 to 2).
If serial clock is input to the SCKn pin when neither reception nor transmission is started, a shift operation
will not be executed.
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Figure 11-15. Transfer Timing
(a) When TRMDn = 1, DIRn = 0, CKPn = 0, and DAPn = 0
SCKn
(Write 55H to SOTBn)
Reg-R/W
SOTBn
55H (transmission data)
SIOn
ABH
56H
ADH
5AH
B5H
6AH
D5H
AAH
CSOTn bit
INTCSIn interrupt
Remark
SIn
1
0
1
0
1
0
1
0
(AAH)
SOn
0
1
0
1
0
1
0
1
(55H)
n = 0 to 2
(b) When TRMDn = 1, DIRn = 0, CKPn = 0, and DAPn = 1
SCKn
(Write 55H to SOTBn)
Reg-R/W
SOTBn
55H (transmission data)
SIOn
ABH
56H
ADH
5AH
B5H
6AH
D5H
AAH
CSOTn bit
INTCSIn interrupt
Remark
SIn
1
0
1
0
1
0
1
0
(AAH)
SOn
0
1
0
1
0
1
0
1
(55H)
n = 0 to 2
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Figure 11-16. Clock Timing
(a) When CKPn = 0 and DAPn = 0
SCKn
SIn capture
D7
SIOn
D6
D5
D4
D3
D2
D1
D0
D2
D1
D0
Reg-R/W
INTCSIn interrupt
CSOTn bit
(b) When CKPn = 1 and DAPn = 0
SCKn
SIn capture
D7
SIOn
D6
D5
D4
D3
Reg-R/W
INTCSIn interrupt
CSOTn bit
(c) When CKPn = 0 and DAPn = 1
SCKn
SIn capture
SIOn
D7
D6
D5
D4
D3
D2
D1
D0
D1
D0
Reg-R/W
INTCSIn interrupt
CSOTn bit
(d) When CKPn = 1 and DAPn = 1
SCKn
SIn capture
SIOn
D7
D6
D5
D4
D3
Reg-R/W
INTCSIn interrupt
CSOTn bit
Remark
396
n = 0 to 2
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CHAPTER 11 SERIAL INTERFACE FUNCTION
11.3.5 Output pins
(1) SCKn pin
When CSIn operation is disabled (CSICAEn = 0), the SCKn pin output state is as follows.
CKPn
SCKn pin output
0
Fixed at high level
1
Fixed at low level
Remarks 1. When the CKPn bit is overwritten, the SCKn pin output changes.
2. n = 0 to 2
(2) SOn pin
When CSIn operation is disabled (CSICAEn = 0), the SOn pin output state is as follows.
TRMDn
DAPn
DIRn
SOn pin output
0
x
x
Fixed at low level
1
0
x
SOn latch value (low level)
1
0
SOTBn7 value
1
SOTBn0 value
Remarks 1. If any of the TRMDn, DAPn, and DIRn bits is overwritten, the SOn pin output changes.
2. n = 0 to 2
3. x: don’t care
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11.3.6 System configuration example
CSIn performs 8-bit length data transfer using three signal lines: a serial clock (SCKn), serial input (SIn), and serial
output (SOn). This is effective when connecting peripheral I/O that incorporate a conventional clocked serial interface,
or a display controller to the V850E/MA1 (n = 2 to 0).
When connecting the V850E/MA1 to several devices, lines for handshake are required.
Since the first communication bit can be selected as an MSB or LSB, communication with various devices can be
achieved.
Figure 11-17. System Configuration Example of CSI
(3-wire serial I/O
3-wire serial I/O)
Master CPU
Slave CPU
SCK
SCK
SO
SI
SI
SO
Port (interrupt)
Port
Port
398
Port (interrupt)
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CHAPTER 12 A/D CONVERTER
12.1 Features
• Analog input: 8 channels
• 10-bit A/D converter
• On-chip A/D conversion result register (ADCR0 to ADCR7)
10 bits × 8
• A/D conversion trigger mode
A/D trigger mode
Timer trigger mode
External trigger mode
• Successive approximation method
12.2 Configuration
The A/D converter of the V850E/MA1 adopts the successive approximation method, and uses A/D converter mode
registers 0, 1, 2 (ADM0, ADM1, ADM2), and the A/D conversion result register (ADCR0 to ADCR7) to perform A/D
conversion operations.
(1) Input circuit
The input circuit selects the analog input (ANI0 to ANI7) according to the mode set by the ADM0 and ADM1
registers and sends the input to the sample & hold circuit.
(2) Sample & hold circuit
The sample & hold circuit samples each of the analog input signals sequentially sent from the input circuit,
and sends them to the voltage comparator. This circuit also holds the sampled analog input signal during A/D
conversion.
(3) Voltage comparator
The voltage comparator compares the analog input signal with the output voltage of the series resistor string
voltage tap.
(4) Series resistor string
The series resistor string is used to generate voltages to match analog inputs.
The series resistor string is connected between the reference voltage pin (AVREF) for the A/D converter and
the GND pin (AVSS) for the A/D converter. To make 1,024 equal voltage steps between these 2 pins, it is
configured from 1,023 equal resistors and 2 resistors with 1/2 of the resistance value.
The voltage tap of the series resistor string is selected by a tap selector controlled by the successive
approximation register (SAR).
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A/D CONVERTER
(5) Successive approximation register (SAR)
The SAR is a 10-bit register that sets series resistor string voltage tap data, whose values match analog input
voltage values, 1 bit at a time starting from the most significant bit (MSB).
If data is set in the SAR all the way to the least significant bit (LSB) (A/D conversion completed), the contents
of the SAR (conversion results) are held in the A/D conversion result register (ADCRn).
(6) A/D conversion result register (ADCRn)
ADCRn is a 10-bit register that holds A/D conversion results. Each time A/D conversion is completed, the
conversion results are loaded from the successive approximation register (SAR).
RESET input sets this register to 0000H.
(7) Controller
The controller selects the analog input, generates the sample & hold circuit operation timing, and controls the
conversion trigger according to the mode set by the ADM0 and ADM1 registers.
(8) ANI0 to ANI7 pins
These are 8-channel analog input pins for the A/D converter. They input the analog signals to be A/D
converted.
Caution
Make sure that the voltages input to ANI0 to ANI7 do not exceed the rated values. If a
voltage higher than AVDD or lower than AVSS (even within the range of the absolute
maximum ratings) is input to a channel, the conversion value of the channel is undefined,
and the conversion values of the other channels may also be affected.
(9) AVREF pin
This is the pin for inputting the reference voltage of the A/D converter. It converts signals input to the ANIn
pin to digital signals based on the voltage applied between AVREF and AVSS.
In the V850E/MA1, the AVREF pin functions alternately as the AVDD pin. It is therefore impossible to set
voltage separately for the AVREF pin and the AVDD pin.
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A/D CONVERTER
Figure 12-1. Block Diagram of A/D Converter
Series resistor string
ANI0
Sample & hold circuit
Input circuit
ANI2
Tap selector
ANI1
ANI3
ANI4
ANI5
ANI6
R/2
AVDD/AVREF
R
R/2
AVSS
Voltage comparator
ANI7
SAR (10)
10
10
φ /2
INTAD
9
0
ADCR0
INTM000
INTM001
INTM010
INTM011
ADCR1
Controller
ADCR2
ADCR3
ADTRG
Edge
detection
ADCR4
ADCR5
7
0
7
0
7
0
ADM0 (8)
ADM1 (8)
ADM2 (8)
8
8
8
ADCR6
ADCR7
10
Internal bus
Cautions 1. If there is noise at the analog input pins (ANI0 to ANI7) or at the reference voltage input
pin (AVREF), that noise may generate an illegal conversion result.
Software processing will be needed to avoid a negative effect on the system from this
illegal conversion result.
An example of this software processing is shown below.
• Take the average result of a number of A/D conversions and use that as the A/D
conversion result.
• Execute a number of A/D conversions consecutively and use those results, omitting
any exceptional results that may have been obtained.
• If an A/D conversion result that is judged to have generated a system malfunction is
obtained, be sure to recheck the system malfunction before performing malfunction
processing.
2. Do not apply a voltage outside the AVSS to AVREF range to the pins that are used as A/D
converter input pins.
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12.3 Control Registers
(1) A/D converter mode register 0 (ADM0)
The ADM0 register is an 8-bit register that selects the analog input pin, specifies the operation mode, and
executes conversion operations.
This register can be read/written in 8-bit or 1-bit units. However, when data is written to the ADM0 register
during an A/D conversion operation, the conversion operation is initialized and conversion is executed from
the beginning. Bit 6 cannot be written to and writing executed is ignored.
Cautions 1. When the ADCE bit is 1 in the timer trigger mode and external trigger mode, the trigger
signal standby state is set. To clear the ADCE bit, write “0” or reset.
In the A/D trigger mode, the conversion trigger is set by writing 1 to the ADCE bit. After
the operation, when the mode is changed to the timer trigger mode or external trigger
mode without clearing the ADCE bit, the trigger input standby state is set immediately
after the change.
2. There are 10 clocks between the beginning of conversion and when the ADCS bit
becomes 1.
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A/D CONVERTER
<7>
<6>
5
4
3
2
1
0
ADCE
ADCS
BS
MS
0
ANIS2
ANIS1
ANIS0
Bit position
Bit name
After reset
00H
Function
7
ADCE
Convert Enable
Enables or disables A/D conversion operation.
0: Disabled
1: Enabled
6
ADCS
Converter Status
Indicates the status of A/D converter. This bit is read only.
0: Stopped
1: Operating
5
BS
Buffer Select
Specifies buffer mode in the select mode.
0: 1-buffer mode
1: 4-buffer mode
4
MS
Mode Select
Specifies operation mode of A/D converter.
0: Scan mode
1: Select mode
ANIS2 to
ANIS0
Analog Input Select
Specifies the analog input pin to be A/D converted.
2 to 0
Address
FFFFF200H
ANIS2 ANIS1 ANIS0
Select mode
A/D trigger
mode
Timer trigger
mode
Scan mode
A/D trigger
mode
Timer trigger
Note
mode
0
0
0
ANI0
ANI0
ANI0
1
0
0
1
ANI1
ANI1
ANI0, ANI1
2
0
1
0
ANI2
ANI2
ANI0 to ANI2
3
0
1
1
ANI3
ANI3
ANI0 to ANI3
4
1
0
0
ANI4
Setting
prohibited
ANI0 to ANI4
4 + ANI4
1
0
1
ANI5
Setting
prohibited
ANI0 to ANI5
4 + ANI4,
ANI5
1
1
0
ANI6
Setting
prohibited
ANI0 to ANI6
4 + ANI4 to
ANI6
1
1
1
ANI7
Setting
prohibited
ANI0 to ANI7
4 + ANI4 to
ANI7
Note In the timer trigger mode (4-trigger mode) in the scan mode, because the scanning sequence of the
ANI0 to ANI3 pins is specified by the sequence in which the match signals are generated from the
compare register, the number of trigger inputs should be specified instead of specifying a certain
analog input pin. When ANIS2 = 1, perform conversion after shifting to A/D trigger scan mode,
which is possible after the trigger has been counted 4 times.
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(2) A/D converter mode register 1 (ADM1)
The ADM1 register is an 8-bit register that specifies the conversion operation time and trigger mode.
This register can be read/written in 8-bit units. However, when data is written to the ADM1 register during an
A/D conversion operation, the conversion operation is initialized and conversion is executed from the
beginning.
ADM1
Bit position
6 to 4
7
6
5
4
3
2
1
0
0
TRG2
TRG1
TRG0
0
FR2
FR1
FR0
Bit name
TRG2 to
TRG0
Address
FFFFF201H
After reset
07H
Function
Trigger Mode
Specifies the trigger mode.
TRG2
TRG1
TRG0
0
0
0/1
0
1
0
Timer trigger mode (1-trigger mode)
0
1
1
Timer trigger mode (4-trigger mode)
1
1
1
External trigger mode
Other than above
Remark
Trigger mode
A/D trigger mode
Setting prohibited
The valid edge of the external input signal in the external trigger mode is
specified by bits 7 and 6 (ES1231, ES1230) of the external interrupt mode
register (INTM3). For details, refer to 7.3.9 (1) External interrupt mode
registers 1 to 4 (INTM1 to INTM4).
2 to 0
FR2 to FR0
Frequency
Specifies the conversion operation time. These bits control the conversion time so that it
is the same value irrespective of the oscillation frequency.
FR2
FR1
FR0
Number of
conversion clocks
Note
Conversion operation time
φ = 50 MHz
φ = 33 MHz
0
0
0
96
Setting prohibited Setting prohibited Setting prohibited
0
0
1
144
Setting prohibited Setting prohibited Setting prohibited
0
1
0
192
Setting prohibited Setting prohibited
0
1
1
240
4.80 µs
6.00 µs
7.27 µs
1
0
0
336
6.72 µs
8.40 µs
10.18 µs
1
0
1
384
7.68 µs
9.60 µs
Setting prohibited
1
1
0
480
9.60 µs
1
1
1
672
Note
Remark
5.82 µs
Setting prohibited Setting prohibited
Setting prohibited Setting prohibited Setting prohibited
Figures in the conversion operation time are target values. Set the conversion
operation time in the range of 5 to 10 µs.
404
φ = 40 MHz
φ = internal system clock frequency
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(3) A/D converter mode register 2 (ADM2)
The ADM2 register is an 8-bit register that controls the reset and clock of the A/D converter.
This register can be read/written in 8-bit or 1-bit units.
Caution
Because ADCAE = 0 after reset release, the A/D converter enters the reset state. When
operating the A/D converter, be sure to write to the ADM0 and ADM1 registers after setting
the ADCAE bit of the ADM2 register to 1 (it is impossible to write to the ADM0 and ADM1
registers when ADCAE = 0). Moreover, when the ADCAE bit is set to 0, all registers related
to the A/D converter are initialized.
ADM2
Bit position
0
7
6
5
4
3
2
1
<0>
0
0
0
0
0
0
0
ADCAE
Bit name
ADCAE
Address
FFFFF202H
After reset
00H
Function
Clock Action Enable
Controls the A/D converter operation.
0: Clock supply to the A/D converter is stopped, the A/D converter is in the reset state
1: The clock is supplied to the A/D converter, A/D converter operation is enabled
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(4) A/D conversion result registers (ADCR0 to ADCR7, ADCR0H to ADCR7H)
The ADCRn register is a 10-bit register holding the A/D conversion results. There are eight 10-bit registers.
These registers are read-only in 16-bit or 8-bit units. During 16-bit access, the ADCRn register is specified,
and during higher 8-bit access, the ADCRnH register is specified (n = 0 to 7).
When reading the 10-bit data of the A/D conversion results from the ADCRn register during 16-bit access,
only the lower 10 bits are valid and the higher 6 bits are always read as 0.
ADCRn
15
14
13
12
11
10
0
0
0
0
0
0
9
8
7
5
4
3
2
1
0
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
7
ADCRnH
Remark
6
6
5
4
3
2
1
0
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
Address
FFFFF210H to
FFFFF21EH
After reset
0000H
Address
FFFFF220H to
FFFFF227H
After reset
00H
n = 0 to 7
The correspondence between each analog input pin and the ADCRn register (except the 4-buffer mode) is
shown below.
Analog Input Pin
406
ADCRn Register
ANI0
ADCR0, ADCR0H
ANI1
ADCR1, ADCR1H
ANI2
ADCR2, ADCR2H
ANI3
ADCR3, ADCR3H
ANI4
ADCR4, ADCR4H
ANI5
ADCR5, ADCR5H
ANI6
ADCR6, ADCR6H
ANI7
ADCR7, ADCR7H
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The relationship between the analog voltage input to the analog input pins (ANI0 to ANI7) and the A/D
conversion result (of the A/D conversion result register (ADCRn)) is as follows:
ADCR = INT (
VIN
AVREF
× 1,024 + 0.5)
or,
(ADCR − 0.5) ×
AVREF
1,024
≤ VIN < (ADCR + 0.5) ×
AVREF
1,024
INT( ): Function that returns the integer of the value in ( )
VIN:
Analog input voltage
AVREF: AVREF pin voltage
ADCR: Value of A/D conversion result register (ADCRn)
Figure 12-2 shows the relationship between the analog input voltage and the A/D conversion results.
Figure 12-2. Relationship Between Analog Input Voltage and A/D Conversion Results
1,023
1,022
A/D conversion
1,021
results (ADCRn)
3
2
1
0
1
1
3
2
5
3
2,048 1,024 2,048 1,024 2,048 1,024
2,043 1,022 2,045 1,023 2,047 1
2,048 1,024 2,048 1,024 2,048
Input voltage/AVREF
Remark
n = 0 to 7
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12.4 A/D Converter Operation
12.4.1 Basic operation of A/D converter
A/D conversion is executed by the following procedure.
(1) The ADCAE bit of the ADM2 register is set (1).
(2) The selection of the analog input and specification of the operation mode, trigger mode, etc. should be
specified using the ADM0 and ADM1 registers
Note 1
.
When the ADCE bit of the ADM0 register is set (1), A/D conversion starts in the A/D trigger mode. In the
timer trigger mode and external trigger mode, the trigger standby state
Note 2
is set.
(3) The voltage generated from the voltage tap of the series resistor string and analog input are compared by the
comparator.
(4) When the comparison of the 10 bits ends, the conversion results are stored in the ADCRn register. When
A/D conversion has been performed the specified number of times, the A/D conversion end interrupt (INTAD)
is generated (n = 0 to 7).
Notes 1.
When the ADM0 to ADM2 registers are changed during the A/D conversion operation, the A/D
conversion operation before the change is stopped and the conversion results are not stored in
the ADCRn register.
2.
During the timer trigger mode and external trigger mode, if the ADCE bit of the ADM0 register is
set to 1, the mode changes to the trigger standby state. The A/D conversion operation is started
by the trigger signal, and the trigger standby state is returned when the A/D conversion operation
ends.
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12.4.2 Operation mode and trigger mode
Various conversion operations can be specified for the A/D converter by specifying the operation mode and trigger
mode. The operation mode and trigger mode are set by the ADM0 and ADM1 registers.
The following shows the relationship between the operation mode and trigger mode.
Trigger Mode
Operation Mode
Setting Value
ADM0
A/D trigger
Select
1 trigger
Select
xx010xxxB
000x0xxxB
4 buffers
xx110xxxB
000x0xxxB
xxx00xxxB
000x0xxxB
1 buffer
xx010xxxB
00100xxxB
4 buffers
xx110xxxB
00100xxxB
xxx00xxxB
00100xxxB
1 buffer
xx010xxxB
00110xxxB
4 buffers
xx110xxxB
00110xxxB
xxx00xxxB
00110xxxB
1 buffer
xx010xxxB
01100xxxB
4 buffers
xx110xxxB
01100xxxB
xxx00xxxB
01100xxxB
Scan
4 trigger
Select
Scan
External trigger
Select
Scan
ADM1
1 buffer
Scan
Timer trigger
Analog Input
ANI0 to ANI7
ANI0 to ANI3
(1) Trigger mode
There are three types of trigger modes that serve as the start timing of A/D conversion processing: A/D
trigger mode, timer trigger mode, and external trigger mode. The ANI0 to ANI3 pins are able to specify all of
these modes, but the ANI4 to ANI7 pins can only specify the A/D trigger mode. The timer trigger mode
consists of the 1-trigger mode and 4-trigger mode as the sub-trigger modes. These trigger modes are set by
the ADM1 register.
(a) A/D trigger mode
This mode starts the conversion timing of the analog input set to the ANI0 to ANI7 pins, and by setting
the ADCE bit of the ADM0 register to 1, starts A/D conversion. The ANI4 to ANI7 pins are always set in
this mode.
(b) Timer trigger mode
Specifies the conversion timing of the analog input set for the ANI0 to ANI3 pins using the values set to
the timer C compare register. This mode can only be specified by pins ANI0 to ANI3.
This register creates the analog input conversion timing by generating the match interrupts of the four
capture/compare registers (CCC00, CCC01, CCC10, CCC11) connected to the 16-bit timer C (TMC0,
TMC1).
There are two sub-trigger modes: 1-trigger mode and 4-trigger mode.
• 1-trigger mode
A mode that uses one match interrupt from timer C as the A/D conversion start timing.
• 4-trigger mode
A mode that uses four match interrupts from timer C as the A/D conversion start timing.
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(c) External trigger mode
A mode that specifies the conversion timing of the analog input to the ANI0 to ANI3 pins using the
ADTRG pin. This mode can be specified only with the ANI0 to ANI3 pins.
(2) Operation mode
There are two operation modes that set the ANI0 to ANI7 pins: select mode and scan mode. The select
mode has sub-modes that consist of 1-buffer mode and 4-buffer mode. These modes are set by the ADM0
register.
(a) Select mode
In this mode, one analog input specified by the ADM0 register is A/D converted. The conversion results
are stored in the ADCRn register corresponding to the analog input (ANIn). For this mode, the 1-buffer
mode and 4-buffer mode are provided for storing the A/D conversion results (n = 0 to 7).
• 1-buffer mode
In this mode, one analog input specified by the ADM0 register is A/D converted. The conversion
results are stored in the ADCRn register corresponding to the analog input (ANIn). The ANIn and
ADCRn register correspond one to one, and an A/D conversion end interrupt (INTAD) is generated
each time one A/D conversion ends.
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Figure 12-3. Select Mode Operation Timing: 1-Buffer Mode (ANI1)
ANI1
(input)
Data 4
Data 1
A/D
conversion
Data 1
(ANI1)
Data 2
Data 2
(ANI1)
Data 1
(ANI1)
ADCR1
register
Data 5
Data 3
Data 3
(ANI1)
Data 2
(ANI1)
Data 6
Data 4
(ANI1)
Data 3
(ANI1)
Data 5
(ANI1)
Data 6
(ANI1)
Data 4
(ANI1)
Data 7
Data 7
(ANI1)
Data 6
(ANI1)
INTAD
interrupt
Conversion ADCE bit set ADCE bit set ADCE bit set ADCE bit set Conversion ADCE bit set
start
start
(ADM0 register setting)
(ADM0 register setting)
Analog input
ADCRn register
ANI0
ADCR0
ANI1
ADCR1
ANI2
ADCR2
ANI3
A/D converter
ADCR3
ANI4
ADCR4
ANI5
ADCR5
ANI6
ADCR6
ANI7
ADCR7
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• 4-buffer mode
In this mode, one analog input is A/D converted four times and the results are stored in the ADCR0 to
ADCR3 registers.
The A/D conversion end interrupt (INTAD) is generated when the four A/D
conversions end.
Figure 12-4. Select Mode Operation Timing: 4-Buffer Mode (ANI6)
ANI6
(input)
A/D
conversion
Data 4
Data 1
Data 2
Data 3
Data 1
(ANI6)
Data 2
(ANI6)
Data 3
(ANI6)
Data 4
(ANI6)
Data 1
(ANI6)
ADCR0
Data 2
(ANI6)
ADCR1
Data 3
(ANI6)
ADCR2
ADCRn
register
Data 5
Data 6
Data 5
(ANI6)
Data 6
(ANI6)
Data 4
(ANI6)
ADCR3
Data 7
Data 7
(ANI6)
Data 6
(ANI6)
ADCR0
INTAD
interrupt
Conversion start
(ADM0 register setting)
Conversion start
(ADM0 register setting)
Analog input
ANI0
ADCR0
ANI1
ADCR1
ANI2
ADCR2
ANI3
412
ADCRn register
A/D converter
ADCR3
ANI4
ADCR4
ANI5
ADCR5
ANI6
ADCR6
ANI7
ADCR7
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(b) Scan mode
In this mode, the analog inputs specified by the ADM0 register are selected sequentially from the ANI0
pin, and A/D conversion is executed. The A/D conversion results are stored in the ADCRn register
corresponding to the analog input (n = 0 to 7). When the conversion of the specified analog input ends,
the A/D conversion end interrupt (INTAD) is generated.
Figure 12-5. Scan Mode Operation Timing: 4-Channel Scan (ANI0 to ANI3)
ANI0
(input)
Data 1
Data 5
Data 6
ANI1
(input)
Data 7
Data 2
ANI2
(input)
Data 3
ANI3
(input)
A/D
conversion
Data 4
Data 1
(ANI0)
ADCRn
register
Data 2
(ANI1)
Data 3
(ANI2)
Data 4
(ANI3)
Data 1
(ANI0)
ADCR0
Data 2
(ANI1)
ADCR1
Data 3
(ANI2)
ADCR2
Data 5
(ANI0)
Data 6
(ANI0)
Data 4
(ANI3)
ADCR3
Data 7
(ANI1)
Data 6
(ANI0)
ADCR0
INTAD
interrupt
Conversion start
(ADM0 register setting)
Conversion start
(ADM0 register setting)
Analog input
ADCRn register
ANI0
ADCR0
ANI1
ADCR1
ANI2
ADCR2
ANI3
A/D converter
ADCR3
ANI4
ADCR4
ANI5
ADCR5
ANI6
ADCR6
ANI7
ADCR7
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12.5 Operation in A/D Trigger Mode
When the ADCE bit of the ADM0 register is set to 1, A/D conversion is started.
12.5.1 Select mode operation
In this mode, the analog input specified by the ADM0 register is A/D converted. The conversion results are stored
in the ADCRn register corresponding to the analog input. In the select mode, the 1-buffer mode and 4-buffer mode
are supported according to the storing method of the A/D conversion results (n = 0 to 7).
(1) 1-buffer mode (A/D trigger select: 1 buffer)
In this mode, one analog input is A/D converted once. The conversion results are stored in one ADCRn
register. The analog input and ADCRn register correspond one to one.
Each time an A/D conversion is executed, an A/D conversion end interrupt (INTAD) is generated and A/D
conversion ends.
Analog Input
ANIn
A/D Conversion Result Register
ADCRn
If 1 is written in the ADCE bit of the ADM0 register, A/D conversion can be restarted.
This mode is most appropriate for applications in which the results of each first-time A/D conversion are read.
Figure 12-6. Example of 1-Buffer Mode Operation (A/D Trigger Select: 1 Buffer)
ADM0
ANI0
ADCR0
ANI1
ADCR1
ANI2
ADCR2
ANI3
414
A/D converter
ADCR3
ANI4
ADCR4
ANI5
ADCR5
ANI6
ADCR6
ANI7
ADCR7
(1)
The ADCE bit of ADM0 is set to 1 (enable)
(2)
ANI2 is A/D converted
(3)
The conversion result is stored in ADCR2
(4)
The INTAD interrupt is generated
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(2) 4-buffer mode (A/D trigger select: 4 buffers)
In this mode, one analog input is A/D converted four times and the results are stored in the ADCR0 to ADCR3
registers. When the 4th A/D conversion ends, an A/D conversion end interrupt (INTAD) is generated and the
A/D conversion is stopped.
Analog Input
A/D Conversion Result Register
ANIn
ADCR0
ANIn
ADCR1
ANIn
ADCR2
ANIn
ADCR3
If 1 is written in the ADCE bit of the ADM0 register, A/D conversion can be restarted.
This mode is suitable for applications in which the average of the A/D conversion results is calculated.
Figure 12-7. Example of 4-Buffer Mode Operation (A/D Trigger Select: 4 Buffers)
ADM0
(×4)
ANI0
ADCR0
ANI1
ADCR1
ANI2
ADCR2
ANI3
ANI4
A/D converter
ADCR3
ADCR4
(×4)
ANI5
ADCR5
ANI6
ADCR6
ANI7
ADCR7
(1)
The ADCE bit of ADM0 is set to 1 (enable)
(6)
ANI4 is A/D converted
(2)
ANI4 is A/D converted
(7)
The conversion result is stored in ADCR2
(3)
The conversion result is stored in ADCR0
(8)
ANI4 is A/D converted
(4)
ANI4 is A/D converted
(9)
The conversion result is stored in ADCR3
(5)
The conversion result is stored in ADCR1
(10) The INTAD interrupt is generated
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12.5.2 Scan mode operations
In this mode, the analog inputs specified by the ADM0 register are selected sequentially from the ANI0 pin, and
A/D conversion is executed. The A/D conversion results are stored in the ADCRn register corresponding to the
analog input (n = 0 to 7).
When conversion of all the specified analog input ends, the A/D conversion end interrupt (INTAD) is generated,
and A/D conversion is stopped.
Analog Input
A/D Conversion Result Register
ANIn
ADCR0
.
.
.
.
.
.
Note
ANIn
ADCRn
Note Set by the ANI0 to ANI2 bits of the ADM0 register.
If 1 is written in the ADCE bit of the ADM0 register, A/D conversion can be restarted.
This mode is most appropriate for applications in which multiple analog inputs are constantly monitored.
Figure 12-8. Example of Scan Mode Operation (A/D Trigger Scan)
ADM0
ANI0
ADCR0
ANI1
ADCR1
ANI2
ADCR2
ANI3
416
A/D converter
ADCR3
ANI4
ADCR4
ANI5
ADCR5
ANI6
ADCR6
ANI7
ADCR7
(1)
The ADCE bit of ADM0 is set to 1 (enable)
(8)
ANI3 is A/D converted
(2)
ANI0 is A/D converted
(9)
The conversion result is stored in ADCR3
(3)
The conversion result is stored in ADCR0
(10) ANI4 is A/D converted
(4)
ANI1 is A/D converted
(11) The conversion result is stored in ADCR4
(5)
The conversion result is stored in ADCR1
(12) ANI5 is A/D converted
(6)
ANI2 is A/D converted
(13) The conversion result is stored in ADCR5
(7)
The conversion result is stored in ADCR2
(14) The INTAD interrupt is generated
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12.6 Operation in Timer Trigger Mode
Conversion timings for up to four-channel analog inputs (ANI0 to ANI3) can be set for the A/D converter using the
interrupt signal output from the TMC compare register.
Two 16-bit timers (TMC0, TMC1) and four capture/compare registers (CCC00, CCC01, CCC10, CC11) are used
for the timer to specify the analog conversion trigger.
The following two modes are provided according to the value set in the TMCC01 or TMCC11 register.
(1) 1-shot mode
To use the 1-shot mode, set the OSTn bit of the TMCCn1 register (overflow stop mode) to 1 (n = 0, 1).
When TMC overflows, 0000H is held, and counter operation stops. Thereafter, TMCn does not output the
match interrupt signal (A/D conversion trigger) of the compare register, and the A/D converter enters the A/D
conversion standby state. The TMCn count operation restarts when the TMCCEn bit of the TMCCn0 register
is set to 1. The 1-shot mode is used when the A/D conversion cycle is longer than the TMC cycle. (n = 0, 1).
(2) Loop mode
To use the loop mode, set the OST bit (free-running mode) of the TMCCn1 register to 0 (n = 0, 1).
When TMCn overflows, it starts counting from 0000H again, and the match interrupt signal (A/D conversion
trigger) of the compare register is repeatedly output. A/D conversion is also repeated.
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12.6.1 Select mode operation
In this mode, an analog input (ANI0 to ANI3) specified by the ADM0 register is A/D converted. The conversion
results are stored in the ADCRn register. In the select mode, the 1-buffer mode and 4-buffer mode are provided
according to the storing method of the A/D conversion results (n = 0 to 3).
(1) 1-buffer mode operation (timer trigger select: 1 buffer)
In this mode, one analog input is A/D converted once and the conversion results are stored in one ADCRn
register.
There are two modes in the 1-buffer mode: 1-trigger mode and 4-trigger mode, according to the number of
triggers.
(a) 1-trigger mode (timer trigger select: 1 buffer, 1 trigger)
In this mode, one analog input is A/D converted once using the trigger of the match interrupt signal
(INTM000) and the results are stored in one ADCRn register. An A/D conversion end interrupt (INTAD)
is generated for each A/D conversion and A/D conversion is stopped (n = 0 to 3).
Trigger
INTM000 interrupt
Analog Input
ANIn
A/D Conversion Result Register
ADCRn
In 1-shot mode, A/D conversion stops after one conversion. To restart A/D conversion, set the TMCCEn
bit of the TMCCn0 register to 1 (n = 0, 1).
When set to the loop mode, unless the ADCE bit of the ADM0 register is set to 0, A/D conversion is
repeated each time a match interrupt is generated.
Figure 12-9. Example of 1-Trigger Mode Operation (Timer Trigger Select: 1 Buffer 1 Trigger)
INTM000
ANI0
ADCR0
ANI1
ADCR1
ANI2
ADCR2
ANI3
A/D converter
ADCR3
ADCR4
ADCR5
ADCR6
ADCR7
(1)
418
The ADCE bit of ADM0 is set to 1 (enable)
(2)
The CCC00 compare is generated
(3)
ANI1 is A/D converted
(4)
The conversion result is stored in ADCR1
(5)
The INTAD interrupt is generated
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(b) 4-trigger mode (timer trigger select: 1 buffer, 4 triggers)
In this mode, one analog input is A/D converted four times using four match interrupt signals (INTM000,
INTM001, INTM010, INTM011) as triggers and the results are stored in one ADCRn register. The A/D
conversion end interrupt (INTAD) is generated with each A/D conversion, and the ADCS bit of the ADM0
register is reset (0). The results of one A/D conversion are held in the ADCRn register until the next A/D
conversion ends. Perform transmission of the conversion results to the memory and other operations
using the INTAD interrupt after each A/D conversion ends (n = 0 to 3).
Trigger
Analog Input
A/D Conversion Result Register
INTM000 interrupt
ANIn
ADCRn
INTM001 interrupt
ANIn
ADCRn
INTM010 interrupt
ANIn
ADCRn
INTM011 interrupt
ANIn
ADCRn
In 1-shot mode, A/D conversion stops after four conversions.
To restart A/D conversion, set the
TMCCEn bit of the TMCCn0 register to 1 to restart the TMCn. When the first match interrupt after TMCn
is restarted is generated, the ADCS bit is set (1) and A/D conversion is started (n = 0, 1).
When set to the loop mode, unless the ADCE bit of the ADM0 register is set to 0, A/D conversion is
repeated each time a match interrupt is generated.
The match interrupts (INTM000, INTM001, INTM010, INTM011) can be generated in any order. Also,
even in cases where the same trigger is input continuously, it is received as a trigger.
Figure 12-10. Example of 4-Trigger Mode Operation (Timer Trigger Select: 1 Buffer 4 Triggers)
ANI0
No particular
order
ADCR0
ANI1
INTM000
ANI2
INTM001
ANI3
ADCR1
(×4)
(×4)
A/D converter
ADCR2
ADCR3
INTM010
ADCR4
INTM011
ADCR5
ADCR6
ADCR7
(1)
The ADCE bit of ADM0 is set to 1 (enable)
(10) The CCC11 compare is generated (random)
(2)
The CCC10 compare is generated (random)
(11) ANI2 is A/D converted
(3)
ANI2 is A/D converted
(12) The conversion result is stored in ADCR2
(4)
The conversion result is stored in ADCR2
(13) The INTAD interrupt is generated
(5)
The INTAD interrupt is generated
(14) The CCC00 compare is generated (random)
(6)
The CCC01 compare is generated (random)
(15) ANI2 is A/D converted
(7)
ANI2 is A/D converted
(16) The conversion result is stored in ADCR2
(8)
The conversion result is stored in ADCR2
(17) The INTAD interrupt is generated
(9)
The INTAD interrupt is generated
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(2) 4-buffer mode operation (timer trigger select: 4 buffers)
In this mode, A/D conversion of one analog input is executed four times, and the results are stored in the
ADCR0 to ADCR3 registers. There are two 4-buffer modes: 1-trigger mode and 4-trigger mode, according to
the number of triggers.
This mode is suitable for applications in which the average of the A/D conversion results is calculated.
(a) 1-trigger mode
In this mode, one analog input is A/D converted four times using the match interrupt signal (INTM000) as
a trigger, and the results are stored in ADCR0 to ADCR3 registers. The A/D conversion end interrupt
(INTAD) is generated when the four A/D conversions end and A/D conversion is stopped.
Trigger
Analog Input
A/D Conversion Result Register
INTM000 interrupt
ANIn
ADCR0
INTM000 interrupt
ANIn
ADCR1
INTM000 interrupt
ANIn
ADCR2
INTM000 interrupt
ANIn
ADCR3
If the one-shot mode is set and the TMCCEn bit of the TMCCn0 register is set to 1, and if the match
interrupt occurs less than four times, the INTAD interrupt does not occur and the standby state is set (n =
0, 1).
Figure 12-11. Example of 1-Trigger Mode Operation (Timer Trigger Select: 4 Buffers 1 Trigger)
ANI0
ADCR0
ANI1
INTM000
(×4)
ANI2
ADCR1
(×4)
ANI3
ADCR2
A/D converter
ADCR3
ADCR4
ADCR5
ADCR6
ADCR7
420
(1)
The ADCE bit of ADM0 is set to 1 (enable)
(8)
The CCC00 compare is generated
(2)
The CCC00 compare is generated
(9)
ANI2 is A/D converted
(3)
ANI2 is A/D converted
(10) The conversion result is stored in ADCR2
(4)
The conversion result is stored in ADCR0
(11) The CCC00 compare is generated
(5)
The CCC00 compare is generated
(12) ANI2 is A/D converted
(6)
ANI2 is A/D converted
(13) The conversion result is stored in ADCR3
(7)
The conversion result is stored in ADCR1
(14) The INTAD interrupt is generated
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(b) 4-trigger mode
In this mode, one analog input is A/D converted four times using four match interrupt signals (INTM000,
INTM001, INTM010, INTM011) as triggers and the results are stored in four ADCRn registers. The A/D
conversion end interrupt (INTAD) is generated when the four A/D conversions end, the ADCS bit is reset
(0), and A/D conversion is stopped.
Trigger
Analog Input
A/D Conversion Result Register
INTM000 interrupt
ANIn
ADCR0
INTM001 interrupt
ANIn
ADCR1
INTM010 interrupt
ANIn
ADCR2
INTM011 interrupt
ANIn
ADCR3
In 1-shot mode, A/D conversion stops after four conversions. To restart the A/D conversion, set the
TMCCEn bit of the TMCCn0 register to 1 to restart TMCn. When the first match interrupt after TMCn is
restarted is generated, the ADCS bit is set (1) and A/D conversion is started (n = 0, 1).
When set to the loop mode, unless the ADCE bit of the ADM0 register is set to 0, A/D conversion is
repeated each time a match interrupt is generated.
The match interrupts (INTM000, INTM001, INTM010, INTM011) can be generated in any order, and the
conversion results are stored in the ADCRn register corresponding to the input trigger. Also, even in
cases where the same trigger is input continuously, it is received as a trigger.
Figure 12-12. Example of 4-Trigger Mode Operation (Timer Trigger Select: 4 Buffers 4 Triggers)
No particular
order
ANI0
No particular
order
ADCR0
ANI1
ADCR1
INTM000
ANI2
ADCR2
INTM001
ANI3
A/D converter
ADCR3
INTM010
ADCR4
INTM011
ADCR5
ADCR6
ADCR7
(1)
The ADCE bit of ADM0 is set to 1 (enable)
(8)
The CCC10 compare is generated (random)
(2)
The CCC01 compare is generated (random)
(9)
ANI2 is A/D converted
(3)
ANI2 is A/D converted
(10) The conversion result is stored in ADCR2
(4)
The conversion result is stored in ADCR1
(11) The CCC00 compare is generated (random)
(5)
The CCC11 compare is generated (random)
(12) ANI2 is A/D converted
(6)
ANI2 is A/D converted
(13) The conversion result is stored in ADCR0
(7)
The conversion result is stored in ADCR3
(14) The INTAD interrupt is generated
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12.6.2 Scan mode operation
In this mode, the analog inputs specified by the ADM0 register are selected sequentially from the ANI0 pin and are
A/D converted the specified number of times using the match interrupt signal as a trigger.
In the conversion operation, first the analog input lower channels (ANI0 to ANI3) are A/D converted the specified
number of times. If the lower channels (ANI0 to ANI3) of the analog input are set by the ADM0 register so that they
are scanned, and when the set number of A/D conversions ends, the A/D conversion end interrupt (INTAD) is
generated and A/D conversion is stopped.
When the higher channels (ANI4 to ANI7) of the analog input are set by the ADM0 register so that they are
scanned, after the conversion of the lower channel is ended, the mode is shifted to the A/D trigger mode, and the
remaining A/D conversions are executed.
The conversion results are stored in the ADCRn register corresponding to the analog input. When conversion of all
the specified analog inputs has ended, the A/D conversion end interrupt (INTAD) is generated and A/D conversion is
stopped (n = 0 to 7).
There are two scan modes: 1-trigger mode and 4-trigger mode, according to the number of triggers.
This mode is most appropriate for applications in which multiple analog inputs are constantly monitored.
(1) 1-trigger mode (timer trigger scan: 1 trigger)
In this mode, analog inputs are A/D converted the specified number of times using the match interrupt signal
(INTM000) as a trigger. The analog input and ADCRn register correspond one to one.
When all the specified A/D conversions have ended, the A/D conversion end interrupt (INTAD) is generated
and A/D conversion is stopped.
Trigger
Analog Input
A/D Conversion Result Register
INTM000 interrupt
ANI0
ADCR0
INTM000 interrupt
ANI1
ADCR1
INTM000 interrupt
ANI2
ADCR2
INTM000 interrupt
ANI3
ADCR3
(A/D trigger mode)
ANI4
ADCR4
ANI5
ADCR5
ANI6
ADCR6
ANI7
ADCR7
When the match interrupt is generated after all the specified A/D conversions have ended, A/D conversion is
restarted.
In 1-shot mode, and when less than a specified number of match interrupts are generated, if the ADCEn bit is
set to 1, the INTAD interrupt is not generated and the standby state is set.
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Figure 12-13. Example of 1-Trigger Mode Operation (Timer Trigger Scan: 1 Trigger)
(a) Setting when scanning ANI0 to ANI3
INTM000
ANI0
ADCR0
ANI1
ADCR1
ANI2
ADCR2
ANI3
(1)
A/D converter
ADCR3
ANI4
ADCR4
ANI5
ADCR5
ANI6
ADCR6
ANI7
ADCR7
The ADCE bit of ADM0 is set to 1 (enable)
(8)
The CCC00 compare is generated
ANI2 is A/D converted
(2)
The CCC00 compare is generated
(9)
(3)
ANI0 is A/D converted
(10) The conversion result is stored in ADCR2
(4)
The conversion result is stored in ADCR0
(11) The CCC00 compare is generated
(5)
The CCC00 compare is generated
(12) ANI3 is A/D converted
(6)
ANI1 is A/D converted
(13) The conversion result is stored in ADCR3
(7)
The conversion result is stored in ADCR1
(14) The INTAD interrupt is generated
Caution
INTM0nn cannot be used as a trigger for the analog inputs enclosed in the broken lines (n
= 0, 1). When a setting is made to scan ANI0 to ANI7, ANI4 to ANI7 are converted in A/D
trigger mode (see (b) below).
(b) Setting when scanning ANI0 to ANI7
INTM000
ANI0
ADCR0
ANI1
ADCR1
ANI2
ADCR2
ANI3
(1) to (13)
A/D converter
ADCR3
ANI4
ADCR4
ANI5
ADCR5
ANI6
ADCR6
ANI7
ADCR7
Same as (a)
(18) ANI6 is A/D converted
(14) ANI4 is A/D converted
(19) The conversion result is stored in ADCR6
(15) The conversion result is stored in ADCR4
(20) ANI7 is A/D converted
(16) ANI5 is A/D converted
(21) The conversion result is stored in ADCR7
(17) The conversion result is stored in ADCR5
(22) The INTAD interrupt is generated
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(2) 4-trigger mode
In this mode, analog inputs are A/D converted for the number of times specified using the match interrupt
signal (INTM000, INTM001, INTM010, INTM011) as a trigger.
The analog input and ADCRn register correspond one to one.
When all the specified A/D conversions have ended, the A/D conversion end interrupt (INTAD) is generated
and A/D conversion is stopped.
Trigger
Analog Input
A/D Conversion Result Register
INTM000 interrupt
ANI0
ADCR0
INTM001 interrupt
ANI1
ADCR1
INTM010 interrupt
ANI2
ADCR2
INTM011 interrupt
ANI3
ADCR3
(A/D trigger mode)
ANI4
ADCR4
ANI5
ADCR5
ANI6
ADCR6
ANI7
ADCR7
To restart A/D conversion in 1-shot mode, restart TMCn. If set to the loop mode and the ADCEn bit is 1, A/D
conversion is restarted when a match interrupt is generated after conversion has ended.
The match interrupt can be generated in any order. However, because the trigger signal and the analog input
correspond one to one, the scanning sequence is determined according to the order in which the match
signals of the compare register are generated.
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Figure 12-14. Example of 4-Trigger Mode Operation (Timer Trigger Scan: 4 Triggers)
(a) Setting when scanning ANI0 to ANI3
random
(1)
INTM000
ANI0
ADCR0
INTM001
ANI1
ADCR1
INTM010
ANI2
ADCR2
INTM011
ANI3
A/D converter
ADCR3
ANI4
ADCR4
ANI5
ADCR5
ANI6
ADCR6
ANI7
ADCR7
The ADCE bit of ADM0 is set to 1 (enable)
(8)
The CCC00 compare is generated (random)
ANI0 is A/D converted
(2)
The CCC01 compare is generated (random)
(9)
(3)
ANI1 is A/D converted
(10) The conversion result is stored in ADCR0
(4)
The conversion result is stored in ADCR1
(11) The CCC10 compare is generated (random)
(5)
The CCC11 compare is generated (random)
(12) ANI2 is A/D converted
(6)
ANI3 is A/D converted
(13) The conversion result is stored in ADCR2
(7)
The conversion result is stored in ADCR3
(14) The INTAD interrupt is generated
Caution
INTM0nn cannot be used as a trigger for the analog inputs enclosed in the broken lines
TM0nn (n = 0, 1).
When a setting is made to scan ANI0 to ANI7, ANI4 to ANI7 are
converted in A/D trigger mode (see (b) below).
(b) Setting when scanning ANI0 to ANI7
random
INTM000
ANI0
ADCR0
INTM001
ANI1
ADCR1
INTM010
ANI2
ADCR2
INTM011
ANI3
(1) to (13)
A/D converter
ADCR3
ANI4
ADCR4
ANI5
ADCR5
ANI6
ADCR6
ANI7
ADCR7
Same as (a)
(18) ANI6 is A/D converted
(14) ANI4 is A/D converted
(19) The conversion result is stored in ADCR6
(15) The conversion result is stored in ADCR4
(20) ANI7 is A/D converted
(16) ANI5 is A/D converted
(21) The conversion result is stored in ADCR7
(17) The conversion result is stored in ADCR5
(22) The INTAD interrupt is generated
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12.7 Operation in External Trigger Mode
In the external trigger mode, the analog inputs (ANI0 to ANI3) are A/D converted by the ADTRG pin input timing.
The ADTRG pin has an alternate function as the P37 and INTP123 pins. To set the external trigger mode, set the
PMC37 bit of the PMC3 register to 1 and bits TRG2 to TRG0 of the ADM1 register to 110.
For the valid edge of the external input signal during the external trigger mode, the rising edge, falling edge, or both
rising and falling edges can be specified using bits ES1231 and ES1230 of the INTM3 register. For details, see 7.3.9
(1) External interrupt mode registers 1 to 4 (INTM1 to INTM4).
12.7.1 Select mode operations (external trigger select)
In this mode, one analog input (ANI0 to ANI3) specified by the ADM0 register is A/D converted. The conversion
results are stored in the ADCRn register corresponding to the analog input. There are two select modes: 1-buffer
mode and 4-buffer mode, according to the storing method of the A/D conversion results (n = 0 to 3).
(1) 1-buffer mode (external trigger select: 1-buffer)
In this mode, one analog input is A/D converted using the ADTRG signal as a trigger. The conversion results
are stored in one ADCRn register. The analog input and the A/D conversion results register correspond one
to one. The A/D conversion end interrupt (INTAD) is generated for each A/D conversion, and A/D conversion
is stopped.
Trigger
ADTRG signal
Analog Input
ANIn
A/D Conversion Result Register
ADCRn
While the ADCE bit of the ADM0 register is 1, A/D conversion is repeated every time a trigger is input from
the ADTRG pin.
This mode is most appropriate for applications in which the results are read after each A/D conversion.
Figure 12-15. Example of 1-Buffer Mode Operation (External Trigger Select: 1 Buffer)
ADTRG
ANI0
ADCR0
ANI1
ADCR1
ANI2
ADCR2
ANI3
A/D converter
ADCR3
ADCR4
ADCR5
ADCR6
ADCR7
426
(1)
The ADCE bit of ADM0 is set to 1 (enable)
(2)
The external trigger is generated
(3)
ANI2 is A/D converted
(4)
The conversion result is stored in ADCR2
(5)
The INTAD interrupt is generated
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(2) 4-buffer mode (external trigger select: 4 buffers)
In this mode, one analog input is A/D converted four times using the ADTRG signal as a trigger and the
results are stored in the ADCR0 to ADCR3 registers. The A/D conversion end interrupt (INTAD) is generated
and A/D conversion is stopped after the 4th A/D conversion.
Trigger
Analog Input
A/D Conversion Result Register
ADTRG signal
ANIn
ADCR0
ADTRG signal
ANIn
ADCR1
ADTRG signal
ANIn
ADCR2
ADTRG signal
ANIn
ADCR3
While the ADCE bit of the ADM0 register is 1, A/D conversion is repeated every time a trigger is input from
the ADTRG pin.
This mode is suitable for applications in which calculate the average of A/D conversion result is calculated.
Figure 12-16. Example of 4-Buffer Mode Operation (External Trigger Select: 4 Buffers)
ANI0
(×4)
ADTRG
ADCR0
ANI1
ADCR1
(×4)
ANI2
ADCR2
ANI3
A/D converter
ADCR3
ADCR4
ADCR5
ADCR6
ADCR7
(1)
The ADCE bit of ADM0 is set to 1 (enable)
(8)
The external trigger is generated
(2)
The external trigger is generated
(9)
ANI2 is A/D converted
(3)
ANI2 is A/D converted
(10) The conversion result is stored in ADCR2
(4)
The conversion result is stored in ADCR0
(11) The external trigger is generated
(5)
The external trigger is generated
(12) ANI2 is A/D converted
(6)
ANI2 is A/D converted
(13) The conversion result is stored in ADCR3
(7)
The conversion result is stored in ADCR1
(14) The INTAD interrupt is generated
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12.7.2 Scan mode operation (external trigger scan)
In this mode, the analog inputs specified by the ADM0 register are selected sequentially from the ANI0 pin using
the ADTRG signal as a trigger, and A/D converted. The A/D conversion results are stored in the ADCRn register
corresponding to the analog input (n = 0 to 7).
When the lower 4 channels (ANI0 to ANI3) of the analog input are set by the ADM0 register so that they are
scanned, the A/D conversion end interrupt (INTAD) is generated when the number of A/D conversions specified have
ended, and A/D conversion is stopped.
When the higher 4 channels (ANI4 to ANI7) of the analog input are set by the ADM0 register so that they are
scanned, after the conversion of the lower 4 channels is ended, the mode is shifted to the A/D trigger mode, and the
remaining A/D conversions are executed. The conversion results are stored in the ADCRn register corresponding to
the analog input (n = 0 to 7).
Trigger
Analog Input
A/D Conversion Result Register
ADTRG signal
ANI0
ADCR0
ADTRG signal
ANI1
ADCR1
ADTRG signal
ANI2
ADCR2
ADTRG signal
ANI3
ADCR3
(A/D trigger mode)
ANI4
ADCR4
ANI5
ADCR5
ANI6
ADCR6
ANI7
ADCR7
When the conversion of all the specified analog inputs has ended, the INTAD interrupt is generated and A/D
conversion is stopped.
When a trigger is input to the ADTRG pin while the ADCE bit of the ADM0 register is 1, A/D conversion is started
again.
This is most appropriate for applications in which multiple analog inputs are constantly monitored.
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Figure 12-17. Example of Scan Mode Operation (External Trigger Scan)
(a) Setting when scanning ANI0 to ANI3
ADTRG
(1)
ANI0
ADCR0
ANI1
ADCR1
ANI2
ADCR2
ANI3
A/D converter
ADCR3
ANI4
ADCR4
ANI5
ADCR5
ANI6
ADCR6
ANI7
ADCR7
The ADCE bit of ADM0 is set to 1 (enable)
(8)
The external trigger is generated
ANI2 is A/D converted
(2)
The external trigger is generated
(9)
(3)
ANI0 is A/D converted
(10) The conversion result is stored in ADCR2
(4)
The conversion result is stored in ADCR0
(11) The external trigger is generated
(5)
The external trigger is generated
(12) ANI3 is A/D converted
(6)
ANI1 is A/D converted
(13) The conversion result is stored in ADCR3
(7)
The conversion result is stored in ADCR1
(14) The INTAD interrupt is generated
Caution
ADTRG cannot be used as a trigger for the analog inputs enclosed in the broken lines.
When a setting is made to scan ANI0 to ANI7, ANI4 to ANI7 are converted in A/D trigger
mode (see (b) below).
(b) Setting when scanning ANI0 to ANI7
ADTRG
(1) to (13)
ANI0
ADCR0
ANI1
ADCR1
ANI2
ADCR2
ANI3
A/D converter
ADCR3
ANI4
ADCR4
ANI5
ADCR5
ANI6
ADCR6
ANI7
ADCR7
Same as (a)
(18) ANI6 is A/D converted
(14) ANI4 is A/D converted
(19) The conversion result is stored in ADCR6
(15) The conversion result is stored in ADCR4
(20) ANI7 is A/D converted
(16) ANI5 is A/D converted
(21) The conversion result is stored in ADCR7
(17) The conversion result is stored in ADCR5
(22) The INTAD interrupt is generated
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12.8 Notes on Operation
12.8.1 Stopping conversion operation
When the ADCE bit of the ADM0 register is set to 0 during a conversion operation, the conversion operation stops
and the conversion results are not stored in the ADCRn register (n = 0 to 7).
12.8.2 External/timer trigger interval
Set the interval (input time interval) of the trigger in the external or timer trigger mode longer than the conversion
time specified by the FR2 to FR0 bits of the ADM1 register.
(1) When interval = 0
When several triggers are input simultaneously, the analog input with the smaller ANIn pin number is
converted. The other trigger signals input simultaneously are ignored, and the number of trigger input is not
counted. Note, therefore, that the saving of the result to the ADCRn register upon the generation of an
interrupt is an abnormality (n = 0 to 7).
(2) When 0 < interval < conversion operation time
When the timer trigger is input during a conversion operation, the conversion operation is aborted and the
conversion starts according to the last timer trigger input.
When conversion operations are aborted, the conversion results are not stored in the ADCRn register, and
the number of trigger input are not counted. Note, therefore, that the saving of the result to the ADCRn
register upon the generation of an interrupt is an abnormality (n = 0 to 7).
(3) When interval = conversion operation time
When a trigger is input concurrently with the end of conversion (the end of conversion signal and the trigger
are in contention), although the number of triggers input are counted, an interrupt is generated, and the value
at the end of conversion is correctly saved in the ADCRn register, design should be performed so that the
interval is greater than the conversion operation time.
12.8.3 Operation in standby mode
(1) HALT mode
In this mode, A/D conversion continues. When this mode is released by NMI input, the ADM0 and ADM1
registers and ADCRn register hold the value (n = 0 to 7).
(2) IDLE mode, STOP mode
As clock supply to the A/D converter is stopped, no conversion operations are performed.
When these modes are released by NMI input or maskable interrupt input (INTP1xx), the ADM0 and ADM1
registers and the ADCRn register hold the value. However, when the IDLE or software STOP mode is set
during a conversion operation, the conversion operation is stopped. At this time, if the mode released by NMI
input or maskable interrupt input (INTP1xx), the conversion operation resumes, but the conversion result
written to the ADCRn register will become undefined (x = 0 to 3, n = 0 to 7).
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CHAPTER 12
A/D CONVERTER
12.8.4 Compare match interrupt in timer trigger mode
The compare register’s match interrupt becomes an A/D conversion start trigger and starts the conversion
operation. When this happens, the compare register’s match interrupt also functions as a compare register match
interrupt for the CPU. In order to prevent match interrupts from the compare register for the CPU, disable interrupts
using the mask bits (P00MK0, P00MK1, P01MK0, P01MK1) of the interrupt control register (P00IC0, P00IC1, P01IC0,
P01IC1).
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CHAPTER 13 PWM UNIT
13.1 Features
• PWMn: 2 channels
• PWMn: Output pulse active level can be selected
• Operation clock can be selected from among φ/2, φ/4, φ/8, φ/16, φ/32, φ/64 (φ is the internal system clock)
• PWMn output resolution can be selected from among 8, 9, 10, 12 bits
Remark
n = 0, 1
13.2 Block Diagram
φ /2
φ /4
φ /8
φ /16
φ /32
φ /64
Selector
selclk
0 to 7
0 to 8
0 to 9
0 to 11
Counter (TMPn)
(Edge latch)
Output control block
S
Q
PWMn
12
RNote
3
0 to 7
0 to 8
0 to 9
0 to 11
Comparator
Match
Overflow
12
Compare register
(CMPn)
(Level latch)
2
12
PWM control register n
(PWMCn) (Edge latch)
Reload processing
PWMCAEn ALVn
PWM buffer register
(PWMBn)
(Level latch)
PRMn1 PRMn0
2
Note Reset has priority.
Remark
432
n = 0, 1
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0
PWPn2 PWPn1 PWPn0
CHAPTER 13 PWM UNIT
13.3 Control Register
(1) PWM control registers 0, 1 (PWMC0, PWMC1)
The PWMCn register is used to control the PWMn’s operations (n = 0, 1).
The PWMCn register can be read/written in 8-bit or 1-bit units.
Caution
When PWMn is used, be sure to set external pins related to PWMn to control mode.
Following that, set the operation clock, etc. using the PWMCn register and set the PWMEn
bit to 1 after the PWMBn register setting is made.
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CHAPTER 13 PWM UNIT
PWMCn
<7>
<6>
5
4
3
2
1
0
Address
After Reset
PWMEn
ALVn
PRMn1
PRMn0
0
PWPn2
PWPn1
PWPn0
FFFFFC00H,
FFFFFC10H
40H
Bit position
7
Bit name
Note
PWMEn
(n = 0, 1)
6
ALVn
(n = 0, 1)
5, 4
PRMn1,
PRMn0
(n = 0, 1)
2 to 0
PWPn2 to
PWPn0
(n = 0, 1)
Description
PWM Enable
This bit is used to enable or disable PWMn operation.
0: PWM operation disabled
1: PWM operation enabled
Active Level
This bit is used to specify the active level for PWMn output.
0: Active level is low level
1: Active level is high level
The PWMn outputs inactive level (low level) of the ALVn bit after reset.
Prescaler Mode
This bit is used to select the bit length for the counter (TMPn) and compare register (CMPn).
PRMn1
PRMn0
Bit length for TMPn and CMPn
0
0
8 bits
0
1
9 bits
1
0
10 bits
1
1
12 bits
PWM Prescaler Clock Mode
This bit is used to select the PWMn’s operating clock.
PWPn2
PWPn1
PWPn0
0
0
0
φ/2
0
0
1
φ/4
0
1
0
φ/8
0
1
1
φ/16
1
0
0
φ/32
1
0
1
φ/64
Other than above
Operating clock
Setting prohibited
Note If PWMEn is changed from 0 to 1, the counter (TMPn) is reset to start counting from 000H (in 12 bits). The
first overflow permits the PWMn signal activation. If the bit length and operating clock of PWM0 and
PWM1 are the same, the activation timing of these two PWMn signals can be adjusted. If PWMEn was
already 1, the counter is not reset upon an additional write of 1. When setting PWMEn to 1, set it to 0
beforehand.
Remark n = 0, 1
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CHAPTER 13 PWM UNIT
(2) PWM buffer registers 0, 1 (PWMB0, PWMB1)
The PWMBn register is a 12-bit buffer register that is used to set control data for the active signal width of
PWMn output. Bits 15 to 12 are fixed to zero. Even if 1 is written in these bits, it is ignored. It is possible to
directly read the values of bits 11 to 8 as written irrespective of the bit length setting made by the PWMCn
register.
The contents in PWMBn registers are transferred to compare registers (CMPn) at the timing of the
generation of an overflow from the PWMn output control counter (TMPn).
The PWM buffer registers can be read or written in 16-bit units.
Remark n = 0, 1
PWMB0
PWMB1
15
14
13
12
11
10
0
0
0
0
PWM11 PWM10 PWM9 PWM8 PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 FFFFFC02H
15
14
13
12
11
0
0
0
0
PWM11 PWM10 PWM9 PWM8 PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 FFFFFC12H
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
Address
Address
After reset
0000H
After reset
0000H
13.4 Operation
13.4.1 Basic operations
When a PWMn pulse is output, the required data is first set to the PWMCn and PWMBn registers, then the
PWMCn register’s PWMEn bit is set (1). This clears (0) the counter (TMPn) and, when the first overflow occurs, the
active level is set for PWMn output and the data is transferred from the PWMBn register to the compare register
(CMPn). Afterward, PWMn output goes inactive when a match occurs between the TMPn and CMPn register values.
When this is repeated, a PWMn signal whose active level is specified by the ALVn bit in the PWMCn register is
output from the PWMn pin.
When the PWMCn register’s PWMEn bit is cleared (0), PWMn output is stopped immediately and is set to the
inactive level for the ALVn level specified by the PWMCn register.
If, during PWMn signal output, the values of the PWPn2 to PWPn0 bits, PRMn1 and PRMn0 bits, or ALVn bit are
changed, the cycle width and pulse width of the PWMn signal are not guaranteed within the cycle where the changes
were made.
Remark n = 0, 1
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CHAPTER 13 PWM UNIT
Figure 13-1. PWM Basic Operation Timing
PWMEn bit
Start TMPn count
Counter
00H
FEH
FFH
00H
01H
02H
FEH
FFH
00H
01H
Overflow
signal
PWMBn
register
FEH
Reload
CMPn
register
00H
FEH
Comparator
match signal
Set
Reset
Set
PWMn
(Output)
FEH count
Full count
Remark
n = 0, 1
Figure 13-2. Timing for Write Operation to PWMBn Register
PWMEn bit
Counter
Start TMPn count
00H
01H
02H
03H
x
FDH FEH
FFH
00H
01H
02H
03H
04H
M
FEH
FFH
00H
01H
N
FBH FCH FDH FEH
FFH
00H
Overflow
signal
PWMBn
PWMBn
register
M
CMPn
register
N
X
Q
M
N
Q
Comparator
match signal
Set
Set
Set
PWMn
(Output)
Full count
Remark
436
M count
n = 0, 1
User’s Manual U14359EJ3V0UM
N count
01H
CHAPTER 13 PWM UNIT
Figure 13-3. Timing When PWMBn Register Is Set to 00H
Counter
FEH
FFH
00H
01H
02H
FEH
FFH
00H
01H
02H
FEH
FFH
00H
01H
FFH
00H
01H
Overflow
signal
PWMBn
register
00H
CMPn
register
00H
Comparator
match signal
PWMn
(Output)
L
Not set to active level
Remark
n = 0, 1
Figure 13-4. Timing When PWMBn Register Is Set to FFH
Counter
FEH
FFH
00H
01H
02H
FEH
FFH
00H
01H
02H
FEH
Overflow
signal
PWMBn
register
FFH
CMPn
register
FFH
Comparator
match signal
PWMn
(Output)
1 count
Remark
n = 0, 1
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CHAPTER 13 PWM UNIT
13.4.2 Repetition frequency
The repetition frequencies of PWMn are shown below (n = 0, 1).
PWMn Operating
Frequency
Resolution
Repetition Frequency
φ/2
8 bits
9 bits
10 bits
12 bits
φ/29
φ/210
φ/211
φ/213
φ/4
8 bits
9 bits
10 bits
12 bits
φ/210
φ/211
φ/212
φ/214
φ/8
8 bits
9 bits
10 bits
12 bits
φ/211
φ/212
φ/213
φ/215
φ/16
8 bits
9 bits
10 bits
12 bits
φ/212
φ/213
φ/214
φ/216
φ/32
8 bits
9 bits
10 bits
12 bits
φ/213
φ/214
φ/215
φ/217
φ/64
8 bits
9 bits
10 bits
12 bits
φ/214
φ/215
φ/216
φ/218
13.5 Cautions
The PWM0 pin has an alternate function as the P00 pin (Port 0) and the PWM1 pin has an alternate function as
the P10 pin (Port 1). When using these pins for PWMn output, set the bits corresponding to the PMC0 and PMC1
registers to 1.
If the bit settings corresponding to the PMC0 and PMC1 registers are changed during PWMn pulse output, the
PWMn pulse output is not guaranteed.
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CHAPTER 14 PORT FUNCTIONS
14.1 Features
• Input-only ports:
9
Input/output ports: 106
• Function alternately as other peripheral I/O pins.
• It is possible to specify input and output in 1-bit units.
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CHAPTER 14 PORT FUNCTIONS
14.2 Port Configuration
The V850E/MA1 incorporates a total of 115 input/output ports (including 9 input-only ports) labeled ports 0 through
5, and AL, AH, DL, CS, CT, CM, CD, and BD. The port configuration is shown below.
P00
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 7
to
PAL0
to
P07
PAL15
P10
PAH0
to
to
P13
PAH9
P20
P21
to
P27
PDL0
PDL15
P30
PCS0
to
to
to
P37
PCS7
P40
to
PCT0
PCT1
PCT4
P45
PCT7
P50
PCM0
to
to
P52
PCM5
P70
PCD0
to
to
P77
Port AL
Port AH
Port DL
Port CS
Port CT
Port CM
Port CD
PCD3
PBD0
to
PBD3
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Port BD
CHAPTER 14 PORT FUNCTIONS
(1) Function of each port
The port functions of this product are shown below.
8-bit and 1-bit operations are possible on all ports, allowing various kinds of control to be performed. In
addition to their port functions, these pins also function as internal peripheral I/O input/output pins in the
control mode. For the block types of each port, see (3) Block diagram of port.
Port Name
Pin Name
Port Function
Function in Control Mode
Block Type
Port 0
P00 to P07
8-bit I/O
Real-time pulse unit (RPU) I/O
External interrupt input
PWM output
DMA controller input
A, B, H
Port 1
P10 to P13
4-bit I/O
Real-time pulse unit (RPU) I/O
External interrupt input
PWM output
A, B
Port 2
P20 to P27
1-bit input,
7-bit I/O
NMI input
Real-time pulse unit (RPU) I/O
External interrupt input
DMA controller output
A, B, F, N
Port 3
P30 to P37
8-bit I/O
Serial interface I/O (CSI2, UART2)
External interrupt input
A/D converter external trigger input
B, H, I, N
Port 4
P40 to P45
6-bit I/O
Serial interface I/O (UART0/CSI0, UART1/CSI1)
H, L, M
Port 5
P50 to P52
3-bit I/O
Real-time pulse unit (RPU) I/O
External interrupt input
A, B
Port 7
P70 to P77
8-bit input
A/D converter input
C
Port AL
PAL0 to PAL15
16-bit I/O
External address bus (A0 to A15)
J
Port AH
PAH0 to PAH9
10-bit I/O
External address bus (A16 to A25)
J
Port DL
PDL0 to PDL15 16-bit I/O
External data bus (D0 to D15)
O
Port CS
PCS0 to PCS7
8-bit I/O
External bus interface control signal output
J, K
Port CT
PCT0,PCT1,
PCT4 to PCT7
6-bit I/O
External bus interface control signal output
J
Port CM
PCM0 to PCM5 6-bit I/O
Wait insertion signal input
Internal system clock output/Bus clock output
External bus interface control signal I/O
Self-refresh request signal input
D, E, J, K
Port CD
PCD0 to PCD3
4-bit I/O
External bus interface control signal output
J, K
Port BD
PBD0 to PBD3
4-bit I/O
DMA controller output
J
Caution
When switching the mode of a port that functions as an output or I/O pin to control mode, be sure
to follow the procedure below.
<1> Set the inactive level of the signals output in control mode to the appropriate bits in port n (n =
0 to 5, AL, AH, DL, CS, CT, CM, CD, and BD).
<2> The mode is switched to control mode by the port n mode control register (PMCn).
If <1> above is not performed, the contents of port n may be output for a moment when the mode is
switched from port mode to control mode.
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CHAPTER 14 PORT FUNCTIONS
(2) Function when each port’s pins are reset and registers that set the port/control mode
(1/2)
Port Name
Pin Name
Pin Function After Reset
Single-Chip
Mode 0
Port 0
Port 1
Port 2
Port 3
Port 4
442
P00/PWM0
P00 (input mode)
P01/INTP000/TI000
P01 (input mode)
P02/INTP001
P02 (input mode)
P03/TO00
P03 (input mode)
P04/DMARQ0/INTP100
P04 (input mode)
P05/DMARQ1/INTP101
P05 (input mode)
P06/DMARQ2/INTP102
P06 (input mode)
Single-Chip
Mode 1
ROMless
Mode 0
ROMless
Mode 1
Register That
Sets the Mode
PMC0
PMC0, PFC0
P07/DMARQ3/INTP103
P07 (input mode)
P10/PWM1
P10 (input mode)
P11/INTP010/TI010
P11 (input mode)
P12/INTP011
P12 (input mode)
P13/TO01
P13 (input mode)
P20/NMI
NMI
P21/INTP020/TI020
P21 (input mode)
P22/INTP021
P22 (input mode)
P23/TO02
P23 (input mode)
P24/TC0/INTP110
P24 (input mode)
P25/TC1/INTP111
P25 (input mode)
P26/TC2/INTP112
P26 (input mode)
P27/TC3/INTP113
P27 (input mode)
P30/SO2/INTP130
P30 (input mode)
P31/SI2/INTP131
P31 (input mode)
P32/SCK2/INTP132
P32 (input mode)
P33/TXD2/INTP133
P33 (input mode)
P34/RXD2/INTP120
P34 (input mode)
P35/INTP121
P35 (input mode)
P36/INTP122
P36 (input mode)
P37/ADTRG/INTP123
P37 (input mode)
P40/TXD0/SO0
P40 (input mode)
P41/RXD0/SI0
P41 (input mode)
P42/SCK0
P42 (input mode)
PMC4
P43/TXD1/SO1
P43 (input mode)
PMC4, PFC4
P44/RXD1/SI1
P44 (input mode)
P45/SCK1
P45 (input mode)
PMC1
–
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PMC2
PMC2, PFC2
PMC3, PFC3
PMC3
PMC4, PFC4
PMC4
CHAPTER 14 PORT FUNCTIONS
(2/2)
Port Name
Pin Name
Pin Function After Reset
Single-Chip
Mode 0
Port 5
Single-Chip
Mode 1
ROMless
Mode 0
ROMless
Mode 1
Register That
Sets the Mode
P50/INTP030/TI030
P50 (input mode)
P51/INTP031
P51 (input mode)
P52/TO03
P52 (input mode)
Port 7
P70/ANI0 to P77/ANI7
P70 to P77 (input mode)
Port BD
PBD0/DMAAK0 to
PBD3/DMAAK3
PBD0 to PBD3 (input mode)
PMCBD
Port CM
PCM0/WAIT
PCM0 (input mode)
WAIT
PMCCM
PCM1/CLKOUT/BUSCLK
PCM1 (input mode)
CLKOUT/BUSCLK
PMCCM,PFCCM
PCM2/HLDAK
PCM2 (input mode)
HLDAK
PMCCM
PCM3/HLDRQ
PCM3 (input mode)
HLDRQ
PCM4/REFRQ
PCM4 (input mode)
REFRQ
PCM5/SELFREF
PCM5 (input mode)
SELFREF
PCT0/LCAS/LWR/LDQM
PCT0 (input mode)
LCAS/LWR/LDQM
Port CT
PMC5
–
PMCCT
PCT1/UCAS/UWR/UDQM PCT1 (input mode)
UCAS/UWR/UDQM
PCT4/RD
PCT4 (input mode)
RD
PCT5/WE
PCT5 (input mode)
WE
PCT6/OE
PCT6 (input mode)
OE
PCT7/BCYST
PCT7 (input mode)
BCYST
PCS0/CS0
PCS0 (input mode)
CS0
PCS1/CS1/RAS1
PCS1 (input mode)
CS1/RAS1
PCS2/CS2/IOWR
PCS2 (input mode)
CS2/IOWR
PMCCS,PFCCS
PCS3/CS3/RAS3
PCS3 (input mode)
CS3/RAS3
PMCCS
PCS4/CS4/RAS4
PCS4 (input mode)
CS4/RAS4
PCS5/CS5/IORD
PCS5 (input mode)
CS5/IORD
PMCCS,PFCCS
PCS6/CS6/RAS6
PCS6 (input mode)
CS6/RAS6
PMCCS
PCS7/CS7
PCS7 (input mode)
CS7
PCD0/SDCKE
PCD0 (input mode)
SDCKE
PCD1/SDCLK
PCD1 (input mode)
SDCLK
PCD2/LBE/SDCAS
PCD2 (input mode)
LBE/SDCAS
PCD3/UBE/SDRAS
PCD3 (input mode)
UBE/SDRAS
Port AH
PAH0/A16 to PAH9/A25
PAH0 to PAH9
(input mode)
A16 to A25
PMCAH
Port AL
PAL0/A0 to PAL15/A15
PAL0 to PAL15
(input mode)
A0 to A15
PMCAL
Port DL
PDL0/D0 to PDL15/D15
PDL0 to PDL15
(input mode)
D0 to D15
PMCDL
Port CS
Port CD
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PMCCS
PMCCD
PMCCD,PFCCD
443
CHAPTER 14 PORT FUNCTIONS
(3) Block diagram of port
Figure 14-1. Block Diagram of Type A
WRPMC
PMCmn
WRPM
Output signal
in control
mode
Selector
Pmn
RDIN
Remark
Address
m: Port number
n: Bit number
444
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Pmn
Selector
WRPORT
Selector
Internal bus
PMmn
CHAPTER 14 PORT FUNCTIONS
Figure 14-2. Block Diagram of Type B
WRPMC
PMCmn
WRPM
WRPORT
Pmn
Selector
Pmn
Selector
Internal bus
PMmn
Address
RDIN
Input signal in
control mode
Remark
Noise elimination
Edge detection
m: Port number
n:
Bit number
Internal bus
Figure 14-3. Block Diagram of Type C
P7n
RDIN
Input signal in
control mode
Remark
Sample & hold
circuit
ANIn
n = 0 to 7
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CHAPTER 14 PORT FUNCTIONS
Figure 14-4. Block Diagram of Type D
MODE0 to MODE2
WRPMC
PMCCMn
WRPM
Internal bus
PMCMn
WRPORT
PCMn
Selector
Selector
PCMn
Address
RDIN
Remark
446
Input signal in
control mode
n = 0, 3
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CHAPTER 14 PORT FUNCTIONS
Figure 14-5. Block Diagram of Type E
MODE0 to MODE2
WRPMC
PMCCM5
WRPM
Internal bus
PMCM5
WRPORT
PCM5
Selector
Selector
PCM5
Address
RDIN
Input signal in
control mode
Selector
Internal bus
Figure 14-6. Block Diagram of Type F
1
Noise
elimination
P20
Address
RDIN
NMI
Edge detection
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CHAPTER 14 PORT FUNCTIONS
Figure 14-7. Block Diagram of Type H
WRPFC
PFCmn
WRPMC
PMCmn
Internal bus
WRPM
PMmn
WRPORT
Pmn
Address
Input signal in
control mode
Remark
m: Port number
n:
448
Selector
RDIN
Bit number
User’s Manual U14359EJ3V0UM
Selector
Selector
Pmn
CHAPTER 14 PORT FUNCTIONS
Figure 14-8. Block Diagram of Type I
WRPFC
PFC32
WRPMC
SCK2 output
enable signal
PMC32
Internal bus
WRPM
PM32
Output signal in
control mode
Selector
Selector
P32
P32
Selector
WRPORT
Address
Input signal in
control mode
Selector
RDIN
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CHAPTER 14 PORT FUNCTIONS
Figure 14-9. Block Diagram of Type J
WRPMC
MODE0 to MODE2
PMCmn
WRPM
Output signal in
control mode
Selector
Pmn
Pmn
Selector
WRPORT
Selector
Internal bus
PMmn
Address
RDIN
Remark
m: Port number
n: Bit number
450
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CHAPTER 14 PORT FUNCTIONS
Figure 14-10. Block Diagram of Type K
WRPFC
MODE0 to MODE2
PFCmn
WRPMC
PMCmn
Internal bus
WRPM
Selector
Pmn
Pmn
Selector
Output signal in
control mode
Selector
WRPORT
Selector
PMmn
Address
RDIN
Remark
m: Port number
n: Bit number
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CHAPTER 14 PORT FUNCTIONS
Figure 14-11. Block Diagram of Type L
WRPFC
PFC4n
WRPMC
PMC4n
Internal bus
WRPM
RDIN
Remark
452
Address
n = 0, 3
User’s Manual U14359EJ3V0UM
P4n
Selector
Selector
P4n
Selector
WRPORT
Output signal in
control mode
Selector
PM4n
CHAPTER 14 PORT FUNCTIONS
Figure 14-12. Block Diagram of Type M
SCKx output
enable signal
WRPMC
PMC4n
WRPM
Output signal in
control mode
Selector
P4n
P4n
Selector
WRPORT
Selector
Internal bus
PM4n
Address
RDIN
Input signal in
control mode
Remark
n = 2, 5
x: 0 (when n = 2)
1 (when n = 5)
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Figure 14-13. Block Diagram of Type N
WRPFC
PFCmn
WRPMC
PMCmn
Internal bus
WRPM
PMmn
Output signal in
control mode
Selector
Selector
Pmn
Address
RDIN
Input signal in
control mode
Remark
Noise elimination
Edge detection
m: Port number
n: Bit number
454
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Selector
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CHAPTER 14 PORT FUNCTIONS
Figure 14-14. Block Diagram of Type O
MODE0 to MODE2
WRPMC
I/O control
PMCDLn
WRPM
Output signal in
control mode
Selector
PDLn
PDLn
Selector
WRPORT
Selector
Internal bus
PMDLn
Address
RDIN
Input signal in
control mode
I/O control
Remark
n = 0 to 15
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14.3 Port Pin Functions
14.3.1 Port 0
Port 0 is an 8-bit I/O port that can be set to the input or output mode in 1-bit units.
P0
7
6
5
4
3
2
1
0
P07
P06
P05
P04
P03
P02
P01
P00
Bit position
7 to 0
Bit name
Address
After reset
FFFFF400H Undefined
Function
P0n (n = 7 to 0) Port 0
I/O port
In addition to their function as port pins, the port 0 pins can also operate as real-time pulse unit (RPU) I/O, external
interrupt request inputs, PWM output, and DMA request inputs in the control mode.
(1) Operation in control mode
Port
Port 0
Alternate Function
Remark
Block Type
P00
PWM0
PWM output
A
P01
INTP000/TI000
External interrupt request input/
Real-time pulse unit (RPU) input
B
P02
INTP001
External interrupt request input
P03
TO00
Real-time pulse unit (RPU) output
A
P04 to P07
DMARQ0/INTP100 to
DMARQ3/INTP103
DMA request input/
external interrupt request input
H
(2) I/O mode/control mode setting
The port 0 I/O mode setting is performed by the port 0 mode register (PM0), and the control mode setting is
performed by the port 0 mode control register (PMC0) and the port 0 function control register (PFC0).
(a) Port 0 mode register (PM0)
This register can be read/written in 8-bit or 1-bit units.
PM0
7
6
5
4
3
2
1
0
Address
After reset
PM07
PM06
PM05
PM04
PM03
PM02
PM01
PM00
FFFFF420H
FFH
Bit position
7 to 0
456
Bit name
PM0n
(n = 7 to 0)
Function
Port Mode
Specifies input/output mode for P0n pin.
0: Output mode (output buffer on)
1: Input mode (output buffer off)
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(b) Port 0 mode control register (PMC0)
This register can be read/written in 8-bit or 1-bit units.
PMC0
7
6
5
4
3
2
1
0
Address
After reset
PMC07
PMC06
PMC05
PMC04
PMC03
PMC02
PMC01
PMC00
FFFFF440H
00H
Bit position
7 to 4
Bit name
Function
PMC0n
(n = 7 to 4)
Port Mode Control
3
PMC03
Port Mode Control
Specifies operation mode of P03 pin.
0: I/O port mode
1: TO00 output mode
2
PMC02
Port Mode Control
Specifies operation mode of P02 pin.
0: I/O port mode
1: External interrupt request (INTP001) input mode
1
PMC01
Port Mode Control
Specifies operation mode of P01 pin.
0: I/O port mode
1: External interrupt request (INTP000) input mode/TI000 input mode
Specifies operation mode of P0n pin in combination with the PFC0 register.
0: I/O port mode (output buffer on)
1: External interrupt request (INTP103 to INTP100) input mode/DMA request
(DMARQ3 to DMARQ0) input mode
There is no register that switches between the external interrupt request
(INTP000) input mode and TI000 input mode
• When TI000 input mode is selected:
Mask the external interrupt request (INTP000) or specify the CCC00 register as
compare register.
• When external interrupt request (INTP000) input mode (including timer capture
input) is selected:
Set the ETI0 bit of the TMCC01 register to 0.
0
PMC00
Port Mode Control
Specifies operation mode of P00 pin.
0: I/O port mode
1: PWM0 output mode
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(c) Port 0 function control register (PFC0)
This register can be read/written in 8-bit or 1-bit units. Bits 3 to 0, however, are fixed to 0, so writing 1 to
these bits is ignored.
Caution
When the port mode is specified by the port 0 mode control register (PMC0), the PFC0
setting becomes invalid.
PFC0
7
6
5
4
3
2
1
0
Address
After reset
PFC07
PFC06
PFC05
PFC04
0
0
0
0
FFFFF460H
00H
Bit position
7 to 4
458
Bit name
PFC0n
(n = 7 to 4)
Function
Port Function Control
Specifies operation mode of P0n pin in control mode.
0: External interrupt request (INTP103 to INTP100) input mode
1: DMA (DMARQ3 to DMARQ0) request input mode
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14.3.2 Port 1
Port 1 is a 4-bit I/O port that can be set to the input or output mode in 1-bit units.
P1
7
6
5
4
3
2
1
0
–
–
–
–
P13
P12
P11
P10
Bit position
3 to 0
Bit name
Address
After reset
FFFFF402H Undefined
Function
P1n
(n = 3 to 0)
Port 1
I/O port
In addition to their function as port pins, the port 1 pins can also operate as real-time pulse unit (RPU) I/O, external
interrupt request inputs, and PWM output in the control mode.
(1) Operation in control mode
Port
Port 1
Alternate Function
Remark
Block Type
P10
PWM1
PWM output
A
P11
TI010/INTP010
External interrupt request input/
Real-time pulse unit (RPU) input
B
P12
INTP011
External interrupt request input
P13
TO01
Real-time pulse unit (RPU) output
A
(2) I/O mode/control mode setting
The port 1 I/O mode setting is performed by the port 1 mode register (PM1), and the control mode setting is
performed by the port 1 mode control register (PMC1).
(a) Port 1 mode register (PM1)
This register can be read/written in 8-bit or 1-bit units.
PM1
7
6
5
4
3
2
1
0
Address
After reset
1
1
1
1
PM13
PM12
PM11
PM10
FFFFF422H
FFH
Bit position
3 to 0
Bit name
PM1n
(n = 3 to 0)
Function
Port Mode
Specifies input/output mode for P1n pin.
0: Output mode (output buffer on)
1: Input mode (output buffer off)
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(b) Port 1 mode control register (PMC1)
This register can be read/written in 8-bit or 1-bit units.
PMC1
7
6
5
4
3
2
1
0
Address
After reset
0
0
0
0
PMC13
PMC12
PMC11
PMC10
FFFFF442H
00H
Bit position
Bit name
Function
3
PMC13
Port Mode Control
Specifies operation mode of P13 pin.
0: I/O port mode
1: TO01 output mode
2
PMC12
Port Mode Control
Specifies operation mode of P12 pin.
0: I/O port mode
1: External interrupt request (INTP011) input mode
1
PMC11
Port Mode Control
Specifies operation mode of P11 pin.
0: I/O port mode
1: External interrupt request (INTP010) input mode/TI010 input mode
There is no register that switches between the external interrupt request
(INTP010) input mode and TI010 input mode.
• When the TI010 input mode is selected:
Mask the external interrupt (INTP010) or specify the CCC10 register as
compare register.
• When external interrupt request (INTP010) input mode (including timer capture
input) is selected:
Set the ETI1 bit of the TMCC11 register to 0.
0
460
PMC10
Port Mode Control
Specifies operation mode of P10 pin.
0: I/O port mode
1: PWM1 output mode
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14.3.3 Port 2
Port 2 is an I/O port that can be set to the input or output mode in 1-bit units except for P20, which is an input-only
pin.
Caution P20 is fixed to NMI input. The level of the NMI input can be read regardless of the PM2 and
PMC2 registers’ values.
P2
7
6
5
4
3
2
1
0
P27
P26
P25
P24
P23
P22
P21
P20
Bit position
7 to 1
Bit name
P2n
(n = 7 to 1)
Address
After reset
FFFFF404H Undefined
Function
Port 2
I/O port
In addition to their function as port pins, the port 2 pins can also operate as the real-time pulse unit (RPU) I/O,
external interrupt request inputs, and the DMA end (terminal count) signal outputs in the control mode.
(1) Operation in control mode
Port
Port 2
Alternate Function
Remark
Block Type
P20
NMI
Non-maskable interrupt request
input
F
P21
INTP020/TI020
External interrupt request input/
Real-time pulse unit (RPU) input
B
P22
INTP021
External interrupt request input
P23
TO02
Real-time pulse unit (RPU) output
A
P24 to 27
TC0/INTP110 to
TC3/INTP113
DMA end signal outputs/External
interrupt request inputs
N
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(2) I/O mode/control mode setting
The port 2 I/O mode setting is performed by the port 2 mode register (PM2), and the control mode setting is
performed by the port 2 mode control register (PMC2) and the port 2 function control register (PFC2).
(a) Port 2 mode register (PM2)
This register can be read/written in 8-bit or 1-bit units.
PM2
7
6
5
4
3
2
1
0
Address
After reset
PM27
PM26
PM25
PM24
PM23
PM22
PM21
1
FFFFF424H
FFH
Bit position
7 to 1
462
Bit name
PM2n
(n = 7 to 1)
Function
Port Mode
Specifies input/output mode for P2n pin.
0: Output mode (output buffer on)
1: Input mode (output buffer off)
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(b) Port 2 mode control register (PMC2)
This register can be read/written in 8-bit or 1-bit units.
PMC2
7
6
5
4
3
2
1
0
Address
After reset
PMC27
PMC26
PMC25
PMC24
PMC23
PMC22
PMC21
1
FFFFF444H
01H
Bit position
7 to 4
Bit name
Function
PMC2n
(n = 7 to 4)
Port Mode Control
Specifies operation mode of P2n pin in combination with the PFC2 register.
0: I/O port mode (output buffer on)
1: External input request (INTP113 to INTP110) input mode/
DMA end signal (TC3 to TC0) output mode
3
PMC23
Port Mode Control
Specifies operation mode of P23 pin.
0: I/O port mode
1: TO02 output mode
2
PMC22
Port Mode Control
Specifies operation mode of P22 pin.
0: I/O port mode
1: External interrupt request (INTP021) input mode
1
PMC21
Port Mode Control
Specifies operation mode of P21 pin.
0: I/O port mode
1: External interrupt request (INTP020) input mode/
TI020 input mode
There is no register that switches between the external interrupt request
(INTP020) input mode and TI020 input mode.
• When the TI020 input mode is selected:
Mask the external interrupt request (INTP020) or specify the CCC20 register as
a compare register.
• When the external interrupt request (INTP020) input mode (including timer
capture input) is selected:
Set the ETI2 bit of the TMCC21 register to 0.
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(c) Port 2 function control register (PFC2)
This register can be read/written in 8-bit or 1-bit units. Bits 3 to 0, however, are fixed to 0 by hardware,
so writing 1 to these bits is ignored.
Caution
When the port mode is specified by the port 2 mode control register (PMC2), the PFC2
setting becomes invalid.
PFC2
7
6
5
4
3
2
1
0
Address
After reset
PFC27
PFC26
PFC25
PFC24
0
0
0
0
FFFFF464H
00H
Bit position
7 to 4
464
Bit name
PFC2n
(n = 7 to 4)
Function
Port Function Control
Specifies operation mode of P2n pin in control mode.
0: External interrupt request (INTP113 to INTP110) input mode
1: DMA end signal (TC3 to TC0) output mode
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14.3.4 Port 3
Port 3 is an 8-bit I/O port that can be set to the input or output mode in 1-bit units.
P3
7
6
5
4
3
2
1
0
P37
P36
P35
P34
P33
P32
P31
P30
Bit position
7 to 0
Bit name
Address
After reset
FFFFF406H Undefined
Function
P3n
(n = 7 to 0)
Port 3
I/O port
In addition to their function as port pins, the port 3 pins can also operate as the serial interface (CSI2, UART2) I/O,
external interrupt request inputs, and A/D converter external trigger input in the control mode.
(1) Operation in control mode
Port
Port 3
Alternate Function
P30
Remark
SO2/INTP130
P31
SI2/INTP131
P32
SCK2/INTP132
P33
TXD2/INTP133
P34
Block Type
N
Serial interface (CSI2) I/O/
External interrupt request inputs
H
I
N
RXD2/INTP120
Serial interface (UART2) I/O/
External interrupt request inputs
H
P35
INTP121
External interrupt request inputs
B
P36
INTP122
P37
ADTRG/INTP123
A/D converter external trigger input/
External interrupt request input
(2) I/O mode/control mode setting
The port 3 I/O mode setting is performed by the port 3 mode register (PM3), and the control mode setting is
performed by the port 3 mode control register (PMC3) and the port 3 function control register 3 (PFC3).
(a) Port 3 mode register (PM3)
This register can be read/written in 8-bit or 1-bit units.
PM3
7
6
5
4
3
2
1
0
Address
After reset
PM37
PM36
PM35
PM34
PM33
PM32
PM31
PM30
FFFFF426H
FFH
Bit position
7 to 0
Bit name
PM3n
(n = 7 to 0)
Function
Port Mode
Specifies input/output mode for P3n pin.
0: Output mode (output buffer on)
1: Input mode (output buffer off)
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(b) Port 3 mode control register (PMC3)
This register can be read/written in 8-bit or 1-bit units.
PMC3
7
6
5
4
3
2
1
0
Address
After reset
PMC37
PMC36
PMC35
PMC34
PMC33
PMC32
PMC31
PMC30
FFFFF446H
00H
Bit position
7
Bit name
PMC37
Function
Port Mode Control
Specifies operation mode of P37 pin.
0: I/O port mode
1: A/D converter external trigger (ADTRG) input mode/
External interrupt request (INTP123) input mode
There is no register that switches between the A/D converter external trigger
(ADTRG) input mode and external interrupt request (INTP123) input mode.
• When the A/D converter external trigger (ADTRG) input mode is selected:
Set to external trigger mode using the ADM1 register.
• When the external interrupt request (INTP123) input mode is selected:
Set to the mode other than external trigger mode using the ADM1 register.
466
6
PMC36
Port Mode Control
Specifies operation mode of P36 pin.
0: I/O port mode
1: External interrupt request (INTP122) input mode
5
PMC35
Port Mode Control
Specifies operation mode of P35 pin.
0: I/O port mode
1: External interrupt request (INTP121) input mode
4
PMC34
Port Mode Control
Specifies operation mode of P34 pin.
0: I/O port mode
1: RXD2 input mode/External interrupt request (INTP120) input mode
3
PMC33
Port Mode Control
Specifies operation mode of P33 pin.
0: I/O port mode
1: TXD2 output mode/External interrupt request (INTP133) input mode
2
PMC32
Port Mode Control
Specifies operation mode of P32 pin.
0: I/O port mode
1: SCK2 input/output mode/External interrupt request (INTP132) input mode
1
PMC31
Port Mode Control
Specifies operation mode of P31 pin.
0: I/O port mode
1: SI2 input mode/External interrupt request (INTP131) input mode
0
PMC30
Port Mode Control
Specifies operation mode of P30 pin.
0: I/O port mode
1: SO2 output mode/External interrupt request (INTP130) input mode
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(c) Port 3 function control register (PFC3)
This register can be read/written in 8-bit or 1-bit units. Bits 5 to 7, however, are fixed to 0, so writing 1 to
these bits is ignored.
Caution
PFC3
When the port mode is specified by the port 3 mode control register (PMC3), the PFC3
setting becomes invalid.
7
6
5
4
3
2
1
0
Address
After reset
0
0
0
PFC34
PFC33
PFC32
PFC31
PFC30
FFFFF466H
00H
Bit position
Bit name
Function
4
PFC34
Port Function Control
Specifies operation mode of P34 pin in control mode.
0: RXD2 input mode
1: External interrupt request (INTP120) input mode
3
PFC33
Port Function Control
Specifies operation mode of P33 pin in control mode.
0: TXD2 output mode
1: External interrupt request (INTP133) input mode
2
PFC32
Port Function Control
Specifies operation mode of P32 pin in control mode.
0: SCK2 I/O mode
1: External interrupt request (INTP132) input mode
1
PFC31
Port Function Control
Specifies operation mode of P31 pin in control mode.
0: SI2 input mode
1: External interrupt request (INTP131) input mode
0
PFC30
Port Function Control
Specifies operation mode of P30 pin in control mode.
0: SO2 output mode
1: External interrupt request (INTP130) input mode
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14.3.5 Port 4
Port 4 is a 6-bit I/O port that can be set to the input or output mode in 1-bit units.
P4
7
6
5
4
3
2
1
0
–
–
P45
P44
P43
P42
P41
P40
Bit position
5 to 0
Bit name
Address
After reset
FFFFF408H Undefined
Function
P4n
(n = 5 to 0)
Port 4
I/O port
In addition to their function as port pins, the port 4 pins can also operate as the serial interface (UART0/CSI0,
UART1/CSI1) I/O in the control mode.
(1) Operation in control mode
Port
Port 4
Alternate Function
Remark
Block Type
P40
TXD0/SO0
P41
RXD0/SI0
H
P42
SCK0
M
P43
TXD1/SO1
P44
RXD1/SI1
H
P45
SCK1
M
Serial interface (UART0/CSI0) I/O
Serial interface (UART1/CSI1) I/O
L
L
(2) I/O mode/control mode setting
The port 4 I/O mode setting is performed by the port 4 mode register (PM4), and the control mode setting is
performed by the port 4 mode control register (PMC4) and the port 4 function control register (PFC4).
(a) Port 4 mode register (PM4)
This register can be read/written in 8-bit or 1-bit units.
PM4
7
6
5
4
3
2
1
0
Address
After reset
1
1
PM45
PM44
PM43
PM42
PM41
PM40
FFFFF428H
FFH
Bit position
5 to 0
468
Bit name
PM4n
(n = 5 to 0)
Function
Port Mode
Specifies input/output mode for P4n pin
0: Output mode (output buffer on)
1: Input mode (output buffer off)
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(b) Port 4 mode control register (PMC4)
This register can be read/written in 8-bit or 1-bit units.
PMC4
7
6
5
4
3
2
1
0
Address
After reset
0
0
PMC45
PMC44
PMC43
PMC42
PMC41
PMC40
FFFFF448H
00H
Bit position
Bit name
Function
5
PMC45
Port Mode Control
Specifies operation mode of P45 pin.
0: I/O port mode
1: SCK1 I/O mode
4
PMC44
Port Mode Control
Specifies operation mode of P44 pin.
0: I/O port mode
1: RXD1/SI1 input mode
3
PMC43
Port Mode Control
Specifies operation mode of P43 pin.
0: I/O port mode
1: TXD1/SO1 output mode
2
PMC42
Port Mode Control
Specifies operation mode of P42 pin.
0: I/O port mode
1: SCK0 I/O mode
1
PMC41
Port Mode Control
Specifies operation mode of P41 pin.
0: I/O port mode
1: RXD0/SI0 input mode
0
PMC40
Port Mode Control
Specifies operation mode of P40 pin.
0: I/O port mode
1: TXD0/SO0 output mode
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(c) Port 4 function control register (PFC4)
This register can be read/written in 8-bit or 1-bit units. Bits 7 to 5 and 2, however, are fixed to 0, so
writing 1 to these bits is ignored.
Caution
When the port mode is specified by the port 4 mode control register (PMC4), the PFC4
register setting becomes invalid.
PFC4
7
6
5
4
3
2
1
0
Address
After reset
0
0
0
PFC44
PFC43
0
PFC41
PFC40
FFFFF468H
00H
Bit position
470
Bit name
Function
4
PFC44
Port Function Control
Specifies operation mode of P44 pin in control mode.
0: SI1 input mode
1: RXD1 input mode
3
PFC43
Port Function Control
Specifies operation mode of P43 pin in control mode.
0: SO1 output mode
1: TXD1 output mode
1
PFC41
Port Function Control
Specifies operation mode of P41 pin in control mode.
0: SI0 input mode
1: RXD0 input mode
0
PFC40
Port Function Control
Specifies operation mode of P40 pin in control mode.
0: SO0 output mode
1: TXD0 output mode
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14.3.6 Port 5
Port 5 is a 3-bit I/O port that can be set to the input or output mode in 1-bit units.
P5
7
6
5
4
3
2
1
0
–
–
–
–
–
P52
P51
P50
Bit position
2 to 0
Bit name
Address
After reset
FFFFF40AH Undefined
Function
P5n
(n = 2 to 0)
Port 5
I/O port
In addition to their function as port pins, the port 5 pins can also operate as the real-time pulse unit (RPU) I/O and
external interrupt request inputs in the control mode.
(1) Operation in control mode
Port
Port 5
Alternate Function
P50
Remark
Block Type
INTP030/TI030
External interrupt request input/
Real-time pulse unit (RPU) input
P51
INTP031
External interrupt request input
P52
TO03
Real-time pulse unit (RPU) output
B
A
(2) I/O mode/control mode setting
The port 5 I/O mode setting is performed by the port 5 mode register (PM5), and the control mode setting is
performed by the port 5 mode control register (PMC5).
(a) Port 5 mode register (PM5)
This register can be read/written in 8-bit or 1-bit units.
PM5
7
6
5
4
3
2
1
0
Address
After reset
1
1
1
1
1
PM52
PM51
PM50
FFFFF42AH
FFH
Bit position
2 to 0
Bit name
PM5n
(n = 2 to 0)
Function
Port Mode
Specifies input/output mode for P5n pin.
0: Output mode (output buffer on)
1: Input mode (output buffer off)
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(b) Port 5 mode control register (PMC5)
This register can be read/written in 8-bit or 1-bit units.
PMC5
7
6
5
4
3
2
1
0
Address
After reset
0
0
0
0
0
PMC52
PMC51
PMC50
FFFFF44AH
00H
Bit position
Bit name
Function
2
PMC52
Port Mode Control
Specifies operation mode of P52 pin.
0: I/O port mode
1: TO03 output mode
1
PMC51
Port Mode Control
Specifies operation mode of P51 pin.
0: I/O port mode
1: External input request (INTP031) input mode
0
PMC50
Port Mode Control
Specifies operation mode of P50 pin.
0: I/O port mode
1: External interrupt request (INTP030) input mode/TI030 input mode
There is no register that switches between the external interrupt request
(INTP030) input mode and TI030 input mode.
• When the TI030 input mode is selected:
Mask the external interrupt request (INTP030) or specify the CCC30 register as
a compare register.
• When the external interrupt request (INTP030) input mode (including timer
capture input) is selected:
Set the ETI3 bit of the TMCC31 register to 0.
472
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14.3.7 Port 7
Port 7 is an 8-bit input-only port whose pins are fixed to input.
P7
7
6
5
4
3
2
1
0
P77
P76
P75
P74
P73
P72
P71
P70
Bit position
7 to 0
Bit name
P7n
(n = 7 to 0)
Address
After reset
FFFFF40EH Undefined
Function
Port 7
Input-only port
In addition to their function as port pins, the port 7 pins can also operate as the analog inputs to the A/D converter
in the control mode.
(1) Operation in control mode
Port
Port 7
P77 to P70
Alternate Function
ANI7 to ANI0
Remark
Analog input to A/D converter
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14.3.8 Port AL
Port AL (PAL) is a 16-bit I/O port that can be set to the input or output mode in 1-bit units.
When the higher 8 bits of port AL are used as port ALH (PALH) and the lower 8 bits as port ALL (PALL), port AL
becomes two 8-bit ports that can be set in the input or output mode in 1-bit units.
PAL
15
14
13
12
11
10
9
8
PAL15
PAL14
PAL13
PAL12
PAL11
PAL10
PAL9
PAL8
7
6
5
4
3
2
1
0
Address
PAL7
PAL6
PAL5
PAL4
PAL3
PAL2
PAL1
PAL0
FFFFF000H
Bit position
Bit name
15 to 0
Address
After reset
FFFFF001H Undefined
Function
PALn
(n = 15 to 0)
Port AL
I/O port
In addition to their functions as port pins, in the control mode, the port AL pins operate as an address bus for when
the memory is externally expanded.
(1) Operation in control mode
Port
Port AL
Alternate Function
Remark
A15 to A0
PAL15 to
PAL0
Block Type
Address bus when memory
expanded
J
(2) I/O mode/control mode setting
The port AL I/O mode setting is performed by the port AL mode register (PMAL), and control mode setting is
performed by the port AL mode control register (PMCAL).
(a) Port AL mode register (PMAL)
The port AL mode register (PMAL) can be read/written in 16-bit units.
If the higher 8 bits of PMAL are used as port AL mode register H (PMALH), and the lower 8 bits as port
AL mode register L (PMALL), these two 8-bit port mode registers can be read/written in 8-bit or 1-bit
units.
15
PMAL
13
12
11
10
PMAL15 PMAL14 PMAL13 PMAL12 PMAL11 PMAL10
9
8
Address
After reset
PMAL9
PMAL8
FFFFF021H
FFFFH
7
6
5
4
3
2
1
0
Address
PMAL7
PMAL6
PMAL5
PMAL4
PMAL3
PMAL2
PMAL1
PMAL0
FFFFF020H
Bit position
15 to 0
474
14
Bit name
PMALn
(n = 15 to 0)
Function
Port Mode
Specifies input/output mode for PALn pin.
0: Output mode (output buffer on)
1: Input mode (output buffer off)
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(b) Port AL mode control register (PMCAL)
The port AL mode control register (PMCAL) can be read/written in 16-bit units.
If the higher 8 bits of PMCAL are used as port AL mode control register H (PMCALH), and the lower 8
bits as port AL mode control register L (PMCALL), these two 8-bit port mode registers can be read/written
in 8-bit or 1-bit units.
15
PMCAL
14
13
12
11
10
9
8
Address
After reset
Note
P M C A L 1 5 P M C A L 1 4 P M C A L 1 3 P M C A L 1 2 P M C A L 1 1 P M C A L 1 0 PMCAL9 PMCAL8 FFFFF041H F F F F H /0 0 0 0 H
7
6
5
4
3
2
1
0
Address
PMCAL7 PMCAL6 PMCAL5 PMCAL4 PMCAL3 PMCAL2 PMCAL1 PMCAL0 FFFFF040H
Note In ROMless modes 0 and 1, and single-chip mode 1:
FFFFH
In single-chip mode 0:
Bit position
15 to 0
Bit name
PMCALn
(n = 15 to 0)
0000H
Function
Port Mode Control
Specifies operation mode of PALn pin.
0: I/O port mode
1: A15 to A0 output mode
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CHAPTER 14 PORT FUNCTIONS
14.3.9 Port AH
Port AH (PAH) is a 16-bit I/O port that can be set in the input or output mode in 1-bit units.
When the higher 8 bits of port AH are used as port AHH (PAHH) and the lower 8 bits as port AHL (PAHL), port AH
becomes two 8-bit ports that can be set in the input or output mode in 1-bit units.
Bits 15 to 10 of port AH (bits 7 to 2 of port AHH) are undefined.
PAH
15
14
13
12
11
10
9
8
–
–
–
–
–
–
PAH9
PAH8
7
6
5
4
3
2
1
0
Address
PAH7
PAH6
PAH5
PAH4
PAH3
PAH2
PAH1
PAH0
FFFFF002H
Bit position
9 to 0
Bit name
PAHn
(n = 9 to 0)
Address
After reset
FFFFF003H Undefined
Function
Port AH
I/O port
In addition to their functions as port pins, in the control mode, the port AH pins operate as an address bus for when
the memory is externally expanded.
(1) Operation in control mode
Port
Port AH
476
PAL9 to
PAL0
Alternate Function Pin Name
A25 to A16
Remark
Address bus when memory
expanded
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CHAPTER 14 PORT FUNCTIONS
(2) I/O mode/control mode setting
The port AH I/O mode setting is performed by the port AH mode register (PMAH), and the control mode
setting is performed by the port AH mode control register (PMCAH).
(a) Port AH mode register (PMAH)
The port AH mode register (PMAH) can be read/written in 16-bit units.
If the higher 8 bits of PMAH are used as port AH mode register H (PMAHH), and the lower 8 bits as port
AH mode register L (PMAHL), these two 8-bit port mode registers can be read/written in 8-bit or 1-bit
units.
Bits 15 to 10 of PMAH (bits 7 to 2 of PMAHH) are fixed to 1.
PMAH
15
14
13
12
11
10
9
8
Address
After reset
1
1
1
1
1
1
PMAH9
PMAH8
FFFFF023H
FFFFH
7
6
5
4
3
2
1
0
Address
PMAH7
PMAH6
PMAH5
PMAH4
PMAH3
PMAH2
PMAH1
PMAH0
FFFFF022H
Bit position
9 to 0
Bit name
Function
PMAHn
(n = 9 to 0)
Port Mode
Specifies input/output mode for PAHn pin.
0: Output mode (output buffer on)
1: Input mode (output buffer off)
(b) Port AH mode control register (PMCAH)
The port AH mode control register (PMCAH) can be read/written in 16-bit units.
If the higher 8 bits of PMCAH are used as port AH mode control register H (PMCAHH), and the lower 8
bits as port AH mode control register L (PMCAHL), these two 8-bit port mode registers can be
read/written in 8-bit or 1-bit units.
Bits 15 to 10 of PMCAH (bits 7 to 2 of PMCAHH) are fixed to 0.
PMCAH
15
14
13
12
11
10
0
0
0
0
0
0
7
6
5
4
3
2
9
8
Address
After reset
Note
PMCAH9 PMCAH8 FFFFF043H 0 0 0 0 H /0 3 F F H
1
0
Address
PMCAH7 PMCAH6 PMCAH5 PMCAH4 PMCAH3 PMCAH2 PMCAH1 PMCAH0 FFFFF042H
Note In ROMless modes 0 and 1, and single-chip mode 1:
In single-chip mode 0:
Bit position
9 to 0
Bit name
PMCAHn
(n = 9 to 0)
03FFH
0000H
Function
Port Mode Control
Specifies operation mode of PAHn pin.
0: I/O port mode
1: A25 to A16 output mode
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CHAPTER 14 PORT FUNCTIONS
14.3.10 Port DL
Port DL (PDL) is a 16-bit I/O port that can be set in the input or output mode in 1-bit units.
When the higher 8 bits of port DL are used as port DLH (PDLH), and the lower 8 bits as port DLL (PDLL), port DL
becomes two 8-bit ports that can be set in the input or output mode in 1-bit units.
PDL
15
14
13
12
11
10
9
8
PDL15
PDL14
PDL13
PDL12
PDL11
PDL10
PDL9
PDL8
7
6
5
4
3
2
1
0
Address
PDL7
PDL6
PDL5
PDL4
PDL3
PDL2
PDL1
PDL0
FFFFF004H
Bit position
Bit name
15 to 0
Address
After reset
FFFFF005H Undefined
Function
PDLn
(n = 15 to 0)
Port DL
I/O port
In addition to their functions as port pins, in the control mode, the port DL pins operate as a data bus for when the
memory is externally expanded.
(1) Operation in control mode
Port
Port DL
Alternate Function Pin Name
D15 to D0
PDL15 to
PDL0
Remark
Block Type
Data bus when memory expanded
O
(2) I/O mode/control mode setting
The port DL I/O mode setting is performed by the port DL mode register (PMDL), and the control mode
setting is performed by the port DL mode control register (PMCDL).
(a) Port DL mode register (PMDL)
The port DL mode register (PMDL) can be read/written in 16-bit units.
If the higher 8 bits of PMDL are used as port DL mode register H (PMDLH), and the lower 8 bits as port
DL mode register L (PMDLL), these two 8-bit port mode registers can be read/written in 8-bit or 1-bit
units.
15
PMDL
13
12
11
10
PMDL15 PMDL14 PMDL13 PMDL12 PMDL11 PMDL10
9
8
Address
After reset
PMDL9
PMDL8
FFFFF025H
FFFFH
7
6
5
4
3
2
1
0
Address
PMDL7
PMDL6
PMDL5
PMDL4
PMDL3
PMDL2
PMDL1
PMDL0
FFFFF024H
Bit position
15 to 0
478
14
Bit name
PMDLn
(n = 15 to 0)
Function
Port Mode
Specifies input/output mode for PDLn pin.
0: Output mode (output buffer on)
1: Input mode (output buffer off)
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CHAPTER 14 PORT FUNCTIONS
(b) Port DL mode control register (PMCDL)
The port DL mode control register (PMCDL) can be read/written in 16-bit units.
If the higher 8 bits of PMCDL are used as port DL mode control register H (PMCDLH), and the lower 8 bits as
port DL mode control register L (PMCDLL), these two 8-bit port mode registers can be read/written in 8-bit or
1-bit units.
15
14
13
12
11
10
9
8
Address
After reset
Note
PMCDL PMCDL15 PMCDL14 PMCDL13 PMCDL12 PMCDL11 PMCDL10 PMCDL9 PMCDL8 FFFFF045H FFFFH/0000H
7
6
5
4
3
2
1
0
Address
PMCDL7 PMCDL6 PMCDL5 PMCDL4 PMCDL3 PMCDL2 PMCDL1 PMCDL0 FFFFF044H
Note In ROMless modes 0 and 1, and single-chip mode 1:
In single-chip mode 0:
Bit position
15 to 0
Bit name
PMCDLn
(n = 15 to 0)
FFFFH
0000H
Function
Port Mode Control
Specifies operation mode of PDLn pin.
0: I/O port mode
1: D15 to D0 output mode
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CHAPTER 14 PORT FUNCTIONS
14.3.11 Port CS
Port CS is an 8-bit I/O port that can be set to the input or output mode in 1-bit units.
PCS
7
6
5
4
3
2
1
0
PCS7
PCS6
PCS5
PCS4
PCS3
PCS2
PCS1
PCS0
Bit position
7 to 0
Bit name
PCSn
(n = 7 to 0)
Address
After reset
FFFFF008H Undefined
Function
Port CS
I/O port
In addition to their function as port pins, in the control mode, the port pins can also operate as the chip select signal
outputs when memory is externally expanded, the row address strobe signal outputs to DRAM, and the read/write
strobe signal output to an external I/O.
(1) Operation in control mode
Port
Port CS
480
Alternate Function Pin Name
Remark
Block Type
J
PCS0
CS0
Chip select signal output
PCS1
CS1/RAS1
Chip select signal output/
row address signal output
PCS2
CS2/IOWR
Chip select signal output/
write strobe signal output
K
PCS3
CS3/RAS3
J
PCS4
CS4/RAS4
Chip select signal output/
row address signal output
PCS5
CS5/IORD
Chip select signal output/
read strobe signal output
K
PCS6
CS6/RAS6
Chip select signal output/
row address signal output
J
PCS7
CS7
Chip select signal output
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(2) I/O mode/control mode setting
The port CS I/O mode setting is performed by the port CS mode register (PMCS), and the control mode
setting is performed by the port CS mode control register (PMCCS) and the port CS function control register
(PFCCS).
(a) Port CS mode register (PMCS)
This register can be read/written in 8-bit or 1-bit units.
PMCS
7
6
5
4
3
2
1
0
Address
After reset
PMCS7
PMCS6
PMCS5
PMCS4
PMCS3
PMCS2
PMCS1
PMCS0
FFFFF028H
FFH
Bit position
7 to 0
Bit name
PMCSn
(n = 7 to 0)
Function
Port Mode
Specifies input/output mode for PCSn pin.
0: Output mode (output buffer on)
1: Input mode (output buffer off)
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CHAPTER 14 PORT FUNCTIONS
(b) Port CS mode control register (PMCCS)
This register can be read/written in 8-bit or 1-bit units.
7
6
5
4
3
2
1
0
Address
PMCCS PMCCS7 PMCCS6 PMCCS5 PMCCS4 PMCCS3 PMCCS2 PMCCS1 PMCCS0 FFFFF048H
Note In ROMless modes 0 and 1, and single-chip mode 1:
In single-chip mode 0:
Bit position
482
Bit name
After reset
00H/FFH
FFH
00H
Function
7
PMCCS7
Port Mode Control
Specifies operation mode of PCS7 pin.
0: I/O port mode
1: CS7 output mode
6
PMCCS6
Port Mode Control
Specifies operation mode of PCS6 pin.
0: I/O port mode
1: CS6/RAS6 output mode (CS6/RAS6 signal automatically switched by
accessing the targeted memory of each signal.)
5
PMCCS5
Port Mode Control
Specifies operation mode of PCS5 pin.
0: I/O port mode
1: CS5 output mode/IORD output mode
4
PMCCS4
Port Mode Control
Specifies operation mode of PCS4 pin.
0: I/O port mode
1: CS4/RAS4 output mode (CS4/RAS4 signal automatically switched by
accessing the targeted memory of each signal.)
3
PMCCS3
Port Mode Control
Specifies operation mode of PCS3 pin.
0: I/O port mode
1: CS3/RAS3 output mode (CS3/RAS3 signal automatically switched by
accessing the targeted memory of each signal.)
2
PMCCS2
Port Mode Control
Specifies operation mode of PCS2 pin.
0: I/O port mode
1: CS2 output mode/IOWR output mode
1
PMCCS1
Port Mode Control
Specifies operation mode of PCS1 pin.
0: I/O port mode
1: CS1/RAS1 output mode (CS1/RAS1 signal automatically switched by
accessing the targeted memory of each signal.)
0
PMCCS0
Port Mode Control
Specifies operation mode of PCS0 pin.
0: I/O port mode
1: CS0 output mode
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Note
CHAPTER 14 PORT FUNCTIONS
(c) Port CS function control register (PFCCS)
This register can be read/written in 8-bit or 1-bit units. Bits 7, 6, 4, 3, 1, and 0, however, are fixed to 0, so
writing 1 to these bits is ignored.
Caution When the port mode is specified by the port CS mode control register (PMCCS), the
PFCCS setting becomes invalid.
PFCCS
7
6
5
4
3
2
1
0
Address
After reset
0
0
PFCCS5
0
0
PFCCS2
0
0
FFFFF049H
00H
Bit position
Note
Bit name
Function
5
PFCCS5
Port Function Control
Specifies operation mode of PCS5 pin in control mode.
0: CS5 output mode
Note
1: IORD output mode
2
PFCCS2
Port Function Control
Specifies operation mode of PCS2 pin in control mode.
0: CS2 output mode
Note
1: IOWR output mode
To output the IORD and IOWR signals during access to the external I/O other than by a DMA flyby
transfer, the IOEN bit of the BCP register must be set.
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14.3.12 Port CT
Port CT is a 6-bit I/O port that can be set to input or output mode in 1-bit units.
PCT
7
6
5
4
3
2
1
0
PCT7
PCT6
PCT5
PCT4
–
–
PCT1
PCT0
Bit position
7 to 4,1,0
Bit name
Address
After reset
FFFFF00AH Undefined
Function
PCTn
Port CT
(n = 7 to 4,1,0) I/O port
In addition to their function as port pins, in the control mode, the port CT pins operate as control signal outputs for
when the memory is externally expanded.
(1) Operation in control mode
Port
Port CT
Alternate Function Pin Name
Remark
Block Type
PCT0
LCAS/LWR/LDQM
Column address signal output/
write strobe signal output/
output disable/write mask signal
PCT1
UCAS/UWR/UDQM
Column address signal output/
write strobe signal output/
output disable/write mask signal
PCT4
RD
Read strobe signal output
PCT5
WE
Write enable signal output
PCT6
OE
Output enable signal output
PCT7
BCYST
Bus cycle status signal output
J
(2) I/O mode/control mode setting
The port CT I/O mode setting is performed by the port CT mode register (PMCT), and the control mode
setting is performed by the port CT mode control register (PMCCT).
(a) Port CT mode register (PMCT)
This register can be read/written in 8-bit or 1-bit units.
PMCT
7
6
5
4
3
2
1
0
Address
After reset
PMCT7
PMCT6
PMCT5
PMCT4
1
1
PMCT1
PMCT0
FFFFF02AH
FFH
Bit position
7 to 4,1,0
484
Bit name
Function
PMCTn
Port Mode
(n = 7 to 4,1,0) Specifies input/output mode for PCTn pin.
0: Output mode (output buffer on)
1: Input mode (output buffer off)
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(b) Port CT mode control register (PMCCT)
This register can be read/written in 8-bit or 1-bit units.
7
6
5
4
PMCCT PMCCT7 PMCCT6 PMCCT5 PMCCT4
3
2
0
0
1
Bit position
Address
PMCCT1 PMCCT0 FFFFF04AH
Note In ROMless modes 0 and 1, and single-chip mode 1:
In single-chip mode 0:
0
After reset
Note
00H/F3H
F3H
00H
Bit name
Function
7
PMCCT7
Port Mode Control
Specifies operation mode of PCT7 pin.
0: I/O port mode
1: BCYST output mode
6
PMCCT6
Port Mode Control
Specifies operation mode of PCT6 pin.
0: I/O port mode
1: OE output mode
5
PMCCT5
Port Mode Control
Specifies operation mode of PCT5 pin.
0: I/O port mode
1: WE output mode
4
PMCCT4
Port Mode Control
Specifies operation mode of PCT4 pin.
0: I/O port mode
1: RD output mode
1
PMCCT1
Port Mode Control
Specifies operation mode of PCT1 pin.
0: I/O port mode
1: UCAS/UWR/UDQM output mode (UCAS/UWR/UDQM signal automatically
switched by accessing the targeted memory of each signal.)
0
PMCCT0
Port Mode Control
Specifies operation mode of PCT0 pin.
0: I/O port mode
1: LCAS/LWR/LDQM output mode (LCAS/LWR/LDQM signal automatically
switched by accessing the targeted memory of each signal.)
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14.3.13 Port CM
Port CM is a 6-bit I/O port that can be set to the input or output mode in 1-bit units.
PCM
7
6
5
4
3
2
1
0
–
–
PCM5
PCM4
PCM3
PCM2
PCM1
PCM0
Bit position
5 to 0
Bit name
Address
After reset
FFFFF00CH Undefined
Function
PCMn
(n = 5 to 0)
Port CM
I/O port
In addition to their function as port pins, in the control mode, the port CM pins operate as the wait insertion signal
input, internal system clock output/bus clock output, bus hold control signal output, and refresh request signal output
from DRAM.
(1) Operation in control mode
Port
Port CM
Alternate Function Pin Name
Remark
Block Type
PCM0
WAIT
Wait insertion signal input
D
PCM1
CLKOUT/BUSCLK
Internal system clock output/bus
clock output
K
PCM2
HLDAK
Bus hold acknowledge signal
output
J
PCM3
HLDRQ
Bus hold request signal input
D
PCM4
REFRQ
Refresh request signal output
J
PCM5
SELFREF
Self-refresh request signal input
E
(2) I/O mode/control mode setting
The port CM I/O mode setting is performed by the port CM mode register (PMCM), and the control mode
setting is performed by the port CM mode control register (PMCCM) and the port CM function control register
(PFCCM).
(a) Port CM mode register (PMCM)
This register can be read/written in 8-bit or 1-bit units.
PMCM
7
6
5
4
3
2
1
1
1
PMCM5
PMCM4
PMCM3
PMCM2
PMCM1
Bit position
5 to 0
486
Bit name
PMCMn
(n = 5 to 0)
0
PMCM0 FFFFF02CH
Function
Port Mode
Specifies input/output mode for PCMn pin.
0: Output mode (output buffer on)
1: Input mode (output buffer off)
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Address
After reset
FFH
CHAPTER 14 PORT FUNCTIONS
(b) Port CM mode control register (PMCCM)
This register can be read/written in 8-bit or 1-bit units.
Caution
If the mode of the PCM1/CLKOUT/BUSCLK pin is changed from the I/O port mode to the
CLKOUT/BUSCLK mode, a glitch may be generated in the CLKOUT/BUSCLK output
immediately after the change. Therefore, pull up the CLKOUT/BUSCLK pin when using
it. In the PLL mode (CKSEL = 0), change the mode to the CLKOUT/BUSCLK mode at a
multiple of 1 (CKDIV2 to CKDIV0 bits of CKC register = 000B).
PMCCM
7
6
0
0
5
4
3
2
0
Address
PMCCM5 PMCCM4 PMCCM3 PMCCM2 PMCCM1 PMCCM0 FFFFF04CH
Note In ROMless modes 0 and 1, and single-chip mode 1:
In single-chip mode 0:
Bit position
1
Bit name
After reset
Note
00H/3FH
3FH
00H
Function
5
PMCCM5
Port Mode Control
Specifies operation mode of PCM5 pin.
0: I/O port mode
1: SELFREF input mode
4
PMCCM4
Port Mode Control
Specifies operation mode of PCM4 pin.
0: I/O port mode
1: REFRQ output mode
3
PMCCM3
Port Mode Control
Specifies operation mode of PCM3 pin.
0: I/O port mode
1: HLDRQ input mode
2
PMCCM2
Port Mode Control
Specifies operation mode of PCM2 pin.
0: I/O port mode
1: HLDAK output mode
1
PMCCM1
Port Mode Control
Specifies operation mode of PCM1 pin.
0: I/O port mode
1: CLKOUT output mode/BUSCLK output mode
0
PMCCM0
Port Mode Control
Specifies operation mode of PCM0 pin.
0: I/O port mode
1: WAIT input mode
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CHAPTER 14 PORT FUNCTIONS
(c) Port CM function control register (PFCCM)
This register can be read/written in 8-bit or 1-bit units. Bits 7 to 2 and 0, however, are fixed to 0, so
writing 1 to these bits is ignored. To output the half clock of the internal system clock from the BUSCLK
pin, the BCP bit of the BCP register must be set to 1.
If the BCP bit of the BCP register is set to 1 with the CLKOUT output mode selected, the external bus
operates at half the frequency of the internal system clock frequency, but the CLKOUT pin outputs the
internal operating frequency.
Caution When the port mode is specified by the port CM mode control register (PMCCM), the
PFCCM setting becomes invalid.
PFCCM
7
6
5
4
3
2
1
0
Address
After reset
0
0
0
0
0
0
PFCCM1
0
FFFFF04DH
00H
Bit position
1
488
Bit name
PFCCM1
Function
Port Function Control
Specifies operation mode of PCM1 pin in control mode.
0: CLKOUT output mode
1: BUSCLK output mode
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CHAPTER 14 PORT FUNCTIONS
14.3.14 Port CD
Port CD is a 4-bit I/O port that can be set to the input or output mode in 1-bit units.
PCD
7
6
5
4
3
2
1
0
–
–
–
–
PCD3
PCD2
PCD1
PCD0
Bit position
3 to 0
Bit name
Address
After reset
FFFFF00EH Undefined
Function
PCDn
(n = 3 to 0)
Port CD
I/O port
In addition to their function as port pins, the port CD pins operate as the clock enable signal output to SDRAM,
synchronous clock output, column address strobe signal output, row address strobe signal output, and byte enable
signal output to SDRAM upon byte access, in the control mode.
(1) Operation in control mode
Port
Port CD
Alternate Function Pin Name
Remark
Block Type
J
PCD0
SDCKE
Clock enable signal output
PCD1
SDCLK
Synchronous clock output
PCD2
LBE/SDCAS
Byte enable signal output/
column address strobe signal output
PCD3
UBE/SDRAS
Byte enable signal output/
row address strobe signal output
K
(2) I/O mode/control mode setting
The port CD I/O mode setting is performed by the port CD mode register (PMCD), and the control mode
setting is performed by the port CD mode control register (PMCCD) and the port CD function control register
(PFCCD).
(a) Port CD mode register (PMCD)
This register can be read/written in 8-bit or 1-bit units.
PMCD
7
6
5
4
3
2
1
1
1
1
1
PMCD3
PMCD2
PMCD1
Bit position
3 to 0
Bit name
PMCDn
(n = 3 to 0)
0
Address
PMCD0 FFFFF02EH
After reset
FFH
Function
Port Mode
Specifies input/output mode for PCDn pin.
0: Output mode (output buffer on)
1: Input mode (output buffer off)
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CHAPTER 14 PORT FUNCTIONS
(b) Port CD mode control register (PMCCD)
This register can be read/written in 8-bit or 1-bit units.
Cautions 1. Do not perform the SDCLK and SDCKE output mode setting simultaneously. Be
sure to perform the SDCLK output mode setting before the SDCKE output mode
setting.
2. When in single-chip mode 1, and in ROMless modes 0 and 1, bits 1 and 0 of the
PMCCD register become SDCLK output mode and SDCKE output mode after the
reset is released, however, bits 3 and 2 become UBE output mode and LBE output
mode. When using SDRAM be sure to set the SDRAS output mode and SDCAS
output mode using the PFCCD register.
PMCCD
7
6
5
4
0
0
0
0
3
2
Bit position
490
Bit name
0
Address
PMCCD3 PMCCD2 PMCCD1 PMCCD0 FFFFF04EH
Note In ROMless modes 0 and 1, and single-chip mode 1:
In single-chip mode 0:
1
0FH
00H
Function
3
PMCCD3
Port Mode Control
Specifies operation mode of PCD3 pin.
0: I/O port mode
1: UBE/SDRAS output mode
2
PMCCD2
Port Mode Control
Specifies operation mode of PCD2 pin.
0: I/O port mode
1: LBE/SDCAS output mode
1
PMCCD1
Port Mode Control
Specifies operation mode of PCD1 pin.
0: I/O port mode
1: SDCLK output mode
0
PMCCD0
Port Mode Control
Specifies operation mode of PCD0 pin.
0: I/O port mode
1: SDCKE output mode
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After reset
00H/0FH
Note
CHAPTER 14 PORT FUNCTIONS
(c) Port CD function control register (PFCCD)
This register can be read/written in 8-bit or 1-bit units. Bits 7 to 4, 1, and 0, however, are fixed to 0, so
writing 1 to these bits is ignored.
Caution When the port mode is specified by the port CD mode control register (PMCCD), the
PFCCD setting becomes invalid.
PFCCD
7
6
5
4
0
0
0
0
Bit position
Bit name
3
2
PFCCD3 PFCCD2
1
0
Address
After reset
0
0
FFFFF04FH
00H
Function
3
PFCCD3
Port Function Control
Specifies operation mode of PCD3 pin in control mode.
0: UBE output mode
1: SDRAS output mode
2
PFCCD2
Port Function Control
Specifies operation mode of PCD2 pin in control mode.
0: LBE output mode
1: SDCAS output mode
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CHAPTER 14 PORT FUNCTIONS
14.3.15 Port BD
Port BD is a 4-bit I/O port that can be set to the input or output mode in 1-bit units.
PBD
7
6
5
4
3
2
1
0
–
–
–
–
PBD3
PBD2
PBD1
PBD0
Bit position
3 to 0
Bit name
Address
After reset
FFFFF012H Undefined
Function
PBDn
(n = 3 to 0)
Port BD
I/O port
In addition to their function as port pins, the port BD pins operate as the DMA acknowledge signal outputs in the
control mode.
(1) Operation in control mode
Port
Port BD
Alternate Function Pin Name
DMAAK0 to DMAAK3
PBD0 to
PBD3
Remark
Block Type
DMA acknowledge signal output
J
(2) I/O mode/control mode setting
The port BD I/O mode setting is performed by the port BD mode register (PMBD), and the control mode
setting is performed by the port BD mode control register (PMCBD).
(a) Port BD mode register (PMBD)
This register can be read/written in 8-bit or 1-bit units.
PMBD
7
6
5
4
3
2
1
0
Address
After reset
1
1
1
1
PMBD3
PMBD2
PMBD1
PMBD0
FFFFF032H
FFH
Bit position
3 to 0
492
Bit name
PMBDn
(n = 3 to 0)
Function
Port Mode
Specifies input/output mode for PBDn pin.
0: Output mode (output buffer on)
1: Input mode (output buffer off)
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CHAPTER 14 PORT FUNCTIONS
(b) Port BD mode control register (PMCBD)
This register can be read/written in 8-bit or 1-bit units.
PMCBD
7
6
5
4
0
0
0
0
Bit position
3 to 0
Bit name
PMCBDn
(n = 3 to 0)
3
2
1
0
Address
PMCBD3 PMCBD2 PMCBD1 PMCBD0 FFFFF052H
After reset
00H
Function
Port Mode Control
Specifies operation mode of PBDn pin.
0: I/O port mode
1: DMAAKn output mode
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CHAPTER 15 RESET FUNCTIONS
When a low-level signal is input to the RESET pin, a system reset is effected and the hardware is initialized.
When the RESET signal level changes from low to high, the reset state is released and CPU starts program
execution. Register contents must be initialized as required in the program.
15.1 Features
.
The reset pin (RESET) incorporates a noise eliminator that uses analog delay (=. 60 ns) to prevent malfunction due
to noise.
15.2 Pin Functions
During a system reset, most pins (all but the CLKOUT
Note
, RESET, X2, VDD, VSS, CVDD, CVSS, AVDD/AVREF, and
AVSS pins) enter the high-impedance state. Therefore, when memory is connected externally, a pull-up or pull-down
resistor must be connected to the specified pins of ports AL, AH, DL, CS, CT, CM, CD, and BD. If no resistor is
connected, external memory may be destroyed when these pins enter the high-impedance state.
For the same reason, the output pins of the internal peripheral I/O functions and other output ports should be
handled in the same manner.
Note In ROMless modes 0 and 1, and in single-chip mode 1, the CLKOUT signal is output even during reset. In
single-chip mode 0, the CLKOUT signal is not output until the PMCCM register is set.
The operation status of each pin during reset is shown below (Table 15-1).
Table 15-1. Operation Status of Each Pin During Reset
Pin Name
Pin State
Single-Chip Mode 0
Single-Chip Mode 1
A0 to A15, A16 to A25, D0 to D15,
CS0 to CS7, RAS1, RAS3, RAS4,
RAS6, LWR, UWR, LCAS, UCAS,
LDQM, UDQM, RD, WE, OE,
BCYST, WAIT, HLDAK, HLDRQ,
REFREQ, SELFREF, SDCKE,
SDCLK, SDCAS, SDRAS
(Port mode)
High impedance
CLKOUT
(Port mode)
Operating
Port pin
494
Ports 0 to 5, 7, BD
(Input)
Ports AL, AH, DL,
CM, CT, CS, CD
(Input)
(Control mode)
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ROMless Mode 0
ROMless Mode 1
CHAPTER 15
RESET FUNCTIONS
(1) Acknowledging the reset signal
RESET (input)
Analog
delay
Analog
delay
Analog
delay
Eliminated as noise
Internal system
reset signal
Note
∆
∆
Reset
acknowledgement
Reset
release
Note The internal system reset signal continues in the active state for at least 4 system clock cycles after
reset clear timing by the RESET signal.
(2) Reset when turning on the power
In a reset operation when the power is turned on, because of the low-level width of the RESET signal, it is
necessary to secure the oscillation stabilization time between when the power is turned on and when the
reset is acknowledged.
VDD
RESET (input)
Oscillation
stabilization time
Analog delay
∆
Reset release
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RESET FUNCTIONS
15.3 Initialization
Initialize the contents of each register as necessary while programming.
The initial values of the CPU, internal RAM, and on-chip peripheral I/O after a reset are shown in Table 15-2.
Table 15-2. Initial Value of CPU, Internal RAM, and On-Chip Peripheral I/O After Reset (1/3)
Internal Hardware
CPU
Program registers
System registers
Register Name
General-purpose register (r0)
00000000H
General-purpose registers (r1 to r31)
Undefined
Program counter (PC)
00000000H
Status saving registers during interrupt (EIPC, EIPSW)
Undefined
Status saving registers during NMI (FEPC, FEPSW)
Undefined
Interrupt source register (ECR)
00000000H
Program status word (PSW)
00000020H
Status saving registers during CALLT execution (CTPC, CTPSW)
Undefined
Status saving registers during exception/debug trap (DBPC, DBPSW)
Undefined
CALLT base pointer (CTBP)
Undefined
Internal RAM
On-chip
peripheral
I/O
Port functions
Timer/counter
functions
496
Initial Value After Reset
—
Undefined
Ports (P0 to P5, P7, PAL, PAH, PDL, PCS, PCT, PCM, PCD, PBD)
Undefined
Mode registers (PM0 to PM5, PMCS, PMCT, PMCM, PMCD,
PMBD)
FFH
Mode registers (PMAL, PMAH, PMDL)
FFFFH
Mode control registers (PMC0, PMC1, PMC3 to PMC5, PMCBD)
00H
Mode control register (PMC2)
01H
Mode control registers (PMCAL, PMCDL)
0000H/FFFFH
Mode control register (PMCAH)
0000H/03FFH
Mode control register (PMCCS)
00H/FFH
Mode control register (PMCCT)
00H/F3H
Mode control register (PMCCM)
00H/3FH
Mode control register (PMCCD)
00H/0FH
Function control registers (PFC0, PFC2 to PFC4, PFCCS, PFCCM,
PFCCD)
00H
Timer Cn (TMCn) (n = 0 to 3)
0000H
Capture/compare registers Cn0 and Cn1 (CCCn0 and CCCn1)
(n = 0 to 3)
0000H
Timer mode control register Cn0 (TMCCn0) (n = 0 to 3)
00H
Timer mode control register Cn1 (TMCCn1) (n = 0 to 3)
20H
Timer Dn (TMDn) (n = 0 to 3)
0000H
Compare register (CMDn) (n = 0 to 3)
0000H
Timer mode control register Dn (n = 0 to 3)
00H
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CHAPTER 15
RESET FUNCTIONS
Table 15-2. Initial Value of CPU, Internal RAM, and On-Chip Peripheral I/O After Reset (2/3)
Internal Hardware
On-chip
peripheral
I/O
Serial interface
functions
A/D converter
PWM
Interrupt/exception
control functions
Memory control
functions
Register Name
Initial Value After Reset
Clocked serial interface mode register n (CSIMn) (n = 0 to 2)
00H
Clocked serial interface clock select register n (CSICn) (n = 0 to 2)
00H
Clocked serial interface transmit buffer register n (SOTBn) (n = 0 to 2)
00H
Serial I/O shift register n (SIOn) (n = 0 to 2)
00H
Receive-only serial I/O shift register n (SIOEn) (n = 0 to 2)
00H
Receive buffer register n (RXBn) (n = 0 to 2)
FFH
Transmit buffer register n (TXBn) (n = 0 to 2)
FFH
Asynchronous serial interface mode register n (ASIMn) (n = 0 to 2)
01H
Asynchronous serial interface status register n (ASISn) (n = 0 to 2)
00H
Asynchronous serial interface transmit status register n (ASIFn)
(n = 0 to 2)
00H
Clock select register n (CKSRn) (n = 0 to 2)
00H
Baud rate generator control register n (BRGCn) (n = 0 to 2)
FFH
A/D converter mode registers 0 and 2 (ADM0 and ADM2)
00H
A/D converter mode register 1 (ADM1)
07H
A/D conversion result register n (10 bits) (n = 0 to 7)
0000H
A/D conversion result register nH (8 bits) (n = 0 to 7)
00H
PWM control register n (PWMCn) (n = 0, 1)
40H
PWM buffer register n (PWMBn) (n = 0, 1)
0000H
In-service priority register (ISPR)
00H
External interrupt mode register n (INTMn) (n = 0 to 4)
00H
Interrupt mask register n (IMRn) (n = 0 to 3)
FFFFH
Valid edge select register Cn (SESCn) (n = 0 to 3)
00H
Interrupt control registers
(OVIC00 to OVIC03, P00IC0, P00IC1, P01IC0, P01IC1, P02IC0,
P02IC1, P03IC0, P03IC1, P10IC0 to P10IC3, P11IC0 to P11IC3,
P12IC0 to P12IC3, P13IC0 to P13IC3, CMICD0 to CMICD3,
DMAIC0 to DMAIC3, CSIIC0 to CSIIC2, SEIC0 to SEIC2, SRIC0 to
SRIC2, STIC0 to STIC2, ADIC)
47H
Page ROM configuration register (PRC)
7000H
DRAM configuration register n (SCRn) (n = 1, 3, 4, 6)
3FC1H
SDRAM configuration register n (SCRn) (n = 1, 3, 4, 6)
0000H
Refresh control register n (RFSn) (n = 1, 3, 4, 6)
0000H
SDRAM refresh control register n (RFSn) (n = 1, 3, 4, 6)
0000H
Refresh wait control register (RWC)
00H
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Table 15-2. Initial Value of CPU, Internal RAM, and On-Chip Peripheral I/O After Reset (3/3)
Internal Hardware
On-chip
peripheral
I/O
DMA functions
Bus control
functions
Power-save control
functions
System control
Caution
Register Name
Initial Value After Reset
DMA addressing control register n (DADCn) (n = 0 to 3)
0000H
DMA byte count register n (DBCn) (n = 0 to 3)
Undefined
DMA channel control register n (DCHCn) (n = 0 to 3)
00H
DMA destination address register nH (DDAnH) (n = 0 to 3)
Undefined
DMA destination address register nL (DDAnL) (n = 0 to 3)
Undefined
DMA disable status register (DDIS)
00H
DMA restart register (DRST)
00H
DMA source address register nH (DSAnH) (n = 0 to 3)
Undefined
DMA source address register nL (DSAnL) (n = 0 to 3)
Undefined
DMA terminal count output control register (DTOC)
01H
DMA trigger source register n (DTFRn) (n = 0 to 3)
00H
Address setup wait control register (ASC)
FFFFH
Bus cycle control register (BCC)
FFFFH
Bus cycle period control register (BCP)
00H
Bus cycle type configuration register n (BCTn) (n = 0, 1)
8888H
Endian configuration register (BEC)
0000H
Bus size configuration register (BSC)
0000H/5555H
Chip area select control register n (CSCn) (n = 0, 1)
2C11H
Data wait control register n (DWCn) (n = 0, 1)
7777H
Command register (PRCMD)
Undefined
Power-save control register (PSC)
00H
Clock control register (CKC)
00H
Power-save mode register (PSMR)
00H
Peripheral command register (PHCMD)
Undefined
Peripheral status register (PHS)
00H
System wait control register (VSWC)
77H
Flash programming mode control register (FLPMC)
08H/0CH/00H
Lock register (LOCKR)
0×H
“Undefined” in the above table is undefined after power-on-reset, or undefined as a result
↓ is input and the data write timing has been synchronized.
of data destruction when RESET↓
↓ signals, data is held in the same state it was in before the RESET
For other RESET↓
operation.
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CHAPTER 16
FLASH MEMORY (µPD70F3107)
The µPD70F3107 is the flash memory version of the V850E/MA1 and it has an on-chip 256 KB flash memory
configured as two 128 KB areas.
Caution There are differences in noise immunity and noise radiation between the flash memory and
mask ROM versions. When preproducing an application set with the flash memory version and
then mass producing it with the mask ROM version, be sure to conduct sufficient evaluations
on the commercial samples (CS) (not engineering samples (ES)) of the mask ROM versions.
Writing to flash memory can be performed with memory mounted on the target system (on board). A dedicated
flash programmer is connected to the target system to perform writing.
The following can be considered as the development environment and the applications using flash memory.
• Software can be changed after the V850E/MA1 is solder mounted on the target system.
• Small scale production of various models is made easier by differentiating software.
• Data adjustment in starting mass production is made easier.
16.1 Features
• All area batch erase, or erase in block units (128 KB)
• Communication through serial interface from the dedicated flash programmer
• Erase/write voltage: VPP = 7.8 V
• On-board programming
• Flash memory programming by self-programming in block units (128 KB) is possible
16.2 Writing with Flash Programmer
Writing can be performed either on-board or off-board by the dedicated flash programmer.
(1) On-board programming
The contents of the flash memory are rewritten after the V850E/MA1 is mounted on the target system. Mount
connectors, etc., on the target system to connect the dedicated flash programmer.
(2) Off-board programming
Writing to flash memory is performed by the dedicated program adapter (FA Series), etc., before mounting
the V850E/MA1 on the target system.
Remark
The FA Series is a product of Naito Densei Machida Mfg. Co., Ltd.
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FLASH MEMORY (µPD70F3107)
Figure 16-1. Connection Example of Adapter (FA-144GJ-UEN) for V850E/MA1 Flash Memory Programming
VDD
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
µPD70F3107
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
GND
GND
VDD
SI
SO
SCK
X1
X2
/RESET
VPP RESERVE/HS
Remarks 1. Pins whose connections are not indicated should be connected according to the recommended
connections of unused pins (refer to 2.4 Pin I/O Circuits and Recommended Connection of
Unused Pins).
2. When connecting to VDD via a resistor, it is recommended to use a resistor of 1 kΩ to 10 kΩ.
3. This adapter is for the 144-pin plastic LQFP package.
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FLASH MEMORY (µPD70F3107)
16.3 Programming Environment
The following shows the environment required for writing programs to the flash memory of the V850E/MA1.
VPP
VDD
RS-232C
VSS
RESET
CSI0
Host machine
V850E/MA1
Dedicated flash
programmer
A host machine is required for controlling the dedicated flash programmer.
CSI0 is used for the interface between the dedicated flash programmer and the V850E/MA1 to perform writing,
erasing, etc. A dedicated program adapter (FA Series) is required for off-board writing.
16.4 Communication Mode
(1) CSI0
Transfer rate: Up to 2 MHz (MSB first)
VPP1
VPP
VDD
VDD
GND
VSS
RESET
Dedicated flash
programmer
RESET
SO
SI0
SI
SO0
SCK
SCK0
CLK
X1
V850E/MA1
The dedicated flash programmer outputs the transfer clock and the V850E/MA1 operates as a slave.
(2) Handshake-supported CSI communication
Transfer rate: Up to 2 MHz (MSB first)
VPP1
VPP
VDD
VDD
GND
VSS
RESET
Dedicated flash
programmer
RESET
SO
SI0
SI
SO0
SCK
SCK0
CLK
X1
HS
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V850E/MA1
PAL0
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FLASH MEMORY (µPD70F3107)
16.5 Pin Connection
When performing on-board writing, install a connector on the target system to connect to the dedicated flash
programmer. Also, install a function to switch from the normal operation mode (single-chip modes 0, 1 or ROMless
modes 0, 1) to the flash memory programming mode.
In the flash memory programming mode, all the pins not used for flash memory programming enter the same
status as they were immediately after reset in single-chip mode 0. Therefore, because all the ports become output
high-impedance, pin connection is required when the external device does not acknowledge the output highimpedance status.
16.5.1 MODE2/VPP pin
In the normal operation mode, 0 V is input to the MODE2/VPP pin. In the flash memory programming mode, a 7.8 V
writing voltage is supplied to the MODE2/VPP pin.
The following shows an example of the connection of the
MODE2/VPP pin.
V850E/MA1
Dedicated flash programmer connection pin
MODE2/VPP
Pull-down resistor (RVPP)
16.5.2 Serial interface pin
The following shows the pins used by each serial interface.
Serial Interface
CSI0
Pins Used
SO0, SI0, SCK0
When connecting a dedicated flash programmer to a serial interface pin that is connected to other devices onboard, care should be taken to avoid the conflict of signals and the malfunction of other devices, etc.
(1) Conflict of signals
When connecting a dedicated flash programmer (output) to a serial interface pin (input) that is connected to
another device (output), a conflict of signals occurs. To avoid the conflict of signals, isolate the connection to
the other device or set the other device to the output high-impedance status.
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CHAPTER 16
FLASH MEMORY (µPD70F3107)
V850E/MA1
Conflict of signals
Dedicated flash programmer connection pin
Input pin
Other device
Output pin
In the flash memory programming mode, the signal that the
dedicated flash programmer sends out conflicts with signals the
other device outputs. Therefore, isolate the signals on the other
device side.
(2) Malfunction of other device
When connecting a dedicated flash programmer (output or input) to a serial interface pin (input or output)
connected to another device (input), the signal output to the other device may cause the device to
malfunction. To avoid this, isolate the connection to the other device or set so that the input signal to the
other device is ignored.
V850E/MA1
Dedicated flash programmer connection pin
Output pin
Other device
Input pin
In the flash memory programming mode, if the signal the
V850E/MA1 outputs affects the other device, isolate the
signal on the other device side.
V850E/MA1
Dedicated flash programmer connection pin
Input pin
Other device
Input pin
In the flash memory programming mode, if the signal the
dedicated flash programmer outputs affects the other
device, isolate the signal on the other device side.
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16.5.3 RESET pin
When connecting the reset signals of the dedicated flash programmer to the RESET pin, which is connected to the
reset signal generator on-board, a conflict of signals occurs. To avoid the conflict of signals, isolate the connection to
the reset signal generator.
When the reset signal is input from the user system in flash memory programming mode, the programming
operations will not be performed correctly. Therefore, do not input signals other than the reset signal from the
dedicated flash programmer.
V850E/MA1
Conflict of signals
Dedicated flash programmer connection pin
RESET
Reset signal generator
Output pin
In the flash memory programming mode, the signal
the reset signal generator outputs conflicts with the
signal the dedicated flash programmer outputs.
Therefore, isolate the signals on the reset signal
generator side.
16.5.4 NMI pin
Do not change the signal input to the NMI pin in flash memory programming mode. If it is changed in flash memory
programming mode, programming may not be performed correctly.
16.5.5 MODE0 to MODE2 pins
If MODE0 is set as a high-level or low-level input and MODE1 is set as a high-level input, a write voltage (7.8 V) is
applied to the MODE2/VPP pin and when reset is released, these pins change to the flash memory programming
mode.
16.5.6 Port pins
When the flash memory programming mode is set, all the port pins except the pins that communicate with the
dedicated flash programmer become output high-impedance.
These pins must be connected according to the
recommended connection of unused pins (refer to 2.4 Pin I/O Circuits and Recommended Connection of Unused
Pins).
16.5.7 Other signal pins
Connect X1 and X2 in the same status as in the normal operation mode.
16.5.8 Power supply
Supply the power (VDD, VSS, AVDD, AVREF, AVSS, CVDD, and CVSS) the same as when in normal operation mode.
Connect VDD and GND of the dedicated flash programmer to VDD and VSS. (VDD of the dedicated flash programmer is
provided with a power supply monitoring function.)
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16.6 Programming Method
16.6.1 Flash memory control
The following shows the procedure for manipulating the flash memory.
Start
Supply RESET pulse
Switch to flash memory programming mode
Select communication mode
Manipulate flash memory
End?
No
Yes
End
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16.6.2 Flash memory programming mode
When rewriting the contents of flash memory using the dedicated flash programmer, set the V850E/MA1 in the
flash memory programming mode. To switch to this mode, set the MODE0 to MODE1 and MODE2/VPP pins before
releasing reset.
When performing on-board writing, switch modes using a jumper, etc.
• MODE0: High-level or low-level input
• MODE1: High-level input
• MODE2/VPP: 7.8 V
Flash memory programming mode
MODE0, MODE1
1, 0
1, 1
7.8 V
1
2
...
n
MODE2/VPP 3 V
0V
RESET
16.6.3 Selection of communication mode
In the V850E/MA1, the communication mode is selected by inputting pulses (16 pulses max.) to the VPP pin after
switching to the flash memory programming mode. The VPP pulse is generated by the dedicated flash programmer.
The following shows the relationship between the number of pulses and the communication mode.
Table 16-1. List of Communication Modes
VPP Pulse
Communication Mode
0
CSI0
3
Handshake-supporting CSI
Other
RFU (reserved)
506
Remarks
V850E/MA1 performs slave operation, MSB first
Setting prohibited
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16.6.4 Communication commands
The V850E/MA1 communicates with the dedicated flash programmer by means of commands. A command sent
from the dedicated flash programmer to the V850E/MA1 is called the “command”. The response signal sent from the
V850E/MA1 to the dedicated flash programmer is called the “response command”.
Command
Response
command
Dedicated flash programmer
V850E/MA1
The following shows the commands for controlling the flash memory of the V850E/MA1. All of these commands
are issued from the dedicated flash programmer, and the V850E/MA1 performs the various processing corresponding
to the commands.
Category
Verify
Erase
Blank check
Data write
System setting and control
Command Name
Function
Batch verify command
Compares the contents of the entire memory and
the input data.
Block verify command
Compares the contents of the specified memory
block and the input data.
Batch erase command
Erases the contents of the entire memory.
Block erase command
Erases the contents of the specified memory
block.
Write back command
Writes back the contents which were erased.
Batch blank check command
Checks the erase state of the entire memory.
Block blank check command
Checks the erase state of the specified memory
block.
High-speed write command
Writes data by the specification of the write
address and the number of bytes to be written,
and executes verify check.
Continuous write command
Writes data from the address following the highspeed write command executed immediately
before, and executes verify check.
Status read out command
Acquires the status of operations.
Oscillating frequency setting command
Sets the oscillation frequency.
Erasure time setting command
Sets the erasing time of batch erase.
Write time setting command
Sets the writing time of data write.
Write back time setting command
Sets the write back time.
Silicon signature command
Reads outs the silicon signature information.
Reset command
Escapes from each state.
The V850E/MA1 sends back response commands for the commands issued from the dedicated flash programmer.
The following shows the response commands the V850E/MA1 sends out.
Response Command Name
Function
ACK (acknowledge)
Acknowledges command/data, etc.
NAK (not acknowledge)
Acknowledges illegal command/data, etc.
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16.7 Flash Memory Programming by Self-Programming
The µPD70F3107 supports a self-programming function to rewrite the flash memory using a user program. By
using this function, the flash memory can be rewritten with a user application. This self-programming function can be
also used to upgrade the program in the field.
16.7.1 Outline of self-programming
Self-programming implements erasure and writing of the flash memory by calling the self-programming function
(device’s internal processing) on the program placed in the block 0 space (000000H to 1FFFFFH) and areas other
than internal ROM area. To place the program in the block 0 space and internal ROM area, copy the program to
areas other than 000000H to 1FFFFFH (e.g. internal RAM area) and execute the program to call the selfprogramming function.
To call the self-programming function, change the operating mode from normal mode to self-programming mode
using the flash programming mode control register (FLPMC).
Figure 16-2. Outline of Self-Programming
Normal operation mode
Self-programming mode
Flash memory
Flash memory
3FFFFH
3FFFFH
Erase areaNote
(128 KB)
FLPMC ← 02H
Self-programming
function
(delete/write routine
incorporated)
256 KB
Erase areaNote
(128 KB)
FLPMC ← 00H
00000H
00000H
Note Data is deleted in area units (128 KB).
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16.7.2 Self-programming function
The µPD70F3107 provides self-programming functions, as shown below.
By combining these functions,
erasing/writing flash memory becomes possible.
Table 16-2. Function List
Type
Function Name
Function
Erase
Area erase
Erases the specified area.
Write
Continuous write in word units
Continuously writes the specified memory contents from
the specified flash memory address, for the number of
words specified in 4-byte units.
Prewrite
Writes 0 to flash memory before erasure.
Erase verify
Checks whether an over erase occurred after erasure.
Erase byte verify
Checks whether erasure is complete.
Internal verify
Checks whether the signal level of the post-write data in
flash memory is appropriate.
Write back
Area write back
Writes back the flash memory area in which an over
erase occurred.
Acquire information
Flash memory information read
Reads out information about flash memory.
Check
16.7.3 Outline of self-programming interface
To execute self-programming using the self-programming interface, the environmental conditions of the hardware
and software for manipulating the flash memory must be satisfied.
It is assumed that the self-programming interface is used in an assembly language.
(1) Entry program
This program is to call the internal processing of the device.
It is a part of the application program, and must be executed in memory other than the block 0 space and
internal ROM area (flash memory).
(2) Device internal processing
This is manipulation of the flash memory executed inside the device.
This processing manipulates the flash memory after it has been called by the entry program.
(3) RAM parameter
This is a RAM area to which the parameters necessary for self-programming, such as write time and erase
time, are written. It is set by the application program and referenced by the device internal processing.
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The self-programming interface is outlined below.
Figure 16-3. Outline of Self-Programming Interface
Application program
RAM parameter
Entry program
Self-programming
interface
Device internal processing
Flash-memory manipulation
Flash memory
16.7.4 Hardware environment
To write or erase the flash memory, a high voltage must be applied to the VPP pin. To execute self-programming, a
circuit that can generate a write voltage (VPP) and that can be controlled by software is necessary on the application
system. An example of a circuit that can select a voltage to be applied to the VPP pin by manipulating a port is shown
below.
Figure 16-4. Example of Self-Programming Circuit Configuration
VDD = 3.3 V ±0.3 V
µ PD70F3107
IC for power supply
VDD
VPP
(VPP = 7.8 V ±0.3 V)
OUTPUT
INPUT
10 kΩ
ON/OFF
Output port
≥ 10 kΩ
VSS
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The voltage applied to the VPP pin must satisfy the following conditions:
• Hold the voltage applied to the VPP pin at 0 V in the normal operation mode and hold the VPP voltage only while
the flash memory is being manipulated.
• The VPP voltage must be stable from before manipulation of the flash memory starts until manipulation is
complete.
Cautions 1. Apply 0 V to the VPP pin when reset is released.
2. Implement self-programming in single-chip mode 0 or 1.
3. Apply the voltage to the VPP pin in the entry program.
4. If both writing and erasing are executed by using the self-programming function and flash
memory programmer on the target board, be sure to communicate with the programmer
using CSI0 (do not use the handshake-supporting CSI).
Figure 16-5. Timing to Apply Voltage to VPP Pin
VDD
RESET signal
0V
VPP
VPP signal
0V
Flash memory
manipulation
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16.7.5 Software environment
The following conditions must be satisfied before using the entry program to call the device internal processing.
Table 16-3. Software Environmental Conditions
Item
Description
Location of entry
program
Execute the entry program in memory other than the block 0 space and flash memory area.
The device internal processing cannot be directly called by the program that is executed on the flash
memory.
Execution status of
program
The device internal processing cannot be called while an interrupt is being serviced (NP bit of PSW =
1, ID bit of PSW = 1).
Masking interrupts
Mask all the maskable interrupts used. Mask each interrupt by using the corresponding interrupt
control register.
To mask a maskable interrupt, be sure to specify masking by using the corresponding interrupt
control register. Mask the maskable interrupt even when the ID bit of the PSW = 1 (interrupts are
disabled).
Manipulation of VPP
voltage
Stabilize the voltage applied to the VPP pin (VPP voltage) before starting manipulation of the flash
memory. After completion of the manipulation, return the voltage of the VPP pin to 0 V.
Initialization of internal
timer
Do not use the internal timer while the flash memory is being manipulated.
Because the internal timer is initialized after the flash memory has been used, initialize the timer with
the application program to use the timer again.
Stopping reset signal
input
Do not input the reset signal while the flash memory is being manipulated.
If the reset signal is input while the flash memory is being manipulated, the contents of the flash
memory under manipulation become undefined.
Stopping NMI signal
input
Do not input the NMI signal while the flash memory is being manipulated.
If the NMI signal is input while the flash memory is being manipulated, the flash memory may not be
correctly manipulated by the device internal processing.
If an NMI occurs while the device internal processing is in progress, the occurrence of the NMI is
reflected in the NMI flag of the RAM parameter. If manipulation of the flash memory is affected by
the occurrence of the NMI, the function of each self-programming function is reflected in the return
value.
Reserving stack area
The device internal processing takes over the stack used by the user program. It is necessary that
an area of 300 bytes be reserved for the stack size of the user program when the device internal
processing is called. r3 is used as the stack pointer.
Saving general-purpose
registers
The device internal processing rewrites the contents of r6 to r14, r20, and r31 (lp).
Save and restore these register contents as necessary.
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16.7.6 Self-programming function number
To identify a self-programming function, the following numbers are assigned to the respective functions. These
function numbers are used as parameters when the device internal processing is called.
Table 16-4. Self-Programming Function Number
Function No.
Function Name
0
Acquiring flash information
1
Erasing area
2 to 4
RFU
5
Area write back
6 to 8
RFU
9
Erase byte verify
10
Erase verify
11 to 15
RFU
16
Successive write in word units
17 to 19
RFU
20
Pre-write
21
Internal verify
Other
Prohibited
Remark
RFU: Reserved for Future Use
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16.7.7 Calling parameters
The arguments used to call the self-programming function are shown in the table below. In addition to these
arguments, parameters such as the write time and erase time are set to the RAM parameters indicated by ep (r30).
Table 16-5. Calling Parameters
Function Name
First Argument (r6)
Function No.
Second Argument
(r7)
Third Argument (r8)
Fourth Argument
(r9)
Return Value (r10)
Acquiring flash
information
0
Option number
−
−
Note 1
Erasing area
1
Area erase start
address
−
−
0: Normal completion
Other than 0: Error
Area write back
5
None (acts on erase
manipulation area
immediately before)
−
−
None
−
0: Normal completion
Other than 0: Error
−
0: Normal completion
Other than 0: Error
Note 1
Erase byte verify 9
Verify start address
Erase verify
None (acts on erase
manipulation area
immediately before)
10
Number of bytes to
be verified
−
0: Normal completion
Other than 0: Error
Successive write 16
Note 2
in word units
Write start
Note 3
address
Start address of
Number of words
Note 3
write source data
to be written (word
units)
Pre-write
20
Write start address
Number of bytes to
be written
−
0: Normal completion
Other than 0: Error
Internal verify
21
Verify start address
Number of bytes to
be verified
−
0: Normal completion
Other than 0: Error
Notes 1.
2.
See 16.7.10 Flash information for details.
Prepare write source data in memory other than the flash memory when data is written successively in
word units.
3.
This address must be at a 4-byte boundary.
Caution For all the functions, ep (r30) must indicate the first address of the RAM parameter.
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16.7.8 Contents of RAM parameters
Reserve the following 48-byte area in the internal RAM or external RAM for the RAM parameters, and set the
parameters to be input. Set the base addresses of these parameters to ep (r30).
Table 16-6. Description of RAM Parameter
Address
ep+0
Size
I/O
4 bytes
−
Description
For internal operations
Note 1
1 bit
Input
Operation flag (Be sure to set this flag to 1 before calling the device internal processing.)
0: Normal operation in progress
1: Self-programming in progress
ep+4:Bit 7
Notes 2, 3
1 bit
Output
NMI flag
0: NMI not detected
1: NMI detected
ep+8
4 bytes
Input
Erase time (unsigned 4 bytes)
Expressed as 1 count value in units of the internal operation unit time (100 µs).
Set value = Erase time (µs)/internal operation unit time (µs)
Example: If erase time is 0.4 s
→ 0.4 × 1,000,000/100 = 4,000 (integer operation)
ep+0xc
4 bytes
Input
Write back time (unsigned 4 bytes)
Expressed as 1 count value in units of the internal operation unit time (100 µs).
Set value = Write back time (µs)/internal operation unit time (µs)
Example: If write back time is 1 ms
→ 1 × 1,000/100 = 10 (integer operation)
ep+0x10
2 bytes
Input
Timer set value for creating internal operation unit time (unsigned 2 bytes)
Write a set value that makes the value of timer D the internal operation unit time (100 µs).
Set value = Operating frequency (Hz)/1,000,000 × Internal operation unit time (µs)/
Note 4
Timer division ratio (4) + 1
ep+4:Bit 5
Example: If the operating frequency is 50 MHz
→ 50,000,000/1,000,000 × 100/4 + 1 = 1,251 (integer operation)
ep+0x12
2 bytes
Input
Timer set value for creating write time (unsigned 2 bytes)
Write a set value that makes the value of timer D the write time.
Note 4
Set value = Operating frequency (Hz)/Write time (µs)/Timer division ratio (4) + 1
Example: If the operating frequency is 50 MHz and the write time is 20 µs
→ 50,000,000/1,000,000 × 20/4 + 1 = 251 (integer operation)
ep+0x14
28 bytes
Notes 1.
−
For internal operations
Fifth bit of address of ep+4 (least significant bit is bit 0.)
2.
Seventh bit of address of ep+4 (least significant bit is bit 0.)
3.
Clear the NMI flag by the user program because it is not cleared by the device internal processing.
4.
The device internal processing sets this value minus 1 to the timer. Because the fraction is rounded up,
add 1 as indicated by the expression of the set value.
Caution Be sure to reserve the RAM parameter area at a 4-byte boundary.
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16.7.9 Errors during self-programming
The following errors related to manipulation of the flash memory may occur during self-programming. An error
occurs if the return value (r10) of each function is not 0.
Table 16-7. Errors During Self-Programming
Error
Function
Description
Overerase error
Erase verify
Excessive erasure occurs.
Undererase error
(blank check error)
Erase byte verify
Erasure is insufficient. Additional erase operation is
needed.
Verify error
Successive writing in word units
The written data cannot be correctly read. Either an
attempt has been made to write to flash memory that
has not been erased, or writing is not sufficient.
Internal verify error
Internal verify
The written data is not at the correct signal level.
Caution The overerase error and undererase error may simultaneously occur in the entire flash memory.
16.7.10 Flash information
For the flash information acquisition function (function No. 0), the option number (r7) to be specified and the
contents of the return value (r10) are as follows. To acquire all flash information, call the function as many times as
required in accordance with the format shown below.
Table 16-8. Flash Information
Option No. (r7)
Return Value (r10)
0
Specification prohibited
1
Specification prohibited
2
Bit representation of return value (MSB: bit 31) FFFFFFFFFFFFFFFFAAAAAAAAFFFFFFFF (LSB: bit 0)
Bits 31 to 16: FFFFFFFFFFFFFFFF (reserved for future use)
Mask bits 31 to 16 because they are not normally 0.
Bits 15 to 8: AAAAAAAA (number of areas) (unsigned 8 bits)
Bits 7 to 0: FFFFFFFF (reserved for future use)
Mask bits 7 to 0 because they are not normally 0.
3+0
End address of area 0
3+1
End address of area 1
Cautions 1.
The start address of area 0 is 0. The “end address + 1” of the preceding area is the start
address of the next area.
2. The flash information acquisition function does not check values such as the maximum
number of areas specified by the argument of an option. If an illegal value is specified, an
undefined value is returned.
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16.7.11 Area number
The area numbers and memory map of the µPD70F3107 are shown below.
Figure 16-6. Area Configuration
0 x 3 F F F F (End address of area 1)
Area 1
(128 KB)
0 x 2 0 0 0 0 (Start address of area 1)
0 x 1 F F F F (End address of area 0)
Area 0
(128 KB)
0 x 0 0 0 0 0 (Start address of area 0)
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16.7.12 Flash programming mode control register (FLPMC)
The flash memory mode control register (FLPMC) is a register used to enable/disable writing to flash memory and
to specify the self-programming mode.
This register can be read/written in 8-bit or 1-bit units (the VPP bit (bit 2) is read-only).
Cautions 1. Be sure to transfer control to the internal RAM or external memory beforehand to
manipulate the FLSPM bit.
However, in on-board programming mode set by the flash
programmer, the specification of FLSPM bit is ignored.
2. Do not change the initial value of bits 0 and 4 to 7.
FLPMC
7
6
5
4
<3>
<2>
<1>
0
0
0
0
0
VPPDIS
VPP
FLSPM
0
Note 08H:
Address
FFFFF8D4H
After resetNote
08H/0CH/00H
When writing voltage is not applied to the VPP pin
0CH: When writing voltage is applied to the VPP pin
00H:
Bit position
518
Product not provided with flash memory (µPD703103, 703105, 703106, 703107)
Bit name
Function
3
VPPDIS
VPP Disable
Enables/disables writing/deleting on-chip flash memory. When this bit is 1,
writing/deleting on-chip flash memory is disabled even if a high voltage is applied to
the VPP pin.
0: Enables writing/deleting flash memory
1: Disables writing/deleting flash memory
2
VPP
VPP
Indicates the voltage applied to the VPP pin reaches the writing-enabled level. This
bit is used to check whether writing is possible or not in the self-programming mode.
0: Indicates high-voltage application is not detected (the voltage has not reached
the writing voltage enable level)
1: Indicates high-voltage application is detected (the voltage has reached the
writing voltage enable level)
1
FLSPM
Flash Self Programming Mode
Controls switching between internal ROM and the self-programming interface. This
bit can switch the mode between the normal mode set by the mode pin on the
application system and the self-programming mode. The setting of this bit is valid
only if the voltage applied to the VPP pin reaches the writing voltage enable level.
0: Normal mode (for all addresses, instruction fetch is performed from on-chip
flash memory)
1: Self-programming mode (device internal processing is started.)
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Setting data to the flash programming mode control register (FLPMC) is performed in the following sequence.
<1> Disable interrupts (set the NP bit and ID bit of the PSW to 1)
<2> Prepare the data to be set in the specific register in a general-purpose register
<3> Write data to the peripheral command register (PHCMD)
<4> Set the flash memory programming mode control register (FLPMC) by executing the following instructions
• Store instruction (ST/SST instructions)
• Bit manipulation instruction (SET1/CLR1/NOT1 instructions)
<5> Insert NOP instructions (5 instructions <5> to <9>)
<10>Cancel the interrupt disabled state (reset the NP bit of the PSW to 0)
[Description example]
<1> LDSR
rX, 5
<2> MOV
0x02, r10
<3> ST.B
r10, PHCMD [r0]
<4> ST.B
r10, FLPMC [r0]
<5> NOP
<6> NOP
<7> NOP
<8> NOP
<9> NOP
<10>LDSR
Remark
rY, 5
rX: Value written to the PSW
rY: Value returned to the PSW
No special sequence is required for reading a specific register.
Cautions 1. If an interrupt is acknowledged between when PHCMD is issued (<3>) and writing to a
specific register (<4>) immediately after issuing PHCMD, writing to the specific register may
not be performed and a protection error may occur (the PRERR bit of the PHS register = 1).
Therefore, set the NP bit of the PSW to 1 (<1>) to disable interrupt acknowledgment.
Similarly, disable acknowledgement of interrupts when a bit manipulation instruction is
used to set a specific register.
2. Use the same general-purpose register used to set a specific register (<3>) for writing to the
PHCMD register (<4>) even though the data written to the PHCMD register is dummy data.
This is the same as when a general-purpose register is used for addressing.
3. Do not use DMA transfer for writing to the PHCMD register and a specific register.
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16.7.13 Calling device internal processing
This section explains the procedure to call the device internal processing from the entry program.
Before calling the device internal processing, make sure that all the conditions of the hardware and software
environments are satisfied and that the necessary arguments and RAM parameters have been set. Call the device
internal processing by setting the FLSPM bit of the flash programming mode control register (FLPMC) to 1 and then
executing the trap 0x1f instruction. The processing is always called using the same procedure. It is assumed that the
program of this interface is described in an assembly language.
<1> Set the FLPMC register as follows:
• VPPDIS bit = 0 (to enable writing/erasing flash memory)
• FLSPM bit = 1 (to select self-programming mode)
<2> Clear the NP bit of the PSW to 0 (to enable NMIs (only when NMIs are used on the application)).
<3> Execute trap 0x1f to transfer the control to the device’s internal processing.
<4> Set the NP bit and ID bit of the PSW to 1 (to disable all interrupts).
<5> Set the value to the peripheral command register (PHCMD) that is to be set to the FLPMC register.
<6> Set the FLPMC register as follows:
• VPPDIS bit = 1 (to disable writing/erasing flash memory)
• FLSPM bit = 0 (to select normal operation mode)
<7> Wait for the internal manipulation setup time (see 16.7.13 (5) Internal manipulation setup parameter).
(1) Parameter
r6: First argument (sets a self-programming function number)
r7: Second argument
r8: Third argument
r9: Fourth argument
ep: First address of RAM parameter
(2) Return value
r10:
Return value (return value from device internal processing of 4 bytes)
ep+4:Bit 7: NMI flag (flag indicating whether an NMI occurred while the device internal processing was being
executed)
0: NMI did not occur while device internal processing was being executed.
1: NMI occurred while device internal processing was being executed.
If an NMI occurs while control is being transferred to the device internal processing, the NMI
request may never be reflected. Because the NMI flag is not internally reset, this bit must be
cleared before calling the device internal processing. After the control returns from the device
internal processing, NMI dummy processing can be executed by checking the status of this flag
using software.
(3) Description
Transfer control to the device internal processing specified by a function number using the trap instruction.
To do this, the hardware and software environmental conditions must be satisfied. Even if trap 0x1f is used in
the user application program, trap 0x1f is treated as another operation after the FLPMC register has been set.
Therefore, use of the trap instruction is not restricted on the application.
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CHAPTER 16
FLASH MEMORY (µPD70F3107)
(4) Program example
An example of a program in which the entry program is executed as a subroutine is shown below. In this
example, the return address is saved to the stack and then the device internal processing is called. This
program must be located in memory other than the block 0 space and flash memory area.
ISETUP
-- Internal manipulation setup parameter
130
EntryProgram:
add
-4, sp
-- Prepare
st.w
lp, 0[sp]
-- Save return address
movea
lo(0x00a0), r0, r10
--
ldsr
r10, 5
-- PSW = NP, ID
mov
lo(0x0002), r10
--
st.b
r10, PHCMD[r0]
-- PHCMD = 2
st.b
r10, FLPMC[r0]
-- VPPDIS = 0, FLSPM = 1
movea
lo(0x0020), r0, r10
--
ldsr
r10, 5
-- PSW = ID
trap
0x1f
-- Device Internal Process
movea
lo(0x00a0), r0, r6
--
ldsr
r6, 5
-- PSW = NP, ID
mov
lo(0x08), r6
st.b
r6, PHCMD[r0]
-- PRCMD = 8
st.b
r6, FLPMC[r0]
-- VPPDIS = 1, FLSPM = 0
ISETUP, lp
-- loop time = 130
divh
r6, r6
-- To kill time
add
-1, lp
-- Decrement counter
jne
loop
--
ld.w
0[sp], lp
-- Reload lp
add
4, sp
-- Dispose
jmp
[lp]
-- Return to caller
nop
nop
nop
nop
nop
nop
nop
nop
nop
nop
mov
loop:
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CHAPTER 16
FLASH MEMORY (µPD70F3107)
(5) Internal manipulation setup parameter
If the self-programming mode is switched to the normal operation mode, the µPD70F3107 must wait for 100
µs before it accesses the flash memory. In the program example in (4) above, the elapse of this wait time is
ensured by setting ISETUP to “130” (@ 50 MHz operation). The total number of execution clocks in this
example is 39 clocks (divh instruction (35 clocks) + add instruction (1 clock) + jne instruction (3 clocks)).
Ensure that a wait time of 100 µs elapses by using the following expression.
39 clocks (total number of execution clocks) × 20 ns (@ 50 MHz operation) × 130 (ISETUP) = 101.4 µs
(wait time)
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CHAPTER 16
FLASH MEMORY (µPD70F3107)
16.7.14 Erasing flash memory flow
The procedure to erase the flash memory is illustrated below. The processing of each function number must be
executed in accordance with the specified calling procedure.
Figure 16-7. Erasing Flash Memory Flow
Erase
Set RAM parameter.
Mask interrupts.
Set VPP voltage.
Pre-write
Write error?
... Function No. 20
Clear VPP voltage.
Unmask interrupts.
Yes
Write error
No
Erase area.
... Function No. 1
Erase byte verify
... Function No. 9
Undererase?
Yes
No
Erase verify
Overerase?
... Function No. 10
Area write back
... Function No. 5
Erase verify
... Function No. 10
Clear number of times
write-back is repeated.
Undererase?
Yes
Clear VPP voltage.
Unmask interrupts.
Undererase error
Clear VPP voltage.
Unmask interrupts.
Normal completion
Yes
No
Erase byte verify
No
No
Yes
Overerase?
Maximum
number of times
of repeating erasure is
exceeded?
... Function No. 9
No
Maximum
number of times
of repeating write-back is
exceeded?
Yes
Clear VPP voltage.
Unmask interrupts.
No
Overerase error
Yes
Clear VPP voltage.
Unmask interrupts.
Normal completion
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CHAPTER 16
FLASH MEMORY (µPD70F3107)
16.7.15 Successive writing flow
The procedure to write data all at once to the flash memory by using the function to successively write data in word
units is illustrated below. The processing of each function number must be executed in accordance with the specified
calling procedure.
Figure 16-8. Successive Writing Flow
Successive writing
Set RAM parameter.
Mask interrupts.
Set VPP voltage.
Successive writing
Error?
... Function No. 16
No
Yes
524
Clear VPP voltage.
Clear VPP voltage.
Unmask interrupts.
Unmask interrupts.
Write error
Normal completion
User’s Manual U14359EJ3V0UM
CHAPTER 16
FLASH MEMORY (µPD70F3107)
16.7.16 Internal verify flow
The procedure of internal verification is illustrated below.
The processing of each function number must be
executed in accordance with the specified calling procedure.
Figure 16-9. Internal Verify Flow
Internal verify
Set RAM parameter.
Mask interrupts.
Set VPP voltage.
Internal verify
Error?
... Function No. 21
No
Yes
Clear VPP voltage.
Clear VPP voltage.
Unmask interrupts.
Unmask interrupts.
Internal verify error
Normal completion
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CHAPTER 16
FLASH MEMORY (µPD70F3107)
16.7.17 Acquiring flash information flow
The procedure to acquire the flash information is illustrated below. The processing of each function number must
be executed in accordance with the specified calling procedure.
Figure 16-10. Acquiring Flash Information Flow
Acquiring flash
information
Set RAM parameter.
Mask interrupts.
Set VPP voltage.
Acquiring flash
information
... Function No. 0
Clear VPP voltage.
Unmask interrupts.
End
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CHAPTER 16
FLASH MEMORY (µPD70F3107)
16.7.18 Self-programming library
An application note for the flash memory self-programming library is available for reference when executing selfprogramming.
In this application note, the library uses the self-programming interface of the V850 Family and can be used in C as
a utility and as part of the application program. To use the library, thoroughly evaluate it on the application system.
(1) Functional outline
Figure 16-11 outlines the function of the self-programming library. In this figure, a rewriting module is located
in area 0 and the data in area 1 is rewritten or erased.
The rewriting module is a user program to rewrite the flash memory. The other areas can be also rewritten by
using the flash functions included in this self-programming library. The flash functions expand the entry
program in the external memory or internal RAM and call the device internal processing.
When using the self-programming library, make sure that the hardware conditions, such as the write voltage,
and the software conditions, such as interrupts, are satisfied.
Figure 16-11. Functional Outline of Self-Programming Library
Flash memory
Area 1
Erase/write
Rewriting module
Flash rewriting program
Rewriting module
Flash function
Area 0
Flash environment
Self-programming
library
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CHAPTER 16
FLASH MEMORY (µPD70F3107)
The configuration of the self-programming library is outlined below.
Figure 16-12. Outline of Self-Programming Library Configuration
Application program
C interface
Self-programming library
Entry program
Self-programming interface
Device internal processing
Flash memory manipulation
Flash memory
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User’s Manual U14359EJ3V0UM
RAM parameter
CHAPTER 16
FLASH MEMORY (µPD70F3107)
16.8 How to Distinguish Flash Memory and Mask ROM Versions
It is possible to distinguish a flash memory version (µPD70F3107) and mask ROM versions (µPD703105, 703106,
703107) by means of software, using the methods shown below.
<1> Disable interrupts (set the NP bit of PSW to 1).
<2> Write data to the peripheral command register (PHCMD).
<3> Set the VPPDIS bit of the flash programming mode control register (FLPMC) to 1.
<4> Insert NOP instructions (5 instructions (<4> to <8>)).
<9> Cancel the interrupt disabled state (reset the NP bit of the PSW to 0).
<10>Read the VPPDIS bit of the flash programming mode control register (FLPMC).
If the value read is 0: Mask ROM version (µPD703105, 703106, 703107)
If the value read is 1: Flash memory version (µPD70F3107)
[Description example]
<1> LDSR
rX, 5
<2> ST.B
r10, PHCMD [r0]
<3> SET1
3, FLPMC [r0]
<4> NOP
<5> NOP
<6> NOP
<7> NOP
<8> NOP
Remark
<9> LDSR
rY, 5
<10>TST1
3, FLPMC [r0]
BNZ
<Start address of self-programming routine>
BR
<Routine when writing is not performed>
rX: Value written to the PSW
rY: Value returned to the PSW
Cautions 1. If an interrupt is acknowledged between when PHCMD is issued (<2>) and writing to a
specific register (<3>) immediately after issuing PHCMD, writing to a specific register may
not be performed and a protection error may occur (the PRERR bit of the PHS register = 1).
Therefore, set the NP bit of the PSW to 1 (<1>) to disable interrupt acknowledgment.
Similarly, disable acknowledgement of interrupts when a bit manipulation instruction is
used to set a specific register.
2. When a store instruction is used for setting a specific register, be sure to use the same
general-purpose register used to set the specific register for writing to the PHCMD register
even though the data written to the PHCMD register is dummy data. This is the same as
when a general-purpose register is used for addressing.
3. Do not use DMA transfer for writing to the PHCMD register and a specific register.
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APPENDIX A REGISTER INDEX
(1/8)
Register Symbol
Register Name
Unit
Page
ADCR0
A/D conversion result register 0 (10 bits)
ADC
406
ADCR0H
A/D conversion result register 0H (8 bits)
ADC
406
ADCR1
A/D conversion result register 1 (10 bits)
ADC
406
ADCR1H
A/D conversion result register 1H (8 bits)
ADC
406
ADCR2
A/D conversion result register 2 (10 bits)
ADC
406
ADCR2H
A/D conversion result register 2H (8 bits)
ADC
406
ADCR3
A/D conversion result register 3 (10 bits)
ADC
406
ADCR3H
A/D conversion result register 3H (8 bits)
ADC
406
ADCR4
A/D conversion result register 4 (10 bits)
ADC
406
ADCR4H
A/D conversion result register 4H (8 bits)
ADC
406
ADCR5
A/D conversion result register 5 (10 bits)
ADC
406
ADCR5H
A/D conversion result register 5H (8 bits)
ADC
406
ADCR6
A/D conversion result register 6 (10 bits)
ADC
406
ADCR6H
A/D conversion result register 6H (8 bits)
ADC
406
ADCR7
A/D conversion result register 7 (10 bits)
ADC
406
ADCR7H
A/D conversion result register 7H (8 bits)
ADC
406
ADIC
Interrupt control register
INTC
277
ADM0
A/D converter mode register 0
ADC
402
ADM1
A/D converter mode register 1
ADC
404
ADM2
A/D converter mode register 2
ADC
405
ASC
Address setup wait control register
BCU
120
ASIF0
Asynchronous serial interface transmission status register 0
UART0
363
ASIF1
Asynchronous serial interface transmission status register 1
UART1
363
ASIF2
Asynchronous serial interface transmission status register 2
UART2
363
ASIM0
Asynchronous serial interface mode register 0
UART0
359
ASIM1
Asynchronous serial interface mode register 1
UART1
359
ASIM2
Asynchronous serial interface mode register 2
UART2
359
ASIS0
Asynchronous serial interface status register 0
UART0
362
ASIS1
Asynchronous serial interface status register 1
UART1
362
ASIS2
Asynchronous serial interface status register 2
UART2
362
BCC
Bus cycle control register
BCU
125
BCP
Bus cycle period control register
BCU
121
BCT0
Bus cycle type configuration register 0
BCU
101
BCT1
Bus cycle type configuration register 1
BCU
101
BEC
Endian configuration register
BCU
104
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APPENDIX A REGISTER INDEX
(2/8)
Register Symbol
Register Name
Unit
Page
BRGC0
Baud rate generator control register 0
BRG0
379
BRGC1
Baud rate generator control register 1
BRG1
379
BRGC2
Baud rate generator control register 2
BRG2
379
BSC
Bus size configuration register
BCU
103
CCC00
Capture/compare register C00
RPU
324
CCC01
Capture/compare register C01
RPU
324
CCC10
Capture/compare register C10
RPU
324
CCC11
Capture/compare register C11
RPU
324
CCC20
Capture/compare register C20
RPU
324
CCC21
Capture/compare register C21
RPU
324
CCC30
Capture/compare register C30
RPU
324
CCC31
Capture/compare register C31
RPU
324
CKC
Clock control register
CG
300
CKSR0
Clock select register 0
UART0
378
CKSR1
Clock select register 1
UART1
378
CKSR2
Clock select register 2
UART2
378
CMD0
Compare register D0
RPU
348
CMD1
Compare register D1
RPU
348
CMD2
Compare register D2
RPU
348
CMD3
Compare register D3
RPU
348
CMICD0
Interrupt control register
INTC
277
CMICD1
Interrupt control register
INTC
277
CMICD2
Interrupt control register
INTC
277
CMICD3
Interrupt control register
INTC
277
CSC0
Chip area select control register 0
BCU
97
CSC1
Chip area select control register 1
BCU
97
CSIC0
Clocked serial interface clock selection register 0
CSI0
389
CSIC1
Clocked serial interface clock selection register 1
CSI1
389
CSIC2
Clocked serial interface clock selection register 2
CSI2
389
CSIIC0
Interrupt control register
INTC
277
CSIIC1
Interrupt control register
INTC
277
CSIIC2
Interrupt control register
INTC
277
CSIM0
Clocked serial interface mode register 0
CSI0
387
CSIM1
Clocked serial interface mode register 1
CSI1
387
CSIM2
Clocked serial interface mode register 2
CSI2
387
DADC0
DMA addressing control register 0
DMAC
212
DADC1
DMA addressing control register 1
DMAC
212
DADC2
DMA addressing control register 2
DMAC
212
DADC3
DMA addressing control register 3
DMAC
212
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APPENDIX A REGISTER INDEX
(3/8)
Register Symbol
Register Name
Unit
Page
DBC0
DMA byte count register 0
DMAC
211
DBC1
DMA byte count register 1
DMAC
211
DBC2
DMA byte count register 2
DMAC
211
DBC3
DMA byte count register 3
DMAC
211
DCHC0
DMA channel control register 0
DMAC
214
DCHC1
DMA channel control register 1
DMAC
214
DCHC2
DMA channel control register 2
DMAC
214
DCHC3
DMA channel control register 3
DMAC
214
DDA0H
DMA destination address register 0H
DMAC
209
DDA0L
DMA destination address register 0L
DMAC
210
DDA1H
DMA destination address register 1H
DMAC
209
DDA1L
DMA destination address register 1L
DMAC
210
DDA2H
DMA destination address register 2H
DMAC
209
DDA2L
DMA destination address register 2L
DMAC
210
DDA3H
DMA destination address register 3H
DMAC
209
DDA3L
DMA destination address register 3L
DMAC
210
DDIS
DMA disable status register
DMAC
215
DMAIC0
Interrupt control register
INTC
277
DMAIC1
Interrupt control register
INTC
277
DMAIC2
Interrupt control register
INTC
277
DMAIC3
Interrupt control register
INTC
277
DRST
DMA restart register
DMAC
215
DSA0H
DMA source address register 0H
DMAC
207
DSA0L
DMA source address register 0L
DMAC
208
DSA1H
DMA source address register 1H
DMAC
207
DSA1L
DMA source address register 1L
DMAC
208
DSA2H
DMA source address register 2H
DMAC
207
DSA2L
DMA source address register 2L
DMAC
208
DSA3H
DMA source address register 3H
DMAC
207
DSA3L
DMA source address register 3L
DMAC
208
DTFR0
DMA trigger factor register 0
DMAC
217
DTFR1
DMA trigger factor register 1
DMAC
217
DTFR2
DMA trigger factor register 2
DMAC
217
DTFR3
DMA trigger factor register 3
DMAC
217
DTOC
DMA terminal count output control register
DMAC
216
DWC0
Data wait control register 0
BCU
118
DWC1
Data wait control register 1
BCU
118
FLPMC
Flash programming mode control register
CPU
518
532
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APPENDIX A REGISTER INDEX
(4/8)
Register Symbol
Register Name
Unit
Page
IMR0
Interrupt mask register 0
INTC
280
IMR1
Interrupt mask register 1
INTC
280
IMR2
Interrupt mask register 2
INTC
280
IMR3
Interrupt mask register 3
INTC
280
INTM0
External interrupt mode register 0
INTC
269
INTM1
External interrupt mode register 1
INTC
282
INTM2
External interrupt mode register 2
INTC
282
INTM3
External interrupt mode register 3
INTC
282
INTM4
External interrupt mode register 4
INTC
282
ISPR
In-service priority register
INTC
281
LOCKR
Lock register
CPU
303
OVIC00
Interrupt control register
INTC
277
OVIC01
Interrupt control register
INTC
277
OVIC02
Interrupt control register
INTC
277
OVIC03
Interrupt control register
INTC
277
P0
Port 0
Port
456
P00IC0
Interrupt control register
INTC
277
P00IC1
Interrupt control register
INTC
277
P01IC0
Interrupt control register
INTC
277
P01IC1
Interrupt control register
INTC
277
P02IC0
Interrupt control register
INTC
277
P02IC1
Interrupt control register
INTC
277
P03IC0
Interrupt control register
INTC
277
P03IC1
Interrupt control register
INTC
277
P1
Port 1
Port
459
P10IC0
Interrupt control register
INTC
277
P10IC1
Interrupt control register
INTC
277
P10IC2
Interrupt control register
INTC
277
P10IC3
Interrupt control register
INTC
277
P11IC0
Interrupt control register
INTC
277
P11IC1
Interrupt control register
INTC
277
P11IC2
Interrupt control register
INTC
277
P11IC3
Interrupt control register
INTC
277
P12IC0
Interrupt control register
INTC
277
P12IC1
Interrupt control register
INTC
277
P12IC2
Interrupt control register
INTC
277
P12IC3
Interrupt control register
INTC
277
P13IC0
Interrupt control register
INTC
277
P13IC1
Interrupt control register
INTC
277
P13IC2
Interrupt control register
INTC
277
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APPENDIX A REGISTER INDEX
(5/8)
Register Symbol
Register Name
Unit
Page
P13IC3
Interrupt control register
INTC
277
P2
Port 2
Port
461
P3
Port 3
Port
465
P4
Port 4
Port
468
P5
Port 5
Port
471
P7
Port 7
Port
473
PAH
Port AH
Port
476
PAL
Port AL
Port
474
PBD
Port BD
Port
492
PCD
Port CD
Port
489
PCM
Port CM
Port
486
PCS
Port CS
Port
480
PCT
Port CT
Port
484
PDL
Port DL
Port
478
PFC0
Port 0 function control register
Port
458
PFC2
Port 2 function control register
Port
464
PFC3
Port 3 function control register
Port
467
PFC4
Port 4 function control register
Port
470
PFCCD
Port CD function control register
Port
491
PFCCM
Port CM function control register
Port
488
PFCCS
Port CS function control register
Port
483
PHCMD
Peripheral command register
CPU
299
PHS
Peripheral status register
CPU
302
PM0
Port 0 mode register
Port
456
PM1
Port 1 mode register
Port
459
PM2
Port 2 mode register
Port
462
PM3
Port 3 mode register
Port
465
PM4
Port 4 mode register
Port
468
PM5
Port 5 mode register
Port
471
PMAH
Port AH mode register
Port
477
PMAL
Port AL mode register
Port
474
PMBD
Port BD mode register
Port
492
PMC0
Port 0 mode control register
Port
457
PMC1
Port 1 mode control register
Port
460
PMC2
Port 2 mode control register
Port
463
PMC3
Port 3 mode control register
Port
466
PMC4
Port 4 mode control register
Port
469
PMC5
Port 5 mode control register
Port
472
534
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APPENDIX A REGISTER INDEX
(6/8)
Register Symbol
Register Name
Unit
Page
PMCAH
Port AH mode control register
Port
477
PMCAL
Port AL mode control register
Port
475
PMCBD
Port BD mode control register
Port
493
PMCCD
Port CD mode control register
Port
490
PMCCM
Port CM mode control register
Port
487
PMCCS
Port CS mode control register
Port
482
PMCCT
Port CT mode control register
Port
485
PMCD
Port CD mode register
Port
489
PMCDL
Port DL mode control register
Port
479
PMCM
Port CM mode register
Port
486
PMCS
Port CS mode register
Port
481
PMCT
Port CT mode register
Port
484
PMDL
Port DL mode register
Port
478
PRC
Page ROM configuration register
MEMC
153
PRCMD
Command register
CPU
306
PSC
Power-save control register
CPU
307
PSMR
Power-save mode register
CPU
306
PWMB0
PWM buffer register 0
PWM
435
PWMB1
PWM buffer register 1
PWM
435
PWMC0
PWM control register 0
PWM
433
PWMC1
PWM control register 1
PWM
433
RFS1
Refresh control register 1
MEMC
169
SDRAM refresh control register 1
MEMC
195
Refresh control register 3
MEMC
169
SDRAM refresh control register 3
MEMC
195
Refresh control register 4
MEMC
169
SDRAM refresh control register 4
MEMC
195
Refresh control register 6
MEMC
169
SDRAM refresh control register 6
MEMC
195
RWC
Refresh wait control register
MEMC
171
RXB0
Receive buffer register 0
UART0
364
RXB1
Receive buffer register 1
UART1
364
RXB2
Receive buffer register 2
UART2
364
SCR1
DRAM configuration register 1
MEMC
161
SDRAM configuration register 1
MEMC
179
DRAM configuration register 3
MEMC
161
SDRAM configuration register 3
MEMC
179
RFS3
RFS4
RFS6
SCR3
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535
APPENDIX A REGISTER INDEX
(7/8)
Register Symbol
SCR4
Register Name
Unit
Page
DRAM configuration register 4
MEMC
161
SDRAM configuration register 4
MEMC
179
DRAM configuration register 6
MEMC
161
SDRAM configuration register 6
MEMC
179
SEIC0
Interrupt control register
INTC
277
SEIC1
Interrupt control register
INTC
277
SEIC2
Interrupt control register
INTC
277
SESC0
Valid edge select register C0
INTC
284, 330
SESC1
Valid edge select register C1
INTC
284, 330
SESC2
Valid edge select register C2
INTC
284, 330
SESC3
Valid edge select register C3
INTC
284, 330
SIO0
Serial I/O shift register 0
CSI0
391
SIO1
Serial I/O shift register 1
CSI1
391
SIO2
Serial I/O shift register 2
CSI2
391
SIOE0
Receive-only serial I/O shift register 0
CSI0
392
SIOE1
Receive-only serial I/O shift register 1
CSI1
392
SIOE2
Receive-only serial I/O shift register 2
CSI2
392
SOTB0
Clocked serial interface transmit buffer register 0
CSI0
393
SOTB1
Clocked serial interface transmit buffer register 1
CSI1
393
SOTB2
Clocked serial interface transmit buffer register 2
CSI2
393
SRIC0
Interrupt control register
INTC
277
SRIC1
Interrupt control register
INTC
277
SRIC2
Interrupt control register
INTC
277
STIC0
Interrupt control register
INTC
277
STIC1
Interrupt control register
INTC
277
STIC2
Interrupt control register
INTC
277
TMC0
Timer C0
RPU
322
TMC1
Timer C1
RPU
322
TMC2
Timer C2
RPU
322
TMC3
Timer C3
RPU
322
TMCC00
Timer mode control register C00
RPU
326
TMCC01
Timer mode control register C01
RPU
328
TMCC10
Timer mode control register C10
RPU
326
TMCC11
Timer mode control register C11
RPU
328
TMCC20
Timer mode control register C20
RPU
326
TMCC21
Timer mode control register C21
RPU
328
TMCC30
Timer mode control register C30
RPU
326
TMCC31
Timer mode control register C31
RPU
328
SCR6
536
User’s Manual U14359EJ3V0UM
APPENDIX A REGISTER INDEX
(8/8)
Register Symbol
Register Name
Unit
Page
TMCD0
Timer mode control register D0
RPU
350
TMCD1
Timer mode control register D1
RPU
350
TMCD2
Timer mode control register D2
RPU
350
TMCD3
Timer mode control register D3
RPU
350
TMD0
Timer D0
RPU
347
TMD1
Timer D1
RPU
347
TMD2
Timer D2
RPU
347
TMD3
Timer D3
RPU
347
TXB0
Transmit buffer register 0
UART0
365
TXB1
Transmit buffer register 1
UART1
365
TXB2
Transmit buffer register 2
UART2
365
VSWC
System wait control register
BCU
93
User’s Manual U14359EJ3V0UM
537
APPENDIX B INSTRUCTION SET LIST
B.1 Convention
(1) Register symbols used to describe operands
Register Symbol
Explanation
reg1
General-purpose register:
Used as source register.
reg2
General-purpose register:
Used mainly as destination register. Also used as source register in some
instructions.
reg3
General-purpose register:
Used mainly to store the remainders of division results and the higher 3 bits of
multiplication results.
bit#3
3-bit data for specifying the bit number
immX
X bit immediate data
dispX
X bit displacement data
regID
System register number
vector
5-bit data that specifies the trap vector (00H to 1FH)
cccc
4-bit data that shows the conditions code
sp
Stack pointer (r3)
ep
Element pointer (r30)
listX
X item register list
(2) Register symbols used to describe opcodes
Register Symbol
Explanation
R
1-bit data of a code that specifies reg1 or regID
r
1-bit data of the code that specifies reg2
w
1-bit data of the code that specifies reg3
d
1-bit displacement data
I
1-bit immediate data (indicates the higher bits of immediate data)
i
1-bit immediate data
cccc
4-bit data that shows the condition codes
CCCC
4-bit data that shows the condition codes of Bcond instruction
bbb
3-bit data for specifying the bit number
L
1-bit data that specifies a program register in the register list
S
1-bit data that specifies a system register in the register list
538
User’s Manual U14359EJ3V0UM
APPENDIX B INSTRUCTION SET LIST
(3) Register symbols used in operation
Register Symbol
Explanation
←
Input for
GR [ ]
General-purpose register
SR [ ]
System register
zero-extend (n)
Expand n with zeros until word length.
sign-extend (n)
Expand n with signs until word length.
load-memory (a, b)
Read size b data from address a.
store-memory (a, b, c)
Write data b into address a in size c.
load-memory-bit (a, b)
Read bit b of address a.
store-memory-bit (a, b, c)
Write c to bit b of address a.
saturated (n)
Execute saturated processing of n (n is a 2’s complement).
If, as a result of calculations,
n ≥ 7FFFFFFFH, let it be 7FFFFFFFH.
n ≤ 80000000H, let it be 80000000H.
result
Reflects the results in a flag.
Byte
Byte (8 bits)
Half-word
Halfword (16 bits)
Word
Word (32 bits)
+
Addition
–
Subtraction
ll
Bit concatenation
×
Multiplication
÷
Division
%
Remainder from division results
AND
Logical product
OR
Logical sum
XOR
Exclusive OR
NOT
Logical negation
logically shift left by
Logical shift left
logically shift right by
Logical shift right
arithmetically shift right by
Arithmetic shift right
(4) Register symbols used in an execution clock
Register Symbol
Explanation
i
If executing another instruction immediately after executing the first instruction (issue).
r
If repeating execution of the same instruction immediately after executing the first instruction (repeat).
l
If using the results of instruction execution in the instruction immediately after the execution (latency).
User’s Manual U14359EJ3V0UM
539
APPENDIX B INSTRUCTION SET LIST
(5) Register symbols used in flag operations
Identifier
Explanation
(Blank)
No change
0
Clear to 0
X
Set or cleared in accordance with the results.
R
Previously saved values are restored.
(6) Condition codes
Condition Name
(cond)
Condition Formula
Condition Code
(cccc)
Explanation
V
0 0 0 0
OV = 1
Overflow
NV
1 0 0 0
OV = 0
No overflow
C/L
0 0 0 1
CY = 1
Carry
Lower (Less than)
NC/NL
1 0 0 1
CY = 0
No carry
Not lower (Greater than or equal)
Z/E
0 0 1 0
Z=1
Zero
Equal
NZ/NE
1 0 1 0
Z=0
Not zero
Not equal
NH
0 0 1 1
(CY or Z) = 1
Not higher (Less than or equal)
H
1 0 1 1
(CY or Z) = 0
Higher (Greater than)
N
0 1 0 0
S=1
Negative
P
1 1 0 0
S=0
Positive
T
0 1 0 1
SA
1 1 0 1
SAT = 1
Saturated
LT
0 1 1 0
(S xor OV) = 1
Less than signed
GE
1 1 1 0
(S xor OV) = 0
Greater than or equal signed
—
Always (Unconditional)
LE
0 1 1 1
((S xor OV) or Z) = 1
Less than or equal signed
GT
1 1 1 1
((S xor OV) or Z) = 0
Greater than signed
540
User’s Manual U14359EJ3V0UM
APPENDIX B INSTRUCTION SET LIST
B.2 Instruction Set (In Alphabetical Order)
(1/6)
Mnemonic
Operand
Opcode
Operation
Flags
Execution
Clock
ADD
ADDI
i
r
l
CY OV S
Z SAT
reg1,reg2
rrrrr001110RRRRR
GR[reg2]←GR[reg2]+GR[reg1]
1
1
1
×
×
×
×
imm5,reg2
rrrrr010010iiiii
GR[reg2]←GR[reg2]+sign-extend(imm5)
1
1
1
×
×
×
×
imm16,reg1,reg2
rrrrr110000RRRRR
GR[reg2]←GR[reg1]+sign-extend(imm16)
1
1
1
×
×
×
×
i i i i i i i i i i i i i i i i
AND
reg1,reg2
rrrrr001010RRRRR
GR[reg2]←GR[reg2]AND GR[reg1]
1
1
1
0
×
×
ANDI
imm16,reg1,reg2
rrrrr110110RRRRR
GR[reg2]←GR[reg1]AND zero-extend(imm16)
1
1
1
0
0
×
2
2
2
i i i i i i i i i i i i i i i i
Bcond
disp9
ddddd1011dddc ccc
if conditions are satisfied
Note 1 then PC←PC+sign-extend(disp9)
When conditions
are satisfied
When conditions
Note 2 Note 2 Note 2
1
1
1
1
1
1
×
0
×
×
1
1
1
×
0
×
×
4
4
4
3
3
3
are not satisfied
BSH
reg2,reg3
rrrrr11111100000
GR[reg3]←GR[reg2] (23 : 16) ll GR[reg2] (31 : 24) ll
wwwww01101000010 GR[reg2] (7 : 0) ll GR[reg2] (15 : 8)
BSW
reg2,reg3
rrrrr11111100000
GR[reg3]←GR[reg2] (7 : 0) ll GR[reg2] (15 : 8) ll GR
wwwww01101000000 [reg2] (23 : 16) ll GR[reg2] (31 : 24)
CALLT
imm6
0000001000iiiiii
CTPC←PC+2(return PC)
CTPSW←PSW
adr←CTBP+zero-extend(imm6 logically shift left by 1)
PC←CTBP+zero-extend(Load-memory(adr,Half-word))
CLR1
bit#3, disp16[reg1]
10bbb111110RRRRR adr←GR[reg1]+sign-extend(disp16)
dddddddddddddddd
Z flag←Not(Load-memory-bit(adr,bit#3))
×
Note 3 Note 3 Note 3
Store-memory-bit(adr,bit#3,0)
reg2,[reg1]
rrrrr111111RRRRR
adr←GR[reg1]
0000000011100100
Z flag←Not(Load-memory-bit(adr,reg2))
3
3
×
3
Note 3 Note 3 Note 3
Store-memory-bit(adr,reg2,0)
CMOV
cccc,imm5,reg2,reg3
rrrrr111111iiiii
if conditions are satisfied
wwwww011000cccc0
then GR[reg3]←sign-extended(imm5)
1
1
1
1
1
1
1
1
1
else GR[reg3]←GR[reg2]
cccc,reg1,reg2,reg3 r r r r r 1 1 1 1 1 1 R R R R
if conditions are satisfied
wwwww011001cccc0 then GR[reg3]←GR[reg1]
else GR[reg3]←GR[reg2]
CMP
reg1,reg2
imm5,reg2
CTRET
DBRET
rrrrr001111RRRRR
result←GR[reg2]–GR[reg1]
×
×
×
×
rrrrr010011iiiii
result←GR[reg2]–sign-extend(imm5)
1
1
1
×
×
×
×
0000011111100000
PC←CTPC
3
3
3
R
R
R
R
R
0000000101000100
PSW←CTPSW
0000011111100000
PC←DBPC
3
3
3
R
R
R
R
R
0000000101000110
PSW←DBPSW
User’s Manual U14359EJ3V0UM
541
APPENDIX B INSTRUCTION SET LIST
(2/6)
Mnemonic
Operand
Opcode
Operation
Execution
Flags
Clock
DBTRAP
1111100001000000
DBPC←PC+2 (returned PC)
i
r
l
3
3
3
1
1
1
CY OV S
Z SAT
DBPSW←PSW
PSW.NP←1
PSW.EP←1
PSW.ID←1
PC←00000060H
DI
0000011111100000
PSW.ID←1
0000000101100000
DISPOSE
imm5,list12
0000011001iiiiiL
sp←sp+zero-extend(imm5 logically shift left by 2)
n+1 n+1 n+1
LLLLLLLLLLL00000
GR[reg in list12]←Load-memory(sp,Word)
Note 4 Note 4 Note 4
sp←sp+4
repeat 2 steps above until all regs in list12 is loaded
imm5,list12,[reg1]
0000011001iiiiiL
sp←sp+zero-extend(imm5 logically shift left by 2)
LLLLLLLLLLLRRRRR R[reg in list12]←Load-memory(sp,Word)
n+3 n+3 n+3
Note 4 Note 4 Note 4
Note 5 sp←sp+4
repeat 2 steps above until all regs in list12 is loaded
PC←GR[reg1]
DIV
reg1,reg2,reg3
rrrrr111111RRRRR
GR[reg2]←GR[reg2}÷GR[reg1]
35 35 35
wwwww01011000000 GR[reg3]←GR[reg2]%GR[reg1]
DIVH
reg1,reg2
reg1,reg2,reg3
rrrrr000010RRRRR
rrrrr111111RRRRR
Note 6
35 35 35
×
×
×
Note 6
35 35 35
×
×
×
34 34 34
×
×
×
34 34 34
×
×
×
0
×
×
GR[reg2]←GR[reg2]÷GR[reg1]
GR[reg2]←GR[reg2]÷GR[reg1]
wwwww01010000000 GR[reg3]←GR[reg2]%GR[reg1]
DIVHU
reg1,reg2,reg3
rrrrr111111RRRRR
Note 6
GR[reg2]←GR[reg2]÷GR[reg1]
wwwww01010000010 GR[reg3]←GR[reg2]%GR[reg1]
DIVU
reg1,reg2,reg3
rrrrr111111RRRRR
GR[reg2]←GR[reg2]÷GR[reg1]
wwwww01011000010 GR[reg3]←GR[reg2]%GR[reg1]
EI
1000011111100000
PSW.ID←0
1
1
1
Stop
1
1
1
GR[reg3]←GR[reg2](15 : 0) ll GR[reg2] (31 : 16)
1
1
1
rrrrr11110dddddd
GR[reg2]←PC+4
2
2
2
ddddddddddddddd0
PC←PC+sign-extend(disp22)
0000000101100000
HALT
0000011111100000
0000000100100000
HSW
reg2,reg3
rrrrr11111100000
wwwww01101000100
JARL
disp22,reg2
Note 7
JMP
[reg1]
00000000011RRRRR
PC←GR[reg1]
3
3
3
JR
disp22
0000011110dddddd
PC←PC+sign-extend(disp22)
2
2
2
rrrrr111000RRRRR
adr←GR[reg1]+sign-extend(disp16)
1
1
Note
dddddddddddddddd
GR[reg2]←sign-extend(Load-memory(adr,Byte))
rrrrr11110bRRRRR
adr←GR[reg1]+sign-extend(disp16)
dddddddddddddd1
GR[reg2]←zero-extend(Load-memory(adr,Byte))
ddddddddddddddd0
Note 7
LD.B
LD.BU
disp16[reg1],reg2
disp16[reg1],reg2
Notes 8, 10
542
User’s Manual U14359EJ3V0UM
11
1
1
Note
11
×
APPENDIX B INSTRUCTION SET LIST
(3/6)
Mnemonic
Operand
Opcode
Operation
Execution
Flags
Clock
LD.H
disp16[reg1],reg2
rrrrr111001RRRRR
adr←GR[reg1]+sign-extend(disp16)
ddddddddddddddd0
GR[reg2]←sign-extend(Load-memory(adr,Half-
i
r
l
1
1
Note
CY OV S
Z SAT
11
Note 8 word))
LDSR
reg2,regID
rrrrr111111RRRRR
SR[regID]←GR[reg2]
0000000000100000
Other than regID = PSW
1
1
1
regID = PSW
1
1
1
1
1
Note
×
×
×
0
×
×
×
Note 12
LD.HU
disp16[reg1],reg2
rrrrr111111RRRRR
adr←GR[reg1]+sign-exend(disp16)
ddddddddddddddd1
GR[reg2]←zero-extend(Load-memory(adr,half-word)
11
Note 8
LD.W
disp16[reg1],reg2
rrrrr111001RRRRR
adr←GR[reg1]+sign-exend(disp16)
ddddddddddddddd1
GR[reg2]←Load-memory(adr,Word)
1
1
Note
11
Note 8
MOV
reg1,reg2
rrrrr000000RRRRR
GR[reg2]←GR[reg1]
1
1
1
imm5,reg2
rrrrr010000iiiii
GR[reg2]←sign-extend(imm5)
1
1
1
imm32,reg1
00000110001RRRRR GR[reg1]←imm32
2
2
2
GR[reg2]←GR[reg1]+sign-extend(imm16)
1
1
1
GR[reg2]←GR[reg1]+(imm16 ll 016)
1
1
1
GR[reg3] ll GR[reg2]←GR[reg2]xGR[reg1]
1
2
2
GR[reg3] ll GR[reg2]←GR[reg2]xsign-extend(imm9)
1
i i i i i i i i i i i i i i i i
i i i i i i i i i i i i i i i i
MOVEA
imm16,reg1,reg2
rrrrr110001RRRRR
i i i i i i i i i i i i i i i i
MOVHI
imm16,reg1,reg2
rrrrr110010RRRRR
i i i i i i i i i i i i i i i i
MUL
reg1,reg2,reg3
rrrrr111111RRRRR
wwwww01000100000
imm9,reg2,reg3
rrrrr111111iiiii
Note14
wwwww01001IIII00
2
2
Note14
Note 13
MULH
MULHI
reg1,reg2
rrrrr000111RRRRR
GR[reg2]←GR[reg2]
Note 6
Note 6
1
1
2
1
1
2
GR[reg3] ll GR[reg2]←GR[reg2]xGR[reg1]
1
2
2
GR[reg3] ll GR[reg2]←GR[reg2]xzero-extend(imm9)
1
xGR[reg1]
imm5,reg2
rrrrr010111iiiii
GR[reg2]←GR[reg2]
Note 6
imm16,reg1,reg2
rrrrr110111RRRRR
GR[reg2]←GR[reg1]
Note 6
xsign-extend(imm5)
ximm16
1
1
2
i i i i i i i i i i i i i i i i
MULU
reg1,reg2,reg3
rrrrr111111RRRRR
wwwww01000100010
imm9,reg2,reg3
rrrrr111111iiiii
Note 14
wwwww01001IIII10
2
2
Note 14
Note 13
NOP
0000000000000000 Pass at least one clock cycle doing nothing.
NOT
reg1,reg2
rrrrr000001RRRRR
NOT1
bit#3,disp16[reg1]
01bbb111110RRRRR adr←GR[reg1]+sign-extend(disp16)
dddddddddddddddd
GR[reg2]←NOT(GR[reg1])
Z flag←Not(Load-memory-bit(adr,bit#3))
1
1
1
1
1
1
3
3
3
×
×
Note 3 Note 3 Note 3
Store-memory-bit(adr,bit#3,Z flag)
reg2,[reg1]
rrrrr111111RRRRR
adr←GR[reg1]
0000000011100010
Z flag←Not(Load-memory-bit(adr,reg2))
3
3
3
×
Note 3 Note 3 Note 3
Store-memory-bit(adr,reg2,Z flag)
User’s Manual U14359EJ3V0UM
543
APPENDIX B INSTRUCTION SET LIST
(4/6)
Mnemonic
Operand
Opcode
Operation
Execution
Flags
Clock
i
r
l
CY OV S
Z SAT
OR
reg1,reg2
rrrrr001000RRRRR
GR[reg2]←GR[reg2]OR GR[reg1]
1
1
1
0
×
×
ORI
imm16,reg1,reg2
rrrrr110100RRRRR
GR[reg2]←GR[reg1]OR zero-extend(imm16)
1
1
1
0
×
×
i i i i i i i i i i i i i i i i
PREPARE list12,imm5
0000011110iiiiiL
Store-memory(sp–4,GR[reg in list12],Word)
LLLLLLLLLLL00001 sp←sp–4
n+1 n+1 n+1
Note 4 Note 4 Note 4
repeat 1 step above until all regs in list12 is stored
sp←sp-zero-extend(imm5)
list12,imm5,
Note 15
sp/imm
0000011110iiiiiL
Store-memory(sp–4,GR[reg in list12],Word)
LLLLLLLLLLLff011
sp←sp–4
imm16/imm32
repeat 1 step above until all regs in list12 is stored
Note 4 Note 4 Note 4
Note17 Note17 Note17
Note 16 sp←sp-zero-extend(imm5)
ep←sp/imm
RETI
n+2 n+2 n+2
0000011111100000 if PSW.EP=1
3
3
3
R
R
R
R
1
1
1
×
0
×
×
1
1
1
×
0
×
×
1
1
1
GR[reg2]←saturated(GR[reg2]+GR[reg1])
1
1
1
×
×
×
×
0000000101000000 then PC
R
←EIPC
PSW ←EIPSW
else if PSW.NP=1
then
PC
←FEPC
PSW ←FEPSW
else
PC
←EIPC
PSW ←EIPSW
SAR
reg1,reg2
rrrrr111111RRRRR
GR[reg2]←GR[reg2]arithmetically shift right
0000000010100000
imm5,reg2
rrrrr010101iiiii
by GR[reg1]
GR[reg2]←GR[reg2]arithmetically shift right
by zero-extend (imm5)
SASF
cccc,reg2
rrrrr1111110cccc
if conditions are satisfied
0000001000000000
then GR[reg2]←(GR[reg2]Logically shift left by 1)
OR 00000001H
else GR[reg2]←(GR[reg2]Logically shift left by 1)
OR 00000000H
rrrrr000110RRRRR
×
SATADD
reg1,reg2
imm5,reg2
rrrrr010001iiiii
GR[reg2]←saturated(GR[reg2]+sign-extend(imm5)
1
1
1
×
×
×
×
×
SATSUB
reg1,reg2
rrrrr000101RRRRR
GR[reg2]←saturated(GR[reg2]–GR[reg1])
1
1
1
×
×
×
×
×
SATSUBI
imm16,reg1,reg2
rrrrr110011RRRRR
GR[reg2]←saturated(GR[reg1]–sign-extend(imm16)
1
1
1
×
×
×
×
×
rrrrr000100RRRRR
GR[reg2]←saturated(GR[reg1]–GR[reg2])
1
1
1
×
×
×
×
×
rrrrr1111110cccc
If conditions are satisfied
1
1
1
0000000000000000
then GR[reg2]←00000001H
i i i i i i i i i i i i i i i i
SATSUBR reg1,reg2
SETF
cccc,reg2
else GR[reg2]←00000000H
544
User’s Manual U14359EJ3V0UM
APPENDIX B INSTRUCTION SET LIST
(5/6)
Mnemonic
Operand
Opcode
Operation
Execution
Flags
Clock
SET1
bit#3,disp16[reg1]
00bbb111110RRRRR adr←GR[reg1]+sign-extend(disp16)
dddddddddddddddd
Z flag←Not (Load-memory-bit(adr,bit#3))
i
r
l
3
3
3
CY OV S
Z SAT
×
Note 3 Note 3 Note 3
Store-memory-bit(adr,bit#3,1)
reg2,[reg1]
rrrrr111111RRRRR
adr←GR[reg1]
0000000011100000
Z flag←Not(Load-memory-bit(adr,reg2))
3
3
×
3
Note 3 Note 3 Note 3
Store-memory-bit(adr,reg2,1)
SHL
reg1,reg2
rrrrr111111RRRRR
GR[reg2]←GR[reg2] logically shift left by GR[reg1]
1
1
1
×
0
×
×
GR[reg2]←GR[reg2] logically shift left
1
1
1
×
0
×
×
GR[reg2]←GR[reg2] logically shift right by GR[reg1]
1
1
1
×
0
×
×
GR[reg2]←GR[reg2] logically shift right
1
1
1
×
0
×
×
1
1
Note 9
1
1
Note 9
1
1
Note 9
1
1
Note 9
1
1
Note 9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0000000011000000
imm5,reg2
rrrrr010110iiiii
by zero-extend(imm5)
SHR
reg1,reg2
rrrrr111111RRRRR
0000000010000000
imm5,reg2
rrrrr010100iiiii
by zero-extend(imm5)
SLD.B
disp7[ep],reg2
rrrrr0110ddddddd
adr←ep+zero-extend(disp7)
GR[reg2]←sign-extend(Load-memory(adr,Byte))
SLD.BU
disp4[ep],reg2
rrrrr0000110dddd
adr←ep+zero-extend(disp4)
Note 18 GR[reg2]←zero-extend(Load-memory(adr,Byte))
SLD.H
disp8[ep],reg2
rrrrr1000ddddddd
adr←ep+zero-extend(disp8)
Note 19 GR[reg2]←sign-extend(Load-memory(adr,Halfword))
SLD.HU
disp5[ep],reg2
r r r r r 0 0 0 0 1 1 1 d d d d adr←ep+zero-extend(disp5)
Notes 18, 20 GR[reg2]←zero-extend(Load-memory(adr,Halfword))
SLD.W
disp8[ep],reg2
rrrrr1010dddddd0
adr←ep+zero-extend(disp8)
Note 21 GR[reg2]←Load-memory(adr,Word)
SST.B
reg2,disp7[ep]
rrrrr0111ddddddd
adr←ep+zero-extend(disp7)
Store-memory(adr,GR[reg2],Byte)
SST.H
reg2,disp8[ep]
rrrrr1001ddddddd
adr←ep+zero-extend(disp8)
Note 19 Store-memory(adr,GR[reg2],Half-word)
SST.W
reg2,disp8[ep]
rrrrr1010dddddd1
adr←ep+zero-extend(disp8)
Note 21 Store-memory(adr,GR[reg2],Word)
ST.B
ST.H
reg2,disp16[reg1]
reg2,disp16[reg1]
rrrrr111010RRRRR
adr←GR[reg1]+sign-extend(disp16)
dddddddddddddddd
Store-memory(adr,GR[reg2],Byte)
rrrrr111011RRRRR
adr←GR[reg1]+sign-extend(disp16)
ddddddddddddddd0
Store-memory (adr,GR[reg2], Half-word)
Note 8
ST.W
reg2,disp16[reg1]
rrrrr111011RRRRR
adr←GR[reg1]+sign-extend(disp16)
ddddddddddddddd1
Store-memory (adr,GR[reg2], Word)
Note 8
STSR
regID,reg2
rrrrr111111RRRRR
GR[reg2]←SR[regID]
0000000001000000
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APPENDIX B INSTRUCTION SET LIST
(6/6)
Mnemonic
Operand
Opcode
Operation
Execution
Flags
Clock
i
r
l
CY OV S
Z SAT
SUB
reg1,reg2
rrrrr001101RRRRR
GR[reg2]←GR[reg2]–GR[reg1]
1
1
1
×
×
×
×
SUBR
reg1,reg2
rrrrr001100RRRRR
GR[reg2]←GR[reg1]–GR[reg2]
1
1
1
×
×
×
×
SWITCH
reg1
00000000010RRRRR
adr←(PC+2) + (GR [reg1] logically shift left by 1)
5
5
5
1
1
1
1
1
1
3
3
3
1
1
1
0
×
×
3
3
3
PC←(PC+2) + (sign-extend
(Load-memory (adr,Half-word)))
logically shift left by 1
SXB
reg1
00000000101RRRRR GR[reg1]←sign-extend
(GR[reg1] (7 : 0))
SXH
reg1
00000000111RRRRR GR[reg1]←sign-extend
(GR[reg1] (15 : 0))
TRAP
vector
00000111111iiiii
EIPC
←PC+4 (Return PC)
0000000100000000
EIPSW
←PSW
ECR.EICC ←Interrupt Code
PSW.EP
←1
PSW.ID
←1
PC
←00000040H (when vector is 00H to
0FH)
00000050H (when vector is 10H to
1FH)
TST
reg1,reg2
rrrrr001011RRRRR
TST1
bit#3,disp16[reg1]
11bbb111110RRRRR adr←GR[reg1]+sign-extend(disp16)
reg2, [reg1]
result←GR[reg2] AND GR[reg1]
dddddddddddddddd
Z flag←Not (Load-memory-bit (adr,bit#3))
rrrrr111111RRRRR
adr←GR[reg1]
0000000011100110
Z flag←Not (Load-memory-bit (adr,reg2))
×
Note 3 Note 3 Note 3
3
3
×
3
Note 3 Note 3 Note 3
XOR
reg1,reg2
rrrrr001001RRRRR
GR[reg2]←GR[reg2] XOR GR[reg1]
1
1
1
0
×
×
XORI
imm16,reg1,reg2
rrrrr110101RRRRR
GR[reg2]←GR[reg1] XOR zero-extend (imm16)
1
1
1
0
×
×
i i i i i i i i i i i i i i i i
ZXB
reg1
00000000100RRRRR
GR[reg1]←zero-extend (GR[reg1] (7 : 0))
1
1
1
ZXH
reg1
00000000110RRRRR
GR[reg1]←zero-extend (GR[reg1] (15 : 0))
1
1
1
Notes 1.
dddddddd: Higher 8 bits of disp9.
2.
3 clocks if the final instruction includes PSW write access.
3.
If there is no wait state (3 + the number of read access wait states).
4.
n is the total number of list X load registers. (According to the number of wait states. Also, if there are
no wait states, n is the number of list X registers.)
5.
RRRRR: other than 00000.
6.
The lower halfword data only is valid.
7.
ddddddddddddddddddddd: The higher 21 bits of disp22.
8.
ddddddddddddddd: The higher 15 bits of disp16.
9.
According to the number of wait states (1 if there are no wait states).
10. b: bit 0 of disp16.
11. According to the number of wait states (2 if there are no wait states).
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APPENDIX B INSTRUCTION SET LIST
Notes 12. In this instruction, for convenience of mnemonic description, the source register is made reg2, but the
reg1 field is used in the opcode. Therefore, the meaning of register specification in the mnemonic
description and in the opcode differs from other instructions.
rrrrr
= regID specification
RRRRR = reg2 specification
13. i i i i i : Lower 5 bits of imm9.
I I I I : Lower 4 bits of imm9.
14. In the case of reg2 = reg3 (the lower 32 bits of the results are not written in the register) or reg3 = r0
(the higher 32 bits of the results are not written in the register), shortened by 1 clock.
15. sp/imm: Specified by bits 19 and 20 of the sub-opcode.
16. ff = 00: Load sp in ep.
01: Load sign expanded 16-bit immediate data (bits 47 to 32) in ep.
10: Load 16-bit logically left shifted 16-bit immediate data (bits 47 to 32) in ep.
11: Load 32-bit immediate data (bits 63 to 32) in ep.
17. If imm = imm32, n + 3 clocks.
18. r r r r r : Other than 00000.
19. ddddddd: Higher 7 bits of disp8.
20. dddd: Higher 4 bits of disp5.
21. dddddd: Higher 6 bits of disp8.
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APPENDIX C INDEX
BCT0, BCT1........................................................... 101
[A]
BCYST ..................................................................... 55
A/D conversion result registers 0 to 7.....................406
BEC........................................................................ 104
A/D conversion result registers 0H to 7H................406
Block transfer mode ............................................... 225
A/D converter mode register 0................................402
Boundary operation conditions............................... 139
A/D converter mode register 1................................404
BRG0 to BRG2....................................................... 377
A/D converter mode register 2................................405
BRGC0 to BRGC2 ................................................. 379
A/D converter operation..........................................408
BSC........................................................................ 103
A0 to A15..................................................................58
Bus access............................................................. 102
A16 to A25................................................................58
Bus control pins ....................................................... 94
ADCR0 to ADCR7 ..................................................406
Bus cycle control register ....................................... 125
ADCR0H to ADCR7H .............................................406
Bus cycle period control register ............................ 121
Address multiplex function (EDO DRAM) ...............160
Bus cycle type configuration registers 0, 1............. 101
Address multiplex function (SDRAM) .....................177
Bus cycle type control function............................... 100
Address setup wait control register.........................120
Bus cycles in which wait function is valid ............... 124
Address space..........................................................71
Bus hold function.................................................... 126
ADIC .......................................................................277
Bus hold procedure ................................................ 127
ADM0......................................................................402
Bus hold timing (EDO DRAM) ................................ 130
ADM1......................................................................404
Bus hold timing (SDRAM) ...................................... 134
ADM2......................................................................405
Bus hold timing (SRAM)......................................... 128
ADTRG .....................................................................49
Bus priority order.................................................... 138
ANI0 to ANI7.............................................................51
Bus size configuration register ............................... 103
Applications ..............................................................29
Bus sizing function ................................................. 103
Area..........................................................................76
Bus width ............................................................... 107
ASC ........................................................................120
BUSCLK................................................................... 53
ASIF0 to ASIF2.......................................................363
ASIM0 to ASIM2 .....................................................359
[C]
ASIS0 to ASIS2 ......................................................362
Capture/compare registers C00, 01, 10, 11 ........... 324
Asynchronous serial interface mode
Capture/compare registers C20, 21 ....................... 324
registers 0 to 2........................................................359
Capture/compare registers C30, 31 ....................... 324
Asynchronous serial interface status
Cautions (DMA)...................................................... 261
registers 0 to 2........................................................362
Cautions (PWM)..................................................... 438
Asynchronous serial interface transmission status
Cautions (timer C) .................................................. 345
registers 0 to 2........................................................363
Cautions (timer D) .................................................. 354
Asynchronous serial interfaces 0 to 2.....................356
Cautions (UART).................................................... 384
AVDD .........................................................................60
CCC00, 01, 10, 11 ................................................. 324
AVREF ........................................................................60
CCC20, 21 ............................................................. 324
AVSS..........................................................................60
CCC30, 31 ............................................................. 324
Chip area select control registers 0, 1...................... 97
[B]
Chip select control function ...................................... 97
Basic configuration of timer C.................................321
CKC ....................................................................... 300
Basic configuration of timer D.................................346
CKSEL ..................................................................... 59
Baud rate generator control registers 0 to 2 ...........379
CKSR0 to CKSR2 .................................................. 378
BCC ........................................................................125
CLKOUT .................................................................. 52
BCP ........................................................................121
Clock control register ............................................. 300
548
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APPENDIX C INDEX
Clock select registers 0 to 2 ...................................378
DMA terminal count output control register............ 216
Clocked serial interface clock selection
DMA transfer end................................................... 261
registers 0 to 2 .......................................................389
DMA transfer start factors ...................................... 256
Clocked serial interface mode registers 0 to 2 .......387
DMA trigger factor registers 0 to 3 ......................... 217
Clocked serial interface transmit buffer
DMAAK0 to DMAAK3 .............................................. 52
registers 0 to 2 .......................................................393
DMAC bus cycle state transition ............................ 222
Clocked serial interfaces 0 to 2 ..............................385
DMAIC0 to DMAIC3............................................... 277
CMD0 to CMD3 ......................................................348
DMARQ0 to DMARQ3 ............................................. 46
CMICD0 to CMICD3...............................................277
DRAM access ........................................................ 164
Command register..................................................306
DRAM configuration registers 1, 3, 4, 6 ................. 161
Compare match interrupt in timer trigger mode......431
DRAM connection .................................................. 159
Compare registers D0 to D3...................................348
DRAM controller (EDO DRAM) .............................. 158
CPU address space .................................................71
DRAM controller (SDRAM) .................................... 176
CPU register set .......................................................65
DRST ..................................................................... 215
CS0 to CS7 ..............................................................56
DSA0H to DSA3H .................................................. 207
CSC0, CSC1 ............................................................97
DSA0L to DSA3L ................................................... 208
CSI0 to CSI2 ..........................................................385
DTFR0 to DTFR3................................................... 217
CSIC0 to CSIC2 .....................................................389
DTOC..................................................................... 216
CSIIC0 to CSIIC2 ...................................................277
DWC0, DWC1........................................................ 118
CSIM0 to CSIM2 ....................................................387
CVDD .........................................................................59
CVSS .........................................................................59
[E]
Edge detection function (non-maskable interrupt) . 269
Endian configuration register ................................. 104
[D]
Endian control function .......................................... 104
D0 to D15 .................................................................59
EP .......................................................................... 287
DADC0 to DADC3 ..................................................212
Exception status flag.............................................. 287
Data space .............................................................139
Exception trap........................................................ 288
Data wait control registers 0, 1...............................118
External bus cycles during DMA transfer ............... 254
DBC0 to DBC3 .......................................................211
External interrupt mode register 0.......................... 269
DCHC0 to DCHC3..................................................214
External interrupt mode registers 1 to 4 ................. 282
DDA0H to DDA3H ..................................................209
External memory expansion .................................... 81
DDA0L to DDA3L ...................................................210
External wait function............................................. 123
DDIS.......................................................................215
External/timer trigger interval ................................. 430
Debug trap .............................................................290
Dedicated baud rate generators 0 to 2 ...................377
[F]
Description of pin functions ......................................46
Flash memory ........................................................ 499
Direct mode............................................................298
Flash memory control ............................................ 505
DMA addressing control registers 0 to 3 ................212
Flash memory programming by self-programming 508
DMA bus states ......................................................220
Flash memory programming mode ........................ 506
DMA byte count registers 0 to 3 .............................211
Flash programming mode control register ............. 518
DMA channel control registers 0 to 3 .....................214
FLPMC................................................................... 518
DMA channel priorities ...........................................254
Flyby transfer ......................................................... 242
DMA destination address registers 0H to 3H .........209
Forcible interruption ............................................... 257
DMA destination address registers 0L to 3L...........210
Forcible termination ............................................... 258
DMA disable status register ...................................215
[H]
DMA restart register ...............................................215
DMA source address registers 0H to 3H ................207
HALT mode............................................................ 309
DMA source address registers 0L to 3L .................208
HLDAK..................................................................... 53
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APPENDIX C INDEX
HLDRQ .....................................................................53
MODE0 to MODE2................................................... 59
How to distinguish flash memory and mask ROM
Multiple interrupt servicing control.......................... 292
versions ..................................................................529
[I]
[N]
Next address setting function................................. 255
ID............................................................................281
NMI .......................................................................... 48
IDLE mode..............................................................311
Noise elimination (maskable interrupt) ................... 282
Idle state insertion function .....................................125
Noise elimination (non-maskable interrupt)............ 269
Illegal opcode definition ..........................................288
Non-maskable interrupts ........................................ 265
Image .......................................................................72
Non-maskable interrupt status flag......................... 269
IMR0 to IMR3 .........................................................280
NP .......................................................................... 269
Input clock selection ...............................................298
Number of access clocks ....................................... 102
In-service priority register .......................................281
Internal block diagram ..............................................34
[O]
Interrupt control register .........................................277
OE............................................................................ 55
Interrupt factors ......................................................261
On-chip units............................................................ 35
Interrupt latency time ..............................................294
One-time transfer during single transfer via
Interrupt mask registers 0 to 3 ................................280
DMARQ0 to DMARQ3 signals ............................... 260
Interrupt trigger mode selection ..............................282
On-page/off-page judgment ................................... 151
INTM0.....................................................................269
Operation in A/D trigger mode ............................... 414
INTM1 to INTM4 .....................................................282
Operation in external trigger mode......................... 426
INTP000, INTP001 ...................................................46
Operation in power-save mode .............................. 127
INTP010, INTP011 ...................................................47
Operation in standby mode .................................... 430
INTP020, INTP021 ...................................................48
Operation in timer trigger mode ............................. 417
INTP030, INTP031 ...................................................51
Operation mode and trigger mode ......................... 409
INTP100 to INTP103 ................................................46
Operating mode specification................................... 70
INTP110 to INTP113 ................................................48
Operating modes...................................................... 69
INTP120 to INTP123 ................................................49
Ordering information ................................................ 29
INTP130 to INTP133 ................................................49
OVIC00 to OVIC03................................................. 277
IORD.........................................................................56
[P]
IOWR........................................................................56
ISPR .......................................................................281
P0........................................................................... 456
P00 to P07 ............................................................... 46
[L]
P00IC0, P00IC1 ..................................................... 277
LBE...........................................................................57
P01IC0, P01IC1 ..................................................... 277
LCAS ........................................................................54
P02IC0, P02IC1 ..................................................... 277
LDQM .......................................................................54
P03IC0, P03IC1 ..................................................... 277
List of pin functions...................................................38
P1........................................................................... 459
Lock register ...........................................................303
P10 to P13 ............................................................... 47
LOCKR ...................................................................303
P10IC0 to P10IC3 .................................................. 277
LWR .........................................................................54
P11IC0 to P11IC3 .................................................. 277
P12IC0 to P12IC3 .................................................. 277
[M]
P13IC0 to P13IC3 .................................................. 277
Maskable interrupt status flag.................................281
P2........................................................................... 461
Maskable interrupts ................................................270
P20 to P27 ............................................................... 48
Maximum response time for DMA transfer request 259
P3........................................................................... 465
Memory block function..............................................96
P30 to P37 ............................................................... 49
Memory map.............................................................74
P4........................................................................... 468
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APPENDIX C INDEX
P40 to P45 ...............................................................50
PM3 ....................................................................... 465
P5...........................................................................471
PM4 ....................................................................... 468
P50 to P52 ...............................................................51
PM5 ....................................................................... 471
P7...........................................................................473
PMAH .................................................................... 477
P70 to P77 ...............................................................51
PMAL ..................................................................... 474
Page ROM access .................................................154
PMBD .................................................................... 492
Page ROM configuration register ...........................153
PMC0..................................................................... 457
Page ROM connection ...........................................150
PMC1..................................................................... 460
Page ROM controller..............................................149
PMC2..................................................................... 463
PAH........................................................................476
PMC3..................................................................... 466
PAH0 to PAH9 .........................................................58
PMC4..................................................................... 469
PAL ........................................................................474
PMC5..................................................................... 472
PAL0 to PAL15.........................................................58
PMCAH.................................................................. 477
PBD........................................................................492
PMCAL .................................................................. 475
PBD0 to PBD3 .........................................................52
PMCBD.................................................................. 493
PCD........................................................................489
PMCCD.................................................................. 490
PCD0 to PCD3 .........................................................57
PMCCM ................................................................. 487
PCM .......................................................................486
PMCCS.................................................................. 482
PCM0 to PCM5 ........................................................52
PMCCT .................................................................. 485
PCS........................................................................480
PMCD .................................................................... 489
PCS0 to PCS7 .........................................................56
PMCDL .................................................................. 479
PCT ........................................................................484
PMCM.................................................................... 486
PCT0, PCT1, PCT4 to PCT7....................................54
PMCS .................................................................... 481
PDL ........................................................................478
PMCT..................................................................... 484
PDL0 to PDL15 ........................................................59
PMDL..................................................................... 478
Periods in which interrupts are not acknowledged .295
Port 0 ..................................................................... 456
Peripheral command register .................................299
Port 0 function control register ............................... 458
Peripheral I/O registers ............................................84
Port 0 mode control register................................... 457
Peripheral status register .......................................302
Port 0 mode register .............................................. 456
PFC0 ......................................................................458
Port 1 ..................................................................... 459
PFC2 ......................................................................464
Port 1 mode control register................................... 460
PFC3 ......................................................................467
Port 1 mode register .............................................. 459
PFC4 ......................................................................470
Port 2 ..................................................................... 461
PFCCD...................................................................491
Port 2 function control register ............................... 464
PFCCM ..................................................................488
Port 2 mode control register................................... 463
PFCCS ...................................................................483
Port 2 mode register .............................................. 462
PHCMD ..................................................................299
Port 3 ..................................................................... 465
PHS........................................................................302
Port 3 function control register ............................... 467
Pin configuration ......................................................30
Port 3 mode control register................................... 466
Pin I/O circuits ..........................................................63
Port 3 mode register .............................................. 465
Pin I/O circuits and recommended connection of
Port 4 ..................................................................... 468
unused pins ..............................................................61
Port 4 function control register ............................... 470
Pin status .................................................................45
Port 4 mode control register................................... 469
PLL lockup .............................................................303
Port 4 mode register .............................................. 468
PLL mode...............................................................299
Port 5 ..................................................................... 471
PM0........................................................................456
Port 5 mode control register................................... 472
PM1........................................................................459
Port 5 mode register .............................................. 471
PM2........................................................................462
Port 7 ..................................................................... 473
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APPENDIX C INDEX
Port AH ...................................................................476
Port AH mode control register ................................477
Port AH mode register ............................................477
Port AL ...................................................................474
Port AL mode control register .................................475
Port AL mode register.............................................474
Port BD ...................................................................492
Port BD mode control register ................................493
Port BD mode register ............................................492
Port CD...................................................................489
Port CD function control register.............................491
Port CD mode control register ................................490
Port CD mode register............................................489
Port CM ..................................................................486
Port CM function control register ............................488
Port CM mode control register................................487
Port CM mode register ...........................................486
Port configuration ...................................................440
Port CS ...................................................................480
Port CS function control register.............................483
Port CS mode control register ................................482
Port CS mode register ............................................481
Port CT ...................................................................484
[R]
RAS1, RAS3, RAS4, RAS6...................................... 56
RD............................................................................ 55
Receive buffer registers 0 to 2 ............................... 364
Receive-only serial I/O shift registers 0 to 2........... 392
Recommended use of address space...................... 82
Refresh control function (EDO DRAM)................... 169
Refresh control function (SDRAM) ......................... 195
Refresh control registers 1, 3, 4, 6 ......................... 169
Refresh wait control register .................................. 171
REFRQ .................................................................... 53
Relationship between programmable wait and
external wait........................................................... 123
Repetition frequency .............................................. 438
RESET ..................................................................... 59
Reset functions ...................................................... 494
RFS1, RFS3, RFS4, RFS6 ............................ 169, 195
ROMC .................................................................... 149
RWC ...................................................................... 171
RXB0 to RXB2 ....................................................... 364
RXD0, RXD1 ............................................................ 50
RXD2 ....................................................................... 49
Port CT mode control register.................................485
[S]
Port CT mode register ............................................484
SCK0, SCK1 ............................................................ 50
Port DL ...................................................................478
SCK2........................................................................ 49
Port DL mode control register.................................479
SCR1, SCR3, SCR4, SCR6........................... 161, 179
Port DL mode register ............................................478
SDCAS..................................................................... 57
Power-save control.................................................304
SDCKE..................................................................... 57
Power-save control register ....................................307
SDCLK ..................................................................... 57
Power-save mode register......................................306
SDRAM access ...................................................... 181
PRC ........................................................................153
SDRAM configuration registers 1, 3, 4, 6 ............... 179
PRCMD ..................................................................306
SDRAM connection................................................ 176
Prescaler unit..........................................................296
SDRAM initialization sequence .............................. 202
Priorities of maskable interrupts .............................273
SDRAM refresh control registers 1, 3, 4, 6............. 195
Program register set .................................................66
SDRAS..................................................................... 57
Program space .......................................................139
Securing oscillation stabilization time..................... 317
Programmable wait function ...................................118
SEIC0 to SEIC2 ..................................................... 277
PRS ........................................................................296
Self-programming function ..................................... 509
PSC ........................................................................307
SELFREF................................................................. 53
PSMR .....................................................................306
Self-refresh control function (EDO DRAM)............. 174
PWM buffer registers 0, 1 .......................................435
Self-refresh control function (SDRAM) ................... 200
PWM control registers 0, 1 .....................................433
Serial I/O shift registers 0 to 2................................ 391
PWM unit ................................................................432
SESC0 to SESC3........................................... 284, 330
PWM0.......................................................................46
SI0, SI1 .................................................................... 50
PWM1.......................................................................47
SI2............................................................................ 49
PWMB0, PWMB1 ...................................................435
Single transfer mode .............................................. 223
PWMC0, PWMC1...................................................433
Single-step transfer mode ...................................... 224
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APPENDIX C INDEX
SIO0 to SIO2..........................................................391
TMCD0 to TMCD3 ................................................. 350
SIOE0 to SIOE2 .....................................................392
TMD0 to TMD3 ...................................................... 347
SO0, SO1.................................................................50
TO00........................................................................ 46
SO2 ..........................................................................49
TO01........................................................................ 47
Software exception.................................................285
TO02........................................................................ 48
Software STOP mode ............................................314
TO03........................................................................ 51
SOTB0 to SOTB2...................................................393
Transfer modes...................................................... 223
Specific registers ......................................................93
Transfer object....................................................... 253
SRAM connection...................................................141
Transfer type and transfer object ........................... 253
SRAM, external ROM, external I/O access ............143
Transfer types........................................................ 226
SRAM, external ROM, external I/O interface..........140
Transmit buffer registers 0 to 2 .............................. 365
SRIC0 to SRIC2 .....................................................277
2-cycle transfer ...................................................... 226
STIC0 to STIC2 ......................................................277
TXB0 to TXB2........................................................ 365
Stopping conversion operation...............................430
TXD0, TXD1 ............................................................ 50
Switching between UART and CSI modes .............355
TXD2........................................................................ 49
System configuration example (CSI0 to CSI2) .......398
Types of bus states................................................ 220
System register set...................................................67
System wait control register .....................................93
[U]
UART0 to UART2 .................................................. 356
[T]
UBE ......................................................................... 57
TBC ........................................................................319
UCAS....................................................................... 54
TC0 to TC3...............................................................48
UDQM...................................................................... 54
Terminal count output upon DMA transfer end.......257
UWR ........................................................................ 54
TI000 ........................................................................46
TI010 ........................................................................47
[V]
TI020 ........................................................................48
Valid edge select registers C0 to C3.............. 284, 330
TI030 ........................................................................51
VDD ........................................................................... 59
Time base counter..................................................319
VPP ........................................................................... 60
Timer C ..................................................................320
VSS ........................................................................... 59
Timer C operation...................................................331
VSWC ...................................................................... 93
Timer D ..................................................................346
[W]
Timer D operation...................................................352
Timer mode control registers C00 to C30...............326
WAIT........................................................................ 52
Timer mode control registers C01 to C31...............328
Wait function .......................................................... 118
Timer mode control registers D0 to D3...................350
WE ........................................................................... 55
Timers C0 to C3 .....................................................322
Wrap-around of CPU address space ....................... 73
Timers D0 to D3 .....................................................347
Writing with flash programmer ............................... 499
Times related to DMA transfer ...............................259
[X]
TMC0 to TMC3.......................................................322
TMCC00 to TMCC30..............................................326
X1, X2 ...................................................................... 59
TMCC01 to TMCC31..............................................328
User’s Manual U14359EJ3V0UM
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554
User’s Manual U14359EJ3V0UM
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