NEC UPD72852AGB-8EU

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD72852A
IEEE1394a-2000 COMPLIANT 400 Mbps TWO-PORT PHY LSI
The µPD72852A is a two-port physical layer LSI that complies with the IEEE1394a-2000 specifications.
FEATURES
• The two-port physical layer LSI complies with IEEE1394a-2000
• Fully interoperable with IEEE1394 std 1394 Link (FireWireTM, i.LINKTM)
• Meets IntelTM Mobile Power Guideline 2000
• Full IEEE1394a-2000 support includes: Suspend/Resume, connection debounce, arbitrated short bus reset, multi-speed
concatenation, arbitration acceleration, fly-by concatenation
• Suspend Debounce timer for ESD
• “BIAS Detected” signal output
• Double speed signal filter for BIAS Ringing
• Small package: 64-pin plastic LQFP
• Super low power : 68 mA (Operating mode)
: 115 µA (Suspend mode)
• Data rate: 400/200/100 Mbps
• Supports PHY pinging and remote PHY access packets
• 3.3 V single power supply (if power not supplied via node: 3.0 V single power supply)
• 24.576 MHz crystal clock generation, 393.216 MHz PLL multiplying frequency
• 64-bit flexible register incorporated in PHY register
• Electrically isolated Link interface
• Supports LPS/Link-on as part of PHY/Link interface
• External filter capacitors for PLL not required
• Extended Resume signaling for compatibility with legacy DV devices
• System power management by signaling of node power class information
• Cable power monitor (CPS) is equipped
ORDERING INFORMATION
Part number
Package
µPD72852AGB-8EU
64-pin plastic LQFP (10 × 10)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No.
Date Published
Printed in Japan
S16725EJ2V0DS00 (2nd edition)
March 2004 NS CP (K)
The mark
shows major revised points.
2003
µPD72852A
BLOCK DIAGRAM
TpA0p
TpA0n
CMC
PC0
PC1
PC2
SUS/RES
LREQ
LPS
DIRECT
SCLK
LKON
CTL0
CTL1
D0
D1
D2
D3
D4
D5
D6
D7
Cable
Port0
Arbitration
and Control
State Machine
Logic
Link
Interface
I/O
Cable
Port1
Receive Data
Decoder and
Retimer
Transmit Data
Encoder
RESETB
2
TpA1p
TpA1n
TpB1p
TpB1n
BDB
CPS
TpB0p
TpB0n
Cable
Power
Status
Data Sheet S16725EJ2V0DS
Voltage
and
Current
Generator
Crystal
Oscillator
PLL
System
and
Transmit
Clock
Generator
TpBias0
TpBias1
RI1
XI
XO
µPD72852A
PIN CONFIGURATION (Top View)
• µPD72852AGB-8EU
DGND
LREQ
FNSel
SPD/BDB
DVDD
LPS
LKON
DGND
DVDD
RESETB
AVDD
AGND
AGND
IC(AL)
DIRECT
AGND
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
64-pin plastic LQFP (10 × 10)
D1
9
40
AVDD
DVDD
10
39
TpA0p
D2
11
38
TpA0n
D3
12
37
TpB0p
DGND
13
36
TpB0n
D4
14
35
AGND
D5
15
34
RI1
DGND
16
33
AGND
32
TpBias0
CPS
41
31
8
AVDD
D0
30
AGND
CMC
42
29
7
IC(AL)
DGND
28
TpB1n
PC2
43
27
6
PC1
CTL1
26
TpB1p
PC0
44
25
5
AVDD
CTL0
24
TpA1n
AGND
45
23
4
XI
DVDD
22
TpA1p
XO
46
21
3
DGND
IC(DL)
20
AVDD
DVDD
47
19
2
SUS/RES
SCLK
18
TpBias1
D7
48
17
1
D6
DGND
Data Sheet S16725EJ2V0DS
3
µPD72852A
PIN NAME
AGND
: Analog GND
AVDD
: Analog Power
CMC
: Configuration Manager Capable
CPS
: Cable Power Status
CTL0
: Link Interface Control (bit 0)
CTL1
: Link Interface Control (bit 1)
D0-D7
: Data Input/Output
DGND
: Digital GND
DIRECT
: PHY/Link Isolation Barrier Control Input
DVDD
: Digital VDD
FNSel
: Function Select
IC(AL)
: Internally Connected (Low Clamped)
IC(DL)
: Internally Connected (Low Clamped)
LKON
: Link-on Signal Output
LPS
: Link Power Status Input
LREQ
: Link Request Input
PC0-PC2
: Power Class Set Input
RESETB
: Power-on Reset Input
RI1
: Reference Power Set, Connect Resistor 1
SCLK
: Link Control Output Clock
SPD/BDB
: Speed Select input / BIAS Detected output
SUS/RES
: Suspend/Resume Function Select
TpA0n
: Port 0 Twisted Pair Cable A Negative Phase I/O
TpA0p
: Port 0 Twisted Pair Cable A Positive Phase I/O
TpA1n
: Port 1 Twisted Pair Cable A Negative Phase I/O
TpA1p
: Port 1 Twisted Pair Cable A Positive Phase I/O
TpB0n
: Port 0 Twisted Pair Cable B Negative Phase I/O
TpB0p
: Port 0 Twisted Pair Cable B Positive Phase I/O
TpB1n
: Port 1 Twisted Pair Cable B Negative Phase I/O
TpB1p
: Port 1 Twisted Pair Cable B Positive Phase I/O
TpBias0
: Port 0 Twisted Pair Output
TpBias1
: Port 1 Twisted Pair Output
XI
: Crystal Oscillator Connection XI
XO
: Crystal Oscillator Connection XO
4
Data Sheet S16725EJ2V0DS
µPD72852A
CONTENTS
1. PIN
1.1
1.2
1.3
1.4
1.5
1.6
FUNCTIONS..................................................................................................................................... 7
Cable Interface Pins ........................................................................................................................ 7
Link Interface Pins .......................................................................................................................... 7
Control Pins ..................................................................................................................................... 8
IC ....................................................................................................................................................... 8
Power Supply Pins .......................................................................................................................... 8
Other Pins ........................................................................................................................................ 9
2. PHY REGISTERS .................................................................................................................................. 10
2.1 Complete Structure for PHY Registers ....................................................................................... 10
2.2 Port Status Page (Page 000) ........................................................................................................ 13
2.3 Vendor ID Page (Page 001)........................................................................................................... 14
2.4 Vendor Dependent Page (Page 111 : Port_select 0000)............................................................ 14
2.5 Vendor Dependent Page (Page 111 : Port_select 0001)............................................................ 15
3. INTERNAL FUNCTION.......................................................................................................................... 16
3.1 Link Interface ................................................................................................................................. 16
3.1.1 Connection Method ............................................................................................................................... 16
3.1.2 LPS (Link Power Status) ....................................................................................................................... 16
3.1.3 LREQ, CTL0, CTL1 and D0-D7 Pins..................................................................................................... 16
3.1.4 SCLK..................................................................................................................................................... 16
3.1.5 LKON .................................................................................................................................................... 17
3.1.6 DIRECT................................................................................................................................................. 17
3.1.7 Isolation Barrier ..................................................................................................................................... 17
3.2 Cable Interface............................................................................................................................... 19
3.2.1 Connections .......................................................................................................................................... 19
3.2.2 Cable Interface Circuit........................................................................................................................... 20
3.2.3 Unused Ports ........................................................................................................................................ 20
3.2.4 CPS....................................................................................................................................................... 20
3.3 Suspend/Resume .......................................................................................................................... 20
3.3.1 Suspend/Resume On Mode (SUS/RES = “H”)...................................................................................... 20
3.3.2 Suspend/Resume Off Mode (SUS/RES = “L”) ...................................................................................... 20
3.4 PLL and Crystal Oscillation Circuit ............................................................................................. 21
3.4.1 Crystal Oscillation Circuit ...................................................................................................................... 21
3.4.2 PLL........................................................................................................................................................ 21
3.5
3.6
3.7
3.8
CMC ................................................................................................................................................ 21
PC0-PC2 ......................................................................................................................................... 21
RESETB .......................................................................................................................................... 21
RI1 ................................................................................................................................................... 21
4. PHY/LINK INTERFACE ......................................................................................................................... 22
4.1 Initialization of Link Power Status (LPS) and PHY/Link Interface............................................ 22
4.2 Link-on Indication ......................................................................................................................... 23
4.3 PHY/Link Interface Operation (CTL0, CTL1, LREQ, D0-D7) ...................................................... 24
4.3.1 CTL0, CTL1 .......................................................................................................................................... 24
4.3.2 LREQ .................................................................................................................................................... 24
Data Sheet S16725EJ2V0DS
5
µPD72852A
4.3.3 SCLK Timing ......................................................................................................................................... 28
4.4
4.5
4.6
4.7
4.8
Acceleration Control ..................................................................................................................... 29
Transmit Status ............................................................................................................................. 30
Transmit ......................................................................................................................................... 31
Cancel............................................................................................................................................. 32
Receive ........................................................................................................................................... 33
5. CABLE PHY PACKET ........................................................................................................................... 34
5.1 Self_ID Packet................................................................................................................................ 34
5.2 Link-on Packet............................................................................................................................... 35
5.3 PHY Configuration Packet............................................................................................................ 35
5.4 Extended PHY Packet ................................................................................................................... 35
5.4.1 Ping Packet ........................................................................................................................................... 36
5.4.2 Remote Access Packet ......................................................................................................................... 36
5.4.3 Remote Reply Packet............................................................................................................................ 37
5.4.4 Remote Command Packet .................................................................................................................... 37
5.4.5 Remote Confirmation Packet ................................................................................................................ 38
5.4.6 Resume Packet..................................................................................................................................... 38
6. ELECTRICAL SPECIFICATIONS ......................................................................................................... 39
7. APPLICATION CIRCUIT EXAMPLE ..................................................................................................... 44
8. PACKAGE DRAWING........................................................................................................................... 45
9. RECOMMENDED SOLDERING CONDITIONS .................................................................................. 46
6
Data Sheet S16725EJ2V0DS
µPD72852A
1. PIN FUNCTIONS
1.1 Cable Interface Pins
Name
Pin No.
I/O
Function
TpA0p
39
I/O
Port 0 twisted pair cable A positive phase I/O
TpA0n
38
I/O
Port 0 twisted pair cable A negative phase I/O
TpB0p
37
I/O
Port 0 twisted pair cable B positive phase I/O
TpB0n
36
I/O
Port 0 twisted pair cable B negative phase I/O
TpA1p
46
I/O
Port 1 twisted pair cable A positive phase I/O
TpA1n
45
I/O
Port 1 twisted pair cable A negative phase I/O
TpB1p
44
I/O
Port 1 twisted pair cable B positive phase I/O
TpB1n
43
I/O
Port 1 twisted pair cable B negative phase I/O
SUS/RES
19
I
Suspend/Resume function select
1: Suspend/Resume on (IEEE1394a-2000 compliant)
0: Suspend/Resume off (P1394a draft 1.3 compliant)
CPS
32
I
Cable power status
Connect to the cable through a 390 kΩ resistor and to GND through a 100 kΩ resistor.
0: Cable power fail
1: Cable power on
1.2 Link Interface Pins
Name
Pin No.
I/O
Function
D0
8
I/O
Data input/output (bit 0)
D1
9
I/O
Data input/output (bit 1)
D2
11
I/O
Data input/output (bit 2)
D3
12
I/O
Data input/output (bit 3)
D4
14
I/O
Data input/output (bit 4)
D5
15
I/O
Data input/output (bit 5)
D6
17
I/O
Data input/output (bit 6)
D7
18
I/O
Data input/output (bit 7)
CTL0
5
I/O
Link interface control (bit 0)
CTL1
6
I/O
LREQ
63
I
Link request input
SCLK
2
O
Link control output clock
Link interface control (bit 1)
LPS 1: 49.152 MHz output
LPS 0: Clamp to 0 (The clock signal will be output within 25 µsec after change to “0”)
LPS
59
I
Link power status input
0: Link power off
1: Link power on (PHY/Link direct connection)
LKON
58
O
Link-on signal output
Link-on signal is 6.144 MHz clock output.
Please refer to 4.2 Link-on Indication.
DIRECT
50
I
PHY/Link isolation barrier control input
0: Isolation barrier
1: PHY/Link direct connection
Data Sheet S16725EJ2V0DS
7
µPD72852A
1.3 Control Pins
Name
Pin No.
I/O
Function
PC0
26
I
Power class set input
PC1
27
I
This pin status will be loaded to Pwr_class bit which allocated to PHY register 4H.
PC2
28
I
IEEE1394a-2000 chapter [4.3.4.1]
CMC
30
I
Configuration manager capable setting
This pin status will be loaded to Contender bit which allocated to PHY register 4H.
0: Non contender
1: Contender
RESETB
55
I
Power-on reset input
Connect to GND through a 0.1 µF capacitor.
0: Reset
1: Normal
FNSel
62
I
Function Select
0: #61 acts as SPD
1: #61 acts as BDB
SPD
61
I
Speed select ( When FNSel set to 0 ; µPD72852A compliant)
0: MAX. S200
1: MAX. S400
BDB
61
O
BIAS Detected (Logical Inverse)
0: BIAS is detected after suspend debounce timer.
1: BIAS is not detected.
1.4 IC
Name
Pin No.
I/O
IC(AL)
29, 51
-
IC(DL)
3
-
Function
Internally Connected (Low Clamped)
Connect to GND.
Internally Connected (Low Clamped)
Connect to GND.
1.5 Power Supply Pins
Name
Pin No.
I/O
Function
AVDD
25, 31, 40, 47, 54
-
Analog power
AGND
24, 33, 35, 42, 49, 52, 53
-
Analog GND
DVDD
4, 10, 20, 56, 60
-
Digital VDD
DGND
1, 7, 13, 16, 21, 57, 64
-
Digital GND
8
Data Sheet S16725EJ2V0DS
µPD72852A
1.6 Other Pins
Name
Pin No.
I/O
Function
TpBias0
41
O
Port 0 twisted pair output
TpBias1
48
O
Port 1 twisted pair output
RI1
34
-
Resistor connection pin1 for reference current generator
XI
23
-
Crystal oscillator connection XI
XO
22
-
Crystal oscillator connection XO
Connect to GND through a 9.1 kΩ resistor.
Data Sheet S16725EJ2V0DS
9
µPD72852A
2. PHY REGISTERS
2.1 Complete Structure for PHY Registers
Figure 2-1. Complete Structure of PHY Registers
0
1
2
0000
0001
3
4
5
Physical_ID
RHB
IBR
6
7
R
PS
Gap_count
0010
Extended (7)
Reserved
Total_ports
0011
Max_speed
Reserved
Delay
Jitter
0100
Link_active
Contender
0101
Watchdog
ISBR
Loop
Pwr_class
Pwr_fail
0110
Timeout
Port_event
Enab_accel
Enab_multi
Reserved
0111
Page_select
Reserved
1000
Register0 (page_select)
1001
Register1 (page_select)
1010
Register2 (page_select)
1011
Register3 (page_select)
1100
Register4 (page_select)
1101
Register5 (page_select)
1110
Register6 (page_select)
1111
Register7 (page_select)
Port_select
Table 2-1. Bit Field Description (1/3)
Size
R/W
Reset value
Physical_ID
Field
6
R
000000
R
1
R
0
Description
Physical_ID value selected from Self_ID period.
If this bit is 1, the node is root.
1: Root
0: Not root
PS
1
R
Cable power status.
1: Cable power on
0: Cable power off
RHB
1
R/W
0
Root Hold -off bit. If 1, becomes root at the bus reset.
IBR
1
R/W
0
Initiate bus reset.
Setting to 1 begins a long bus reset.
Long bus reset signal duration: 166 µsec.
Returns to 0 at the beginning of bus reset.
Gap_count
6
R/W
111111
Gap count value.
It is updated by the changes of transmitting and receiving the PHY
configuration packet Tx/Rx.
The value is maintained after first bus reset.
After the second bus reset it returns to reset value.
Extended
10
3
R
111
Shows the extended register map.
Data Sheet S16725EJ2V0DS
µPD72852A
Table 2-1. Bit Field Description (2/3)
Field
Total_ports
Size
R/W
Reset value
4
R
0010
Description
Supported port number.
0010: 2 ports
Max_speed
3
R
See
Description
Indicate the maximum speed that this node supports.
Set variable by SPD pin (61 pin).
When SPD = “0” then 001: 98.304 and 196.608 Mbps.
When SPD = “1” then 010: 98.304, 196.608 and 393.216 Mbps.
Delay
4
R
0000
Link_active
1
R/W
1
Indicate worst case repeating delay time. 144 + (Delay × 20) = 144 nsec
Link active.
1: Enable
0: Disable
The logical AND status of this bit and LPS pin.
State will be referred to “L bit” of Self-ID Packet#0.
Contender
1
R/W
See
Description
Contender.
“1” indicate this node support bus manager function. This bit will be referred
to “C bit” of Self-ID Packet#0.
The reset data is depending on CMC pin setting.
CMC pin condition
1: Pull up (Contender)
0: Pull down (Non Contender)
Jitter
3
R
Pwr_class
3
R/W
010
The difference of repeating time (Max.-Min.). (2+1) × 20 = 60 nsec
See
Power class.
Description
Please refer to IEEE1394a-2000 [4.3.4.1].
This bit will be referred to Pwr field of Self-ID Packet#0.
The reset data will be determined by PC0-PC2 Pin status.
Watchdog
1
R/W
0
Watchdog Enable.
This bit serves two purposes.
When set to 1, if any one port does resume, the Port_event bit becomes 1.
This function has no effect when SUS/RES (19 pin) = “0”.
To determine whether or not an interrupt condition shall be indicated to the
Link. On condition of LPS = 0 and Watchdog = 0, LKON as interrupt of Loop,
Pwr_fail, Timeout is not output. This function has effect both when SUS/RES
(19 pin) = “1” or “0”.
ISBR
1
R/W
0
Initiate short (arbitrated) bus reset.
Setting to 1 acquires the bus and begins short bus reset.
Short bus reset signal output : 1.3 µsec
Returns to 0 at the beginning of the bus reset.
Loop
1
R/W
0
Loop detection output.
1: Detection
Writing 1 to this bit clears it to 0.
Writing 0 has no effect.
Pwr_fail
1
R/W
1
Power cable disconnect detect.
It becomes 1 when there is a change from 1 to 0 in the CPS bit.
Writing 1 to this bit clears it to 0.
Writing 0 has no effect.
Data Sheet S16725EJ2V0DS
11
µPD72852A
Table 2-1. Bit Field Description (3/3)
Field
Timeout
Size
R/W
Reset value
1
R/W
0
Description
Arbitration state machine time-out.
Writing 1 to this bit clears it to 0.
Writing 0 has no effect.
Port_event
1
R/W
0
Set to 1 when the Int_enable bit in the register map of each port is 1 and there
is a change in the ports connected, Bias, Disabled and Fault bits.
Set to 1 when the Watchdog bit is 1 and any one port does resume.
Writing 1 to this bit clears it to 0.
Writing 0 has no effect.
This bit is not settable when SUS/RES (19 pin) = “0”.
Enab_accel
1
R/W
0
Enables arbitration acceleration.
Ack-acceleration and Fly-by arbitration are enabled.
1: Enabled
0: Disabled
If this bit changes while the bus request is pending, the operation is not
guaranteed.
Enab_multi
1
R/W
0
Enable multi-speed packet concatenation.
Setting this bit to 1 follows multi-speed transmission.
When this bit is set to 0,the packet will be transmitted with the same speed as
the first packet.
Page_select
3
R/W
000
Select page address between 1000 to 1111.
000: Port Status Page
001: Vendor ID Page
111: Vendor Dependent Page
Others: Unused
Port_select
4
R/W
0000
Port Selection.
Selecting 000 (Port Status Page) with the Page_select selects the port.
Selecting 111 (Vendor Dependent Page) with the Page_select have to select
the Port 1.
0000: Port 0
0001: Port 1
Others: Unused
Reserved
12
-
R
000…
Reserved. Read as 0.
Data Sheet S16725EJ2V0DS
µPD72852A
2.2 Port Status Page (Page 000)
Figure 2-2. Port Status Page
0
1
1000
2
AStat
1001
3
BStat
Negotiated_speed
Int_enable
4
5
6
7
Child
Connected
Bias
Disabled
Fault
1010
Reserved
1011
Reserved
1100
Reserved
1101
Reserved
1110
Reserved
1111
Reserved
Reserved
Table 2-2. Bit Field Description
Field
AStat
Size
R/W
Reset value
2
R
XX
Description
A port status value.
00: invalid, 10: “0”
01: “1”, 11: “Z”
BStat
2
R
XX
B port status value.
00: invalid, 10: “0”
01: “1”, 11: “Z”
Child
1
R
Child node status value.
1: Connected to child node
0: Connected to parent node
Connected
1
R
0
Connection status value.
1: Connected
0: Disconnected
Bias
1
R
Bias voltage status value.
1: Bias voltage
0: No bias voltage
Disabled
1
R/W
Negotiated_
3
R
See
The reset value is set to 0: Enabled.
Description
Shows the maximum data transfer rate of the node connected to this port.
speed
000: 100 Mbps
001: 200 Mbps
010: 400 Mbps
Int_enable
1
R/W
0
When set to 1, the Port_event is set to 1 if any of this port's Connected, Bias,
Disabled or Fault bits change state.
This bit has no effect when SUS/RES (19 pin) = “0”.
Fault
1
R/W
0
Set to 1 if an error occurs during Suspend/Resume.
Writing 1 to this bit clears it to 0.
Writing 0 has no effect.
This bit has no effect when SUS/RES (19 pin) = “0”
Reserved
-
R
000…
Reserved. Read as 0.
Data Sheet S16725EJ2V0DS
13
µPD72852A
2.3 Vendor ID Page (Page 001)
Figure 2-3. Vendor ID Page
0
1
2
3
4
1000
Compliance_level
1001
Reserved
5
6
7
6
7
1010
1011
Vendor_ID
1100
1101
1110
Product_ID
1111
Table 2-3. Bit Field Description
Field
Size
R/W
Reset value
Compliance_level
8
R
00000001
According to IEEE1394a-2000.
Vendor_ID
24
R
00004CH
Company ID Code value, NEC IEEE OUI.
Product_ID
24
R
-
R
Reserved
Description
Product code.
000…
Reserved. Read as 0.
2.4 Vendor Dependent Page (Page 111 : Port_select 0000)
Figure 2-4. Vendor Dependent Page
0
1
2
1000
1001
3
4
5
Reserved
Reserved
Long
Reserved
Debounce
1010
1011
Reserved
1100
W_SPD_
DIS
1101
1110
Rerserved
1111
14
Data Sheet S16725EJ2V0DS
µPD72852A
Table 2-4. Bit Field Description
Field
Size
R/W
Reset value
Long Debounce
2
R/W
00b
W_SPD_DIS
1
R/W
0
Description
00: suspend debounce timer sets to 420 ns
11: suspend debounce timer sets to 1000 ns.
0: NOT Receive Double speed signal
Only First speed signal will be repeated for next port and packet will be
decoded by highest speed within received.
1: Receive Double speed signal (IEEE1394a-2000 complient).
Second speed signal will be applied for repeating /decoding.
2.5 Vendor Dependent Page (Page 111 : Port_select 0001)
Figure 2-5. Vendor Dependent Page contd.
0
1
2
3
4
5
6
7
1000
1001
1010
1011
Reg_array
1100
1101
1110
1111
Table 2-5. Bit Field Description
Field
Reg_array
Size
R/W
Reset value
64
R/W
0
Description
This register array is possible R/W.
Data Sheet S16725EJ2V0DS
15
µPD72852A
3. INTERNAL FUNCTION
3.1 Link Interface
3.1.1 Connection Method
Figure 3-1. PHY/Link Connection Method
D0-D7
CTL0,CTL1
LREQ
SCLK
PHY
LPS
Link
µPD72852A
LKON
DIRECT
Note
Note Clamping to VDD provides direct connection to Link.
Clamping to GND connects through isolation barrier to Link.
The isolation barrier connection circuit is described in 3.1.7 Isolation Barrier.
3.1.2 LPS (Link Power Status)
LPS is a function to monitor the On/Off status of the Link power supply. After 1.2 µsec or more, LPS is Low, the
PHY/Link is reset and D and CTL are output Low (when the isolation barrier is Hi-Z). After 2.5 µsec or more, LPS is
Low, moreover, the PHY stops the supply of SCLK and SCLK outputs Low (when the isolation barrier is Hi-Z).
3.1.3 LREQ, CTL0, CTL1 and D0-D7 Pins
LREQ
: Indicates that a request is received from Link.
CTL0, CTL1 : Bi-directional pin which controls the functions between the PHY/Link interface.
D0-D7
: Bi-directional pin which controls the data Transfer/Receive status signal, and the speed code
Transfer/Receive status signal.
3.1.4 SCLK
49.152 MHz clock supplied by PHY for the PHY/Link interface synchronization.
16
Data Sheet S16725EJ2V0DS
µPD72852A
3.1.5 LKON
When the Link power is off, it outputs a clock of 6.144 MHz. LKON outputs under the following conditions: LPS is
Low and the internal PHY register of the Link_active bit is 0.
• Link-on packet is received.
• Any bit of Loop, Pwr_fail, Timeout or Port_event is the PHY internal register becomes 1, and moreover either LPS
or Link_active bit is 0.
When LPS is asserted, LKON returns to Low.
3.1.6 DIRECT
Set DIRECT to Low for using the isolation barrier.
3.1.7 Isolation Barrier
The IEEE1394 cable holds signals for Data/Strobe in addition to power and ground.
When the ground potential is different between connecting devices, the DC and AC current flows through the
ground line in the cable and there is a possibility of malfunction due to ground difference between the two PHY.
The µPD72852A uses the isolation barrier to couple the AC between the PHY/Link interface to overcome the
ground difference problem. Connecting the DIRECT pin to Low enables the digital differential circuit of the
µPD72852A. The differential circuit propagates only the change in the signal; the interface will be driven only during
transitions High → Low or Low → High. The interface will assume the high impedance state when there is no signal
change. The µPD72852A uses Schmitt trigger input buffers for D, CTL, LREQ and LPS pins to prevent noise when the
bus assumes a high impedance state.
The digital differential circuit and the Schmitt trigger input buffers are needed on the Link layer controller LSI to
implement the isolation barrier.
Figure 3-2. Waveforms of the Isolation Barrier
Isolation Barrier not used
0
1
1
0
0
0
1
0
0
Using Isolation Barrier
(Digital differential circuit)
0
1
Z
0
Z
Z
1
0
Z
Data Sheet S16725EJ2V0DS
17
µPD72852A
Figure 3-3. Isolation Barrier Circuits
(a)
Link
CTL0, CTL1, D0-Dn Isolation Barrier Circuit
Required when LinkVDD is 5 V
DVDD
µPD72852A
LinkVDD
5.6 kΩ
5 kΩ
100 Ω
0.001 µF
0.001 µF
4.7 kΩ
300 Ω
5 kΩ
LinkGND
(b)
LinkGND
GND
Link-on Isolation Barrier Circuit
LinkVDD
Link
µPD72852A
5 kΩ
100 Ω
0.01 µF
1.6 kΩ
LinkGND
(c)
LPS Isolation Barrier Circuit
DVDD
Link
5 kΩ
µPD72852A
100 Ω
0.033 µF
1.6 kΩ
GND
(d)
LREQ Isolation Barrier Circuit
Required when LinkVDD is 5 V
Link
LinkVDD
DVDD
0.001 µF
5 kΩ
LinkGND
(e)
Link
µPD72852A
5.6 kΩ
5 kΩ
100 Ω
0.001 µF
4.7 kΩ
300 Ω
LinkGND
GND
SCLK Isolation Barrier Circuit
LinkVDD
5 kΩ
DVDD
µPD72852A
5 kΩ
0.001 µF
5 kΩ
LinkGND
5 kΩ
GND
The Operating range of the power supply voltage is between 3.0 V and 3.45 V.
Please refer to IEEE1394a-2000 [5A.8.4].
18
Data Sheet S16725EJ2V0DS
µPD72852A
3.2 Cable Interface
3.2.1 Connections
Figure 3-4. Cable Interface
Connection Detection Current
Connection Detection Comparator
Common Mode Speed Current Driver
TpBias
+
–
TpBp
TpAp
Driver
Receiver
+
–
7 kΩ
56 Ω
56 Ω
7 kΩ
7 kΩ
TpAn
56 Ω
56 Ω
7 kΩ
TpBn
1 µF
5.1 kΩ
270 pF
Arbitration Comparators
+
–
+
–
Driver
Receiver
+
–
Arbitration Comparators
+
–
+
–
Common Mode Comparators
+
–
TpBias Detection Comparator
+
–
+
–
Connection Detection Current
Connection Detection Comparator
Common Mode Speed Current Driver
TpBias
TpBp
Driver
Receiver
+
–
TpAp
7 kΩ
56 Ω
56 Ω
7 kΩ
7 kΩ
TpBn
56 Ω
56 Ω
7 kΩ
TpAn
270 pF
+
–
5.1 kΩ
Arbitration Comparators
+
–
1 µF
Driver
Receiver
+
–
Arbitration Comparators
+
–
+
–
+
–
TpBias Detection Comparator
+
–
+
–
Common Mode Comparators
+
–
Data Sheet S16725EJ2V0DS
19
µPD72852A
3.2.2 Cable Interface Circuit
Each port is configured with two twisted-pairs of TpA and TpB.
TpA and TpB are used to monitor the state of the Transmit/Receive line, control signals, data and cables.
During transmission to the IEEE1394 bus, the Data/Strobe signal received from the Link layer controller is encoded,
converted from parallel to serial and transmitted.
While receiving from the IEEE1394 bus, the Data/Strobe signal from TpA, TpB is converted from serial to parallel
after synchronization by SCLK, then transmitted to the Link layer controller in 2/4/8 bits according to the data rate of
100/200/400 Mbps.
The bus arbitration for TpA and TpB and the state of the line are monitored by the built-in comparator. The state of
the IEEE1394 bus is transmitted to the state machine in the LSI.
3.2.3 Unused Ports
TpAp, TpAn : Not connected
TpBp, TpBn : GND
TpBias
: Not connected
3.2.4 CPS
Connect an external resistor of 390 kΩ between the CPS pin and the power cable, and an external resistor of 100
kΩ between the CPS pin and GND to monitor the power of the power cable.
If the cable power falls under 7.5 V there is an indication to the Link layer controller that the power has failed.
3.3 Suspend/Resume
3.3.1 Suspend/Resume On Mode (SUS/RES = “H”)
There are two ways of transition from the active status to the suspended status.
One is when the receipt of a remote command packet that sets the initiate suspend command. After that, the PHY
transmits a remote confirmation packet with the ok bit set, subsequently signals TX_SUSPEND to the connected peer
PHY with the port which specified by the port field in the remote command packet, and then the PHY port transitions to
the suspended state.
The other is when the receipt of a RX_SUSPEND or RX_DISABLE_NOTIFY signal. When the port observes
RX_SUSPEND, it transmits TX_SUSPEND to the active ports.
The TX_SUSPEND transmitted propagates until it reaches a leaf node. The PHY port transitions to the suspended
state. The propagation of the suspended domain may be blocked by a PHY compliant with IEEE1394a-2000, a
disabled or a suspended port.
Any one of a number of reasons may cause a suspended port to attempt to resume normal operations:
• Bias is detected and there is no fault condition;
• A resume packet is received or transmitted by the PHY;
• A remote command packet that sets the resume port command is received; or
• Either port of a node without active ports detects bias.
3.3.2 Suspend/Resume Off Mode (SUS/RES = “L”)
• Remote command packet is ignored.
• Resume packet is ignored.
• Disabled, Int_enable and resume_int bits in PHY register are ignored.
• Responses to Remote access packet.
• Detects the connection of the port in TpBias.
• Output the 1.85 V voltage of the port in TpBias.
20
Data Sheet S16725EJ2V0DS
µPD72852A
3.4 PLL and Crystal Oscillation Circuit
3.4.1 Crystal Oscillation Circuit
To supply the clock of 24.576 MHz ± 100 ppm, use an external capacitor of 10 pF and a crystal of 50 ppm.
3.4.2 PLL
The crystal oscillator multiplies the 24.576 MHz frequency by 16 (393.216 MHz).
3.5 CMC
CMC shows the bus manager function which corresponds to the c bit of the Self_ID packet and the Contender bit in
the PHY register when the input is High.
The value of CMC can be changed with software through the Link layer; this pin sets the initial value during Poweron Reset. Use a pull-up or pull-down resistor of 10 kΩ, based on the device’s specification.
3.6 PC0-PC2
The PC0-PC2 pin corresponds to the power field of the Self_ID packet and Pwr_class in the PHY register. Refer to
Section 4.3.4.1 of the IEEE1394a-2000 specification for information regarding the Pwr_class. The value of Pwr can be
changed with software through the Link layer controller; this pin sets the initial value during Power-on Reset. Use a
pull-up or pull-down resistor of 10 kΩ based on the application.
3.7 RESETB
Connect an external capacitor of 0.1 µF between the RESETB pin and GND. If the voltage drops below 0 V, a reset
pulse is generated. All of the circuits are initialized, including the contents of the PHY register.
3.8 RI1
Connect an external resistor of 9.1 kΩ between the RI1 pin and GND to limit the LSI’s current.
Data Sheet S16725EJ2V0DS
21
µPD72852A
4. PHY/LINK INTERFACE
4.1 Initialization of Link Power Status (LPS) and PHY/Link Interface
The LPS pin monitors the On/Off status of the Link power state. This pin is used during the PHY/Link interface
Enable/Disable (initialization).
Reset
When the LPS input pin is Low for TLPS_RESET:
• CTL0, CTL1 and D0-D7 output Low (When the isolation barrier is Hi-Z).
• SCLK continuously supplies the clock signal to the Link.
Disable
When the LPS input pin is Low for TLPS_DISABLE:
• CTL0, CTL1, D0-D7 continue to output Low as TLPS_RESET has already occurred (When the isolation barrier is Hi-Z).
• SCLK to Link stops and it outputs Low (When the isolation barrier is Hi-Z).
Table 4-1. LPS Timing Parameters
Parameter
Symbol
MIN.
MAX.
Unit
1.00
µs
LPS = Low propagation delay (with isolation barrier)
tLPSL
0.09
LPS = High propagation delay (with isolation barrier)
tLPSH
0.09
1.00
µs
Reset active
tLPS_RESET
1.2
2.75
µs
Disable active
tLPS_DISABLE
25
30
µs
Setup time when using isolation barrier
tRESTORE
15
20
µs
Figure 4-1. LPS Waveform when Connected to Isolation Barrier
tLPSH
22
tLPSL
Data Sheet S16725EJ2V0DS
µPD72852A
Figure 4-2. PHY/Link Interface Reset and Disable
(a)
Reset
D, CTL, LREQ
LPS
LPS
(with isolation barrier)
SCLK
tLPS_RESET
tRESTORE
(b)
Disable
D, CTL, LREQ
LPS
LPS
(with isolation barrier)
SCLK
tLPS_DISABLE
tRESTORE
4.2 Link-on Indication
When the power supply of Link is off (LPS is Low and the internal PHY register Link_active bit is 0), the pin LKON
outputs a clock of 6.144 MHz according to the following conditions:
• Link-on packet is received.
• When any bit of the µPD72852A PHY register’s loop, Pwr_fail, Timeout or Port_event becomes 1, and either LPS
or the Link_active bit is 0.
Table 4-2. Link-on Timing
Parameter
MIN.
MAX.
Unit
Frequency
4
8
MHz
Duty Cycle
40
60
%
500
ns
Propagation delay before the Link becomes active (LPS is
asserted and the Link_active bit in the PHY register is 1).
• If LPS or the Link_active bit is 0, the Link is considered inactive.
When the Link is inactive and any of Loop, Pwr_fail, Timeout, Port_event becomes 1, then Link-on is asserted
High.
• When the Link is active (both LPS and Link_active become 1) and Loop, Pwr_fail, Timeout and Port_event
become 1, Status transfer is sent on the PHY/Link interface.
• The µPD72852A activates the PHY/Link interface when LPS is 1, regardless of the value of the Link active bit.
Data Sheet S16725EJ2V0DS
23
µPD72852A
4.3 PHY/Link Interface Operation (CTL0, CTL1, LREQ, D0-D7)
The PHY/Link Interface consists of the following operations:
• Status transfer to the Link layer controller by CTL
• Transmit packet
• Receive packet
• Request from the Link layer controller by LREQ
4.3.1 CTL0, CTL1
CTL0, CTL1 controls the PHY/Link interface as shown in the Table 4-3.
Table 4-3. CTL Controls PHY
CTL0,CTL1
00
Type
Content
Idle
PHY is in idle function
01
Status
PHY transmitting status information to Link
10
Receive
PHY receiving data from the Link
11
Grant
PHY allows Link to transmit data
This is the operation by which, after Grant, the Link obtains the right to control the interface.
Table 4-4. CTL Controls Link
CTL0,CTL1
Type
00
Idle
01
Hold
Content
Link completes the packet transmission and releases the PHY/Link interface.
1) Link transmits Hold until the data is ready for transmission.
2) Link transmits the interface connect packet.
10
Transmit
Link transmits the data to PHY.
11
-
Not used.
4.3.2 LREQ
Access to the PHY register and the bus is controlled from the Link layer controller through the LREQ pin of PHY.
Figure 4-3. LREQ and CTL Timing
LREQ
CTL0,CTL1
LR0
CA
LR1
LR2
LR3
CB
CA : CTL before generation of LREQ
CB : CTL during LREQ execution
24
Data Sheet S16725EJ2V0DS
LR(n-2)
LR(n-1)
µPD72852A
(1) LREQ format
• Bus Request
Table 4-5. Bus Request Format
Bit
Type
Content
0
start
Signal that starts a request : 1
1-3
request
Bus request type:
000: ImmReq acknowledge packet transmit
001: IsoReq isochronous packet transmit
010: PriReq cycle start packet transmit
011: FairReq asynchronous packet transmit
4-6
speed
Transmit speed:
000: 100 Mbps
010: 200 Mbps
100: 400 Mbps
other: reserved
7
stop
End request signal : 0 (optional)
• PHY Register Read Request
Table 4-6. Read Request Register Format
Bit
Type
Content
0
start
Signal that starts a request : 1
1-3
request
Read Request.
100 : ReadReq
4-7
access address
PHY register address.
8
stop
End request signal : 0
• PHY Register Write Request
Table 4-7. Write Request Register Format
Bit
Type
Content
0
start
Signal that starts a request : 1
1-3
request
Write Request.
4-7
access address
PHY register address.
8-15
write data
Write data.
16
stop
End request signal : 0
101 : WriteReq
Data Sheet S16725EJ2V0DS
25
µPD72852A
• Acceleration Controller
Table 4-8. Acceleration Controller Request Format
Bit
Type
Content
0
start
Signal that starts a request : 1
1-3
request
110 : Acc Ctrl accelerate controller
4
access address
0: Accelerate disable
5
stop
End request signal : 0
1: Accelerate enable
Table 4-9. Request Type List
Bit
000
Type
ImmReq
Content
Used to acknowledge packet transmit.
When Idle is detected, PHY immediately controls the bus.
001
IsoReq
Used to transmit isochronous packet.
PHY does arbitration after isochronous gap is detected and acquires the bus.
010
PriReq
Used for Cycle master request.
011
FairReq
Fair request.
100
RdReg
PHY register read request.
101
WrReg
PHY register write request.
110
AccCtrl
Disable/enable of arbitration acceleration.
111
-
Unused.
For the Link to execute Priority request and Fair, start the request using LREQ when CTL0, CTL1 becomes idle,
after one clock. When request is acknowledged, the µPD72852A outputs Grant to CTL0, CTL1.
The Link of cycle master uses PriReq to transmit the cycle start packet. IsoReq transmits the isochronous
packet.
IsoReq becomes effective only as follows:
• The transmission of the cycle start packet is performed on the same isochronous period as Receive. (The
period until the subaction gap is detected.)
• During isochronous packet Transmit or Receive.
The µPD72852A cancels IsoReq with the subaction gap detection or bus reset. To meet the timing, do not
issue the IsoReq to PHY when CRC operation is performed.
The Link cancel method is described later.
After the packet is received, Link issues ImmReq as the acknowledge packet transmission. The purpose is to
prevent another node from detecting subaction gap as ACK_RESPONSE_TIME. The µPD72852A acquires the
bus after packet receive and returns Grant to CTL0, CTL1. When CRC fails, before Link detects Grant, assert 3
Idle cycles to CTL0, CTL1.
When the bus reset is generated, the unprocessed requests are canceled.
The µPD72852A updates the data of the Write request register and the contents of the Read register are
changed. The contents of the register of the specified address are output to the Link as a status transfer in the
Read request register, When the status transmission is interrupted by transmitting/receiving packets, the status
transmission will re-start from the first bit after completing the transmit/receive of the packets.
The bus request (ImmReq, IsoReq, PriReg, FairReq) is completed (in case of ImmReq, IsoReq, when the
subaction gap is detected) when the packet is transmitted or canceled by canceling the bus request.
26
Data Sheet S16725EJ2V0DS
µPD72852A
(2) LREQ rules
The Link request and the status of the serial bus are asynchronous; the bus request can be canceled by the
status of the serial bus.
The following rules apply to a request by LREQ:
• Link cannot issue a bus request (ImmReq, IsoReq, PriReq, FairReq) if Grant is given to an LREQ request or
until the Link’s request is canceled. The request can be canceled by the µPD72852A if it detects subaction
gap at ImmReq, IsoReq.
• Do not issue a RdReg or WrReg request when the status transmission is not completed by the Read request
register.
• All of the bus requests (ImmReq, IsoReq, PriReq, FairReq) are canceled by a bus reset.
In addition, there is a limitation in the request of LREQ according to the state of CTL as shown in Table 4-10.
Table 4-10. Rules for Other Requests
Request
Fair, Priority
State of CTL in CA to
LREQ issues
which LREQ is allowed
permission when Link
when PHY drives CTL
drives CTL
Idle, Status
wrong
Note
Fair, Priority request cannot be issued until the
unprocessed bus request is completed.
Immediate
Receive, Idle
wrong
Link issues the request after completing the decoding of
Destination_ID, when the acknowledge packet is ready.
After the packet is received, it is necessary to transmit the
first bit of the request within four cycles.
Isochronous
any
correct
If the isochronous packet transmission is prepared for the
isochronous period, it is issued.
Do not issue the request to transmit the isochronous
packet appending to the currently transmitted isochronous
packet (Using Hold).
Register Read
any
correct
Register Write
AccCtrl
Do not issue this request if the unprocessed Read request
has not been completed.
any
correct
To set acceleration bit 0:
When the isochronous period starts, if the Enab_accel bit
is one, Cycle slave should adjust accelerate bit to 0.
To set acceleration bit 1:
Do not set the cycle master.
It is issued when the isochronous period ends.
Data Sheet S16725EJ2V0DS
27
µPD72852A
Table 4-11. PHY Operation Before LREQ Request to the CTL Function Changes
Request
State of CTL in CB after
Operation of the PHY
LREQ was issued
Fair, Priority
• Hold the request if the acceleration of arbitration packet transmitted with
Receive
enable is 8 bits (ACK).
Except for 8 bits, the requests are ignored.
• Ignore the request when the acceleration of arbitration is disabled.
Immediate
Isochronous
Grant
Arbitration Won.
Idle, Status
Excluding when the bus reset is generated, Hold the requests.
Grant
Receive
The packet is being transmitted to Link. Request Hold.
Idle, Status
Excluding when the bus reset is generated, hold the request.
Transmit Idle (driven by Link)
Request Hold.
Grant
Arbitration Won.
Receive
Request Hold.
Status
Request is ignored when sub-action gap is detected.
Idle
Register Read
Any (driven by Link)
Grant
Request Hold.
Receive
Request Hold.
Status
Hold the request until the corresponding register value is returned.
Idle
Register Write,
Any
Request is completed.
Acceleration
control
4.3.3 SCLK Timing
Table 4-12. SCLK Timing
Timing Constant
BUS_TO_LINK_DELAY
Comment
Period from receiving RX_DATA_PREFIX until
MIN.
MAX.
Unit
2
9
SCLK cycle
25
SCLK cycle
5
SCLK cycle
47
SCLK cycle
Receive to CTL is output.
DATA_PREFIX_TO_GRANT
Period when the Grant is output to CTL after
TX_DATA_PREFIX is output to a port.
LINK_TO_BUS_DELAY
Period when TX_DATA_END is output to all ports after
2
transmitting the packet by Link after idle was asserted
to CTL.
MAX_HOLD
Maximum period when Hold can be asserted by Link
to confirm Grant.
28
Data Sheet S16725EJ2V0DS
µPD72852A
4.4 Acceleration Control
Enable of ack-acceleration and fly-by on the same isochronous period may create a problem. The isochronous
cycle may extend unintentionally when transmitting the asynchronous packet by a node using ack-acceleration and flyby.
To avoid this problem, Link should control Disable/Enable of these enhancements (ack-Acceleration, fly-by), by
Acceleration Control requests. Cycle master cannot issue the Acceleration Control request.
The enhancements should not be used from the generation of the local cycle synchronization event to the
confirmation of cycle start. In this period, all Links except for Cycle Master use Acceleration Control as follows:
• Do not issue Fair nor Priority request to Link after generating local cycle synchronization, if the Acceleration
Control request’s Accelerate bit is not set to 0.
• Link must not use Hold when transmitting continuous primary asynchronous packet after the Acknowledge packet,
except after ack_pending to complete the split transaction.
• Ending the Link during the isochronous period issues the acceleration control request to set the Accelerate bit to 1,
enabling these enhancements.
The µPD72852A does not require setting the Acceleration Control during isochronous transmit to enable the
isochronous request fly-by acceleration.
It is not necessary to issue Acceleration Control request when the cycle master is absent from the serial bus. These
enhancements are enabled if the Enab_accel bit in the PHY register is set. The µPD72852A supports Variable
Acceleration controlled by the Acceleration Control during power-on reset.
Data Sheet S16725EJ2V0DS
29
µPD72852A
4.5 Transmit Status
Pin D0, D1 of the µPD72852A transmits status information to the Link. Status is asserted to CTL while transmitting
Status. The status transmission is interrupted if the serial bus receives a packet which contains states other than
status to CTL. Between two status transmissions, assert Idle to CTL for at least one SCLK cycle.
The µPD72852A transmits status in 16 bits as follows:
• In response to the register request
• After deciding the new Physical_ID for the Self_ID period resetting the bus (after a Self_ID packet is transmitted)
The event indication is the only 4-bit transmission of the µPD72852A.
Figure 4-4. Status Timing
PHY CTL0,CTL1
00
01
01
01
00
00
PHY D0-D7
00
S0,S1
S2,S3
S14,
S15
00
00
Table 4-13. Status Data Format
Bit(s)
Name
Description
0
ARB_RESET_GAP
Arbitration Reset gap detect
1
SUBACTION_GAP
Subaction gap detect
2
BUS_RESET_START
Bus reset detect
3
Phy_interrupt
Either of the following states is detected:
• The topology of the bus is a loop
• Voltage drop on the power cable
• Arbitration state machine timeout
• Port Event
4-7
Address
PHY register address
8-15
Data
Register data
The bits already transmitted are set to 0.
Example If the status transmission is interrupted after S0, S1 bit was transmitted, then in the next status transfer,
S0, S1 becomes 0.
Therefore one of the following situations will occur when the µPD72852A re-transmits status after an
interruption of the status transmission:
• At least one bit of S0-S3 is 1
• The PHY register data contains the interrupt status information
The status transmission always begins with S0, S1.
If the Link executes read request, and Subaction gap and arbitration reset gap are detected, priority is given to the
transmission of gap status, postponing the response to the register read request.
30
Data Sheet S16725EJ2V0DS
µPD72852A
4.6 Transmit
The µPD72852A arbitrates the serial bus using Link’s LREQ.
• When the µPD72852A acquires the bus, a Grant period of 1 SCLK is executed to CTL0, CTL1. After that, an Idle
period of 1 SCLK cycle is executed.
• Link controls the interface executing Idle, Hold of Transmit to CTL0, CTL1 after 1 SCLK cycle when Grant from
PHY is detected.
• Before asserting Hold and Transmit, assert 1 Idle cycle. Do not execute Idle for 2 or more cycles.
• If the packet transmit is not ready, the Hold period can be extended up to MAX_HOLD.
• The µPD72852A outputs DATA_PREFIX to the serial bus while Hold is being asserted to CTL.
• When the packet transmit is ready, Link outputs the first bit of the packet and Transmit is asserted to CTL at the
same time.
• After transmitting the last bit of the packet, Link outputs for Idle or Hold to CTL for 1 cycle. After that, it outputs Idle
for 1 cycle.
When PHY/Link releases the bus, output Low to CTL and D0-D7 within 1 cycle.
Figure 4-5. Transmit Timing
(a) Single Packet
PHY CTL0,CTL1
00
11
00
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
00
PHY D0-D7
00
00
00
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
ZZ
00
Link CTL0,CTL1
ZZ
ZZ
ZZ
00
01
01
10
10
10
10
00
00
ZZ
Link D0-D7
ZZ
ZZ
ZZ
00
00
00
D0
D1
D2
Dn
00
00
ZZ
(b) Concatenated Packet
PHY CTL0,CTL1
ZZ
ZZ
ZZ
ZZ
00
00
11
00
ZZ
ZZ
ZZ
ZZ
ZZ
PHY D0-D7
ZZ
ZZ
ZZ
ZZ
00
00
00
00
ZZ
ZZ
ZZ
ZZ
ZZ
Link CTL0,CTL1
10
10
01
00
ZZ
ZZ
ZZ
ZZ
00
01
01
10
10
Link D0-D7
Dn-1
Dn
SP
00
ZZ
ZZ
ZZ
ZZ
00
00
00
D0
D1
Note In case of packet transmission after Grant, before actual transmission, Hold does not need to be asserted.
Link can transmit continuous packets without releasing the bus.
• Hold is asserted to CTL. This function is used when the Link transmits continuous packets after acknowledge and
isochronous packets. Link outputs the transfer rate signal of the following packet to D0-D7 and asserts Hold
simultaneously.
• After Hold is detected by MIN_PACKET_SEPARATION, the µPD72852A outputs Grant to CTL.
Data Sheet S16725EJ2V0DS
31
µPD72852A
• Link controls the interface by generating Idle, Hold or Transmit to CTL0, CTL1, after 1 SCLK cycle when Grant
from PHY is detected.
• Assert 1 Idle cycle before asserting Hold and Transmit (do not output 2 or more Idle cycles). When the packet
transmission is not ready, assert Hold. The Hold output period after Grant is detected should not exceed the
period provided by MAX_HOLD.
The following limitations exist though Link can transmit the concatenated packet with a different transfer rate. Link
cannot transmit other than S100 connecting packets after S100 (concatenated) packets have been transmitted. A new
request to transmit must be issued in order to transmit S100 packets at a transfer rate of S200 or more.
If the Enab_Multi bit in the PHY register is 0, the µPD72852A assumes the same speed as the first packet, for all of
the concatenated packets.
At the end of packet transmission, Link asserts Idle to CTL for a period of 2 cycles.
After sampling Idle from Link, the µPD72852A asserts Idle to CTL for a period of 1 cycle.
4.7 Cancel
This section describes how Link operates, when after the bus has been acquired by the request of LREQ, there is
no data transmission. In this case, a Null packet with no data is transmitted to the serial bus (DATA_PREFIX →
DATA_END).
Following are two method for canceling the Link:
1. As explained in Section 4.6, the Link outputs Idle or Hold, then outputs Transmit to CTL after confirming Grant.
Here, the Link asserts Idle for two cycles to CTL, then switches to high impedance.
The µPD72852A confirms Cancel at the second Idle cycle. To prevent the bus from switching to high impedance,
a third Idle cycle is needed.
Figure 4-6. Link Cancel Timing (After Grant)
PHY CTL0,CTL1
00
11
00
ZZ
ZZ
ZZ
00
PHY D0-D7
00
00
00
ZZ
ZZ
ZZ
00
Link CTL0,CTL1
ZZ
ZZ
ZZ
00
00
00
ZZ
Link D0-D7
ZZ
ZZ
ZZ
00
00
00
ZZ
2. To cancel after asserting Hold, assert Idle between two cycles; it switches to high impedance. This method
cancels the packet transmission connection (concatenated) after Grant is received. The µPD72852A cancels
with the next Idle cycle of Hold. To prevent CTL from switching to high impedance, assert a second Idle cycle.
32
Data Sheet S16725EJ2V0DS
µPD72852A
Figure 4-7. Link Cancel Timing (After Hold)
PHY CTL0,CTL1
00
11
00
ZZ
ZZ
ZZ
ZZ
ZZ
00
PHY D0-D7
00
00
00
ZZ
ZZ
ZZ
ZZ
ZZ
00
Link CTL0,CTL1
ZZ
ZZ
ZZ
00
01
01
00
00
ZZ
Link D0-D7
ZZ
ZZ
ZZ
00
00
00
00
00
ZZ
4.8 Receive
This section shows the operation when the packet is received from the serial bus.
• When the µPD72852A detects DATA_PREFIX on the serial bus, it asserts receive to CTL and all of the D pins
assume the logic value of 1.
• The µPD72852A shows the speed code of the transfer rate ahead of the packet using bits D0-D7. Transmitting
the speed code with the speed signal is the protocol of the PHY/Link interface. The speed code is not included in
the CRC calculation.
• The µPD72852A continues to assert Receive to CTL until the packet is finally transmitted.
• Idle is asserted to CTL, indicating completion of the packet transmission.
Figure 4-8. Receive Timing
PHY CTL0,CTL1
(Binary)
00
10
10
10
10
10
10
00
00
PHY D0-D7
(Hex)
00
FF
FF
SP
D0
D1
Dn
00
00
The packet transfer rate of the serial bus depends on the topology of the bus. The µPD72852A checks if the node
can receive at the faster transfer rate. At this time, DATA_PREFIX → DATA_END is transmitted to the µPD72852A.
After DATA_PREFIX is transmitted to the Link, Receive from the serial bus is completed, asserting Idle.
Table 4-14 shows the speed code encoding.
Table 4-14. Speed Encoding
D0-D7
Data rate
Transmitted
Observed
00000000
00xxxxxx
S100
01000000
0100xxxx
S200
01010000
01010000
S400
11111111
11xxxxxx
Data Prefix
Data Sheet S16725EJ2V0DS
33
µPD72852A
5. CABLE PHY PACKET
The node on the serial bus transmits and receives the PHY packet to control the bus.
The PHY packet is composed of 2 quadlets (64-bit); the second quadlet (32-bit) contains the inverse value of the
first quadlet.
The PHY packet is transmitted at a transfer rate of S100. All of the PHY packets received from the serial bus are
transmitted to the Link.
Though the PHY packet from the µPD72852A is transmitted to the Link, the PHY packet which was transmitted
from the Link of the node is not transmitted to the Link.
There are four types of PHY packets, as follows:
• Self_ID packet
• Link-on packet
• PHY configuration packet
• Extended PHY packet
The Self_ID packet transmitted automatically by the µPD72852A is also transmitted to the Link of a local node.
The µPD72852A PHY packet Receive from the serial bus operates similar to the PHY packet transmitted by the
Link (when the packet transmission to the Link is executed).
5.1 Self_ID Packet
During the Self_ID phase of the initialization or when the Ping packet responds, the µPD72852A transmits the
Self_ID packet.
Figure 5-1. Self_ID Packet Format
10
phy_ID
0
L
gap_cnt
sp
rsv
c
pwr
p0
p1
p2
Logical Inverse of the first quadlet
Table 5-1. Self_ID Packet
Field
Description
phy_ID
Physical ID of the node.
L
Logical product of Link_active and LPS in the PHY register.
gap_cnt
Gap_count value in the PHY register.
sp
Physpeed 10 (corresponds to 98.304, 196.608, 393.216 Mbps).
c
C bit values in the PHY register.
pwr
pwr value in the PHY register.
000: The node does not need the power supply. No power repeat.
001: Obtains power supply for the node. Can supply 15 W or more.
010: Obtains power supply for the node. Can supply 30 W or more.
011: Obtains power supply for the node. Can supply 45 W or more.
100: The node consumes 3 W maximum power.
110: The node consumes 3 W maximum power. At least 3 W are necessary to enable Link.
111: The node consumes 3 W maximum power. At least 7 W are necessary to enable Link.
i
It shows that the node issued Bus Reset and the bus was reset.
m
Read as 0.
rsv
Read as 00.
34
Data Sheet S16725EJ2V0DS
i
m
µPD72852A
5.2 Link-on Packet
The µPD72852A outputs the Link-on signal of 6.144 MHz from the pin LKON when receiving the Link-on packet.
Figure 5-2. Link-on Packet Format
01
phy_ID
0000
0000
0000
0000
0000
0000
0000
0000
Logical Inverse of the first quadlet
Table 5-2. Link-on Packet
Field
Description
phy_ID
Physical_ID of the destination of the Link-on packet
5.3 PHY Configuration Packet
Use the PHY configuration packet to set the gap count for the bus.
Figure 5-3. PHY Configuration Packet Format
00
root_ID
R
T
gap_cnt
0000
0000
Logical Inverse of the first quadlet
Table 5-3. PHY Configuration Packet
Field
Description
root_ID
Sets the Physical_ID node as root contender (for the next reset).
R
When this bit is set to 1 and the Phyisical_ID of the node corresponds to the rootID of this packet, the
µPD72852A sets the force_root bit. The force_root bit is cleared if there is discrepancy.
T
If this bit is 1, the gap_cnt value of this packet is used as the gap_count value. The gap_count value must
not be cleared by the following bus reset, set the gap_count_reset_disable flag in the µPD72852A to
TRUE.
gap_cnt
When this packet is received, the gap count is set to this value. While it remains effective for the next bus
reset, it will be cleared by the second bus reset to 3FH.
Remark Applying 0 to both R,T, regards the following packets as extended PHY packets, the PHY configuration is not
recognized.
5.4 Extended PHY Packet
An extended PHY packet is defined when both the R (in the PHY configuration packet) and T bits are transmitted as
0. The extended PHY packet does not influence the force_root_bit and the gap_count bit on any node.
Following are the types of extended PHY packets:
• Ping packet
• Remote access packet
• Remote reply packet
• Remote command packet
• Remote confirmation packet
• Resume packet
Data Sheet S16725EJ2V0DS
35
µPD72852A
5.4.1 Ping Packet
When the µPD72852A receives the Ping packet, it will transmit the Self_ID packet within the RESPONSE_TIME.
Figure 5-4. Ping Packet Format
00
phy_ID
00
type (0)
00
0000
0000
0000
0000
Logical Inverse of the first quadlet
Table 5-4. Ping Packet
Field
Description
phy_ID
Physical ID of the destination node of the Ping packet
type
Indicates that there is a Ping packet with a value of 0
5.4.2 Remote Access Packet
The Remote access packet reads information in the PHY register of another node. The PHY specified by the
Remote access packet transmits the value in the register using the Remote Reply packet.
Figure 5-5. Remote Access Packet Format
00
phy_ID
00
type
page
port
reg
Logical Inverse of the first quadlet
Table 5-5. Remote Access Packet
Field
Description
phy_ID
Physical ID of the destination node of the Remote access packet
type
1 = read register (base register), 5 = read register (page register)
page
Specifies the page of the PHY register
port
Specifies the register of each port in the PHY register
reg
Specifies the address when reading the base register.
In case of the Page and port registers, specifies the address with 1000+reg.
36
Data Sheet S16725EJ2V0DS
reserved
µPD72852A
5.4.3 Remote Reply Packet
The µPD72852A transmits the value in the register by using the Remote reply packet as a response to the Remote
access packet.
Figure 5-6. Remote Reply Packet Format
00
phy_ID
00
type
page
port
reg
data
Logical Inverse of the first quadlet
Table 5-6. Remote Reply Packet
Field
Description
phy_ID
Physical ID of the node (Node’s original packet transmit)
type
3 = register read (base register), 7 = read register (page register)
page
Used when specifying the page of the PHY register
port
Used to specify the register of each port in the PHY register
reg
Specifies the address when reading the base register.
In case of the Page and port registers, specify the address with 1000+reg.
data
Contents of the specified register
5.4.4 Remote Command Packet
Use the Remote command packet to operate the function of the port of the PHY of another node.
Figure 5-7. Remote Command Packet Format
00
phy_ID
00
type(8)
000
port
0000
0000
cmnd
Logical Inverse of the first quadlet
Table 5-7. Remote Command Packet
Field
Description
phy_ID
Physical ID of the destination packet
type
Extended PHY packet type; set to 8 for Remote command packet
port
Port of the PHY of the operating node
cmnd
Command
0: NOP
1: Disables the port after transmission of the TX_DISABLE_NOTIFY
2: Suspend initiator
4: Clears to 0 the Fault bit of the port
5: Enables the port
6: Resumes the port
Data Sheet S16725EJ2V0DS
37
µPD72852A
5.4.5 Remote Confirmation Packet
The µPD72852A transmits the Remote confirmation when the Remote command packet is received, responding
whether cmnd can be executed.
Figure 5-8. Remote Confirmation Packet Format
00
phy_ID
00
type(A16)
000
port
000
f
c
b
d
ok
cmnd
Logical Inverse of the first quadlet
Table 5-8. Remote Confirmation Packet
Field
Description
phy_ID
Physical ID of the node (node’s original packet transmit)
type
Extended PHY packet type; set to A16 for Remote confirmation packet
port
Port set from the Remote command packet
f
Fault bit value of the PHY register of this port
c
Connected bit value of the PHY register of this port
b
Bias bit value of the PHY register of this port
d
Disable bit value of the PHY register of this port
ok
1 indicates executing; otherwise it is 0
cmnd
Specifies the command value with the Remote command packet
5.4.6 Resume Packet
When the µPD72852A receives the Resume packet, all of the ports that were suspended resume the connection.
The Resume packet does the broadcast.
Figure 5-9. Resume Packet Format
00
phy_ID
00
type (F16)
00
0000
Logical Inverse of the first quadlet
Table 5-9. Resume Packet
Field
Description
phy_ID
Physical ID of the original packet transmit
type
Extended PHY packet type; set to F16 for Resume packet
38
Data Sheet S16725EJ2V0DS
0000
0000
0000
µPD72852A
6. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Parameter
Symbol
Condition
Rating
Unit
Power supply voltage
VDDm
–0.5 to +4.6
V
Input voltage
VIN
–0.5 to VDD+0.5
V
Output voltage
VOUT
–0.5 to VDD+0.5
V
Storage temperature
Tstg
–40 to +125
°C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
A CMOS device may cause unusual operation or destruction by Latch-up phenomenon. For your
safety, be careful of the factor (serge, noise, static electricity) considered as external stress to
Input/Output pins.
In order to avoid outbreak of heat/destruction of the device/board/equipment by an over-current
continuing input, please prepare the current restrictions below 1.5 [A] as VCC input.
Recommended Operating Ranges
Parameter
Power supply voltage
Symbol
VDD
Condition
Source power node
Non-source power node
Operating temperature
TA
Power dissipation
PD
MIN.
TYP.
MAX.
Unit
3.0
3.3
3.6
V
3.0
3.6
V
Note
2.7
0.0
70.0
°C
440
mW
Note For a node does not source power.
Data Sheet S16725EJ2V0DS
39
µPD72852A
DC Characteristics
Common
Parameter
Supply current
Symbol
IDD
Condition
MIN.
TYP.
MAX.
Unit
Note 1
68
mA
Note 2
60
mA
Note 3
41
mA
Note 4
31
mA
Note 5
115
µA
Notes 1. Transmit maximum packet (all ports transmitting maximum size isochronous packet - 4096 bytes, sent on
every isochronous interval, S400, data value of CCCCCCCCH), VDD = 3.3 V, TA = 25°C
2. Repeat typical packet (receiving on one port DV packets on every isochronous interval, S100, and
transmitting on the other port), VDD = 3.3 V, TA = 25°C
3. Idle (one port receiving and one port transmitting cycle starts), VDD = 3.3 V, TA = 25°C
4. 1 port receiving cycle start packet only, VDD = 3.3 V, TA = 25°C
5. Suspend mode, VDD = 3.3 V, TA = 25°C
PHY/Link Interface
Parameter
High-level output voltage
Symbol
VOH
Condition
CTL0, CTL1, D0-D7, LKON, SCLK,
MIN.
TYP.
MAX.
Unit
VDD–0.45
V
VDD–0.4
V
IOH = –9 mA, VDD > 3 V
CTL0, CTL1, D0-D7, LKON, SCLK,
IOH = –4 mA, VDD = 2.7 V
Low-level output voltage
VOL
CTL0, CTL1, D0-D7, LKON, SCLK,
0.4
V
0.4
V
IOH = +9 mA, VDD > 3 V
CTL0, CTL1, D0-D7, LKON, SCLK,
IOH = +4 mA, VDD = 2.7 V
High-level input voltage
VIH
LPS, SPD, DIRECT, PC0-PC2, SUS/RES,
0.7VDD
V
CMC
Low-level input voltage
VIL
0.2VDD
V
0.456VDD
0.456VDD
V
+0.3
+0.9
0.456VDD
0.456VDD
VDD > 3 V
–0.9
–0.3
CTL0, CTL1, D0-D7,
–10
µA
–10
µA
LPS, SPD, DIRECT, PC0-PC2, SUS/RES,
CMC
High-level input voltage (schmitt)
VIHS
CTL0, CTL1, D0-D7, LREQ,
VDD > 3 V
Low-level input voltage (schmitt)
VILS
High-level input current
IIH
CTL0, CTL1, D0-D7, LREQ,
V
VI = VDD, DIRECT = 0 V
LPS, SPD, DIRECT, PC0-PC2, SUS/RES,
CMC,
VI = VDD
Low-level input current
IIL
CTL0, CTL1, D0-D7, LKON, SCLK,
10
µA
10
µA
VI = 0 V, DIRECT = 0 V
LPS, SPD, DIRECT, PC0-PC2, SUS/RES,
CMC,
VI = 0 V
40
Data Sheet S16725EJ2V0DS
µPD72852A
Cable Interface
Parameter
Differential input voltage
Symbol
VID
Condition
VICM
TYP.
MAX.
Unit
Cable input, 100 Mbps operation
142
260
mV
Cable input, 200 Mbps operation
132
260
mV
Cable input, 400 Mbps operation
TpB common mode input voltage
MIN.
118
260
mV
100 Mbps speed signaling off
1.165
2.515
V
200 Mbps speed signaling
0.935
2.515
V
400 Mbps speed signaling
0.523
2.515
V
Differential output voltage
VOD
Cable output (Test load 55 Ω)
172.0
265.0
mV
TpA common mode output voltage
VOCM
100 Mbps speed signaling off
1.665
2.015
V
TpA common mode output current
ICM
Power status threshold voltage
VTH
TpBias output voltage
VTPBIAS
200 Mbps speed signaling
1.438
2.015
V
400 Mbps speed signaling
1.030
2.015
V
100 Mbps speed signaling off
–0.81
+0.44
mA
200 Mbps speed signaling
–4.84
–2.53
mA
400 Mbps speed signaling
–12.40
–8.10
mA
7.5
V
2.015
V
CPS
1.665
Data Sheet S16725EJ2V0DS
41
µPD72852A
AC Characteristics
PHY/Link Interface
Parameter
Symbol
Condition
MIN.
TYP.
MAX.
Unit
D, CTL, LREQ setup time
tSU
5
ns
D, CTL, LREQ hold time
tHD
0
ns
D, CTL output timing
tD
0.5
SCLK cycle time
tSCLK
20
SCLK high level time
tSCLKH
9
11
ns
SCLK low level time
tSCLKL
9
11
ns
LKON cycle time
tLINKON
160
Link Interface Timing (SCLK, LKON)
SCLK
tSCLKH
tSCLKL
tSCLK
LKON
tLINKON
42
Data Sheet S16725EJ2V0DS
9
ns
ns
ns
µPD72852A
Link Interface Timing (CTL, D)
SCLK
tD
tD
tD
tD
tD
tD
Transmit
CTL0,CTL1
D0-D7
tSU
tH
tSU
tH
Receive
CTL0,CTL1
D0-D7
Link Interface Timing (LREQ)
SCLK
tSU
tH
LREQ
Cable Interface
Parameter
Symbol
Condition
TpA, TpB transfer jitter
tJITTER
TpA strobe, TpB data transfer
tSKEW
Between TpA and TpB
TPA, TPB rise time/fall time
tR/tF
10 % to 90 %, via 55 Ω and 10 pF
Speed
MIN.
Between TpA and TpB
Data Sheet S16725EJ2V0DS
TYP.
MAX.
Unit
±0.15
ns
±0.10
ns
S100
0.5
3.2
ns
S200
0.5
2.2
ns
S400
0.5
1.2
ns
43
µPD72852A
7. APPLICATION CIRCUIT EXAMPLE
• IEEE1394 Interface
0.1 µF
Note
5.1 kΩ
270 pF
56 Ω
56 Ω
56 Ω
56 Ω
56 Ω
56 Ω
44
Common mode choke.
Recommendation : TDK Part No. ACM2012-121
: MURATA Part No.PLP31DN161SL4
Data Sheet S16725EJ2V0DS
390 kΩ
VP
(Cable Supply Voltage)
Power Class
Programming
0.1 µF
24.576 MHz
10 pF
22 µF
10 pF
AVDDPOWER (3.3 V)
GND
0.1 µF
GND
0.1 µF
22 µF
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
DVDDPOWER (3.3 V)
0.1 µF
0.1 µF
0.1 µF
Note
100 kΩ
0.1 µF
CPS
AVDD
CMC
IC(AL)
PC2
PC1
PC0
AVDD
AGND
XI
XO
DGND
DVDD
SUS/RES
D7
D6
DGND
SCLK
IC(DL)
DVDD
CTL0
CTL1
DGND
D0
D1
DVDD
D2
D3
DGND
D4
D5
DGND
AGND
DIRECT
IC(AL)
AGND
AGND
AVDD
RESETB
DVDD
DGND
LKON
LPS
DVDD
SPD
FNSel
LREQ
DGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
49
50
51
52
53
0.1 µF
54
0.1 µF
55
0.1 µF
56
57
58
59
60
61
0.1 µF
62
63
64
TpBias1
AVDD
TpA1p
TpA1n
TpB1p
TpB1n
AGND
TpBias0
AVDD
TpA0p
TpA0n
TpB0p
TpB0n
AGND
RI1
AGND
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
56 Ω
56 Ω
9.1 kΩ (0.5%)
1 µF
1 µF
5.1 kΩ
270 pF
0.1 µF
Note
µPD72852A
8. PACKAGE DRAWING
64-PIN PLASTIC LQFP (10x10)
A
B
48
detail of lead end
33
32
49
S
P
C
T
D
R
64
U
17
Q
16
1
L
F
G
J
H
I
M
ITEM
A
K
B
S
N
S
M
MILLIMETERS
12.0±0.2
10.0±0.2
C
10.0±0.2
D
12.0±0.2
F
1.25
G
1.25
H
0.22±0.05
I
0.08
J
0.5 (T.P.)
NOTE
K
1.0±0.2
Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
L
0.5
M
0.17 +0.03
−0.07
N
0.08
P
1.4
Q
0.1±0.05
R
3° +4°
−3°
S
1.5±0.10
T
0.25
U
0.6±0.15
S64GB-50-8EU-2
Data Sheet S16725EJ2V0DS
45
µPD72852A
9. RECOMMENDED SOLDERING CONDITIONS
The µPD72852A should be soldered and mounted under the following recommended conditions.
For soldering methods and conditions other than those recommended below, contact your NEC Electronics sales
representative.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Table 9-1. Surface Mounting Type Soldering Conditions
µPD72852AGB-8EU: 64-pin plastic LQFP (10 × 10)
Soldering
Soldering Conditions
Method
Infrared reflow
Recommended
Condition Symbol
Package peak temperature: 235°C, Time: 30 sec. Max. (at 210°C or higher).
IR35-103-3
Count: three times or less
Exposure limit: 3 daysNote (after that prebake at 125°C for 10 hours)
Partial heating
Pin temperature: 300°C Max., Time: 3 sec. Max. (per pin row)
—
Note After opening the dry pack, store it at 25°C or less and 65 % RH or less for the allowable storage period.
46
Data Sheet S16725EJ2V0DS
µPD72852A
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
VIH (MIN).
2
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or
GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins
must be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred.
Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded.
The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
PAY ATTENTION TO CHARGING WITH STATIC ELECTRICITY OF THE DEVICE OR THE SURFACE
OF THE DEVICE PACKAGE
In case the handing of this product and the production manufacturing process, please use the ionizer for
this device to eliminate static electricity.
Data Sheet S16725EJ2V0DS
47
µPD72852A
FireWire is a trademark of Apple Computer, Inc.
i.LINK is a trademark of Sony Corporation.
Intel is a trademark of Intel Corporation.
• The information in this document is current as of March, 2004. The information is subject to change
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M8E 02. 11-1