[ /Title (CD74 HC253 , CD74 HCT25 3) /Subject (High Speed CMOS Logic Dual 4-Input Multiplexer) CD74HC253, CD74HCT253 Data sheet acquired from Harris Semiconductor SCHS170 High Speed CMOS Logic Dual 4-Input Multiplexer November 1997 Features at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH • Common Select Inputs • Separate Output-Enable Inputs • Three-State Outputs • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Description The Harris CD74HC253 and CD74HCT253 are dual 4-to-1 line selector/multiplexers having three-state outputs. One of four sources for each section is selected by the common select inputs, S0 and S1. When the output enable (1OE, 2OE) is HIGH, the output is in the high-impedance state. • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs Ordering Information • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC PART NUMBER TEMP. RANGE (oC) PACKAGE PKG. NO. Pinout CD74HC253, CD74HCT253 (PDIP, SOIC) TOP VIEW 1OE 1 16 VCC S1 2 15 2OE 1I3 3 14 S0 1I2 4 13 2I3 1I1 5 12 2I2 1I0 6 11 2I1 1Y 7 10 2I0 GND 8 9 2Y CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1997 1 File Number 1673.1 CD74HC253, CD74HCT253 Functional DiagramS 15 13 2I0 2I1 2I2 2I3 2OE 12 11 S0 10 S1 14 1I0 2 1I1 6 1I2 5 1I3 4 1OE 3 1 2OE 1OE 2OE 1OE 16 VCC 8 GND P N N P 2OE 2OE 1OE 1OE 7 9 2Y 1Y TRUTH TABLE SELECT INPUTS DATA INPUTS OUTPUT ENABLE OUTPUT S1 S0 I0 I1 I2 I3 OE Y X X X X X X H Z L L L X X X L L L L H X X X L H L H X L X X L L L H X H X X L H H L X X L X L L H L X X H X L H H H X X X L L L H H X X X H L H NOTE: Select inputs S1 and S0 are common to both sections. H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, Z = High Impedance (Off). 2 CD74HC253, CD74HCT253 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA Thermal Resistance (Typical, Note 3) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. θJA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications TEST CONDITIONS PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) VIH - - 2 1.5 - - 1.5 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V MIN TYP MAX MIN MAX MIN MAX UNITS - 1.5 - V HC TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads VIL VOH - VIH or VIL High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads Input Leakage Current II VCC or GND - 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V -0.02 2 1.9 - - 1.9 - 1.9 - V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -0.02 6 5.9 - - 5.9 - 5.9 - V - - - - - - - - - V -6 4.5 3.98 - - 3.84 - 3.7 - V -7.8 6 5.48 - - 5.34 - 5.2 - V 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.1 V - - - - - - - - - V -6 4.5 - - 0.26 - 0.33 - 0.4 V -7.8 6 - - 0.26 - 0.33 - 0.4 V - 6 - - ±0.1 - ±1 - ±1 µA 3 CD74HC253, CD74HCT253 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) ICC VCC or GND 0 6 - - 8 - 80 - 160 µA High Level Input Voltage VIH - - 4.5 to 5.5 2 - - 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V High Level Output Voltage CMOS Loads VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V PARAMETER Quiescent Device Current MIN TYP MAX MIN MAX MIN MAX UNITS HCT TYPES High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads VOL VIH or VIL Low Level Output Voltage TTL Loads II VCC and GND 0 5.5 - - ±0.1 - ±1 - ±1 µA ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA Additional Quiescent Device Current Per Input Pin: 1 Unit Load ∆ICC (Note) VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA Three-State Leakage Current IOZ VIL or VIH VO = VCC or GND 5.5 - - ±0.5 - ±5 - ±10 µA Input Leakage Current Quiescent Device Current NOTE: For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA. HCT Input Loading Table INPUT UNIT LOADS 1IO - 1I3, 2IO-2l3 0.4 1EO, 2EO, S0, S1 1 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g., 360µA max at 25oC. Switching Specifications Input tr, tf = 6ns PARAMETER TEST SYMBOL CONDITIONS -40oC TO 85oC 25oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 175 - 220 - 265 ns 4.5 - - 35 - 44 - 53 ns CL =15pF 5 - 14 - - - - - ns CL = 50pF 6 - - 30 - 37 - 45 ns HC TYPES Propagation Delay Select to Outputs tPLH, tPHL CL = 50pF 4 CD74HC253, CD74HCT253 Switching Specifications Input tr, tf = 6ns PARAMETER Data to Outputs Disable Delay Times Enable Delay Times Output Transition Times Input Capacitance (Continued) TEST SYMBOL CONDITIONS tPLH, tPHL -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 175 - 220 - 265 ns 4.5 - - 35 - 44 - 53 ns CL =15pF 5 - 14 - - - - - ns CL = 50pF 6 - - 30 - 37 - 45 ns tPHZ, tPLZ CL = 50pF 2 - - 150 - 190 - 225 ns CL = 50pF 4.5 - - 30 - 38 - 45 ns CL = 15pF 5 - 12 - - - - - ns CL = 50pF 6 - - 26 - 33 - 38 ns CL = 50pF 2 - - 110 - 140 - 165 ns CL = 50pF 4.5 - - 22 - 28 - 33 ns CL = 15pF 5 - 9 - - - - - ns tPZH, tPZL CL = 50pF -40oC TO 85oC 25oC CL = 50pF 6 - - 19 - 24 - 28 ns tTLH, tTHL CL = 50pF 2 - - 60 - 75 - 90 ns 4.5 - - 12 - 15 - 18 ns 6 - - 10 - 13 - 15 ns - - - 10 - 10 - 10 pF CI - Three-State Output Capacitance CO - - - - 20 - 20 - 20 pF Power Dissipation Capacitance (Notes 4, 5) CPD - 5 - 46 - - - - - pF CL = 50pF 4.5 - - 40 - 50 - 60 ns CL =15pF 5 - 16 - - - - ns tPLH, tPHL CL = 50pF 4.5 - - 38 - 48 - 57 ns CL =15pF 5 - 16 - - - - - ns tPLH, tPHL CL = 50pF 4.5 - 30 - 38 - 45 ns CL =15pF 5 - 12 - - - - - ns tPZH, tPZL CL = 50pF 4.5 - - 30 - 38 - 45 ns HCT TYPES Propagation Delay Select to Outputs Data to Outputs Disable Delay Times Enable Delay Times Output Transition Time tPLH, tPHL CL =15pF tTLH, tTHL CL = 50pF 5 - 12 - - - - - ns 4.5 - - 12 - 15 - 18 ns Input Capacitance CIN - - - - 10 - 10 - 10 pF Three-State Output Capacitance CO - - - - 20 - 20 - 20 pF Power Dissipation Capacitance (Notes 4, 5) CPD - 5 - 52 - - - - - pF NOTES: 4. CPD is used to determine the dynamic power consumption, per multiplexer. 5. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. 5 CD74HC253, CD74HCT253 Test Circuits and Waveforms tr = 6ns tf = 6ns 90% 50% 10% INPUT GND tTLH tPHL 6ns 10% 2.7 1.3 OUTPUT LOW TO OFF 90% OUTPUT HIGH TO OFF 50% OUTPUTS DISABLED FIGURE 3. HC THREE-STATE PROPAGATION DELAY WAVEFORM OTHER INPUTS TIED HIGH OR LOW OUTPUT DISABLE IC WITH THREESTATE OUTPUT GND 1.3V tPZH 90% OUTPUTS ENABLED OUTPUTS ENABLED 0.3 10% tPHZ tPZH 3V tPZL tPLZ 50% OUTPUTS ENABLED 6ns GND 10% tPHZ tf OUTPUT DISABLE tPZL tPLZ OUTPUT HIGH TO OFF 6ns tr VCC 90% tPLH FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 6ns OUTPUT LOW TO OFF 1.3V 10% INVERTING OUTPUT FIGURE 1. HC AND HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 50% tTLH 90% tPLH tPHL GND tTHL 90% 50% 10% INVERTING OUTPUT 3V 2.7V 1.3V 0.3V INPUT tTHL OUTPUT DISABLE tf = 6ns tr = 6ns VCC 1.3V OUTPUTS DISABLED OUTPUTS ENABLED FIGURE 4. HCT THREE-STATE PROPAGATION DELAY WAVEFORM OUTPUT RL = 1kΩ CL 50pF VCC FOR tPLZ AND tPZL GND FOR tPHZ AND tPZH NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1kΩ to VCC, CL = 50pF. FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT 6 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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