NPC SM5902

SM5902AF
compression and non compression type
shock-proof memory controller
NIPPON PRECISION CIRCUITS INC.
Overview
The SM5902 is a compression and non compression type shock-proof memory controller LSI for
compact disc players. The compression level can
be set in 4 levels, and external memory can be
selected from 4 options (1M, 4M, 4M× 2, 16M).
Digital attenuator, soft mute and related functions
are also incorporated. It operates from a 2.4 to 5.5
V wide supply voltage range.
Features
- 2-channel processing
- Serial data input
⋅ 2s complement, 16-bit/MSB first, right-justified
format
⋅ Wide capture function
(up to 3 × speed input rate)
- System clock input
⋅ 384fs (16.9344 MHz)
- Shock-proof memory controller
⋅ ADPCM compression method
⋅ 4-level compression mode selectable
4-bit compression mode 2.78 s/Mbit
5-bit compression mode 2.22 s/Mbit
6-bit compression mode 1.85 s/Mbit
Full-bit non compression mode 0.74 s/Mbit
⋅ 4 external DRAM configurations selectable
1 × 16M DRAM (4M × 4 bits, refresh cycle =
2048 cycle)
1 × or 2 × 4M DRAM (1M × 4 bits)
1 × 1M DRAM (256k × 4 bits)
⋅ DRAM at 5V operation is usable for Low-voltage operation
- Compression mode selectable
- Microcontroller interface
⋅ Serial command write and status read-out
⋅ Data residual detector:
15-bit operation, 16-bit output
⋅ Digital attenuator
8-bit setting
⋅ Soft attenuator function
Noiseless attenuation-level switching
(256- step switching in 23 ms max.)
⋅ Soft mute function
Mute ON in 23 ms max.
Direct return after soft mute release
⋅ Forced mute
- Extension I/O
Microcontroller interface for external control
using 5 extension I/O pins
- +2.4 to +5.5 V wide operating voltage range
- Schmitt inputs
All input pins (including I/O pins) except CLK
(system clock)
- Reset signal noise elimination
Approximately 3.8 µs or longer (65 system
clock pulses) continuous LOW-level reset
- Digital audio interface (DIT)
- 44-pin QFP package (0.8 mm pin pitch)
Ordering Information
SM5902AF
44pin QFP
NIPPON PRECISION CIRCUITS-1
SM5902AF
Package dimensions (Unit: mm)
44-pin QFP 1
12.80 + 0.30
10.00 + 0.30
10.00 + 0.30
0 to 10
12.80 + 0.30
(1.40)
0.60 + 0.20
0.80
0.35 + 0.10
0.15
+ 0.20
1.55 0.10
0.10 + 0.10
0.17 + 0.05
(1.45)
0.20 M
44-pin QFP 2
12.80 0.30
10.00 0.30
10.00 0.30
(1.40)
0 to 10
12.80 0.30
0.17 0.05
4
C0
0.80
0.60 0.20
0.20
1.50 0.10
(1.40)
0.10
0.10 0.05
.7
0.15
0.35 0.10
0.20 M
A3
A2
A1
A0
A4
A5
A6
A7
A8
A9
NRAS
44
43
42
41
40
39
38
37
36
35
34
Pinout (Top View)
1
33
NWE
UC1
2
32
D1
UC2
3
31
D0
UC3
4
30
D3
UC4
5
29
D2
UC5
6
28
NCAS
DIT
7
27
A10/ NCAS2
NTEST
8
26
YMCLK
CLK
9
25
YMDATA
VSS
10
24
YMLD
YSRDATA
11
23
YDMUTE
20
21
22
ZSENSE
VDD1
17
YFLAG
NRESET
16
ZSRDATA
19
15
ZLRCK
18
14
ZSCK
YFCLK
13
YSCK
YBLKCK
12
YLRCK
SM5 9 0 2 A F
VDD2
NIPPON PRECISION CIRCUITS-2
SM5902AF
Pin description
Pin number
Pin name
I/O
Function
Setting
H
1
VDD2
-
VDD supply pin
2
UC1
Ip/O
Microcontroller interface extension I/O 1
3
UC2
Ip/O
Microcontroller interface extension I/O 2
4
UC3
Ip/O
Microcontroller interface extension I/O 3
5
UC4
Ip/O
Microcontroller interface extension I/O 4
6
UC5
Ip/O
Microcontroller interface extension I/O 5
7
DIT
O
Digital audio interface
8
NTEST
Ip
Test pin
9
CLK
I
16.9344 MHz clock input
10
VSS
-
Ground
11
YSRDATA
I
Audio serial input data
12
YLRCK
I
Audio serial input LR clock
13
YSCK
I
Audio serial input bit clock
14
ZSCK
O
Audio serial output bit clock
Test
15
ZLRCK
O
Audio serial output LR clock
16
ZSRDATA
O
Audio serial output data
17
YFLAG
I
Signal processor IC RAM overflow flag
18
YFCLK
I
Crystal-controlled frame clock
19
YBLKCK
I
Subcode block clock signal
20
NRESET
I
System reset pin
21
ZSENSE
O
Microcontroller interface status output
22
VDD1
-
VDD supply pin
23
YDMUTE
I
Forced mute pin
24
YMLD
I
Microcontroller interface latch clock
25
YMDATA
I
Microcontroller interface serial data
26
YMCLK
I
Microcontroller interface shift clock
A10
O
DRAM address 10
(NCAS2)
O
DRAM2 CAS control (with 2 DRAMs)
27
28
NCAS
O
DRAM CAS control
29
D2
I/O
DRAM data input/output 2
30
D3
I/O
DRAM data input/output 3
31
D0
I/O
DRAM data input/output 0
32
D1
I/O
DRAM data input/output 1
33
NWE
O
DRAM WE control
34
NRAS
O
DRAM RAS control
35
A9
O
DRAM address 9
36
A8
O
DRAM address 8
37
A7
O
DRAM address 7
38
A6
O
DRAM address 6
39
A5
O
DRAM address 5
40
A4
O
DRAM address 4
41
A0
O
DRAM address 0
42
A1
O
DRAM address 1
43
A2
O
DRAM address 2
44
A3
O
DRAM address 3
Ip : Input pin with pull-up resistor
L
Left channel
Right channel
Left channel
Right channel
Overflow
Reset
Mute
Ip/O : Input/Output pin (With pull-up resistor when in input mode)
NIPPON PRECISION CIRCUITS-3
SM5902AF
Absolute maximum ratings
(VSS = 0V, VDD1, VDD2 pin voltage = VDD)
Rating
Unit
Parameter
Symbol
Supply voltage
VDD
- 0.3 to 7.0
Input voltage
VI
VSS - 0.3 to VDD + 0.3
V
Storage temperature
TSTG
- 55 to 125
˚C
V
Power dissipation
PD
350
mW
Soldering temperature
TSLD
255
˚C
Soldering time
tSLD
10
sec
(*1) Refer to pin summary on the next page.
Note. Values also apply for supply inrush and switch-off.
Electrical characteristics
Recommended operating conditions
(VSS = 0V, VDD1, VDD2 pin voltage = VDD)
Parameter
Symbol
Rating
Unit
Supply voltage
VDD
2.4 to 5.5
V
Operating temperature
TOPR
- 40 to 85
˚C
DC characteristics
Standard voltage: (VDD1 = VDD2 = 4.5 to 5.5 V, VSS = 0 V, Ta = - 40 to 85 ˚C)
Parameter
Pin
Symbol
Condition
Rating
Min
Current consumption
Input voltage
VDD
CLK
IDD
H level
VIH1
L level
VIL1
VINAC
Output voltage
Input leakage current
Max
(*A)SHPRF ON
13.5
25.0
mA
(*A)Through mode
5.0
7.5
mA
0.7VDD
AC coupling
H level
L level
VIL2
(*5)
H level
VIH3
L level
VIL3
(*4,6)
H level
VOH1
L level
VOL1
IOL = 0.5 mA
(*5,7)
H level
VOH2
IOH = - 0.5 mA
VOL2
IOL = 0.5 mA
CLK
V
0.3VDD
(*2,3,4)
VIH2
0.3
VP-P
0.7VDD
V
0.3VDD
0.6VDD
V
V
0.2VDD
IOH = - 0.5 mA
V
VDD - 0.4
V
V
0.4
VDD - 0.4
V
V
0.4
V
IIH1
VIN = VDD
40
95
190
µA
L level
Input current
Unit
Typ
IIL1
VIN = 0V
40
95
190
µA
(*3,4)
IIL2
VIN = 0V
6
12
25
µA
(*2,3,4,5)
ILH
VIN = VDD
1.0
µA
(*2,5)
ILL
VIN = 0V
1.0
µA
(*A) VDD1 = VDD2 = 5 V, CLK input frequency fXTI= 384fs = 16.9344 MHz, all outputs unloaded,
SHPRF: Shock-proof,
typical values are for VDD1 = VDD2 = 5 V.
NIPPON PRECISION CIRCUITS-4
SM5902AF
Low-voltage:(VDD1 = VDD2 = 2.4 to 4.5 V, VSS = 0 V, Ta = - 20 to 70 ˚C)
Parameter
Pin
Symbol
Condition
Rating
Min
Current consumption
Input voltage
VDD
CLK
IDD
H level
VIH1
L level
VIL1
Input leakage current
(*B)SHPRF ON
6.0
12.0
mA
(*B)Through mode
2.5
4.0
mA
AC coupling
H level
L level
VIL2
(*5)
H level
VIH3
L level
VIL3
(*4,6)
H level
VOH1
L level
VOL1
IOL = 0.5 mA
(*5,7)
H level
VOH2
IOH = - 0.5 mA
VOL2
IOL = 0.5 mA
CLK
V
0.3VDD
(*2,3,4)
VIH2
L level
Input current
Max
0.7VDD
VINAC
Output voltage
Unit
Typ
0.3
VP-P
0.7VDD
V
0.3VDD
0.6VDD
IIH1
VIN = VDD
V
V
0.2VDD
IOH = - 0.5 mA
V
VDD - 0.4
V
V
0.4
VDD - 0.4
V
V
0.4
V
10
30
115
µA
IIL1
VIN = 0V
10
30
115
µA
(*3,4)
IIL2
VIN = 0V
1.5
3
15
µA
(*2,3,4,5)
ILH
VIN = VDD
1.0
µA
(*2,5)
ILL
VIN = 0V
1.0
µA
(*B) VDD1 = VDD2 = 3 V, CLK input frequency fXTI= 384fs = 16.9344 MHz, all outputs unloaded,
SHPRF: Shock-proof,
typical values are for VDD1 = VDD2 = 3 V.
<Pin summary>
(*1)
(*2)
Pin function
Clock input pin (AC input)
Pin name
CLK
Pin function
Schmitt input pins
Pin name
YSRDATA, YLRCK, YSCK, YFLAG, YFCLK, NRESET,
YBLKCK, YDMUTE, YMLD, YMDATA, YMCLK
(*3)
Pin function
Schmitt input pin with pull-up
Pin name
NTEST
(*4)
Pin function
I/O pins (Schmitt input with pull-up in input state)
Pin name
UC1, UC2, UC3, UC4, UC5
(*5)
Pin function
I/O pins (Schmitt input in input state)
Pin name
D0, D1, D2, D3
(*6)
Pin function
Outputs
Pin name
ZSCK, ZLRCK, ZSRDATA, ZSENSE, DIT
(*7)
Pin function
Outputs
Pin name
NCAS, NWE, NRAS, A0, A1, A2, A3, A4, A5, A6, A7, A8, A9,A10
NIPPON PRECISION CIRCUITS-5
SM5902AF
AC characteristics
Standard voltage: VDD1 = VDD2 = 4.5 to 5.5 V, VSS = 0 V, Ta = -40 to 85 ˚C
Low-voltage: VDD1 = VDD2 = 2.4 to 4.5 V, VSS = 0 V, Ta = -20 to 70 ˚C
(*) Typical values are for fs = 44.1 kHz
System clock (CLK pin)
Parameter
Symbol
Clock pulsewidth (HIGH level)
tCWH
tCWL
tCY
Condition
Rating
System clock
Clock pulsewidth (LOW level)
Clock pulse cycle
384fs
Unit
Min
Typ
Max
26
29.5
125
ns
26
29.5
125
ns
56
59
250
ns
System clock input
CLK
0.5VDD
t CWH
t CWL
t CY
Serial input (YSRDATA, YLRCK, YSCK pins)
Parameter
Symbol
Rating
Min
YSCK pulsewidth (HIGH level)
YSCK pulsewidth (LOW level)
YSCK pulse cycle
YSRDATA setup time
YSRDATA hold time
Last YSCK rising edge to YLRCK edge
YLRCK edge to first YSCK rising edge
tBCWH
tBCWL
tBCY
tDS
tDH
tBL
tLB
Typ
Unit
Condition
Max
75
ns
75
ns
150
ns
50
ns
50
ns
50
ns
50
ns
0
3fs
Memory system ON
fs
fs
Memory system OFF
YLRCK pulse frequency
(MSON=H)
See note below.
(MSON=L)
Note. When the memory system is OFF (through mode), the input data rate is synchronized to the system clock input (384fs), so input
data needs to be at 1/384 of this frequency. But, this IC can tolerate a certain amount of jitter. For details, refer to Through-mode
operation.
t BCWH
t BCY
t BCWL
YSCK
0.5VDD
t DS
t DH
YSRDATA
0.5VDD
t BL
YLRCK
t LB
0.5VDD
NIPPON PRECISION CIRCUITS-6
SM5902AF
Microcontroller interface (YMCLK, YMDATA, YMLD, ZSENSE pins)
Parameter
Symbol
YMCLK LOW-level pulsewidth
tMCWL
tMCWH
tMDS
tMDH
tMLWL
tMLS
tMLH
tr
tf
tPZS
Rating
Min
YMCLK HIGH-level pulsewidth
YMDATA setup time
YMDATA hold time
YMLD LOW-level pulsewidth
YMLD setup time
YMLD hold time
Rise time
Fall time
ZSENSE output delay
Unit
Typ
Max
30 + 2tCY
ns
30 + 2tCY
ns
30 + tCY
ns
30 + tCY
ns
30 + 2tCY
ns
30 + tCY
ns
30 + tCY
ns
100
ns
100
ns
100 + 3tCY
ns
Note. tCY is the system clock cycle time (59ns typ).
YMDATA
0.5VDD
t MDS
t MDH
YMCLK
0.5VDD
t MCWL
t MCWH
t MLS
t MLH
YMLD
0.5VDD
t MLWL
t PZS
ZSENSE
0.5VDD
tf
YMCLK
YMDATA
YMLD
tr
0.7 V DD
0.7 V DD
0.3 V DD
0.3 V DD
0.5VDD
Reset input (NRESET pin)
Parameter
Symbol
First HIGH-level after supply voltage rising edge
tHNRST
tNRST
Rating
Min
NRESET pulsewidth
0
64
Typ
Unit
Max
tCY (Note)
tCY (Note)
Note. tCY is the system clock (CLK) input (384fs) cycle time.
tCY = 59 ns, tNRST (min) = 3.8 µs when fs = 44.1 kHz
VDD
NRESET
t HNRST
t NRST
NIPPON PRECISION CIRCUITS-7
SM5902AF
Serial output (ZSRDATA, ZLRCK, ZSCK pins)
Parameter
Symbol
Condition
Rating
Min
ZSCK pulsewidth
ZSCK pulse cycle
ZSRDATA and ZLRCK output delay time
tSCOW
tSCOY
tDHL
tDLH
Unit
Typ
Max
15 pF load
1/96fs
15 pF load
1/48fs
15 pF load
0
60
ns
15 pF load
0
60
ns
ZSCK
0.5VDD
t SCOW
t SCOW
t SCOY
ZSRDATA
ZLRCK
0.5VDD
t DHL
t DLH
DRAM access timing (NRAS, NCAS, NCAS2, NWE, A0 to A10, D0 to D3)
Parameter
Symbol
Condition
NRAS pulsewidth
tRASL
tRASH
tRCD
tCASH
tCASL
tRADS
tRADH
tCADS
tCADH
tCWDS
tCWDH
tCRDS
tCRDH
tWEL
tWCS
15 pF load
Rating
Min
NRAS falling edge to NCAS falling edge
NCAS pulsewidth
NRAS
Setup time
falling edge to address
Hold time
NCAS
Setup time
falling edge to address
Hold time
NCAS
Setup time
falling edge to data write
Hold time
NCAS
Input setup
rising edge to data read
Input hold
NWE pulsewidth
NWE falling edge to NCAS falling edge
Refresh cycle
15 pF load
tREF
(RDEN=H)
3
2
5
15 pF load
3
15 pF load
1
15 pF load
1
15 pF load
1
15 pF load
5
15 pF load
3
15 pF load
3
40
ns
0
ns
15 pF load
6
15 pF load
3
tCY
tCY
1.5
ms
6-bit compression
3.7
ms
DRAM 5-bit compression
4.4
ms
4-bit compression
5.5
ms
Non compression
3.0
ms
6-bit compression
7.3
ms
DRAM 5-bit compression
8.8
ms
× 1 or × 2 4-bit compression
10.9
ms
Non compression
5.9
ms
6-bit compression
14.6
ms
DRAM 5-bit compression
17.5
ms
21.8
ms
×1
Memory system ON
Decode sequence operation
tCY(note)
tCY
tCY
tCY
tCY
tCY
tCY
tCY
tCY
tCY
tCY
Non compression
1M
(fs = 44.1 kHz playback)
Max
5
15 pF load
15 pF load
Typ
Unit
4M
16M
×1
4-bit compression
Note. tCY is the system clock (CLK) input (384fs) cycle time. tCY = 59 ns when fs = 44.1 kHz
NIPPON PRECISION CIRCUITS-8
SM5902AF
DRAM access timing (with single DRAM)
t RASL
5 tCY
t RASH
3 tCY
NRAS
t RCD
2tCY
t CASH
5tCY
t CASL
3 tCY
NCAS
,,,,,,,
A0 to A10 ,,,,,,,
,,,,,,,
,,,,,,,
,,,,,,,
t RADS
1tCY
t RADH
1tCY
t CADS
1tCY
t CADH
5tCY
t CWDS
3tCY
,,,,,,,,,,,,
,,,,,,,,,
,,,,,,,,,,,,
,,,,,,,,,
,,,,,,,,,,,,
,,,,,,,,,
,,,,,,,,,,,,
,,,,,,,,,
,,,,,,,,,,,,
,,,,,,,,,
t CWDH
3tCY
,,,,,,,,,,,,,,
,,,,,,,,,,,,,,
,,,,,,,,,,,,,,
,,,,,,,,,,,,,,
,,,,,,,,,,,,,,
D0 to D3
(WRITE)
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
D0 to D3 ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
(READ) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
t WCS
3tCY
t CRDS
t CRDH
,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,
t WEL
6tCY
NWE
(WRITE)
The NWE terminal output is fixed HIGH during read timing.
DRAM access timing (with 2 DRAMs)
t RASL
5 tCY
t RASH
3tCY
NRAS
NCAS
(DRAM1 SELECT)
NCAS2
(DRAM2 SELECT)
A0 to A9
,,,,,,,
,,,,,,,
,,,,,,,
,,,,,,,
,,,,,,,
t RADS
1tCY
t CASL
3tCY
t CASH
5tCY
t RDC
2 tCY
t CASL
3tCY
t CASH
5tCY
t CADS
1tCY
t CWDS
3tCY
D0 to D3
(WRITE)
D0 to D3
(READ)
t RADH
1tCY
t RCD
2tCY
t CADH
5tCY
,,,,,,,,,,,
,,,,,,,,,
,,,,,,,,,,,
,,,,,,,,,
,,,,,,,,,,,
,,,,,,,,,
,,,,,,,,,,,
,,,,,,,,,
,,,,,,,,,,,
,,,,,,,,,
t CWDH
3tCY
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
t
t CRDS
t CRDH
WCS
NWE
(WRITE)
3 tCY
t WCS
,,,,,,,,,,,,,,
,,,,,,,,,,,,,,
,,,,,,,,,,,,,,
,,,,,,,,,,,,,,
,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,
t WEL
6 tCY
The NWE terminal output is fixed HIGH during read timing.
NCAS terminal output is fixed HIGH when selecting "DRAM2".
NCAS2 terminal output is fixed HIGH when selecting "DRAM1".
NIPPON PRECISION CIRCUITS-9
SM5902AF
DIT Interface (DIT pin)
Parameter
Symbol
Condition
Rating
Min
0 data H level
0 data L level
1 data H level
1 data L level
tDI0H
tDI0L
tDI1H
tDI1L
Typ
15 pF load
6
15 pF load
6
15 pF load
3
15 pF load
3
Unit
Max
tCY(Note)
tCY
tCY
tCY
Note. tCY is the system clock (CLK) input (384fs) cycle time. tCY = 59 ns when fs = 44.1 kHz.
0.5VDD
DIT
tDI0H
6tCY
tDI0L
6tCY
tDI1H tDI1L
3tCY 3tCY
NIPPON PRECISION CIRCUITS-10
SM5902AF
YBLKCK
YFCLK
YSRDATA
YSCK
YLRCK
ZSRDATA
ZSCK
SM5902
ZLRCK
Block diagram
Output Interface
Input Interface
Attenuator
Input Buffer
Control
Input 1
YFLAG
YMDATA
YMCLK
YMLD
Microcontroller
Interface
ZSENSE
DIT
Compression
Mode
UC1 to UC5
Through
Mode
General
Port
Decoder
Encoder
YDMUTE
Control
Input 2
D0 to D3
A0 to A10
NCAS
NRAS
CLK
NWE
DRAM Interface
NTEST
NCAS2
NRESET
NIPPON PRECISION CIRCUITS-11
SM5902AF
Functional description
SM5902AF has two modes of operation; shockproof mode and through mode.
The operating sequences are controlled using commands from a microcontroller.
Microcontroller interface
Commands from the microcontroller are input using
3-wire serial interface inputs; data (YMDATA), bit
clock (YMCLK) and load signal (YMLD).
In the case of a read command from the microcontroller, bit serial data is output (ZSENSE) synchronized to the bit clock input (YMCLK).
Write command format (Commands 80 to 86)
DATA 8bit
YMDATA
D7
D6
D5
D4
D3
COMMAND 8bit
D2
D1
D0
B7
B6
B5
B4
B3
B2
B1
B0
B1
B0
YMCLK
YMLD
Write command format (Commands 87)
DATA 12bit
YMDATA
D11 D10
D4
D3
COMMAND 8bit
D2
D1
D0
B1
B0
B7
B6
B5
B4
S7
S6
S5
B3
B2
YMCLK
YMLD
Read command format (Commands 90, 91, 93)
COMMAND 8bit
YMDATA
B7
B6
B5
B4
B3
B2
YMCLK
YMLD
STATUS 8bit
ZSENSE
S4
S3
S2
S1
S0
Read command format (Command 92 (memory residual read))
COMMAND 8bit
YMDATA
B7
B6
B5
B4
B3
B2
B1
B0
YMCLK
YMLD
RESIDUAL DATA 16bit
ZSENSE
S7
S6
S1
S0
M1 M2
M7
M8
NIPPON PRECISION CIRCUITS-12
SM5902AF
Command table
Write command summary
B3
B2
B1
B0
B7
B6
B5
B4
MS command 80
80hex = 1000 0000
Shock-proof memory system settings
Bit
Name
Function
H operation Reset level
D7
MSWREN
Encode sequence start/stop
Start
L
D6
MSWACL
Write address reset
Reset
L
D5
MSRDEN
Decode sequence start/stop
Start
L
D4
MSRACL
Read address reset
Reset
L
D3
MSDCN2
MSDCN2=H, MSDCN1=H: 3-pair comparison start
L
MSDCN2=H, MSDCN1=L: 2-pair comparison start
D2
MSDCN1
MSDCN2=L, MSDCN1=H: Direct-connect start
L
D1
WAQV
Q data valid
Valid
L
D0
MSON
Memory system ON
ON
L
MSDCN2=L, MSDCN1=L: Connect operation stop
81hex = 1000 0001
Extension I/O port input/output settings
Bit
B3
B2
B1
B0
B7
B6
B5
B4
Extension I/O settings 81
Name
Function
D4
UC5OE
Extension I/O port UC5 input/output setting
Output
L
D3
UC4OE
Extension I/O port UC4 input/output setting
Output
L
D2
UC3OE
Extension I/O port UC3 input/output setting
Output
L
D1
UC2OE
Extension I/O port UC2 input/output setting
Output
L
D0
UC1OE
Extension I/O port UC1 input/output setting
Output
L
H operation Reset level
D7
D6
D5
B7
B6
B5
B4
Extension port HIGH/LOW output level
A port setting is invalid if that port has already been defined as an input using the 81H command above.
Bit
B3
B2
B1
B0
Extension I/O output data settings 82
82hex = 1000 0010
Name
Function
D4
UC5WD
Extension I/O port UC5 output data setting
H output
L
D3
UC4WD
Extension I/O port UC4 output data setting
H output
L
D2
UC3WD
Extension I/O port UC3 output data setting
H output
L
D1
UC2WD
Extension I/O port UC2 output data setting
H output
L
D0
UC1WD
Extension I/O port UC1 output data setting
H output
L
H operation Reset level
D7
D6
D5
NIPPON PRECISION CIRCUITS-13
SM5902AF
B3
B2
B1
B0
B7
B6
B5
B4
ATT, MUTE settings 83
83hex = 1000 0011
Bit
Name
Function
H operation
Reset level
D7
ATT
Attenuator enable
Attenuator ON
L
D6
MUTE
Forced muting (changes instantaneously)
Mute ON
L
D5
SOFT
Soft muting (changes smoothly when ON only)
Soft mute
L
D4
NS
Includes noise shaper function when encoding
NS ON
L
D3
CMP12
12-bit comparison connect/ 16-bit comparison connect
12-bit comparison
L
D2
D1
D0
Refer to "Attenuation", "Soft mute", "Force mute", "12-bit comparison connection".
B3
B2
B1
B0
B7
B6
B5
B4
Attenuation level settings 84
84hex = 1000 0100
Bit
Name
Function
D7
K7
MSB 2-1
L
D6
K6
-2
2
H
D5
K5
2
-3
L
D4
K4
2
-4
L
-5
H operation Reset level
D3
K3
2
L
D2
K2
2-6
L
D1
K1
2
-7
L
D0
K0
LSB 2
-8
L
Refer to "Attenuation", "Soft mute", "Force mute".
B3
B2
B1
B0
B7
B6
B5
B4
Option settings 85
85hex = 1000 0101
Bit
Name
Function
D7
RAMS1
DRAM type setting
H operation Reset level
L
RAMS1=0 RAMS2=0 when 1MDRAM(256k × 4bit) × single
RAMS1=1 RAMS2=0 when 4MDRAM(1M × 4bit) × single
D6
RAMS2
RAMS1=0 RAMS2=1 when 4MDRAM(1M × 4bit) × double
L
RAMS1=1 RAMS2=1 when 16MDRAM(4M × 4bit) × single
D5
YFLGS
FLAG6 set conditions (reset using status read command 90H)
L
- When YFLGS=0, YFCKP=0, YFCLK input falling edge, YFLAG=L
- When YFLGS=0, YFCKP=1, YFCLK input rising edge, YFLAG=L
D4
YFCKP
- When YFLGS=1, YFCKP=0, YFLAG=L
L
- When YFLGS=1, YFCKP=1, YFLAG=H
D3
COMPFB
Full-bit compression mode
L
D2
COMP6B
6-bit compression mode
H
D1
COMP5B
5-bit compression mode
L
D0
COMP4B
4-bit compression mode
L
When the number of compression bits is set incorrectly (2 or more bits in D0 to D3 are set to 1 or all bits are set to 0),
6-bit compression mode is selected.
NIPPON PRECISION CIRCUITS-14
SM5902AF
B3
B2
B1
B0
B7
B6
B5
B4
Digital Audio Interface settings 86
86hex = 1000 0110
Bit
Name
Function
D7
CP1
Channel status and clock accuracy setting
H operation Reset level
L
CP1= 0, CP2= 0 Level 2 (max ± 300 ppm)
D6
CP2
CP1= 0, CP2= 1 Level 3 (max ± 10 %)
L
CP1= 1, CP2= 0 Level 1 (max ± 50 ppm)
CP1= 1, CP2= 1 Not supported
D5
LBIT
Digital audio signal generation logic. 0 = post-recording software
Unassigned
L
D4
DIT
Digital audio interface (DIT) enable. 0 = DIT output LOW
DIT= ON
L
D3
D2
D1
D0
B3
B2
B1
B0
B7
B6
B5
B4
Sub code Q data settings 87
87hex = 1000 0111
Bit
Name
Function
D11
QAD3
Q data setting and word address specification
L
D10
QAD2
QAD3 (MSB) to QAD0 (LSB) specify one of 10 valid addresses in the range 0000 to 1001.
L
D9
QAD1
* If an address in the range 1010 to 1111 is specified, the data on QD7 to QD0 is ignored.
L
D8
QAD0
L
D7
QD7
Note that writing to address 1001 also functions as the write stop command.
MSB
Q data setting ward data
Indefined
D6
QD6
Q data setting ward data
Indefined
D5
QD5
Q data setting ward data
Indefined
D4
QD4
Q data setting ward data
Indefined
D3
QD3
Q data setting ward data
Indefined
D2
QD2
Q data setting ward data
Indefined
D1
QD1
Q data setting ward data
Indefined
D0
QD0
Q data setting ward data
Indefined
LSB
H operation Reset level
Adderss map for Q data setting beuffer
QAD3
QAD2
QAD1
QAD0
QD7
QD6
QD5
QD4
QD3
QD2
QD1
QD0
0
0
0
0
CTL0
CTL1
CTL2
CTL3
ADR3
ADR2
ADR1
ADR0
0
0
0
1
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
0
0
1
0
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
0
0
1
1
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
0
1
0
0
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
0
1
0
1
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
0
1
1
0
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
0
1
1
1
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
1
0
0
0
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ64
1
0
0
1
DQ65
DQ66
DQ67
DQ68
DQ69
DQ70
DQ71
DQ72
When shockproof mode is ON, the Q data is specified according to the data output from the SM5902AF.
NIPPON PRECISION CIRCUITS-15
SM5902AF
Read command summary
B3
B2
B1
B0
B7
B6
B5
B4
Shock-proof memory status (1) 90
90hex = 1001 0000
Bit
Name
Function
S7
FLAG6
Signal processor IC jitter margin exceeded
HIGH-level state
Exceeded
S6
MSOVF
Write overflow (Read once only when RA exceeds WA)
DRAM overflow
S5
BOVF
Input buffer memory overflow
Input buffer memory overflow
because sampling rate of input data is too fast
S4
S3
DCOMP
Data compare-connect sequence operating
S2
MSWIH
Encode sequence stop due to internal factors
Compare-connect sequence operating
Encoding stopped
S1
MSRIH
Decode sequence stop due to internal factors
Decoding stopped
S0
Refer to "Status flag operation summary".
B3
B2
B1
B0
B7
B6
B5
B4
Shock-proof memory status (2) 91
91hex = 1001 0001
Bit
Name
Function
HIGH-level state
S7
MSEMP
Valid data empty state (Always HIGH when RA exceeds VWA)
No valid data
S6
OVFL
Write overflow state (Always HIGH when WA exceeds RA)
Memory full
S5
ENCOD
Encode sequence operating state
Encoding
S4
DECOD
Decode sequence operating state
Decoding
S3
QRDY
Subcode Q data write-buffer write enable
Write enabled
S2
S1
S0
Refer to "Status flag operation summary".
NIPPON PRECISION CIRCUITS-16
SM5902AF
B3
B2
B1
B0
B7
B6
B5
B4
Shock-proof memory valid data residual 92
92hex = 1001 0010
Bit
Name
Function
S7
AM21
Valid data accumulated VWA-RA (MSB) 8M bits
S6
AM20
4M bits
S5
AM19
2M bits
S4
AM18
1M bits
S3
AM17
512k bits
S2
AM16
256k bits
S1
AM15
S0
AM14
128k bits
64k bits
M1
AM13
32k bits
M2
AM12
16k bits
M3
AM11
8k bits
M4
AM10
4k bits
M5
AM09
2k bits
M6
AM08
M7
AM07
M8
AM06
1k bits
512 bits
256 bits
Note. The time conversion factor varies depending on the compression bit mode.(M = 1,048,576 K= 1,024)
Residual time (sec) = Valid data residual (Mbits) × Time conversion value K
where the Time conversion value K (sec/Mbit) ≈ 2.78 (4 bits), 2.22 (5 bits), 1.85 (6 bits) and 0.74 (Full bits).
Bit
Name
Function
B3
B2
B1
B0
Input data entering (or output data from) an extension port terminal is echoed to the microcontroller.
(That is, the input data entering an I/O port configured as an input port using the 81H command,
OR the output data from a pin configured as an output port using the 82H command.)
B7
B6
B5
B4
Extension I/O inputs 93
93hex = 1001 0011
HIGH-level state
S7
S6
S5
S4
UC5RD
S3
UC4RD
S2
UC3RD
S1
UC2RD
S0
UC1RD
NIPPON PRECISION CIRCUITS-17
SM5902AF
Status flag operation summary
Flag
Read
name
method
FLAG6
READ
Meaning
90H
bit 7
- Indicates to the CD signal processor DSP (used for error correction, de-interleaving) that a
disturbance has exceeded the RAM jitter margin.
Set
- Set according to the YFLAG input and the operating state of YFCKP and YFLGS.
FLAG6 set conditions
When YFLGS=0, YFCKP=0, YFCLK input falling edge, YFLAG=L
When YFLGS=0, YFCKP=1, YFCLK input rising edge, YFLAG=L
When YFLGS=1, YFCKP=0, YFLAG=L
When YFLGS=1, YFCKP=1, YFLAG=H
Reset
- By 90H status read
- By 80H command when MSON=ON
- After external reset
MSOVF
READ
Meaning
90H
bit 6
- Indicates once only that a write to external DRAM has caused an overflow. (When reset
by the 90H status read command, this flag is reset even if the overflow condition continues.)
Set
Reset
- When the write address (WA) exceeds the read address (RA)
- By 90H status read
- When a read address clear (MSRACL) or write address clear (MSWACL) command is issued
- After external reset
BOVF
READ
Meaning
- Indicates input data rate was too fast causing buffer overflow and loss of data
90H
Set
- When inputs a data during a buffer memory overflow
bit 5
Reset
- By 90H status read
- When a read address clear (MSRACL) or write address clear (MSWACL) command is issued
- After external reset
DCOMP
READ
Meaning
- Indicates that a compare-connect sequence is operating
90H
Set
- When a (3-pair or 2-pair) compare-connect start command is received (MSDCN2=1)
bit 3
- When a direct connect command is received (MSDCN2=0, MSDCN1=1)
Reset
- When a (3-pair or 2-pair) comparison detects conforming data
- When the connect has been performed after receiving a direct connect command
- When a compare-connect stop command (MSDCN2=0, MSDCN1=0) is received
- When a MSWREN=1 command is received (However, if a compare-connect command is
received at the same time, the compare-connect command has priority.)
- After external reset
MSWIH
READ
Meaning
90H
bit 2
- Indicates that the encode sequence has stopped due to internal factors
(not microcontroller commands)
Set
- When FLAG6 (above) is set
- When BOVF (above) is set
- When MSOVF (above) is set
Reset
- When conforming data is detected after receiving a compare-connect start command
- When the connect has been performed after receiving a direct connect command
- When a read address clear (MSRACL) or write address clear (MSWACL) command is received
- After external reset
MSRIH
READ
Meaning
90H
bit 1
- Indicates that the decode sequence has stopped due to internal factors
(not microcontroller commands)
Set
- When the valid data residual becomes 0
Reset
- By 90H status read
- When a read address clear (MSRACL) or write address clear (MSWACL) command is issued
- After external reset
NIPPON PRECISION CIRCUITS-18
SM5902AF
Flag
Read
name
method
MSEMP
READ
Meaning
91H
Set
bit 7
OVFL
- Indicates that the valid data residual has become 0
- When the VWA (final valid data's next address)
= RA (address from which the next read would take place)
Reset
- Whenever the above does not apply
READ
Meaning
- Indicates a write to external DRAM overflow state
91H
Set
bit 6
- When the write address (WA) exceeds the read address (RA).
(Note: This flag is not set when WA=RA through an address initialize or reset operation.)
Reset
- When the read address (RA) is advanced by the decode sequence
- When a read address clear (MSRACL) or write address clear (MSWACL) command is issued
- After external reset
ENCOD
READ
Meaning
91H
Set
bit 5
- Indicates that the encode sequence (input data entry, encoding, DRAM write) is operating
- By the 80H command when MSWREN=1
- When conforming data is detected during compare-connect operation
- When the connect has been performed after receiving a direct connect command
Reset
- When the FLAG6 flag=1 (above)
- When the OVFL flag=1 (above)
- By the 80H command when MSWREN=0
- By the 80H command when MSDCN1=1 or MSDCN2=1 (compare-connect start command)
- By the 80H command when MSON=0
- After external reset
Note. Reset conditions have priority over set conditions. For example, if the 80H command has
MSWREN=1 and MSDCN1=1, the ENCOD flag is reset and compare-connect operation starts.
DECOD
READ
Meaning
- Indicates that the decode sequence (read from DRAM, decoding,
bit 4
Set
- By a new 80H command when MSRDEN=1 and the MSEMP flag=0 (above)
Reset
- Whenever the above does not apply
READ
Meaning
Subcode Q data write-buffer write enable indicator
91H
Set
After internal subcode Q data write-buffer contents are read out.
bit 3
Reset
When data is written to address 1001 using the 87H command.
91H
QRDY
attenuation, data output) is operating
NIPPON PRECISION CIRCUITS-19
SM5902AF
Write command supplementary information
80H (MS command)
- MSWREN
When 1: Encode sequence starts
Invalid when MSON is not 1 within the
same 80H command
Invalid when FLAG6=1
Invalid when OVFL=1
Invalid when a compare-connect start
command (MSDCN2=1 or MSDCN1=1)
occurs simultaneously
Direct connect if a compare-connect
sequence is already operating
When 0: Encode sequence stops
- MSWACL
When 1: Initializes the write address (WA)
When 0: No operation
- MSRDEN
When 1: Decode sequence starts
Does not perform decode sequence if
MSON=1.If there is no valid data, decode
sequence temporarily stops. But, because
the MSRDEN flag setting is maintained as
is, the sequence automatically re-starts
when valid data appears.
When 0: Decode sequence stops
-MSRACL
When 1: Initializes the read address (RA)
When 0: No operation
- MSDCN2, MSDCN1
When 1 and 1: 3-pair compare-connect sequence
starts
When 1 and 0: 2-pair compare-connect sequence
starts
When 0 and 1: Direct connect sequence starts
When 0 and 0: Compare-connect sequence stops.
No operation if a compare-connect
sequence is not operating.
- WAQV
When 1: The immediately preceding YBLKCK
falling-edge timing WA (write address)
becomes the VWA (valid write address).
When 0: No operation
- MSON
When 1: Memory system turns ON and shockproof operation starts
When 0: Memory system turns OFF and throughmode playback starts. (In this mode, the
attenuator is still active.)
81H (Extension I/O port settings)
82H (Extension I/O port output data settings)
NIPPON PRECISION CIRCUITS-20
SM5902AF
83H (ATT, MUTE, 12-bit comparison connection settings)
- ATT (attenuator enable)
When 1: Attenuator settings become active (84H
command)
When 0: Attenuator settings become inactive, and
output continues without attenuation
- MUTE (forced muting)
When 1: Outputs are instantaneously muted to
0.(note 1)
Same effect as taking the YDMUTE pin
HIGH.
When 0: No muting(note 1)
(note1) Effective at the start of left-channel output
data.
- SOFT (soft muting)
- MUTE, SOFT, YDMUTE relationship
When all mute inputs are 0, mute is released.
- NS (noise shaper enable)
When 1: Includes noise shaper function in compression-mode shockproof operation.
When 0: Performs comparison connection using
all 16 bits of input data.
- CMP12 (12-bit comparison connection)
When 1: Performs comparison connection using
only the most significant 12 bits of input
data.
When 0: Performs comparison connection using
all 16 bits of input data.
When 1: Outputs are smoothly muted to 0.
When 0: No muting.
Soft mute release occurs instantaneously
to either the value set by the 84H command (When ATT=1) or 0dB (When
ATT=0)
85H (option settings)
- RAMS1, RAMS2
When 0 and 0 : 1M DRAMs (256k×4 bits)×single
When 1 and 0 : 4M DRAMs (1M×4 bits)×single
When 0 and 1 : 4M DRAMs (1M×4 bits)×double
When 1 and 1 : 16M DRAMs (4M×4 bits)×single
- RAMX2
When 1: Uses 2 DRAMs
When 0: Uses a single DRAM
- YFLGS, YFCKP
When 0 and 0: Sets FLAG6 on the falling edge of
YFCLK when YFLAG=0
When 1 and 0: Sets FLAG6 when YFLAG=0
When 1 and 1: Sets FLAG6 when YFLAG=1
- COMPFB, COMP6B, COMP5B, COMP4B
When 0, 0, 0 and 1: Selects 4-bit compression
mode
When 0, 0, 1 and 0: Selects 5-bit compression
mode
When 1, 0, 0 and 0: Selects full-bit compression
mode
In all other cases: Selects 6-bit compression mode
Changing mode without initializing during operation is possible.
When 0 and 1: Sets FLAG6 on the rising edge of
YFCLK when YFLAG=0
NIPPON PRECISION CIRCUITS-21
SM5902AF
86H (digital audio interface settings)
- CP1, CP2 (channel status and clock accuracy setting)
- LBIT (digital audio signal generation logic)
When 1: Not assigned
When 0 and 0: Level 2 (max ± 300 ppm)
When 0: Post-recording software
- DIT (digital audio interface enable)
When 0 and 1: Level 3I (max ± 10%)
When 1 and 0: Level 1 (max ± 50 ppm)
When 1: DIT output enable
When 1 and 1: Not supported
When 0: DIT LOW-level output
87H (subcode Q data setting)
- QAD3 to QAD0 (Q data setting and word address
specification)
QAD3 (MSB) to QAD0 (LSB) specify one of 10
valid addresses in the range 0000 to 1001.
If an address in the range 1010 to 1111 is speci-
- QD7 to QD0 (Q data setting and word data)
The CD Q-channel has the general data format
shown below.
The write data required to fully specify the Q data
is the 80 bits comprising CONTROL, ADR, and
DATA-Q.
The CRC write data is not required because it is
generated by recalculation.
fied, the data on QD7 to QD0 is ignored.
Note that writing to address 1001 also functions
as the write stop command.
bit
ADR
Control
S0, S1
0
1
2
3
4
5
DATA-Q
6
7
8
9
CRC
78 79 80
S0, S1
95
80 bit
96 bit
Adderss map for Q data setting beuffer
QAD3
QAD2
QAD1
QAD0
QD7
QD6
QD5
QD4
QD3
QD2
QD1
QD0
0
0
0
0
CTL0
CTL1
CTL2
CTL3
ADR3
ADR2
ADR1
ADR0
0
0
0
1
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
0
0
1
0
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
0
0
1
1
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
0
1
0
0
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
0
1
0
1
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
0
1
1
0
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
0
1
1
1
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
1
0
0
0
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ64
1
0
0
1
DQ65
DQ66
DQ67
DQ68
DQ69
DQ70
DQ71
DQ72
- Subcode Q data setting process
Initially, data is written to word address range
0000 to 1000, and then data is written to address
1001. Next, only data that needs to be changed
is written if the 91H command QRDY bit is 1, and
then address 1001 is written again. Note that
when shockproof mode is ON, the Q data is
specified according to the data output from the
SM5902AF.
NIPPON PRECISION CIRCUITS-22
SM5902AF
Shock-proof operation overview
Shock-proof mode is the mode that realizes shockproof operation using external DRAM. Shock-proof
mode is invoked by setting MSON=H in microcon-
troller command 80H.
This mode comprises the following 3 sequences.
- Encode sequence
1. Input data from a signal processor IC is stored in
internal buffers.
2. Encoder starts after a fixed number of data have
been received.
3. The encoder, after the most suitable predicting
filter type and quantization steps have been determined, performs ADPCM encoding and then writes
to external DRAM.
- Decode sequence
1. Reads compressed data stored in external buffer
RAM at rate fs.
2. Decoder starts, using the predicting filter type
and quantization levels used when encoded.
3. Performs attenuation operation (including muting
operation)
4. Outputs the result.
- Compare-connect sequence
1. Encoding immediately stops when either external
buffer RAM overflows or when a CD read error
occurs due to shock vibrations.
2. Then, using microcontroller command 80H, the
compare-connect start command is executed and
compare-connect sequence starts.
3. Compares data re-read from the CD with the processed final valid data stored in RAM (confirms its
correctness).
4. As soon as the comparison detects conforming
data, compare-connect sequence stops and
encode sequence re-starts, connecting the data
directly behind previous valid data.
NIPPON PRECISION CIRCUITS-23
SM5902AF
RAM addresses
The SM5902 uses either 1 or 2 external 1M or 4M
DRAMs as external buffers.
Connect data work area
Three kinds of addresses are used for external
RAM control.
WA (write address)
RA (read address)
VWA (valid write address)
Among these, VWA is the write address for conforming data whose validity has been confirmed.
Determination of the correctness of data read from
the CD is delayed relative to the encode write processing, so VWA is always delayed relative to WA.
RA
WA
VWA
Valid data
area
The region available for valid data is the area
between VWA-RA.
- Connect data work area
This is an area of memory reserved for connect
data. This area is 2k bits if using 1M DRAMs, 4k
bits if using 4M DRAMs, or 8k bits if using 16M
DRAMs.
Fig 1. RAM addresses
VWA (valid write address)
The VWA is determined according to the YBLKCK
pin and WAQV command. Refer to the timing chart
below.
1.YBLKCK is a 75 Hz clock(HIGH for 136 µs) when
used for normal read mode and it is a 150 Hz clock
when used for double-speed read mode, synchronized to the CD format block end timing.
When this clock goes LOW, WA which is the write
address of internal encode sequence, is stored
(see note 2).
2.The microcontroller checks the subcode and, if
confirmed to be correct, generates a WAQV command (80H).
3.When the WAQV command is received, the previously latched WA is stored as the VWA.
(note 2) Actually, there is a small time difference, or
gap, between the input data and YBLKCK. This gap
serves to preserves the preceding WA to protect
against incorrect operation.
13.3ms
VWA latch set
YBLKCK
WAQV set
Microcontroller data set
Refer to Microcontroller interface
VWA
VWA(x)
VWA(x + 1)
Values shown are for rate fs. The values are 1/2 those shown at rate 2fs.
Fig 2. YBLKCK and VWA relationship
NIPPON PRECISION CIRCUITS-24
SM5902AF
YFLAG, YFCLK, FLAG6
Correct data demodulation becomes impossible for
the CD signal processor IC when a disturbance
exceeding the RAM jitter margin occurs. The
YFLAG signal input pin is used to indicate when
such a condition has occurred.
The YFCLK is a 7.35 kHz clock synchronized to the
CD format frame 1.
The IC checks the YFLAG input and stops the
encode sequence when such a disturbance has
occurred, and then makes FLAG6 active.
The YFLAG check method used changes depending on the YFLGS flag and YFCKP flag (85H command). See table1.
If YFLAGS is set to 1, then YFCLK should be tied
either High or Low.
85H command
1
YFLGS
YFCKP
FLAG6 set conditions
FLAG6 reset conditions
0
0
When YFLAG=LOW on YFCLK input falling edge
- By status read (90H command)
When YFLAG=LOW on YFCLK input rising edge
- When MSON=LOW
2
3
4
1
1
0
When YFLAG=LOW
1
When YFLAG=HIGH
YFCLK be tied either High or Low
- After system reset
Table 1. YFLAG signal check method
NIPPON PRECISION CIRCUITS-25
SM5902AF
Compare-connect sequence
The SM5902AF supports three kinds of connect
modes; 3-pair compare-connect, 2-pair compareconnect and direct connect.
Note that the SM5902AF can also operate in 12-bit
comparison connect mode using only the most significant 12 bits of data for connection operation.
In 3-pair compare-connect mode, the final 6 valid
data (3 pairs of left- and right-channel data input
before encode processing) and the most recently
input data are compared until three continuous data
pairs all conform. At this point, the encode
sequence is re-started and data is written to VWA.
In 2-pair compare-connect mode, comparison
occurs just as for 3-pair comparison except that
only 2 pairs from the three compared need to conform with the valid data. At this point, the encode
sequence is re-started and data is written to VWA.
In direct-connect mode, comparison is not performed at all, and encode sequence starts and data
is written to the VWA. This mode is for systems that
cannot perform compare-connect operation.
- Compare-connect preparation time
1. Comparison data preparation time
Internally, when the compare-connect start command is issued, a sequence starts to restore the
data for comparison. The time required for this
preparation after receiving the command is approximately 2.5 × (1/fs). (approximately 60 µs when fs =
44.1 kHz)
2. After the above preparation is finished, data is
input beginning from the left-channel data and comparison starts.
3. If the compare-connect command is issued
again, the preparation time above is not necessary
and operation starts from step 2.
4. The same sequence takes place in direct-connect mode also. However, at the point when 3
words have been input, all data is directly connected as if comparison and conformance had taken
place.
- Compare-connect sequence stop
If a compare-connect stop command (80H with
MSDCN1= 1, MSDCN2= 0) is input from the microcontroller, compare-connect sequence stops.
If compare-connect sequence was not operating,
the compare-connect stop command performs no
operation. However, make sure that the other bit
settings within the same 80H command are valid.
NIPPON PRECISION CIRCUITS-26
SM5902AF
Encode sequence temporary stop
- When RAM becomes full, MSWREN is set LOW
using the 80H command and encode sequence
stops. (For details of the stop conditions, refer to
the description of the ENCOD flag.)
- Then, if MSWREN is set HIGH without issuing a
compare-connect start command, the encode
sequence re-starts. At this time, new input data is
written not to VWA, but to WA. In this way, the data
already written to the region between VWA and WA
is not lost.
- But if the MSWREN is set HIGH (80H command)
after using the compare-connect start command
even only once, data is written to VWA. If data is
input before comparison and conformance is
detected, the same operation as direct-connect
mode takes place when the command is issued.
After comparison and conformance are detected,
no operation is performed because the encode
sequence has already been started. However,
make sure that the other bit settings within the
same 80H command are valid.
DRAM refresh
- DRAM initialization refresh
A 15-cycle RAS-only refresh is carried out for
DRAM initialization under the following conditions.
When MSON changes from 0 to 1 using command
80H.
When from MSON=1, MSRDEN=0 and
MSWREN=0 states only MSWREN changes to 1.
In this case, encode sequence immediately starts
and initial data is written (at 2fs rate input) after a
delay of 0.7ms.
- Refresh during Shock-proof mode operation
In this IC, a data access operation to any address
also serves as a data refresh. Accordingly, there
are no specific refresh cycles other than the initialization refresh cycle (described above).
This has the resulting effect of saving on DRAM
power dissipation.
A data access to DRAM can occur in an encode
sequence write operation or in a decode sequence
read operation. Write sequence write operation
stops during a connect operation whereas a read
sequence read operation always continues while
data is output to the D/A. The refresh rate for each
DRAM during decode sequence is shown in the
table below.
The decode sequence, set by MSON=1 and MSRDEN=1, operates when valid data is in DRAM
(when MSEMP=0).
- When MSON=0, DRAM is not refreshed because
no data is being accessed. Although MSON=1,
DRAM is not refreshed if ENCOD=0 and DECOD=0
(both encode and decode sequence are stopped).
DRAMs used (same for 1 or 2 DRAMs)
Data compression mode
1M (256K×4 bits)
4M (1M×4 bits)
16M(4M×4 bits)
4 bit
5.44 ms
10.88 ms
21.77ms
5 bit
4.35 ms
8.71 ms
17.42ms
6 bit
3.63 ms
7.26 ms
14.52ms
Full bit
1.36 ms
2.72 ms
5.81ms
Table 2. Decode sequence refresh rate
NIPPON PRECISION CIRCUITS-27
SM5902AF
Selecting compression mode
Even when the compression mode in selected with
the 85H command during shock-proof operation,no
malfunction occurs.
The compression mode change is not performed
immediately after input of the 85H command, but it
is performed at the following timing.
YMLD
When 85H generated
WA CAS
3FE
RA CAS
3FD
Encode compression mode
001
3FF
3FE
003
3FF
A
Decode compression mode
002
004
005
001
002
B
A
B
(note) CAS-000 is connect data.
NIPPON PRECISION CIRCUITS-28
SM5902AF
Through-mode operation
If MSON is set LOW (80H command), an operating
mode that does not perform shock-proof functions
becomes active. In this case, input data is passed
as-is (after attenuator and mute operations) to the
output. External DRAM is not accessed.
- In this case, input data needs to be at a rate fs
and the input word clock must be synchronized to
the CLK input (384fs). However, short range jitter
can be tolerated (jitter-free system).
- Jitter-free system timing starts from the first
YLRCK rising edge after either (A) a reset (NRESET= 0) release by taking the reset input from
LOW to HIGH or (B) by taking MSON from HIGH to
LOW. Accordingly, to provide for the largest possible jitter margin, it is necessary that the YLRCK
clock be at rate fs by the time jitter-free timing
starts.
The jitter margin is 0.2/ fs (80 clock cycles).
This jitter margin is the allowable difference
between the system clock (CLK) divided by 384 (fs
rate clock) and the YLRCK input clock.
If the timing difference exceeds the jitter margin,
irregular operation like data being output twice or,
conversely, incomplete data output may occur. In
the worst case, a click noise may also be generated.
When switching from shock-proof mode to through
mode, an output noise may be generated, and it is
therefore recommended to use the YDMUTE setting to mute ZSRDATA until just before data output.
Attenuation
- The attenuation register is set by the 84H command.
- The attenuation register set value becomes active
when the 83H command sets the ATT flag to 1.
When the ATT flag is 0, the attenuation register
value is considered to be the equivalent of 256 for a
maximum gain of 0 dB.
- The gain (dB) is given from the set value (Datt)
by the following equation.
Gain = 20 × log(Datt/256) [dB]; left and right channels
- For the maximum attenuation register set value
(Datt = 255), the corresponding gain is -0.03 dB.
But when the ATT flag is 0 (Datt = 256), there is no
attenuation.
- After a system reset initialization, the attenuation
register is set to 64 (-12 dB). However, because the
ATT flag is reset to 0, there is no attenuation.
- When the attenuation register setting changes or
when the ATT flag changes, the gain changes
smoothly from the previous set gain towards the
new set value. If a new value for the attenuation
level is set before the previously set level is
reached, the gain changes smoothly towards the
latest setting.
The gain changes at a rate of 4 × (1/fs) per step. A
full-scale change (255 steps) takes approximately
23.3 ms (when fs = 44.1 kHz). See fig 3.
set 1
set 5
set 3
Gain
set 2
set 4
time
Fig 3. Attenuation operation example
NIPPON PRECISION CIRCUITS-29
SM5902AF
Soft mute
Soft mute operation is controlled by the SOFT flag
using a built-in attenuation counter.
Mute is ON when the SOFT flag is 1. When ON, the
attenuation counter output decrement by 1 step at a
time, thereby reducing the gain. Complete mute
takes 1024/fs (or approximately 23.2 ms for fs =
44.1 kHz).
Conversely, mute is released when the SOFT flag
is 0. In this case, the attenuation counter instantaneously increases. The attenuation register takes
on the value when the ATT flag was 1. If the ATT
flag was 0, the new set value is 256 (0 dB).
SOFT
Attenation level
or full scale
(Gain)
−∞
256 step
/ 1024TS
Fig 4. Soft mute operation example
Force mute
Serial output data is muted by setting the YDMUTE
pin input HIGH or by setting the MUTE flag to 1.
Mute starts and finishes on the leading left-channel
bit.
When MSON is HIGH and valid data is empty
(MSEMP=H), the output is automatically forced into
the mute state.
12-bit comparison connection
When the CMP12 flag is set to 1, the least significant 4 bits of the 16-bit comparison connection
input data are discarded and comparison connection is performed using the remaining 12 bits.
Note that if the CMP12 flag is set to 1 during a comparison connection operation, only the most significant 12 bits are used for comparison connection
from that point on.
NIPPON PRECISION CIRCUITS-30
SM5902AF
Digital audio interface
When the DIT flag is set to 1, the digital audio interface output from pin DIT is enabled. The output
M
W
Channel 1
Channel 2
B
Channel 1
Sub Frame
Frame 191
data structure is modulated using a preamble and
biphase mark encoding.
W
Channel 2
M
Channel 1
W
Channel 2
Sub Frame
Frame 0
Frame 1
Start Block
Figure 5. Frame format
LSB
(Sync Groupe)
7 8
Auxiliary
27 28
Digital Audio Sample Data
MSB
3 4
Preamble
MSB
LSB
0
31
V
U
C
P
Audio Sample Validity
User Bit Data
Audio Channel Status
Sub Frame Parity
Figure 6. Subframe format
Preamble
The preamble is a particular bit pattern used to perform subframe and block synchronization and discrimination, assigned to one of 4 time slot divisions
(0 to 3), comprising 8 continuous biphase modulated transfer rate status indicators.
Preamble
There are 3 types of preamble. The leading preamble pattern of all blocks is preamble pattern B,
which is then followed by preamble pattern M for
channel 1, and preamble pattern W for channel 2.
Channel coding
Leading symbol = 0
Leading symbol = 1
B
11101000
00010111
M
11100010
00011101
W
11100100
00011011
The SM5902AF starts with 0, so only the preamble patterns for leading symbol = 0 are used.
Digital audio sample data and auxiliary audio
The digital audio sample data is a 20-bit digitized
audio signal. Auxiliary audio data, on the other
hand, can be audio sample data of varying length.
The SM5902AF uses a 16-bit audio data structure
internally with audio data output bits 4 to 11 set to 0
and bits 12 to 27 output in LSB first format.
Audio sample validity
The validity flag is set to 0 when the digital audio
sample data is output correctly, or it is set to 1 if the
output is incorrect. It is also set to 1 if encoding
does not start when the device is operating in
forced mute, microcontroller forced mute, and
shockproof mode.
NIPPON PRECISION CIRCUITS-31
SM5902AF
User bit data
User bit data is data specified by the user. The data
is output, after the Q data has been specified, in the
following sequence.
0
1
2
3
4
5
6
7
8
9
10
11
0
0
0
0
0
0
0
0
0
0
0
0
0
12
0
0
0
0
0
0
0
0
0
0
0
0
24
1
Q1
0
0
0
0
0
0
0
0
0
0
36
1
Q2
0
0
0
0
0
0
0
0
0
0
•
•
•
•
•
•
•
•
•
•
•
•
1
Q96
0
0
0
0
0
0
0
0
0
0
1164
- Using Q data
Initially, Q1 to Q80 are set using the 87H command,
the DIT flag is set using the 86H command, and
then data is output from DIT according to the digital
audio interface format. Q 81 to Q 96 data are not
required as these are set internally by CRC calculation.
There are 2 Q data buffers; a data output buffer
and a data storage buffer. As a result, after all data
has been specified in the first data write, only that
data that has changed needs to be written during
the 2nd and subsequent data write operations.
Note that address 1001 is the write stop command
and is, therefore, required after every data write
operation.
When space becomes available in the data output
buffer, QRDY is set to 1 (91H command status bit
S3) to indicate available space and then the contents of the data storage buffer are transferred to
the data output buffer. After data is transferred, a
data write to address 1001 (write stop command)
resets the QRDY flag to 0.
The Q data buffer read access time for a complete
data cycle is approximately 13.3 ms.
Audio channel status
The channel status are information bits transferred
to indicate the audio sample data length, preemphasis, sampling frequency, time code, source
0
0
1
2
3
CTL0 CTL1 CTL2 CTL3
number, destination code, and other information.
Seven bits comprising CP1, CP2, LBIT, and CTL0
to CTL3 can be set. All other bits are fixed.
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
1
0
0
0
0
0
0
LBIT
16
0
0
0
0
L= 1
R= 1
0
0
0
0
0
0
CP1
CP2
0
0
32
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
48
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
64
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
80
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
96
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
112
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
128
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
144
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
160
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
176
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Subframe parity
The parity bit is used to indicate the detection of an
odd number of bit errors. It is set to 1 if the number
of 1s in the digital audio interface 27-bit data is odd,
and is set to 0 if the number of 1s is even. The 27bit data plus parity bit form 28-bit data that always
has an even number of 1s.
NIPPON PRECISION CIRCUITS-32
SM5902AF
Timing charts
Input timing (YSCK, YSRDATA, YLRCK)
16
16
L ch
R ch
YSCK
LSB
MSB
LSB
MSB
LSB
YSRDATA
YLRCK
1/(3fs )
Output timing (ZSCK, ZSRDATA, ZLRCK)
1
9
24
33
48
ZSCK
L ch
LSB
MSB
LSB
MSB
LSB
ZSRDATA
R ch
ZLRCK
1/fs
NIPPON PRECISION CIRCUITS-33
SM5902AF
DRAM write timing (NRAS, NCAS, NCAS2, NWE, A0 to A10, D0 to D3)
Write timing (with single DRAM)
t RASL
t RASH
NRAS
t RDC
t CASH
t CASL
NCAS
t RADS
A0 to A10
,,,,,,,,
,,,,,,,,
,,,,,,,,
,,,,,,,,
t CADS
t RADH
t CADH
t CWDS
,,,,,,,,,,,,
,,,,,,,,,
,,,,,,,,,,,,
,,,,,,,,,
,,,,,,,,,,,,
,,,,,,,,,
,,,,,,,,,,,,
,,,,,,,,,
t CWDH
,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,
D0 to D3
(WRITE)
t WEL
NWE
Write timing (with 2 DRAMs)
t RASL
t RASH
NRAS
t RDC
t CASL
t CASH
t RDC
t CASL
t CASH
NCAS1
(DRAM1 SELECT)
NCAS2
(DRAM2 SELECT)
t RADS
A0 to A9
,,,,,,,
,,,,,,,
,,,,,,,
,,,,,,,
t RADH
t CADS
t CADH
t CWDS
t CWDH
D0 to D3
(WRITE)
t WEL
,,,,,,,,,,,,
,,,,,,,,
,,,,,,,,,,,,
,,,,,,,,
,,,,,,,,,,,,
,,,,,,,,
,,,,,,,,,,,,
,,,,,,,,
,,,,,,,,,,,,,,
,,,,,,,,,,,,,,
,,,,,,,,,,,,,,
,,,,,,,,,,,,,,
NWE
NIPPON PRECISION CIRCUITS-34
SM5902AF
DRAM read timing (NRAS, NCAS, NCAS2, NWE, A0 to A10, D0 to D3)
Read timing (with single DRAM)
t RASL
t RASH
NRAS
t RCD
t CASL
t CASH
NCAS
t RADS
t RADH
t CADS
t CADH
,,,,,,,,
,,,,,,,,
,,,,,,,,
,,,,,,,,,,,,
,,,,,,,,,
,,,,,,,,,,,,
,,,,,,,,,
,,,,,,,,,,,,
,,,,,,,,,
,,,,,,,,,,,,
,,,,,,,,,
A0 to A10 ,,,,,,,,
t CRDS
t CRDH
D0 to D3 ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
(READ) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
t OEL
NWE
Read timing (with 2 DRAMs)
t RASL
t RASH
NRAS
t RCD
t CASL
t CASH
t RCD
t CASL
t CASH
NCAS1
(DRAM1 SELECT)
NCAS2
(DRAM2 SELECT)
t RADS
A0 to A9
D0 to D3
(READ)
t RADH
t CADS
,,,,,,,
,,,,,,,
,,,,,,,
,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
t CADH
t CRDS
t CRDH
,,,,,,,,,,,,
,,,,,,,,
,,,,,,,,,,,,
,,,,,,,,
,,,,,,,,,,,,
,,,,,,,,
,,,,,,,,,,,,
,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,
,,,,,,,,,,,,,,,,,,,,,,,,,
NWE
NIPPON PRECISION CIRCUITS-35
SM5902AF
Connection example
SM5902
Microcontroller
YMDATA
YMCLK
YMLD
ZSENSE
UC1 to UC5
DIT
DRAM 1
YBLKCK
YFCLK
YFLAG
NRAS
NWE
A0 to A10
D0 to D3
NCAS
DSP
Matsushita
MN662740 YSCK
YLRCK
YSRDATA
DRAM 2
RAS
WE
A0 to A10
D0 to D3
CAS
OE
RAS
WE
A0 to A9
D0 to D3
CAS
OE
DRAM 1
DRAM 2
RAS
WE
A0 to A10
D0 to D3
CAS
OE
RAS
WE
A0 to A9
D0 to D3
CAS
OE
NCAS2
D/A
converter
ZSCK
ZLRCK
ZSRDATA
CLK
NRESET
YDMUTE
SM5902
Microcontroller
YMDATA
YMCLK
YMLD
ZSENSE
SCOR
XROF
DSP
SONY
CXD2517
UC1 to UC5
DIT
YBLKCK
YFLAG
YFCLK
NRAS
NWE
A0 to A10
D0 to D3
NCAS
YSCK
NCAS2
YLRCK
YSRDATA
ZSCK
ZLRCK
D
A
ZSRDATA
CLK
NRESET
YDMUTE
note1
- When 2 DRAMs are used, the DRAM OE pins should be tied LOW.
- When single DRAM is used, the DRAM OE pin should be tied LOW
or controlled by the SM5902 NOE signal.
note 2 When CXD 2517 (Sony) is used
Set 85H of microcontroller command (option setting) as setting YFLAG take in;
D5: YFLAGS= 1
D4: YFCKP= 0
NIPPON PRECISION CIRCUITS-36
SM5902AF
Device comparison with SM5856A1F
Pin differences
Pin No.
SM5856A1F
SM5902AF
1
VDD
VDD2
7
NTEST1
DIT
8
NTEST2
NTEST
22
UC6
VDD1
27
NOE / NCAS2
A10 / NCAS2
VDD pins
The SM5902AF operates from a 3 V supply voltage, but a built-in level shifter is provided for use
with external 5 V DRAM ICs. There are, therefore, 2
supply pins. VDD1 is the internal 3 V IC supply, and
VDD2 is the external DRAM interface supply.
If, however, the DRAM also operates from a 3 V
supply, VDD1 and VDD2 can be connected to the
same supply.
DIT pin
The SM5902AF incorporates a digital audio interface output from pin DIT. Leave open circuit if not
used.
Microcontroller interface extensions
The SM5902AF supports additional function extensions. Also, the UC6 pin has been removed, which
means that UC6-related commands have been
redefined.
Additional commands
Command
Bit
Name
Function
83H
D4
NS
Noise shaper ON/OFF switch
D5
CMP12
12-bit comparison connection ON/OFF switch
86H
D4 to D7
CP1, 2, LBIT, DIT
Digital audio interface settings
87H
D0 to D11
QAD0 to 3, QD0 to 7
Subcode Q data settings
90H
S5
BOVF
Input buffer overflow
91H
S3
QRDY
Q data write buffer status
Modified commands
Command
Bit
Name
Function
85H
D6, D7
RAMS1, 2
External DRAM capacity
92H
S0 to 7, M1 to 8
AM06 to 21
Place of data residual
Obsolete commands
Command
Bit
Name
Function
81H
D5
UC6OE
UC6 input/output settings
82H
D5
UC6WD
UC6 output settings
93H
S5
UC6RD
UC6 settings status
NIPPON PRECISION CIRCUITS-37
SM5902AF
Compression mode switching
The SM5902AF guarantees correct operation if the
compression mode is switched, using the 85H com-
mand, during normal operation. However, all other
settings should remain unchanged while switching.
Attenuation
The SM5902AF supports attenuation level adjustments in steps 1/4 of the minimum level for smooth
attenuation and soft muting.
16MDRAM
The SM5902AF can use with up to 16MDRAM.
(in case of SM5856A1F, up to 4M×2.)
Note that acceptable 16MDRAM is 2048-refresh
type only. (Can not use with 4096-refresh type.)
So you can get a long shock-proof time.
NIPPON PRECISION CIRCUITS-38
SM5902AF
NIPPON PRECISION CIRCUITS-39
SM5902AF
NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to
improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for
the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits
are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision
Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or
malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies.
NIPPON PRECISION CIRCUITS INC.
NIPPON PRECISION CIRCUITS INC.
4-3, FUKUZUMI 2 CHOME, KOTO-KU
TOKYO,135-8430, JAPAN
Telephon: +81-3-3642-6661
Facsimile: +81-3-3642-6698
NC9618BE
1999.8
NIPPON PRECISION CIRCUITS-40