NPC SM8702AM

SM8702AM
Clock Generator IC
NIPPON PRECISION CIRCUITS INC.
OVERVIEW
FEATURES
Intel Pentium II, Pentium III, and AMD x86compatibles supported
2.5/3.3V CPU clock outputs and IOAPIC clock
output
14 × SDRAM clock outputs (3 DIMMs)
2 × CPU clock outputs
(60), 66, 75, 83, 95, 100, 103, 112, (124), 133MHz
CPU/SDRAM clock frequencies. Values in parentheses are available as mask options.
6 × PCI bus clock outputs (one free-running output)
33MHz or 1/2, 1/3, 1/4 of the CPU clock frequency
2 × reference clock outputs and 1 × IOAPIC clock
output
14.318MHz REF/IOAPIC clock frequency
1 × 48MHz USB interface clock output
1 × 24MHz clock output for Super I/O chip
I2C serial data bus for frequency/mode output control
CPU-stop and PCI-stop functions
Spread Spectrum Clock Generator (SSCG) outputs
Center spread/Down spread, ± 0.5% or ± 1.5%
3.3V (VDD) and 2.5/3.3V (VDDL) supply voltages
48-pin SSOP package (pin compatible with
ICS9148-26)
PINOUT
48-pin SSOP (300 mil)
pre
lim
ina
■
ry
The SM8702AM is a clock generator IC that can generate clock signals up to and exceeding 100MHz for personal computer (PC) motherboards. It uses a single 14.318MHz crystal oscillator element and 2 built-in PLLs
to simultaneously and independently generate 2 CPU clocks, 6 PCI bus clocks, 2 reference clocks with the
same frequency as the crystal element, 48MHz USB interface clock, and 24MHz Super I/O chip clock outputs.
It also has 14 outputs that can function as SDRAM clocks by buffering an external input SDRAM clock.
■
■
■
■
■
■
■
■
■
■
■
APPLICATIONS
■
VDD1
REF0
VSS
XT
XTN
VDD2
PCICLK_F/MODE
PCICLK0
VSS
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDD2
BUFFERIN
VSS
SDRAM11/CPU_STOP#
SDRAM10/PCI_STOP#
VDD3
SDRAM9
SDRAM8
VSS
SDATA
SCLK
1
48
SM8702AM
■
(Top view)
24
25
VDDL1
IOAPIC
REF1/FS2
VSS
CPUCLK0
CPUCLK1
VDDL2
SDRAM13
SDRAM12
VSS
SDRAM0
SDRAM1
VDD3
SDRAM2
SDRAM3
VSS
SDRAM4
SDRAM5
VDD3
SDRAM6
SDRAM7
VDD4
48MHz/FS0
24MHz/FS1
ORDERING INFORMATION
D e vice
P ackag e
SM8702AM
48-pin SSOP
PC motherboards using Intel Pentium, Pentium II/III, AMD-K6 devices, and x86 architecture CPUs
Intel and Pentium are registered trademarks of Intel co..
AMD and AMD-K6 are registered trademarks of Advanced Micro Devices, Inc..
I2C Bus is a registered trademark of Philips Electronics N. V..
NIPPON PRECISION CIRCUITS—1
SM8702AM
PACKAGE DIMENSIONS
(Unit: mm)
10.285 0.125
7.50 0.05
ina
ry
15.85 0.1
0.80 0.1
0 8
pre
2.29 0.05
0.12 M
2.59 0.15
0.05
0.25 0.03
lim
0.635
0.3 0.1
0.5 45
2
0.20 0.0
NIPPON PRECISION CIRCUITS—2
SM8702AM
BLOCK DIAGRAM
(1st PLL)
Unlock Detector
PCICLK_F
XTN
Phase
Detector
R-Countor
N-Countor
5
PCICLK
[0:4]
2
CPUCLK
[0:1]
14
SDRAM
[0:13]
ina
ry
XT
Charge
Pump
DIV/3
to DIV/6
VCO
Current
Source
DIV/2
SS_CONTROLLER
(MS)
BUFFERIN
Buff. Amp.
(2nd PLL)
Unlock Detector
Phase
Detector
R-Countor
Charge
Pump
Current
Source
N-Countor
VCO
48MHz
(USB)
DIV/3
24MHz
(Super I/O)
1/2
2
FS[0:2]
MODE
SDATA
SCLK
CPU_STOP#
PCI_STOP#
3
lim
REF[0:1]
I/O
Latch
ROM
I2C
Control Logic
IOAPIC
PIN DESCRIPTION
Name
I/O
pre
Number
1
VDD1
–
2
REF0
I/O
Function
3.3V supply
3
VSS
–
Ground
XT
I
Cr ystal oscillator input
5
XTN
O
Cr ystal oscillator output
6
VDD2
–
3.3V supply
PCICLK_F
O
PCI bus free-running clock output
8
X T, XTN oscillator, REF[0:1] buffer, stop logic, 3.3V line
14.318MHz reference clock output
4
7
Notes
MODE
I
Mode settings (latch input)
PCICLK0
O
PCI bus clock output
9
VSS
–
Ground (3.3V supply)
10
PCICLK1
O
PCI bus clock output
Cr ystal oscillator, REF[0:1], 3.3Vline
PCI clock output buffers, pre-buffer, stop logic, and
internal circuit logic supply
C P U _ S T OP# (pin 17) and PCI_STOP# (pin 18) mode
select pin.
M O D E = H I G H : Desktop mode
M O D E = L OW : Mobile mode
PCI clock output buffers, pre-buffer, stop logic
NIPPON PRECISION CIRCUITS—3
SM8702AM
Number
Name
I/O
11
PCICLK2
O
PCI bus clock output
Function
12
PCICLK3
O
PCI bus clock output
Notes
PCICLK4
O
PCI bus clock output
VDD2
–
3.3V supply
PCI clock output buffers, pre-buffer, stop logic
15
BUFFERIN
I
S D R A M c l o ck input
Input on BUFFERIN is buffered and then output on
SDRAM[0:13]
VSS
–
16
SDRAM11
17
C P U _ S TO P #
P C I _ S TO P #
Ground (3.3V supply)
I/O
CPU clock outputs stop control
PCI clock outputs stop control
In mobile mode (MODE = LOW), PCICLK[0:4] tied LOW
w h e n P C I _ S TO P # = L OW .
S D R A M c l o ck output buffers, pre-buffer, stop logic
19
VDD3
–
3.3V supply
SDRAM9
O
S D R A M c l o ck output
21
SDRAM8
O
S D R A M c l o ck output
22
VSS
–
Ground (3.3V supply)
23
S D ATA
I/O
24
SCLK
I
27
28
29
30
31
32
33
48MHz
I/O
I2 C clock input
24MHz clock output
Frequency select 1 (latch input)
FS0
I/O
48MHz USB clock output
Frequency select 0 (latch input)
VDD4
–
3.3V supply
SDRAM7
O
S D R A M c l o ck output
SDRAM6
O
S D R A M c l o ck output
VDD3
–
3.3V supply
SDRAM5
O
S D R A M c l o ck output
SDRAM4
O
S D R A M c l o ck output
VSS
–
Ground (3.3V supply)
SDRAM3
O
S D R A M c l o ck output
pre
34
FS1
35
SDRAM2
O
S D R A M c l o ck output
36
VDD3
–
3.3V supply
37
SDRAM1
O
S D R A M c l o ck output
38
SDRAM0
O
S D R A M c l o ck output
39
VSS
–
Ground (3.3V supply)
40
SDRAM12
O
S D R A M c l o ck output
41
SDRAM13
O
S D R A M c l o ck output
42
VDDL2
–
2.5/3.3V supply
43
CPUCLK1
O
CPU clock output
44
CPUCLK0
O
CPU clock output
45
VSS
–
Ground (2.5/3.3V supply)
46
REF1
FS2
I/O
PLL and internal logic ground, I 2 C interface,
24MHz/48MHz output ground
I2 C serial data input
lim
26
24MHz
In mobile mode (MODE = LOW), CPUCLK[0:1] tied LOW
w h e n C P U _ S TO P # = L OW .
S D R A M c l o ck output
I/O
20
25
S D R A M c l o ck output buffers, pre-buffer, stop logic
S D R A M c l o ck output
SDRAM10
18
ina
ry
13
14
I2 C interface, 24MHz/48MHz output supply, PLL and
internal logic supply
S D R A M c l o ck output buffers, pre-buffer, stop logic
S D R A M c l o ck output buffers, pre-buffer, stop logic
S D R A M c l o ck output buffers, pre-buffer, stop logic
S D R A M c l o ck output buffers, pre-buffer, stop logic
CPU clock output buffers, pre-buffer, stop logic
CPU clock output buffers, pre-buffer, stop logic
14.318MHz reference clock output
Frequency select 2 (latch input)
47
IOA P I C
O
14.318MHz IOAPIC clock output
48
VDDL1
–
2.5/3.3V supply
IOAPIC output buffer, pre-buffer, stop logic
NIPPON PRECISION CIRCUITS—4
SM8702AM
SPECIFICATIONS
Absolute Maximum Ratings
VDD:VDD1, VDD2, VDD3, VDD4
VDDL:VDDL1, VDDL2 unless otherwise noted.
Symbol
Rating
Unit
VDD
(V D D 1 , V D D 2 , V D D 3 , V D D 4 )
−0.3 to 6.0
V
VDDL
(V D D L 1 , V D D L 2 )
−0.3 to 6.0
V
VSS
0
V
V IN
− 0.3 to V D D + 0.3
V
VOUT
− 0.3 to V D D + 0.3
V
T stg
−55 to 125
°C
PD
0.8
W
Supply voltage range
Input voltage range
Output voltage range
Storage temperature range
Pow er dissipation
ina
ry
P arameter
Recommended Operating Conditions
VSS = 0V
Rating
Supply voltages
Operating temperature range
M a x i m um load capacitance
Condition
Unit
min
typ
max
VDD
(V D D 1 , V D D 2 ,
VDD3, VDD4)
Excludes internal core, CPU
clock and IOAPIC output
stages
3.135
3.300
3.465
V
VDDL
(V D D L 1 , V D D L 2 )
Internal core, CPU clock
and IOAPIC output stages
2.375
2.500
2.625
V
0
–
70
°C
T opr
C L1
CPUCLK
10
–
20
pF
C L2
PCICLK, SDRAM
20
–
30
pF
C L3
R E F, 24/48MHz, IOA P I C
10
–
20
pF
–
14.318
–
MHz
fR E F
pre
Reference frequency
Symbol
lim
P arameter
NIPPON PRECISION CIRCUITS—5
SM8702AM
DC Electrical Characteristics
Ta = 0 to 70°C, VDD = 3.3V ± 5%, VDDL = 2.5V ± 5%, VSS = 0V unless otherwise noted.
Rating
Symbol
HIGH-level input voltage
V IH
L O W -level input voltage
V IL
Condition
All pins excl. XT, XTN
All pins excl. XT, XTN, SDATA, SCLK
S D ATA,
SCLK: I2 C
HIGH-level input current
IIH
V IH = V D D
L O W -level input current
IIL
V IL = 0V
interface
HIGH-level output voltage
V OH(3.3V)
All clock outputs:
IO H = −1mA, V D D = 3.135V
L O W -level output voltage
V OL(3.3V)
All clock outputs:
IO L = 1mA, V D D = 3.135V
HIGH-level output voltage
V OH(2.5V)
CPUCLK[0:1], IOAPIC:
IO H = −1mA, V D D L = 2.375V
L O W -level output voltage
V OL(2.5V)
CPUCLK[0:1], IOAPIC:
IO L = 1mA, V D D L = 2.375V
P C I C L K , S D R A M , R E F,
24/48MHz pins.
Also, CPUCLK[0:1] and
IOAPIC outputs, when
VDDL[1:2] = 3.3V.
CPUCLK[0:1] and
IOAPIC outputs, when
VDDL[1:2] = 2.5V.
L O W -level output current
2.0
–
VDD
–
0.8
VSS
–
0.7
−10
–
10
µA
–
–
10
µA
2.4
–
–
V
–
–
0.4
V
2.0
–
–
V
–
–
0.4
V
18.7
–
42.6
18.7
–
42.6
REF[0:1], 24/48MHz:
V O H = 2.0V
18.7
–
42.6
IOAPIC: V O H = 1.7V
8.5
–
23.0
CPUCLK[0:1]: V O L = 0.7V
11.0
–
25.3
P C I C L K _ F, PCICLK[0:4]:
V O L = 0.8V
18.7
–
40.3
18.7
–
40.3
18.7
–
40.3
IOAPIC: V O L = 0.7V
11.0
–
25.3
IO Z
Outputs high impedance
−10
–
10
ID D
C L = 0pF, V D D = 3.465V
–
–
180
ID D L 1
C L = 0pF, V D D L = 3.465V
–
–
30
ID D L 2
C L = 0pF, V D D L = 2.625V
–
–
20
IO H
SDRAM[0:13]: V O H = 2.0V
fO U T = 66.5MHz
IO L
SDRAM[0:13]: V O L = 0.8V
V
VSS
P C I C L K _ F, PCICLK[0:4]:
V O H = 2.0V
pre
Current consumption
max
8.5
REF[0:1], 24/48MHz:
V O L = 0.8V
Output leakage current
typ
CPUCLK[0:1]: V O H = 1.7V
lim
HIGH-level output current
Unit
min
ina
ry
P arameter
V
23.0
mA
mA
fO U T = 66.5MHz
fO U T = 66.5MHz
µA
mA
NIPPON PRECISION CIRCUITS—6
SM8702AM
AC Electrical Characteristics
CPU clock characteristics 1
Ta = 0 to 70°C, VDD = 3.3V ± 5%, VDDL = 2.5V ± 5%, VSS = 0V, fX’tal = 14.318MHz, CL = 20pF unless otherwise noted.
Rating
Symbol
Condition
Unit
ina
ry
P arameter
min
typ
max
tr
V O L = 0.4V → V O H = 2.0V transition time
–
–
2.0
ns
tf
V O H = 2.0V → V O L = 0.4V transition time
–
–
2.0
ns
Dt
V T = 1.25V
45
50
55
%
tjc
V T = 1.25V, rising edge
Cycle-to-cycle jitter
–
–
250
ps
Output clock skew 1
ts k w
V T = 1.25V, rising edge
Between CPUCLK0 and
CPUCLK1
–
–
250
ps
Clock frequency stabilize time 1
tstb
Cold start
Supply ON (V D D = 3.3V)
until clock reaches
specified frequency
–
–
3
ms
Output impedance 2
ZO
V O = 0.5V D D L
10
–
90
Ω
Output clock rise time 1
Output clock fall
time 1
Duty cycle
Output
clock jitter1
1. Design maximum values, not 100% guaranteed.
2. Design estimate values, not 100% guaranteed.
CPU clock characteristics 2
P arameter
lim
Ta = 0 to 70°C, VDD = VDDL = 3.3V ± 5%, VSS = 0V, fX’tal = 14.318MHz, CL = 20pF unless otherwise noted.
Symbol
Rating
Condition
Unit
min
typ
max
tr
V O L = 0.4V → V O H = 2.4V transition time
–
–
2.5
ns
tf
V O H = 2.4V → V O L = 0.4V transition time
–
–
2.5
ns
Dt
V T = 1.5V
45
50
55
%
tjc
V T = 1.5V, rising edge
Cycle-to-cycle jitter
–
–
250
ps
ts k w
V T = 1.5V, rising edge
Between CPUCLK0 and
CPUCLK1
–
–
250
ps
Clock frequency stabilize time 1
tstb
Cold start
Supply ON (V D D = 3.3V)
until clock reaches
specified frequency
–
–
3
ms
Output impedance 2
ZO
V O = 0.5V D D L
10
–
60
Ω
Output clock rise time 1
Output clock fall
time 1
Duty cycle
Output
clock jitter1
pre
Output clock skew 1
1. Design maximum values, not 100% guaranteed.
2. Design estimate values, not 100% guaranteed.
NIPPON PRECISION CIRCUITS—7
SM8702AM
PCI clock characteristics
Ta = 0 to 70°C, VDD = 3.3V ± 5%, VSS = 0V, fX’tal = 14.318MHz, CL = 30pF unless otherwise noted.
Rating
P arameter
Symbol
Condition
Unit
min
typ
max
–
–
2.0
Output clock rise time 1
tr
V O L = 0.8V → V O H = 2.4V transition time
Output clock fall time 1
tf
V O H = 2.4V → V O L = 0.8V transition time
–
–
2.0
ns
Duty cycle
Dt
V T = 1.5V
45
50
55
%
Output clock jitter1
tjc
V T = 1.5V, rising edge
Cycle-to-cycle jitter
–
–
250
ps
Output clock skew 1
ts k w
V T = 1.5V, rising edge
Between PCI clocks:
PCICLK_F and
PCICLK[0:4]
–
–
250
ps
CPU/PCI clock skew 2
thpsk
V T- C P U C L K = 1.25/1.5V,
V T- P C I C L K = 1.5V, rising
edges
Between CPU and PCI
clocks: CPUCLK[0:1] and
PCICLK_F/PCICLK[0:4]
1.0
2.2
4.0
ns
Clock frequency stabilize time 1
tstb
Cold start
Supply ON (V D D = 3.3V)
until clock reaches
specified frequency
–
–
3
ms
Output impedance 3
ZO
V O = 0.5V D D
10
–
60
Ω
ina
ry
ns
1. Design maximum values, not 100% guaranteed.
2. CPUCLK and PCICLK r ising edges, V T- C P U C L K = 1.25V (V D D L = 2.5V)/1.5V (V D D L = 3.3V), V T- P C I C L K = 1.5V skew measurement.
3. Design estimate values, not 100% guaranteed.
lim
SDRAM clock characteristics
Ta = 0 to 70°C, VDD = VDDL = 3.3V ± 5%, VSS = 0V, fX’tal = 14.318MHz, CL = 30pF unless otherwise noted.
P arameter
Symbol
Rating
Condition
Unit
min
typ
max
tr
V O L = 0.8V → V O H = 2.4V transition time
–
–
2.0
ns
tf
V O H = 2.4V → V O L = 0.8V transition time
–
–
2.0
ns
Dt
V T = 1.5V, BU F F E R I N
input clock signal rise
and fall time rate ≥ 1V/ns
3.3V BUFFERIN input
clock signal logic level
40
50
60
%
ts k w
V T = 1.5V, rising edge,
B UFFERIN input clock
signal rise and fall time
rate ≥ 1V/ns
Between SDRAM clocks:
SDRAM[0:13]
–
200
600
ps
Input to output propagation
delay 2 ,3
tp d
V T-BU F F E R I N = 1.5V,
V T- S D R A M = 1.5V, rising
edges, BUFFERIN input
clock signal rise and fall
time rate ≥ 1V/ns
Between BUFFERIN and
SDRAM[0:13]
–
5.5
7.0
ns
Output impedance 3
ZO
V O = 0.5V D D
10
–
60
Ω
Output clock rise time 1
Output clock fall
time 1
Duty cycle 1
pre
Output clock skew 1
1. Design maximum values, not 100% guaranteed.
2. B U F F E R I N a n d S D R A M r ising edges, V T-BU F F E R I N = 1.5V (logic level = 3.3V), V T- S D R A M = 1.5V delay measurement.
3. Design estimate values, not 100% guaranteed.
NIPPON PRECISION CIRCUITS—8
SM8702AM
24MHz/48MHz, REF[0:1] clock characteristics
Ta = 0 to 70°C, VDD = 3.3V ± 5%, VSS = 0V, fX’tal = 14.318MHz, CL = 20pF unless otherwise noted.
Rating
P arameter
Symbol
Condition
Unit
min
typ
max
–
–
2.0
Output clock rise time 1
tr
V O L = 0.8V → V O H = 2.4V transition time
Output clock fall time 1
tf
V O H = 2.4V → V O L = 0.8V transition time
–
–
2.0
ns
Duty cycle 1
Dt
V T = 1.5V
40
50
60
%
Output clock jitter1
tjc
V T = 1.5V, rising edge
Absolute jitter
–
250
800
ps
Clock frequency stabilize time 1
tstb
Cold start
Supply ON (V D D = 3.3V)
until clock reaches
specified frequency
–
–
3
ms
Output impedance 2
ZO
V O = 0.5V D D
10
–
60
Ω
IOAPIC clock characteristics
ina
ry
1. Design maximum values, not 100% guaranteed.
2. Design estimate values, not 100% guaranteed.
ns
Ta = 0 to 70°C, VDD = 3.3V ± 5%, VSS = 0V, fX’tal = 14.318MHz, CL = 20pF unless otherwise noted.
Rating
Symbol
Output clock rise time 1
Output clock fall
time 1
Duty cycle 1
Output
clock jitter1
Condition
typ
max
V O L = 0.8V → V O H = 2.4V transition time,
V D D L 1 = 3.3V
–
–
2.0
V O L = 0.4V → V O H = 2.0V transition time,
V D D L 1 = 2.5V
–
–
2.0
V O H = 2.4V → V O L = 0.8V transition time,
V D D L 1 = 3.3V
–
–
2.0
V O H = 2.0V → V O L = 0.4V transition time,
V D D L 1 = 2.5V
–
–
2.0
Dt
V T = 1.5V, V D D L 1 = 3.3V
40
50
60
%
tjc
V T = 1.5V, rising edge
Absolute jitter
–
250
800
ps
tstb
Cold start
Supply ON (V D D = 3.3V)
until clock reaches
specified frequency
–
–
3
ms
10
–
90
Ω
tr
tf
pre
Clock frequency stabilize time 1
Output impedance 2
Unit
min
lim
P arameter
ZO
V O = 0.5V D D
ns
ns
1. Design maximum values, not 100% guaranteed.
2. Design estimate values, not 100% guaranteed.
NIPPON PRECISION CIRCUITS—9
SM8702AM
I2C serial interface electrical characteristics
Ta = 0 to 70°C, VDD = 3.3V ± 5%, VSS = 0V, fX’tal = 14.318MHz, CL = 30pF unless otherwise noted.
Rating
Symbol
Serial clock frequency
fS C L K
Serial clock start state hold time
tH D ; S TA
Serial clock LOW -level pulsewidth
tL O W
Serial clock HIGH-level pulsewidth
tH I G H
Successive start state setup time
tS U ; S TA
Data hold time
tH D ; DAT
Data input setup time
tS U ; DAT
Pulse rise time
tr
Pulse fall time
tf
Stop state setup time
tS U ; S TO
Serial data bus buffer time
tB U F
Bus line load capacitance
Cb
Condition
Unit
I2 C standard mode
min
typ
max
0
–
100
kHz
ina
ry
P arameter
I2 C device data
4.0
–
–
µs
4.7
–
–
µs
4.0
–
–
µs
4.7
–
–
µs
0
–
3.45
µs
250
–
–
ns
–
–
1000
ns
–
–
300
ns
4.0
–
–
µs
4.7
–
–
µs
–
–
400
pF
SDATA
lim
tBUF
tf
tLOW
SCLK
tHD;STA
tr
tHD;DAT
tSU;DAT
tf
tHIGH
tHD;STA
tSU;STA
tr
tSU;STO
pre
I 2 C serial data timing
NIPPON PRECISION CIRCUITS—10
SM8702AM
FUNCTIONAL DESCRIPTION
Mode Setting Overview
There are 2 methods that can be used to set the frequency and clock output start/stop operating modes.
■
Using external inputs (pins 7, 17, 18, 25, 26, 46) or,
Using data read in from an I2C serial interface.
ina
ry
■
The default state is where the operating state is set by external pin control. Thus, the output frequency can be
set by FS[0:2] (pins 25, 26, 46). Note that the SSCG function is OFF in this case. If the I2C serial data byte 0
bit 3 is set to 1, then the output frequency is determined by data using the I2C interface. Then, the Spread Spectrum function (SSCG) can be selected using I2C data. However, if mode settings using I2C data and external
pin control conflict or overlap, the mode settings dictated by I2C data have precedence over external pin control.
During normal operation, pins 17 and 18 can function as SDRAM clock outputs (desktop mode) or they can
function as CPUCLK output stop control and PCICLK output stop control (mobile mode), depending on the
state of MODE (pin 7) when power is first applied.
In addition to output frequency settings, other operating mode settings which can be controlled by I2C serial
data include SSCG operation and mode, and output pin grouping enable/disable switching.
Hardware Frequency Selection
When power is applied, the frequency setting is controlled by FS[0:2] when byte 0 bit 3 is set to 0. Note that if
byte 0 bit 3 is set to 1, the frequency is selected by bits 4 to 6 in the same manner as inputs FS0 to FS2.
FS1
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
HIGH
LOW
LOW
HIGH
LOW
HIGH
LOW
LOW
LOW
LOW
FS0
CPUCLK
[MHz]
PCICLK
[MHz]
HIGH
100.2
33.4
LOW
133
33.2
HIGH
112.1
37.3
LOW
103
34.3
HIGH
66.5
33.2
LOW
83.3
41.6
HIGH
74.9
37.4
LOW
94.7
31.6
pre
FS2
Output frequency
lim
Inputs
Mode and Power Management Inputs
The SM8702AM supports 2 operating modes, desktop mode and mobile mode, selected by MODE (pin 7).
If MODE is HIGH when power is first applied, desktop mode is selected. In this mode, pins 17 and 18 function
as SDRAM clock outputs, SDRAM11 and SDRAM10, respectively.
If MODE is LOW when power is first applied, mobile mode is selected. In this mode, pins 17 and 18 function
as the CPU clock (CPUCLK[0:1]) and PCI clock (PCICLK[0:4]) output stop control signal inputs,
CPU_STOP# and PCI_STOP#, respectively. This function is used mainly to reduce power consumption.
MODE
Pin 17
Pin 18
Mode
HIGH
SDRAM11
SDRAM10
Desktop mode
Pins 17 and 18 are outputs.
LOW
CPU_STOP# P C I _ S TO P #
Mobile mode
Pins 17 and 18 are inputs.
NIPPON PRECISION CIRCUITS—11
SM8702AM
Operating Mode Summary
The state of the various external inputs and outputs in the operating modes is indicated in the following table.
VCO
P C I C L K _ F,
Cr ystal
(internal
CPUCLK[0:1] PCICLK[0:4] 2 4 M H z / 4 8 M H z ,
oscillator
signal)
SDRAM[0:13]
SDRAM11/
C P U _ S TO P #
SDRAM10/
P C I _ S TO P #
MODE = HIGH
(desktop
mode)
E n a bled
(SDRAM output)
E n a bled
(SDRAM output)
Notes 1
E n a bled
E n a bled
E n a bled
E n a bled
Desktop mode.
E n a bled Pins 17 and 18
function as outputs.
E n a bled
E n a bled
E n a bled
E n a bled
E n a bled
ina
ry
MODE
HIGH
HIGH
( C P U _ S TOP# input) (PCI_STOP# input)
HIGH
LOW
(
C
P
U
_
S
TOP#
input)
(PCI_STOP#
input)
M O D E = L OW
(mobile mode)
LOW
HIGH
( C P U _ S TOP# input) (PCI_STOP# input)
LOW
LOW
( C P U _ S TOP# input) (PCI_STOP# input)
E n a bled
Disabled
E n a bled
E n a bled
Disabled
E n a bled
E n a bled
E n a bled
Disabled
Disabled
E n a bled
E n a bled
Mobile mode.
Pins 17 and 18
E n a bled function as inputs.
Pin 17 =
E n a bled C P U _ S T O P #
Pin 18 =
P C I _ S TO P #
E n a bled
1. E n a bled = output functions active. Disabled = LOW -level output.
CPU Clock Stop Function
In mobile mode, selected using MODE (pin 7), the CPUCLK[0:1] clock outputs can be stopped by external pin
control. The asynchronous stop signal input on CPU_STOP# is sampled internally on the rising edge of the
PCI free-running output clock (PCICLK_F).
lim
When CPU_STOP# goes LOW, the CPU clock outputs (CPUCLK) stop after a delay of 2 to 4 clock cycles.
When CPU_STOP# goes HIGH, the CPU clock outputs start after a delay of 2 to 4 clock cycles. The actual
start and stop delay varies with the output frequency up to a maximum of 4 CPU clock cycles.
CPUCLK
(internal)
PCICLK
(internal)
PCICLK_F
(free-running)
pre
CPU_STOP#
PCI_STOP#
(All "H")
CPUCLK
(external)
NIPPON PRECISION CIRCUITS—12
SM8702AM
PCI Clock Stop Function
In mobile mode, selected using MODE (pin 7), the PCICLK[0:4] clock outputs can be stopped by external pin
control, in the same way as the CPU clock stop function.
CPUCLK
(internal)
PCICLK
(internal)
PCICLK_F
(free-running)
CPU_STOP#
(All "H")
PCI_STOP#
pre
lim
PCICLK
(external)
ina
ry
When PCI_STOP# goes LOW, the PCI clock outputs (PCICLK) stop, and when PCI_STOP# goes HIGH, the
PCI clock outputs start. In either case, the PCI_STOP# signal is sampled internally on the rising edge of PCICLK, and the output state transition occurs with 1 PCI clock cycle delay.
NIPPON PRECISION CIRCUITS—13
SM8702AM
I2C Bus Serial Data Format
The format of the I2C serial data on SDATA (pin 23) which is input in sync with the serial data clock on SCLK
(pin 24) is shown below.
A6
A5
1
1
ina
ry
The SM8702AM I2C address is given below.
A4
A3
A2
A1
A0
R/W#
0
1
0
0
1
−
R/W# = 0 or 1
In the start sequence, the I2C bus serial data is fed into the clock generator in the following direction.
1.
2.
3.
4.
I2C address with R/W# = 0
ACK acknowledge bit
Two successive 8-bit dummy command code data words (including ACK acknowledge bit)
8-bit dummy command code (Byte 0 to Byte 5)
The direction of I 2 C Data for Clock Generator
1bit
8bit
1bit
8bit
1bit
8bit
1bit
8bit
A
C
K
Byte 1
lim
I 2 C Addr. A Dummy A Dummy A
+R/W# C Command C Command C
K Code K Code K
D2h
Bit 7
Bit 6
Byte 0
Bit 5
Bit 4
Bit 3
1bit
8bit
1bit
A
C
K
Byte 2
A
C
K
Bit 2
Bit 1
8bit
1bit
S
A
T
Byte 5 C
O
K
P
Bit 0
The data transfer speed is 100k bps (I2C standard mode), with input logic level of 3.3V. When power is first
applied, all internal registers are restored to their default state as below.
Byte0 : default = 0 (bit 0 to bit 3 and bit 7)
: default = 1 (bit 4 to bit 6)
Byte 1 to Byte 5 : default = 1 (all bits)
pre
■
■
NIPPON PRECISION CIRCUITS—14
SM8702AM
I2C Bus Data Bytes
Byte 0: function and frequency select
Bit
P o w e r-ON
default
Function
0: Spread spectrum ± 1.5% modulation
1: Spread spectrum ± 0.5% modulation
0
Frequency select bits
Bit 6
Bit 5
Bit 4
CPUCLK
[MHz]
PCICLK
[MHz]
1
1
1
100.2
33.4
1
1
0
133
33.2
1
0
1
112.1
37.3
1
0
0
103
34.3
0
1
1
66.5
33.2
0
1
0
83.3
41.6
0
0
1
74.9
37.4
0
0
0
94.7
31.6
6:4
1
The pow er-ON default for bits 4 to 6 is 1.
When bit 3 is set to 1 (I 2 C select), bits 4 to 6 select
the frequency in the same write cycle timing.
FS[0:2] are latch inputs
0: Hardware frequency select using FS[0:2]
1: I2 C bus serial data frequency select
0
2
0: Spread spectrum center spread select
1: Spread spectrum down spread select
0
1
0: Normal operating mode (SSCG disabled)
1: Spread spectrum operating mode (SSCG enabled)
0
0
0: Normal output mode (running)
1: Three-state output mode
0
lim
3
Byte 1: CPU register
Pin
number
P o w e r-ON
default 1
7
26
1
6
25
1
All outputs are high impedance when bit 0 is set to 1.
Byte 2: PCI register
Bit
Pin
number
P o w e r-ON
default 1
48MHz USB
7
–
1
(Reser ved)
24MHz (Super I/O)
6
7
1
P C I C L K _ F e n a ble
Notes
pre
Bit
The spread spectrum accuracy of modulation is not
guaranteed.
ina
ry
7
Notes
Notes
5
–
1
(Reser ved)
5
–
1
(Reser ved)
4
–
1
(Reser ved)
4
14
1
PCICLK4 enable
3
–
1
(Reser ved)
3
12
1
PCICLK3 enable
2
–
1
(Reser ved)
2
11
1
PCICLK2 enable
1
43
1
C P U C L K 1 e n a ble
1
10
1
PCICLK1 enable
0
44
1
C P U C L K 0 e n a ble
0
8
1
PCICLK0 enable
1. 1 = enabled, 0 = disabled
1. 1 = enabled, 0 = disabled
NIPPON PRECISION CIRCUITS—15
SM8702AM
Byte 3: SDRAM register
Byte 5: REF/IOAPIC register
Bit
Pin
number
P o w e r-ON
default 1
7
–
1
(Reser ved)
6
–
1
(Reser ved)
5
–
1
(Reser ved)
4
–
1
(Reser ved)
3
17, 18
1
SDRAM[10:11] enable in
desktop mode only (MODE =
HIGH)
2
20, 21, 40,
41
1
SDRAM[8,9,12,13] enable
1
28, 29, 31,
32
1
SDRAM[4:7] enable
0
34, 35, 37,
38
1
SDRAM[0:3] enable
P o w e r-ON
default 1
Notes
ina
ry
Pin
number
7
–
1
(Reser ved)
6
–
1
(Reser ved)
5
–
1
(Reser ved)
4
47
1
IOAPIC enable
3
–
1
(Reser ved)
2
–
1
(Reser ved)
1
46
1
R E F 1 e n a ble
0
2
1
R E F 0 e n a ble
1. 1 = enabled, 0 = disabled
lim
1. 1 = enabled, 0 = disabled
Bit
Notes
Byte 4: Reserved register
Bit
Pin
number
P o w e r-ON
default 1
7
–
1
(Reser ved)
6
–
1
(Reser ved)
5
–
1
(Reser ved)
pre
Notes
4
–
1
(Reser ved)
3
–
1
(Reser ved)
2
–
1
(Reser ved)
1
–
1
(Reser ved)
0
–
1
(Reser ved)
1. 1 = enabled, 0 = disabled
NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to
improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility fo r
the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits
are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision
Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification.
The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or
malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter,
including compliance with expor t controls on the distribution or dissemination of the products. Customers shall not expor t, directly or
indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies.
NIPPON PRECISION CIRCUITS INC.
NIPPON PRECISION CIRCUITS INC.
4-3, Fukuzumi 2-chome
Koto-ku, Tokyo 135-8430, Japan
Telephone: 03-3642-6661
Facsimile: 03-3642-6698
NP9907AE
1999.07
NIPPON PRECISION CIRCUITS—16